drivers/usb/host/ohci-hcd.c

   1 /*
   2  * Open Host Controller Interface (OHCI) driver for USB.
   3  *
   4  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
   5  *
   6  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   7  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
   8  *
   9  * [ Initialisation is based on Linus'  ]
  10  * [ uhci code and gregs ohci fragments ]
  11  * [ (C) Copyright 1999 Linus Torvalds  ]
  12  * [ (C) Copyright 1999 Gregory P. Smith]
  13  *
  14  *
  15  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  16  * interfaces (though some non-x86 Intel chips use it).  It supports
  17  * smarter hardware than UHCI.  A download link for the spec available
  18  * through the http://www.usb.org website.
  19  *
  20  * This file is licenced under the GPL.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/pci.h>
  26 #include <linux/kernel.h>
  27 #include <linux/delay.h>
  28 #include <linux/ioport.h>
  29 #include <linux/sched.h>
  30 #include <linux/slab.h>
  31 #include <linux/errno.h>
  32 #include <linux/init.h>
  33 #include <linux/timer.h>
  34 #include <linux/list.h>
  35 #include <linux/usb.h>
  36 #include <linux/usb/otg.h>
  37 #include <linux/usb/hcd.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/dmapool.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/debugfs.h>
  42
  43 #include <asm/io.h>
  44 #include <asm/irq.h>
  45 #include <asm/unaligned.h>
  46 #include <asm/byteorder.h>
  47
  48
  49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  51
  52 /*-------------------------------------------------------------------------*/
  53
  54 /* For initializing controller (mask in an HCFS mode too) */
  55 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
  56 #define OHCI_INTR_INIT \
  57                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
  58                 | OHCI_INTR_RD | OHCI_INTR_WDH)
  59
  60 #ifdef __hppa__
  61 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  62 #define IR_DISABLE
  63 #endif
  64
  65 #ifdef CONFIG_ARCH_OMAP
  66 /* OMAP doesn't support IR (no SMM; not needed) */
  67 #define IR_DISABLE
  68 #endif
  69
  70 /*-------------------------------------------------------------------------*/
  71
  72 static const char       hcd_name [] = "ohci_hcd";
  73
  74 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
  75 #define IO_WATCHDOG_DELAY       msecs_to_jiffies(275)
  76 #define IO_WATCHDOG_OFF         0xffffff00
  77
  78 #include "ohci.h"
  79 #include "pci-quirks.h"
  80
  81 static void ohci_dump(struct ohci_hcd *ohci);
  82 static void ohci_stop(struct usb_hcd *hcd);
  83 static void io_watchdog_func(unsigned long _ohci);
  84
  85 #include "ohci-hub.c"
  86 #include "ohci-dbg.c"
  87 #include "ohci-mem.c"
  88 #include "ohci-q.c"
  89
  90
  91 /*
  92  * On architectures with edge-triggered interrupts we must never return
  93  * IRQ_NONE.
  94  */
  95 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
  96 #define IRQ_NOTMINE     IRQ_HANDLED
  97 #else
  98 #define IRQ_NOTMINE     IRQ_NONE
  99 #endif
 100
 101
 102 /* Some boards misreport power switching/overcurrent */
 103 static bool distrust_firmware;
 104 module_param (distrust_firmware, bool, 0);
 105 MODULE_PARM_DESC (distrust_firmware,
 106         "true to distrust firmware power/overcurrent setup");
 107
 108 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
 109 static bool no_handshake;
 110 module_param (no_handshake, bool, 0);
 111 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
 112
 113 /*-------------------------------------------------------------------------*/
 114
 115 static int number_of_tds(struct urb *urb)
 116 {
 117         int                     len, i, num, this_sg_len;
 118         struct scatterlist      *sg;
 119
 120         len = urb->transfer_buffer_length;
 121         i = urb->num_mapped_sgs;
 122
 123         if (len > 0 && i > 0) {         /* Scatter-gather transfer */
 124                 num = 0;
 125                 sg = urb->sg;
 126                 for (;;) {
 127                         this_sg_len = min_t(int, sg_dma_len(sg), len);
 128                         num += DIV_ROUND_UP(this_sg_len, 4096);
 129                         len -= this_sg_len;
 130                         if (--i <= 0 || len <= 0)
 131                                 break;
 132                         sg = sg_next(sg);
 133                 }
 134
 135         } else {                        /* Non-SG transfer */
 136                 /* one TD for every 4096 Bytes (could be up to 8K) */
 137                 num = DIV_ROUND_UP(len, 4096);
 138         }
 139         return num;
 140 }
 141
 142 /*
 143  * queue up an urb for anything except the root hub
 144  */
 145 static int ohci_urb_enqueue (
 146         struct usb_hcd  *hcd,
 147         struct urb      *urb,
 148         gfp_t           mem_flags
 149 ) {
 150         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 151         struct ed       *ed;
 152         urb_priv_t      *urb_priv;
 153         unsigned int    pipe = urb->pipe;
 154         int             i, size = 0;
 155         unsigned long   flags;
 156         int             retval = 0;
 157
 158         /* every endpoint has a ed, locate and maybe (re)initialize it */
 159         ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval);
 160         if (! ed)
 161                 return -ENOMEM;
 162
 163         /* for the private part of the URB we need the number of TDs (size) */
 164         switch (ed->type) {
 165                 case PIPE_CONTROL:
 166                         /* td_submit_urb() doesn't yet handle these */
 167                         if (urb->transfer_buffer_length > 4096)
 168                                 return -EMSGSIZE;
 169
 170                         /* 1 TD for setup, 1 for ACK, plus ... */
 171                         size = 2;
 172                         /* FALLTHROUGH */
 173                 // case PIPE_INTERRUPT:
 174                 // case PIPE_BULK:
 175                 default:
 176                         size += number_of_tds(urb);
 177                         /* maybe a zero-length packet to wrap it up */
 178                         if (size == 0)
 179                                 size++;
 180                         else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
 181                                 && (urb->transfer_buffer_length
 182                                         % usb_maxpacket (urb->dev, pipe,
 183                                                 usb_pipeout (pipe))) == 0)
 184                                 size++;
 185                         break;
 186                 case PIPE_ISOCHRONOUS: /* number of packets from URB */
 187                         size = urb->number_of_packets;
 188                         break;
 189         }
 190
 191         /* allocate the private part of the URB */
 192         urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
 193                         mem_flags);
 194         if (!urb_priv)
 195                 return -ENOMEM;
 196         INIT_LIST_HEAD (&urb_priv->pending);
 197         urb_priv->length = size;
 198         urb_priv->ed = ed;
 199
 200         /* allocate the TDs (deferring hash chain updates) */
 201         for (i = 0; i < size; i++) {
 202                 urb_priv->td [i] = td_alloc (ohci, mem_flags);
 203                 if (!urb_priv->td [i]) {
 204                         urb_priv->length = i;
 205                         urb_free_priv (ohci, urb_priv);
 206                         return -ENOMEM;
 207                 }
 208         }
 209
 210         spin_lock_irqsave (&ohci->lock, flags);
 211
 212         /* don't submit to a dead HC */
 213         if (!HCD_HW_ACCESSIBLE(hcd)) {
 214                 retval = -ENODEV;
 215                 goto fail;
 216         }
 217         if (ohci->rh_state != OHCI_RH_RUNNING) {
 218                 retval = -ENODEV;
 219                 goto fail;
 220         }
 221         retval = usb_hcd_link_urb_to_ep(hcd, urb);
 222         if (retval)
 223                 goto fail;
 224
 225         /* schedule the ed if needed */
 226         if (ed->state == ED_IDLE) {
 227                 retval = ed_schedule (ohci, ed);
 228                 if (retval < 0) {
 229                         usb_hcd_unlink_urb_from_ep(hcd, urb);
 230                         goto fail;
 231                 }
 232
 233                 /* Start up the I/O watchdog timer, if it's not running */
 234                 if (ohci->prev_frame_no == IO_WATCHDOG_OFF &&
 235                                 list_empty(&ohci->eds_in_use) &&
 236                                 !(ohci->flags & OHCI_QUIRK_QEMU)) {
 237                         ohci->prev_frame_no = ohci_frame_no(ohci);
 238                         mod_timer(&ohci->io_watchdog,
 239                                         jiffies + IO_WATCHDOG_DELAY);
 240                 }
 241                 list_add(&ed->in_use_list, &ohci->eds_in_use);
 242
 243                 if (ed->type == PIPE_ISOCHRONOUS) {
 244                         u16     frame = ohci_frame_no(ohci);
 245
 246                         /* delay a few frames before the first TD */
 247                         frame += max_t (u16, 8, ed->interval);
 248                         frame &= ~(ed->interval - 1);
 249                         frame |= ed->branch;
 250                         urb->start_frame = frame;
 251                         ed->last_iso = frame + ed->interval * (size - 1);
 252                 }
 253         } else if (ed->type == PIPE_ISOCHRONOUS) {
 254                 u16     next = ohci_frame_no(ohci) + 1;
 255                 u16     frame = ed->last_iso + ed->interval;
 256                 u16     length = ed->interval * (size - 1);
 257
 258                 /* Behind the scheduling threshold? */
 259                 if (unlikely(tick_before(frame, next))) {
 260
 261                         /* URB_ISO_ASAP: Round up to the first available slot */
 262                         if (urb->transfer_flags & URB_ISO_ASAP) {
 263                                 frame += (next - frame + ed->interval - 1) &
 264                                                 -ed->interval;
 265
 266                         /*
 267                          * Not ASAP: Use the next slot in the stream,
 268                          * no matter what.
 269                          */
 270                         } else {
 271                                 /*
 272                                  * Some OHCI hardware doesn't handle late TDs
 273                                  * correctly.  After retiring them it proceeds
 274                                  * to the next ED instead of the next TD.
 275                                  * Therefore we have to omit the late TDs
 276                                  * entirely.
 277                                  */
 278                                 urb_priv->td_cnt = DIV_ROUND_UP(
 279                                                 (u16) (next - frame),
 280                                                 ed->interval);
 281                                 if (urb_priv->td_cnt >= urb_priv->length) {
 282                                         ++urb_priv->td_cnt;     /* Mark it */
 283                                         ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
 284                                                         urb, frame, length,
 285                                                         next);
 286                                 }
 287                         }
 288                 }
 289                 urb->start_frame = frame;
 290                 ed->last_iso = frame + length;
 291         }
 292
 293         /* fill the TDs and link them to the ed; and
 294          * enable that part of the schedule, if needed
 295          * and update count of queued periodic urbs
 296          */
 297         urb->hcpriv = urb_priv;
 298         td_submit_urb (ohci, urb);
 299
 300 fail:
 301         if (retval)
 302                 urb_free_priv (ohci, urb_priv);
 303         spin_unlock_irqrestore (&ohci->lock, flags);
 304         return retval;
 305 }
 306
 307 /*
 308  * decouple the URB from the HC queues (TDs, urb_priv).
 309  * reporting is always done
 310  * asynchronously, and we might be dealing with an urb that's
 311  * partially transferred, or an ED with other urbs being unlinked.
 312  */
 313 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 314 {
 315         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 316         unsigned long           flags;
 317         int                     rc;
 318         urb_priv_t              *urb_priv;
 319
 320         spin_lock_irqsave (&ohci->lock, flags);
 321         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
 322         if (rc == 0) {
 323
 324                 /* Unless an IRQ completed the unlink while it was being
 325                  * handed to us, flag it for unlink and giveback, and force
 326                  * some upcoming INTR_SF to call finish_unlinks()
 327                  */
 328                 urb_priv = urb->hcpriv;
 329                 if (urb_priv->ed->state == ED_OPER)
 330                         start_ed_unlink(ohci, urb_priv->ed);
 331
 332                 if (ohci->rh_state != OHCI_RH_RUNNING) {
 333                         /* With HC dead, we can clean up right away */
 334                         ohci_work(ohci);
 335                 }
 336         }
 337         spin_unlock_irqrestore (&ohci->lock, flags);
 338         return rc;
 339 }
 340
 341 /*-------------------------------------------------------------------------*/
 342
 343 /* frees config/altsetting state for endpoints,
 344  * including ED memory, dummy TD, and bulk/intr data toggle
 345  */
 346
 347 static void
 348 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
 349 {
 350         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 351         unsigned long           flags;
 352         struct ed               *ed = ep->hcpriv;
 353         unsigned                limit = 1000;
 354
 355         /* ASSERT:  any requests/urbs are being unlinked */
 356         /* ASSERT:  nobody can be submitting urbs for this any more */
 357
 358         if (!ed)
 359                 return;
 360
 361 rescan:
 362         spin_lock_irqsave (&ohci->lock, flags);
 363
 364         if (ohci->rh_state != OHCI_RH_RUNNING) {
 365 sanitize:
 366                 ed->state = ED_IDLE;
 367                 ohci_work(ohci);
 368         }
 369
 370         switch (ed->state) {
 371         case ED_UNLINK:         /* wait for hw to finish? */
 372                 /* major IRQ delivery trouble loses INTR_SF too... */
 373                 if (limit-- == 0) {
 374                         ohci_warn(ohci, "ED unlink timeout\n");
 375                         goto sanitize;
 376                 }
 377                 spin_unlock_irqrestore (&ohci->lock, flags);
 378                 schedule_timeout_uninterruptible(1);
 379                 goto rescan;
 380         case ED_IDLE:           /* fully unlinked */
 381                 if (list_empty (&ed->td_list)) {
 382                         td_free (ohci, ed->dummy);
 383                         ed_free (ohci, ed);
 384                         break;
 385                 }
 386                 /* else FALL THROUGH */
 387         default:
 388                 /* caller was supposed to have unlinked any requests;
 389                  * that's not our job.  can't recover; must leak ed.
 390                  */
 391                 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
 392                         ed, ep->desc.bEndpointAddress, ed->state,
 393                         list_empty (&ed->td_list) ? "" : " (has tds)");
 394                 td_free (ohci, ed->dummy);
 395                 break;
 396         }
 397         ep->hcpriv = NULL;
 398         spin_unlock_irqrestore (&ohci->lock, flags);
 399 }
 400
 401 static int ohci_get_frame (struct usb_hcd *hcd)
 402 {
 403         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 404
 405         return ohci_frame_no(ohci);
 406 }
 407
 408 static void ohci_usb_reset (struct ohci_hcd *ohci)
 409 {
 410         ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
 411         ohci->hc_control &= OHCI_CTRL_RWC;
 412         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 413         ohci->rh_state = OHCI_RH_HALTED;
 414 }
 415
 416 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
 417  * other cases where the next software may expect clean state from the
 418  * "firmware".  this is bus-neutral, unlike shutdown() methods.
 419  */
 420 static void _ohci_shutdown(struct usb_hcd *hcd)
 421 {
 422         struct ohci_hcd *ohci;
 423
 424         ohci = hcd_to_ohci (hcd);
 425         ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
 426
 427         /* Software reset, after which the controller goes into SUSPEND */
 428         ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
 429         ohci_readl(ohci, &ohci->regs->cmdstatus);       /* flush the writes */
 430         udelay(10);
 431
 432         ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
 433         ohci->rh_state = OHCI_RH_HALTED;
 434 }
 435
 436 static void ohci_shutdown(struct usb_hcd *hcd)
 437 {
 438         struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 439         unsigned long flags;
 440
 441         spin_lock_irqsave(&ohci->lock, flags);
 442         _ohci_shutdown(hcd);
 443         spin_unlock_irqrestore(&ohci->lock, flags);
 444 }
 445
 446 /*-------------------------------------------------------------------------*
 447  * HC functions
 448  *-------------------------------------------------------------------------*/
 449
 450 /* init memory, and kick BIOS/SMM off */
 451
 452 static int ohci_init (struct ohci_hcd *ohci)
 453 {
 454         int ret;
 455         struct usb_hcd *hcd = ohci_to_hcd(ohci);
 456
 457         /* Accept arbitrarily long scatter-gather lists */
 458         if (!(hcd->driver->flags & HCD_LOCAL_MEM))
 459                 hcd->self.sg_tablesize = ~0;
 460
 461         if (distrust_firmware)
 462                 ohci->flags |= OHCI_QUIRK_HUB_POWER;
 463
 464         ohci->rh_state = OHCI_RH_HALTED;
 465         ohci->regs = hcd->regs;
 466
 467         /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
 468          * was never needed for most non-PCI systems ... remove the code?
 469          */
 470
 471 #ifndef IR_DISABLE
 472         /* SMM owns the HC?  not for long! */
 473         if (!no_handshake && ohci_readl (ohci,
 474                                         &ohci->regs->control) & OHCI_CTRL_IR) {
 475                 u32 temp;
 476
 477                 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
 478
 479                 /* this timeout is arbitrary.  we make it long, so systems
 480                  * depending on usb keyboards may be usable even if the
 481                  * BIOS/SMM code seems pretty broken.
 482                  */
 483                 temp = 500;     /* arbitrary: five seconds */
 484
 485                 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
 486                 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
 487                 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
 488                         msleep (10);
 489                         if (--temp == 0) {
 490                                 ohci_err (ohci, "USB HC takeover failed!"
 491                                         "  (BIOS/SMM bug)\n");
 492                                 return -EBUSY;
 493                         }
 494                 }
 495                 ohci_usb_reset (ohci);
 496         }
 497 #endif
 498
 499         /* Disable HC interrupts */
 500         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 501
 502         /* flush the writes, and save key bits like RWC */
 503         if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
 504                 ohci->hc_control |= OHCI_CTRL_RWC;
 505
 506         /* Read the number of ports unless overridden */
 507         if (ohci->num_ports == 0)
 508                 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
 509
 510         if (ohci->hcca)
 511                 return 0;
 512
 513         setup_timer(&ohci->io_watchdog, io_watchdog_func,
 514                         (unsigned long) ohci);
 515         ohci->prev_frame_no = IO_WATCHDOG_OFF;
 516
 517         ohci->hcca = dma_alloc_coherent (hcd->self.controller,
 518                         sizeof(*ohci->hcca), &ohci->hcca_dma, GFP_KERNEL);
 519         if (!ohci->hcca)
 520                 return -ENOMEM;
 521
 522         if ((ret = ohci_mem_init (ohci)) < 0)
 523                 ohci_stop (hcd);
 524         else {
 525                 create_debug_files (ohci);
 526         }
 527
 528         return ret;
 529 }
 530
 531 /*-------------------------------------------------------------------------*/
 532
 533 /* Start an OHCI controller, set the BUS operational
 534  * resets USB and controller
 535  * enable interrupts
 536  */
 537 static int ohci_run (struct ohci_hcd *ohci)
 538 {
 539         u32                     mask, val;
 540         int                     first = ohci->fminterval == 0;
 541         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
 542
 543         ohci->rh_state = OHCI_RH_HALTED;
 544
 545         /* boot firmware should have set this up (5.1.1.3.1) */
 546         if (first) {
 547
 548                 val = ohci_readl (ohci, &ohci->regs->fminterval);
 549                 ohci->fminterval = val & 0x3fff;
 550                 if (ohci->fminterval != FI)
 551                         ohci_dbg (ohci, "fminterval delta %d\n",
 552                                 ohci->fminterval - FI);
 553                 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
 554                 /* also: power/overcurrent flags in roothub.a */
 555         }
 556
 557         /* Reset USB nearly "by the book".  RemoteWakeupConnected has
 558          * to be checked in case boot firmware (BIOS/SMM/...) has set up
 559          * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
 560          * If the bus glue detected wakeup capability then it should
 561          * already be enabled; if so we'll just enable it again.
 562          */
 563         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
 564                 device_set_wakeup_capable(hcd->self.controller, 1);
 565
 566         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
 567         case OHCI_USB_OPER:
 568                 val = 0;
 569                 break;
 570         case OHCI_USB_SUSPEND:
 571         case OHCI_USB_RESUME:
 572                 ohci->hc_control &= OHCI_CTRL_RWC;
 573                 ohci->hc_control |= OHCI_USB_RESUME;
 574                 val = 10 /* msec wait */;
 575                 break;
 576         // case OHCI_USB_RESET:
 577         default:
 578                 ohci->hc_control &= OHCI_CTRL_RWC;
 579                 ohci->hc_control |= OHCI_USB_RESET;
 580                 val = 50 /* msec wait */;
 581                 break;
 582         }
 583         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 584         // flush the writes
 585         (void) ohci_readl (ohci, &ohci->regs->control);
 586         msleep(val);
 587
 588         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 589
 590         /* 2msec timelimit here means no irqs/preempt */
 591         spin_lock_irq (&ohci->lock);
 592
 593 retry:
 594         /* HC Reset requires max 10 us delay */
 595         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
 596         val = 30;       /* ... allow extra time */
 597         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 598                 if (--val == 0) {
 599                         spin_unlock_irq (&ohci->lock);
 600                         ohci_err (ohci, "USB HC reset timed out!\n");
 601                         return -1;
 602                 }
 603                 udelay (1);
 604         }
 605
 606         /* now we're in the SUSPEND state ... must go OPERATIONAL
 607          * within 2msec else HC enters RESUME
 608          *
 609          * ... but some hardware won't init fmInterval "by the book"
 610          * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
 611          * this if we write fmInterval after we're OPERATIONAL.
 612          * Unclear about ALi, ServerWorks, and others ... this could
 613          * easily be a longstanding bug in chip init on Linux.
 614          */
 615         if (ohci->flags & OHCI_QUIRK_INITRESET) {
 616                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 617                 // flush those writes
 618                 (void) ohci_readl (ohci, &ohci->regs->control);
 619         }
 620
 621         /* Tell the controller where the control and bulk lists are
 622          * The lists are empty now. */
 623         ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
 624         ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
 625
 626         /* a reset clears this */
 627         ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
 628
 629         periodic_reinit (ohci);
 630
 631         /* some OHCI implementations are finicky about how they init.
 632          * bogus values here mean not even enumeration could work.
 633          */
 634         if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
 635                         || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
 636                 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
 637                         ohci->flags |= OHCI_QUIRK_INITRESET;
 638                         ohci_dbg (ohci, "enabling initreset quirk\n");
 639                         goto retry;
 640                 }
 641                 spin_unlock_irq (&ohci->lock);
 642                 ohci_err (ohci, "init err (%08x %04x)\n",
 643                         ohci_readl (ohci, &ohci->regs->fminterval),
 644                         ohci_readl (ohci, &ohci->regs->periodicstart));
 645                 return -EOVERFLOW;
 646         }
 647
 648         /* use rhsc irqs after hub_wq is allocated */
 649         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 650         hcd->uses_new_polling = 1;
 651
 652         /* start controller operations */
 653         ohci->hc_control &= OHCI_CTRL_RWC;
 654         ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
 655         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 656         ohci->rh_state = OHCI_RH_RUNNING;
 657
 658         /* wake on ConnectStatusChange, matching external hubs */
 659         ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
 660
 661         /* Choose the interrupts we care about now, others later on demand */
 662         mask = OHCI_INTR_INIT;
 663         ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
 664         ohci_writel (ohci, mask, &ohci->regs->intrenable);
 665
 666         /* handle root hub init quirks ... */
 667         val = roothub_a (ohci);
 668         /* Configure for per-port over-current protection by default */
 669         val &= ~RH_A_NOCP;
 670         val |= RH_A_OCPM;
 671         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
 672                 /* NSC 87560 and maybe others.
 673                  * Ganged power switching, no over-current protection.
 674                  */
 675                 val |= RH_A_NOCP;
 676                 val &= ~(RH_A_POTPGT | RH_A_NPS | RH_A_PSM | RH_A_OCPM);
 677         } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
 678                         (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
 679                 /* hub power always on; required for AMD-756 and some
 680                  * Mac platforms.
 681                  */
 682                 val |= RH_A_NPS;
 683         }
 684         ohci_writel(ohci, val, &ohci->regs->roothub.a);
 685
 686         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
 687         ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
 688                                                 &ohci->regs->roothub.b);
 689         // flush those writes
 690         (void) ohci_readl (ohci, &ohci->regs->control);
 691
 692         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 693         spin_unlock_irq (&ohci->lock);
 694
 695         // POTPGT delay is bits 24-31, in 2 ms units.
 696         mdelay ((val >> 23) & 0x1fe);
 697
 698         ohci_dump(ohci);
 699
 700         return 0;
 701 }
 702
 703 /* ohci_setup routine for generic controller initialization */
 704
 705 int ohci_setup(struct usb_hcd *hcd)
 706 {
 707         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 708
 709         ohci_hcd_init(ohci);
 710
 711         return ohci_init(ohci);
 712 }
 713 EXPORT_SYMBOL_GPL(ohci_setup);
 714
 715 /* ohci_start routine for generic controller start of all OHCI bus glue */
 716 static int ohci_start(struct usb_hcd *hcd)
 717 {
 718         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 719         int     ret;
 720
 721         ret = ohci_run(ohci);
 722         if (ret < 0) {
 723                 ohci_err(ohci, "can't start\n");
 724                 ohci_stop(hcd);
 725         }
 726         return ret;
 727 }
 728
 729 /*-------------------------------------------------------------------------*/
 730
 731 /*
 732  * Some OHCI controllers are known to lose track of completed TDs.  They
 733  * don't add the TDs to the hardware done queue, which means we never see
 734  * them as being completed.
 735  *
 736  * This watchdog routine checks for such problems.  Without some way to
 737  * tell when those TDs have completed, we would never take their EDs off
 738  * the unlink list.  As a result, URBs could never be dequeued and
 739  * endpoints could never be released.
 740  */
 741 static void io_watchdog_func(unsigned long _ohci)
 742 {
 743         struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
 744         bool            takeback_all_pending = false;
 745         u32             status;
 746         u32             head;
 747         struct ed       *ed;
 748         struct td       *td, *td_start, *td_next;
 749         unsigned        frame_no, prev_frame_no = IO_WATCHDOG_OFF;
 750         unsigned long   flags;
 751
 752         spin_lock_irqsave(&ohci->lock, flags);
 753
 754         /*
 755          * One way to lose track of completed TDs is if the controller
 756          * never writes back the done queue head.  If it hasn't been
 757          * written back since the last time this function ran and if it
 758          * was non-empty at that time, something is badly wrong with the
 759          * hardware.
 760          */
 761         status = ohci_readl(ohci, &ohci->regs->intrstatus);
 762         if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
 763                 if (ohci->prev_donehead) {
 764                         ohci_err(ohci, "HcDoneHead not written back; disabled\n");
 765  died:
 766                         usb_hc_died(ohci_to_hcd(ohci));
 767                         ohci_dump(ohci);
 768                         _ohci_shutdown(ohci_to_hcd(ohci));
 769                         goto done;
 770                 } else {
 771                         /* No write back because the done queue was empty */
 772                         takeback_all_pending = true;
 773                 }
 774         }
 775
 776         /* Check every ED which might have pending TDs */
 777         list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
 778                 if (ed->pending_td) {
 779                         if (takeback_all_pending ||
 780                                         OKAY_TO_TAKEBACK(ohci, ed)) {
 781                                 unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO);
 782
 783                                 ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
 784                                                 0x007f & tmp,
 785                                                 (0x000f & (tmp >> 7)) +
 786                                                         ((tmp & ED_IN) >> 5));
 787                                 add_to_done_list(ohci, ed->pending_td);
 788                         }
 789                 }
 790
 791                 /* Starting from the latest pending TD, */
 792                 td = ed->pending_td;
 793
 794                 /* or the last TD on the done list, */
 795                 if (!td) {
 796                         list_for_each_entry(td_next, &ed->td_list, td_list) {
 797                                 if (!td_next->next_dl_td)
 798                                         break;
 799                                 td = td_next;
 800                         }
 801                 }
 802
 803                 /* find the last TD processed by the controller. */
 804                 head = hc32_to_cpu(ohci, ACCESS_ONCE(ed->hwHeadP)) & TD_MASK;
 805                 td_start = td;
 806                 td_next = list_prepare_entry(td, &ed->td_list, td_list);
 807                 list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
 808                         if (head == (u32) td_next->td_dma)
 809                                 break;
 810                         td = td_next;   /* head pointer has passed this TD */
 811                 }
 812                 if (td != td_start) {
 813                         /*
 814                          * In case a WDH cycle is in progress, we will wait
 815                          * for the next two cycles to complete before assuming
 816                          * this TD will never get on the done queue.
 817                          */
 818                         ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
 819                         ed->pending_td = td;
 820                 }
 821         }
 822
 823         ohci_work(ohci);
 824
 825         if (ohci->rh_state == OHCI_RH_RUNNING) {
 826
 827                 /*
 828                  * Sometimes a controller just stops working.  We can tell
 829                  * by checking that the frame counter has advanced since
 830                  * the last time we ran.
 831                  *
 832                  * But be careful: Some controllers violate the spec by
 833                  * stopping their frame counter when no ports are active.
 834                  */
 835                 frame_no = ohci_frame_no(ohci);
 836                 if (frame_no == ohci->prev_frame_no) {
 837                         int             active_cnt = 0;
 838                         int             i;
 839                         unsigned        tmp;
 840
 841                         for (i = 0; i < ohci->num_ports; ++i) {
 842                                 tmp = roothub_portstatus(ohci, i);
 843                                 /* Enabled and not suspended? */
 844                                 if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
 845                                         ++active_cnt;
 846                         }
 847
 848                         if (active_cnt > 0) {
 849                                 ohci_err(ohci, "frame counter not updating; disabled\n");
 850                                 goto died;
 851                         }
 852                 }
 853                 if (!list_empty(&ohci->eds_in_use)) {
 854                         prev_frame_no = frame_no;
 855                         ohci->prev_wdh_cnt = ohci->wdh_cnt;
 856                         ohci->prev_donehead = ohci_readl(ohci,
 857                                         &ohci->regs->donehead);
 858                         mod_timer(&ohci->io_watchdog,
 859                                         jiffies + IO_WATCHDOG_DELAY);
 860                 }
 861         }
 862
 863  done:
 864         ohci->prev_frame_no = prev_frame_no;
 865         spin_unlock_irqrestore(&ohci->lock, flags);
 866 }
 867
 868 /* an interrupt happens */
 869
 870 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
 871 {
 872         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 873         struct ohci_regs __iomem *regs = ohci->regs;
 874         int                     ints;
 875
 876         /* Read interrupt status (and flush pending writes).  We ignore the
 877          * optimization of checking the LSB of hcca->done_head; it doesn't
 878          * work on all systems (edge triggering for OHCI can be a factor).
 879          */
 880         ints = ohci_readl(ohci, &regs->intrstatus);
 881
 882         /* Check for an all 1's result which is a typical consequence
 883          * of dead, unclocked, or unplugged (CardBus...) devices
 884          */
 885         if (ints == ~(u32)0) {
 886                 ohci->rh_state = OHCI_RH_HALTED;
 887                 ohci_dbg (ohci, "device removed!\n");
 888                 usb_hc_died(hcd);
 889                 return IRQ_HANDLED;
 890         }
 891
 892         /* We only care about interrupts that are enabled */
 893         ints &= ohci_readl(ohci, &regs->intrenable);
 894
 895         /* interrupt for some other device? */
 896         if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
 897                 return IRQ_NOTMINE;
 898
 899         if (ints & OHCI_INTR_UE) {
 900                 // e.g. due to PCI Master/Target Abort
 901                 if (quirk_nec(ohci)) {
 902                         /* Workaround for a silicon bug in some NEC chips used
 903                          * in Apple's PowerBooks. Adapted from Darwin code.
 904                          */
 905                         ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
 906
 907                         ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
 908
 909                         schedule_work (&ohci->nec_work);
 910                 } else {
 911                         ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
 912                         ohci->rh_state = OHCI_RH_HALTED;
 913                         usb_hc_died(hcd);
 914                 }
 915
 916                 ohci_dump(ohci);
 917                 ohci_usb_reset (ohci);
 918         }
 919
 920         if (ints & OHCI_INTR_RHSC) {
 921                 ohci_dbg(ohci, "rhsc\n");
 922                 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 923                 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
 924                                 &regs->intrstatus);
 925
 926                 /* NOTE: Vendors didn't always make the same implementation
 927                  * choices for RHSC.  Many followed the spec; RHSC triggers
 928                  * on an edge, like setting and maybe clearing a port status
 929                  * change bit.  With others it's level-triggered, active
 930                  * until hub_wq clears all the port status change bits.  We'll
 931                  * always disable it here and rely on polling until hub_wq
 932                  * re-enables it.
 933                  */
 934                 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
 935                 usb_hcd_poll_rh_status(hcd);
 936         }
 937
 938         /* For connect and disconnect events, we expect the controller
 939          * to turn on RHSC along with RD.  But for remote wakeup events
 940          * this might not happen.
 941          */
 942         else if (ints & OHCI_INTR_RD) {
 943                 ohci_dbg(ohci, "resume detect\n");
 944                 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
 945                 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 946                 if (ohci->autostop) {
 947                         spin_lock (&ohci->lock);
 948                         ohci_rh_resume (ohci);
 949                         spin_unlock (&ohci->lock);
 950                 } else
 951                         usb_hcd_resume_root_hub(hcd);
 952         }
 953
 954         spin_lock(&ohci->lock);
 955         if (ints & OHCI_INTR_WDH)
 956                 update_done_list(ohci);
 957
 958         /* could track INTR_SO to reduce available PCI/... bandwidth */
 959
 960         /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
 961          * when there's still unlinking to be done (next frame).
 962          */
 963         ohci_work(ohci);
 964         if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
 965                         && ohci->rh_state == OHCI_RH_RUNNING)
 966                 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
 967
 968         if (ohci->rh_state == OHCI_RH_RUNNING) {
 969                 ohci_writel (ohci, ints, &regs->intrstatus);
 970                 if (ints & OHCI_INTR_WDH)
 971                         ++ohci->wdh_cnt;
 972
 973                 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
 974                 // flush those writes
 975                 (void) ohci_readl (ohci, &ohci->regs->control);
 976         }
 977         spin_unlock(&ohci->lock);
 978
 979         return IRQ_HANDLED;
 980 }
 981
 982 /*-------------------------------------------------------------------------*/
 983
 984 static void ohci_stop (struct usb_hcd *hcd)
 985 {
 986         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 987
 988         ohci_dump(ohci);
 989
 990         if (quirk_nec(ohci))
 991                 flush_work(&ohci->nec_work);
 992         del_timer_sync(&ohci->io_watchdog);
 993         ohci->prev_frame_no = IO_WATCHDOG_OFF;
 994
 995         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 996         ohci_usb_reset(ohci);
 997         free_irq(hcd->irq, hcd);
 998         hcd->irq = 0;
 999
1000         if (quirk_amdiso(ohci))
1001                 usb_amd_dev_put();
1002
1003         remove_debug_files (ohci);
1004         ohci_mem_cleanup (ohci);
1005         if (ohci->hcca) {
1006                 dma_free_coherent (hcd->self.controller,
1007                                 sizeof *ohci->hcca,
1008                                 ohci->hcca, ohci->hcca_dma);
1009                 ohci->hcca = NULL;
1010                 ohci->hcca_dma = 0;
1011         }
1012 }
1013
1014 /*-------------------------------------------------------------------------*/
1015
1016 #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1017
1018 /* must not be called from interrupt context */
1019 int ohci_restart(struct ohci_hcd *ohci)
1020 {
1021         int temp;
1022         int i;
1023         struct urb_priv *priv;
1024
1025         ohci_init(ohci);
1026         spin_lock_irq(&ohci->lock);
1027         ohci->rh_state = OHCI_RH_HALTED;
1028
1029         /* Recycle any "live" eds/tds (and urbs). */
1030         if (!list_empty (&ohci->pending))
1031                 ohci_dbg(ohci, "abort schedule...\n");
1032         list_for_each_entry (priv, &ohci->pending, pending) {
1033                 struct urb      *urb = priv->td[0]->urb;
1034                 struct ed       *ed = priv->ed;
1035
1036                 switch (ed->state) {
1037                 case ED_OPER:
1038                         ed->state = ED_UNLINK;
1039                         ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1040                         ed_deschedule (ohci, ed);
1041
1042                         ed->ed_next = ohci->ed_rm_list;
1043                         ed->ed_prev = NULL;
1044                         ohci->ed_rm_list = ed;
1045                         /* FALLTHROUGH */
1046                 case ED_UNLINK:
1047                         break;
1048                 default:
1049                         ohci_dbg(ohci, "bogus ed %p state %d\n",
1050                                         ed, ed->state);
1051                 }
1052
1053                 if (!urb->unlinked)
1054                         urb->unlinked = -ESHUTDOWN;
1055         }
1056         ohci_work(ohci);
1057         spin_unlock_irq(&ohci->lock);
1058
1059         /* paranoia, in case that didn't work: */
1060
1061         /* empty the interrupt branches */
1062         for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1063         for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1064
1065         /* no EDs to remove */
1066         ohci->ed_rm_list = NULL;
1067
1068         /* empty control and bulk lists */
1069         ohci->ed_controltail = NULL;
1070         ohci->ed_bulktail    = NULL;
1071
1072         if ((temp = ohci_run (ohci)) < 0) {
1073                 ohci_err (ohci, "can't restart, %d\n", temp);
1074                 return temp;
1075         }
1076         ohci_dbg(ohci, "restart complete\n");
1077         return 0;
1078 }
1079 EXPORT_SYMBOL_GPL(ohci_restart);
1080
1081 #endif
1082
1083 #ifdef CONFIG_PM
1084
1085 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1086 {
1087         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1088         unsigned long   flags;
1089         int             rc = 0;
1090
1091         /* Disable irq emission and mark HW unaccessible. Use
1092          * the spinlock to properly synchronize with possible pending
1093          * RH suspend or resume activity.
1094          */
1095         spin_lock_irqsave (&ohci->lock, flags);
1096         ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1097         (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1098
1099         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1100         spin_unlock_irqrestore (&ohci->lock, flags);
1101
1102         synchronize_irq(hcd->irq);
1103
1104         if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1105                 ohci_resume(hcd, false);
1106                 rc = -EBUSY;
1107         }
1108         return rc;
1109 }
1110 EXPORT_SYMBOL_GPL(ohci_suspend);
1111
1112
1113 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1114 {
1115         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
1116         int                     port;
1117         bool                    need_reinit = false;
1118
1119         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1120
1121         /* Make sure resume from hibernation re-enumerates everything */
1122         if (hibernated)
1123                 ohci_usb_reset(ohci);
1124
1125         /* See if the controller is already running or has been reset */
1126         ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1127         if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1128                 need_reinit = true;
1129         } else {
1130                 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1131                 case OHCI_USB_OPER:
1132                 case OHCI_USB_RESET:
1133                         need_reinit = true;
1134                 }
1135         }
1136
1137         /* If needed, reinitialize and suspend the root hub */
1138         if (need_reinit) {
1139                 spin_lock_irq(&ohci->lock);
1140                 ohci_rh_resume(ohci);
1141                 ohci_rh_suspend(ohci, 0);
1142                 spin_unlock_irq(&ohci->lock);
1143         }
1144
1145         /* Normally just turn on port power and enable interrupts */
1146         else {
1147                 ohci_dbg(ohci, "powerup ports\n");
1148                 for (port = 0; port < ohci->num_ports; port++)
1149                         ohci_writel(ohci, RH_PS_PPS,
1150                                         &ohci->regs->roothub.portstatus[port]);
1151
1152                 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1153                 ohci_readl(ohci, &ohci->regs->intrenable);
1154                 msleep(20);
1155         }
1156
1157         usb_hcd_resume_root_hub(hcd);
1158
1159         return 0;
1160 }
1161 EXPORT_SYMBOL_GPL(ohci_resume);
1162
1163 #endif
1164
1165 /*-------------------------------------------------------------------------*/
1166
1167 /*
1168  * Generic structure: This gets copied for platform drivers so that
1169  * individual entries can be overridden as needed.
1170  */
1171
1172 static const struct hc_driver ohci_hc_driver = {
1173         .description =          hcd_name,
1174         .product_desc =         "OHCI Host Controller",
1175         .hcd_priv_size =        sizeof(struct ohci_hcd),
1176
1177         /*
1178          * generic hardware linkage
1179         */
1180         .irq =                  ohci_irq,
1181         .flags =                HCD_MEMORY | HCD_USB11,
1182
1183         /*
1184         * basic lifecycle operations
1185         */
1186         .reset =                ohci_setup,
1187         .start =                ohci_start,
1188         .stop =                 ohci_stop,
1189         .shutdown =             ohci_shutdown,
1190
1191         /*
1192          * managing i/o requests and associated device resources
1193         */
1194         .urb_enqueue =          ohci_urb_enqueue,
1195         .urb_dequeue =          ohci_urb_dequeue,
1196         .endpoint_disable =     ohci_endpoint_disable,
1197
1198         /*
1199         * scheduling support
1200         */
1201         .get_frame_number =     ohci_get_frame,
1202
1203         /*
1204         * root hub support
1205         */
1206         .hub_status_data =      ohci_hub_status_data,
1207         .hub_control =          ohci_hub_control,
1208 #ifdef CONFIG_PM
1209         .bus_suspend =          ohci_bus_suspend,
1210         .bus_resume =           ohci_bus_resume,
1211 #endif
1212         .start_port_reset =     ohci_start_port_reset,
1213 };
1214
1215 void ohci_init_driver(struct hc_driver *drv,
1216                 const struct ohci_driver_overrides *over)
1217 {
1218         /* Copy the generic table to drv and then apply the overrides */
1219         *drv = ohci_hc_driver;
1220
1221         if (over) {
1222                 drv->product_desc = over->product_desc;
1223                 drv->hcd_priv_size += over->extra_priv_size;
1224                 if (over->reset)
1225                         drv->reset = over->reset;
1226         }
1227 }
1228 EXPORT_SYMBOL_GPL(ohci_init_driver);
1229
1230 /*-------------------------------------------------------------------------*/
1231
1232 MODULE_AUTHOR (DRIVER_AUTHOR);
1233 MODULE_DESCRIPTION(DRIVER_DESC);
1234 MODULE_LICENSE ("GPL");
1235
1236 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1237 #include "ohci-sa1111.c"
1238 #define SA1111_DRIVER           ohci_hcd_sa1111_driver
1239 #endif
1240
1241 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1242 #include "ohci-ppc-of.c"
1243 #define OF_PLATFORM_DRIVER      ohci_hcd_ppc_of_driver
1244 #endif
1245
1246 #ifdef CONFIG_PPC_PS3
1247 #include "ohci-ps3.c"
1248 #define PS3_SYSTEM_BUS_DRIVER   ps3_ohci_driver
1249 #endif
1250
1251 #ifdef CONFIG_MFD_SM501
1252 #include "ohci-sm501.c"
1253 #define SM501_OHCI_DRIVER       ohci_hcd_sm501_driver
1254 #endif
1255
1256 #ifdef CONFIG_MFD_TC6393XB
1257 #include "ohci-tmio.c"
1258 #define TMIO_OHCI_DRIVER        ohci_hcd_tmio_driver
1259 #endif
1260
1261 #ifdef CONFIG_TILE_USB
1262 #include "ohci-tilegx.c"
1263 #define PLATFORM_DRIVER         ohci_hcd_tilegx_driver
1264 #endif
1265
1266 static int __init ohci_hcd_mod_init(void)
1267 {
1268         int retval = 0;
1269
1270         if (usb_disabled())
1271                 return -ENODEV;
1272
1273         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1274         pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name,
1275                 sizeof (struct ed), sizeof (struct td));
1276         set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1277
1278         ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1279         if (!ohci_debug_root) {
1280                 retval = -ENOENT;
1281                 goto error_debug;
1282         }
1283
1284 #ifdef PS3_SYSTEM_BUS_DRIVER
1285         retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1286         if (retval < 0)
1287                 goto error_ps3;
1288 #endif
1289
1290 #ifdef PLATFORM_DRIVER
1291         retval = platform_driver_register(&PLATFORM_DRIVER);
1292         if (retval < 0)
1293                 goto error_platform;
1294 #endif
1295
1296 #ifdef OF_PLATFORM_DRIVER
1297         retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1298         if (retval < 0)
1299                 goto error_of_platform;
1300 #endif
1301
1302 #ifdef SA1111_DRIVER
1303         retval = sa1111_driver_register(&SA1111_DRIVER);
1304         if (retval < 0)
1305                 goto error_sa1111;
1306 #endif
1307
1308 #ifdef SM501_OHCI_DRIVER
1309         retval = platform_driver_register(&SM501_OHCI_DRIVER);
1310         if (retval < 0)
1311                 goto error_sm501;
1312 #endif
1313
1314 #ifdef TMIO_OHCI_DRIVER
1315         retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1316         if (retval < 0)
1317                 goto error_tmio;
1318 #endif
1319
1320         return retval;
1321
1322         /* Error path */
1323 #ifdef TMIO_OHCI_DRIVER
1324         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1325  error_tmio:
1326 #endif
1327 #ifdef SM501_OHCI_DRIVER
1328         platform_driver_unregister(&SM501_OHCI_DRIVER);
1329  error_sm501:
1330 #endif
1331 #ifdef SA1111_DRIVER
1332         sa1111_driver_unregister(&SA1111_DRIVER);
1333  error_sa1111:
1334 #endif
1335 #ifdef OF_PLATFORM_DRIVER
1336         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1337  error_of_platform:
1338 #endif
1339 #ifdef PLATFORM_DRIVER
1340         platform_driver_unregister(&PLATFORM_DRIVER);
1341  error_platform:
1342 #endif
1343 #ifdef PS3_SYSTEM_BUS_DRIVER
1344         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1345  error_ps3:
1346 #endif
1347         debugfs_remove(ohci_debug_root);
1348         ohci_debug_root = NULL;
1349  error_debug:
1350
1351         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1352         return retval;
1353 }
1354 module_init(ohci_hcd_mod_init);
1355
1356 static void __exit ohci_hcd_mod_exit(void)
1357 {
1358 #ifdef TMIO_OHCI_DRIVER
1359         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1360 #endif
1361 #ifdef SM501_OHCI_DRIVER
1362         platform_driver_unregister(&SM501_OHCI_DRIVER);
1363 #endif
1364 #ifdef SA1111_DRIVER
1365         sa1111_driver_unregister(&SA1111_DRIVER);
1366 #endif
1367 #ifdef OF_PLATFORM_DRIVER
1368         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1369 #endif
1370 #ifdef PLATFORM_DRIVER
1371         platform_driver_unregister(&PLATFORM_DRIVER);
1372 #endif
1373 #ifdef PS3_SYSTEM_BUS_DRIVER
1374         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1375 #endif
1376         debugfs_remove(ohci_debug_root);
1377         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1378 }
1379 module_exit(ohci_hcd_mod_exit);
1380