drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <asm/unaligned.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  32                          PORT_RC | PORT_PLC | PORT_PE)
  33
  34 /* USB 3 BOS descriptor and a capability descriptors, combined.
  35  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  36  */
  37 static u8 usb_bos_descriptor [] = {
  38         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  39         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  40         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  41         0x1,                            /*  __u8 bNumDeviceCaps */
  42         /* First device capability, SuperSpeed */
  43         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  44         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  45         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  46         0x00,                           /* bmAttributes, LTM off by default */
  47         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  48         0x03,                           /* bFunctionalitySupport,
  49                                            USB 3.0 speed only */
  50         0x00,                           /* bU1DevExitLat, set later. */
  51         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  52         /* Second device capability, SuperSpeedPlus */
  53         0x0c,                           /* bLength 12, will be adjusted later */
  54         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  55         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  56         0x00,                           /* bReserved 0 */
  57         0x00, 0x00, 0x00, 0x00,         /* bmAttributes, get from xhci psic */
  58         0x00, 0x00,                     /* wFunctionalitySupport */
  59         0x00, 0x00,                     /* wReserved 0 */
  60         /* Sublink Speed Attributes are added in xhci_create_usb3_bos_desc() */
  61 };
  62
  63 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  64                                      u16 wLength)
  65 {
  66         int i, ssa_count;
  67         u32 temp;
  68         u16 desc_size, ssp_cap_size, ssa_size = 0;
  69         bool usb3_1 = false;
  70
  71         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  72         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  73
  74         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  75         if (xhci->usb3_rhub.min_rev >= 0x01 && xhci->usb3_rhub.psi_uid_count) {
  76                 /* two SSA entries for each unique PSI ID, one RX and one TX */
  77                 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  78                 ssa_size = ssa_count * sizeof(u32);
  79                 desc_size += ssp_cap_size;
  80                 usb3_1 = true;
  81         }
  82         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  83
  84         if (usb3_1) {
  85                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  86                 buf[4] += 1;
  87                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  88         }
  89
  90         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  91                 return wLength;
  92
  93         /* Indicate whether the host has LTM support. */
  94         temp = readl(&xhci->cap_regs->hcc_params);
  95         if (HCC_LTC(temp))
  96                 buf[8] |= USB_LTM_SUPPORT;
  97
  98         /* Set the U1 and U2 exit latencies. */
  99         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 100                 temp = readl(&xhci->cap_regs->hcs_params3);
 101                 buf[12] = HCS_U1_LATENCY(temp);
 102                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 103         }
 104
 105         if (usb3_1) {
 106                 u32 ssp_cap_base, bm_attrib, psi;
 107                 int offset;
 108
 109                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 110
 111                 if (wLength < desc_size)
 112                         return wLength;
 113                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 114
 115                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 116                 bm_attrib = (ssa_count - 1) & 0x1f;
 117                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 118                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 119
 120                 if (wLength < desc_size + ssa_size)
 121                         return wLength;
 122                 /*
 123                  * Create the Sublink Speed Attributes (SSA) array.
 124                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 125                  * but link type bits 7:6 differ for values 01b and 10b.
 126                  * xhci has also only one PSI entry for a symmetric link when
 127                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 128                  */
 129                 offset = desc_size;
 130                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 131                         psi = xhci->usb3_rhub.psi[i];
 132                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 133                         if ((psi & PLT_MASK) == PLT_SYM) {
 134                         /* Symmetric, create SSA RX and TX from one PSI entry */
 135                                 put_unaligned_le32(psi, &buf[offset]);
 136                                 psi |= 1 << 7;  /* turn entry to TX */
 137                                 offset += 4;
 138                                 if (offset >= desc_size + ssa_size)
 139                                         return desc_size + ssa_size;
 140                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 141                                 /* Asymetric RX, flip bits 7:6 for SSA */
 142                                 psi ^= PLT_MASK;
 143                         }
 144                         put_unaligned_le32(psi, &buf[offset]);
 145                         offset += 4;
 146                         if (offset >= desc_size + ssa_size)
 147                                 return desc_size + ssa_size;
 148                 }
 149         }
 150         /* ssa_size is 0 for other than usb 3.1 hosts */
 151         return desc_size + ssa_size;
 152 }
 153
 154 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 155                 struct usb_hub_descriptor *desc, int ports)
 156 {
 157         u16 temp;
 158
 159         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 160         desc->bHubContrCurrent = 0;
 161
 162         desc->bNbrPorts = ports;
 163         temp = 0;
 164         /* Bits 1:0 - support per-port power switching, or power always on */
 165         if (HCC_PPC(xhci->hcc_params))
 166                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 167         else
 168                 temp |= HUB_CHAR_NO_LPSM;
 169         /* Bit  2 - root hubs are not part of a compound device */
 170         /* Bits 4:3 - individual port over current protection */
 171         temp |= HUB_CHAR_INDV_PORT_OCPM;
 172         /* Bits 6:5 - no TTs in root ports */
 173         /* Bit  7 - no port indicators */
 174         desc->wHubCharacteristics = cpu_to_le16(temp);
 175 }
 176
 177 /* Fill in the USB 2.0 roothub descriptor */
 178 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 179                 struct usb_hub_descriptor *desc)
 180 {
 181         int ports;
 182         u16 temp;
 183         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 184         u32 portsc;
 185         unsigned int i;
 186
 187         ports = xhci->num_usb2_ports;
 188
 189         xhci_common_hub_descriptor(xhci, desc, ports);
 190         desc->bDescriptorType = USB_DT_HUB;
 191         temp = 1 + (ports / 8);
 192         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 193
 194         /* The Device Removable bits are reported on a byte granularity.
 195          * If the port doesn't exist within that byte, the bit is set to 0.
 196          */
 197         memset(port_removable, 0, sizeof(port_removable));
 198         for (i = 0; i < ports; i++) {
 199                 portsc = readl(xhci->usb2_ports[i]);
 200                 /* If a device is removable, PORTSC reports a 0, same as in the
 201                  * hub descriptor DeviceRemovable bits.
 202                  */
 203                 if (portsc & PORT_DEV_REMOVE)
 204                         /* This math is hairy because bit 0 of DeviceRemovable
 205                          * is reserved, and bit 1 is for port 1, etc.
 206                          */
 207                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 208         }
 209
 210         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 211          * ports on it.  The USB 2.0 specification says that there are two
 212          * variable length fields at the end of the hub descriptor:
 213          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 214          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 215          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 216          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 217          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 218          * set of ports that actually exist.
 219          */
 220         memset(desc->u.hs.DeviceRemovable, 0xff,
 221                         sizeof(desc->u.hs.DeviceRemovable));
 222         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 223                         sizeof(desc->u.hs.PortPwrCtrlMask));
 224
 225         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 226                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 227                                 sizeof(__u8));
 228 }
 229
 230 /* Fill in the USB 3.0 roothub descriptor */
 231 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 232                 struct usb_hub_descriptor *desc)
 233 {
 234         int ports;
 235         u16 port_removable;
 236         u32 portsc;
 237         unsigned int i;
 238
 239         ports = xhci->num_usb3_ports;
 240         xhci_common_hub_descriptor(xhci, desc, ports);
 241         desc->bDescriptorType = USB_DT_SS_HUB;
 242         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 243
 244         /* header decode latency should be zero for roothubs,
 245          * see section 4.23.5.2.
 246          */
 247         desc->u.ss.bHubHdrDecLat = 0;
 248         desc->u.ss.wHubDelay = 0;
 249
 250         port_removable = 0;
 251         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 252         for (i = 0; i < ports; i++) {
 253                 portsc = readl(xhci->usb3_ports[i]);
 254                 if (portsc & PORT_DEV_REMOVE)
 255                         port_removable |= 1 << (i + 1);
 256         }
 257
 258         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 259 }
 260
 261 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 262                 struct usb_hub_descriptor *desc)
 263 {
 264
 265         if (hcd->speed >= HCD_USB3)
 266                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 267         else
 268                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 269
 270 }
 271
 272 static unsigned int xhci_port_speed(unsigned int port_status)
 273 {
 274         if (DEV_LOWSPEED(port_status))
 275                 return USB_PORT_STAT_LOW_SPEED;
 276         if (DEV_HIGHSPEED(port_status))
 277                 return USB_PORT_STAT_HIGH_SPEED;
 278         /*
 279          * FIXME: Yes, we should check for full speed, but the core uses that as
 280          * a default in portspeed() in usb/core/hub.c (which is the only place
 281          * USB_PORT_STAT_*_SPEED is used).
 282          */
 283         return 0;
 284 }
 285
 286 /*
 287  * These bits are Read Only (RO) and should be saved and written to the
 288  * registers: 0, 3, 10:13, 30
 289  * connect status, over-current status, port speed, and device removable.
 290  * connect status and port speed are also sticky - meaning they're in
 291  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 292  */
 293 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 294 /*
 295  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 296  * bits 5:8, 9, 14:15, 25:27
 297  * link state, port power, port indicator state, "wake on" enable state
 298  */
 299 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 300 /*
 301  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 302  * bit 4 (port reset)
 303  */
 304 #define XHCI_PORT_RW1S  ((1<<4))
 305 /*
 306  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 307  * bits 1, 17, 18, 19, 20, 21, 22, 23
 308  * port enable/disable, and
 309  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 310  * over-current, reset, link state, and L1 change
 311  */
 312 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 313 /*
 314  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 315  * latched in
 316  */
 317 #define XHCI_PORT_RW    ((1<<16))
 318 /*
 319  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 320  * bits 2, 24, 28:31
 321  */
 322 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 323
 324 /*
 325  * Given a port state, this function returns a value that would result in the
 326  * port being in the same state, if the value was written to the port status
 327  * control register.
 328  * Save Read Only (RO) bits and save read/write bits where
 329  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 330  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 331  */
 332 u32 xhci_port_state_to_neutral(u32 state)
 333 {
 334         /* Save read-only status and port state */
 335         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 336 }
 337
 338 /*
 339  * find slot id based on port number.
 340  * @port: The one-based port number from one of the two split roothubs.
 341  */
 342 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 343                 u16 port)
 344 {
 345         int slot_id;
 346         int i;
 347         enum usb_device_speed speed;
 348
 349         slot_id = 0;
 350         for (i = 0; i < MAX_HC_SLOTS; i++) {
 351                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 352                         continue;
 353                 speed = xhci->devs[i]->udev->speed;
 354                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 355                                 && xhci->devs[i]->fake_port == port) {
 356                         slot_id = i;
 357                         break;
 358                 }
 359         }
 360
 361         return slot_id;
 362 }
 363
 364 /*
 365  * Stop device
 366  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 367  * to complete.
 368  * suspend will set to 1, if suspend bit need to set in command.
 369  */
 370 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 371 {
 372         struct xhci_virt_device *virt_dev;
 373         struct xhci_command *cmd;
 374         unsigned long flags;
 375         int ret;
 376         int i;
 377
 378         ret = 0;
 379         virt_dev = xhci->devs[slot_id];
 380         if (!virt_dev)
 381                 return -ENODEV;
 382
 383         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 384         if (!cmd) {
 385                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 386                 return -ENOMEM;
 387         }
 388
 389         spin_lock_irqsave(&xhci->lock, flags);
 390         for (i = LAST_EP_INDEX; i > 0; i--) {
 391                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 392                         struct xhci_command *command;
 393                         command = xhci_alloc_command(xhci, false, false,
 394                                                      GFP_NOWAIT);
 395                         if (!command) {
 396                                 spin_unlock_irqrestore(&xhci->lock, flags);
 397                                 ret = -ENOMEM;
 398                                 goto cmd_cleanup;
 399                         }
 400
 401                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 402                                                        i, suspend);
 403                         if (ret) {
 404                                 spin_unlock_irqrestore(&xhci->lock, flags);
 405                                 xhci_free_command(xhci, command);
 406                                 goto cmd_cleanup;
 407                         }
 408                 }
 409         }
 410         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 411         if (ret) {
 412                 spin_unlock_irqrestore(&xhci->lock, flags);
 413                 goto cmd_cleanup;
 414         }
 415
 416         xhci_ring_cmd_db(xhci);
 417         spin_unlock_irqrestore(&xhci->lock, flags);
 418
 419         /* Wait for last stop endpoint command to finish */
 420         wait_for_completion(cmd->completion);
 421
 422         if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
 423                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 424                 ret = -ETIME;
 425         }
 426
 427 cmd_cleanup:
 428         xhci_free_command(xhci, cmd);
 429         return ret;
 430 }
 431
 432 /*
 433  * Ring device, it rings the all doorbells unconditionally.
 434  */
 435 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 436 {
 437         int i, s;
 438         struct xhci_virt_ep *ep;
 439
 440         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 441                 ep = &xhci->devs[slot_id]->eps[i];
 442
 443                 if (ep->ep_state & EP_HAS_STREAMS) {
 444                         for (s = 1; s < ep->stream_info->num_streams; s++)
 445                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 446                 } else if (ep->ring && ep->ring->dequeue) {
 447                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 448                 }
 449         }
 450
 451         return;
 452 }
 453
 454 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 455                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 456 {
 457         /* Don't allow the USB core to disable SuperSpeed ports. */
 458         if (hcd->speed >= HCD_USB3) {
 459                 xhci_dbg(xhci, "Ignoring request to disable "
 460                                 "SuperSpeed port.\n");
 461                 return;
 462         }
 463
 464         /* Write 1 to disable the port */
 465         writel(port_status | PORT_PE, addr);
 466         port_status = readl(addr);
 467         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 468                         wIndex, port_status);
 469 }
 470
 471 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 472                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 473 {
 474         char *port_change_bit;
 475         u32 status;
 476
 477         switch (wValue) {
 478         case USB_PORT_FEAT_C_RESET:
 479                 status = PORT_RC;
 480                 port_change_bit = "reset";
 481                 break;
 482         case USB_PORT_FEAT_C_BH_PORT_RESET:
 483                 status = PORT_WRC;
 484                 port_change_bit = "warm(BH) reset";
 485                 break;
 486         case USB_PORT_FEAT_C_CONNECTION:
 487                 status = PORT_CSC;
 488                 port_change_bit = "connect";
 489                 break;
 490         case USB_PORT_FEAT_C_OVER_CURRENT:
 491                 status = PORT_OCC;
 492                 port_change_bit = "over-current";
 493                 break;
 494         case USB_PORT_FEAT_C_ENABLE:
 495                 status = PORT_PEC;
 496                 port_change_bit = "enable/disable";
 497                 break;
 498         case USB_PORT_FEAT_C_SUSPEND:
 499                 status = PORT_PLC;
 500                 port_change_bit = "suspend/resume";
 501                 break;
 502         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 503                 status = PORT_PLC;
 504                 port_change_bit = "link state";
 505                 break;
 506         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 507                 status = PORT_CEC;
 508                 port_change_bit = "config error";
 509                 break;
 510         default:
 511                 /* Should never happen */
 512                 return;
 513         }
 514         /* Change bits are all write 1 to clear */
 515         writel(port_status | status, addr);
 516         port_status = readl(addr);
 517         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 518                         port_change_bit, wIndex, port_status);
 519 }
 520
 521 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 522 {
 523         int max_ports;
 524         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 525
 526         if (hcd->speed >= HCD_USB3) {
 527                 max_ports = xhci->num_usb3_ports;
 528                 *port_array = xhci->usb3_ports;
 529         } else {
 530                 max_ports = xhci->num_usb2_ports;
 531                 *port_array = xhci->usb2_ports;
 532         }
 533
 534         return max_ports;
 535 }
 536
 537 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 538                                 int port_id, u32 link_state)
 539 {
 540         u32 temp;
 541
 542         temp = readl(port_array[port_id]);
 543         temp = xhci_port_state_to_neutral(temp);
 544         temp &= ~PORT_PLS_MASK;
 545         temp |= PORT_LINK_STROBE | link_state;
 546         writel(temp, port_array[port_id]);
 547 }
 548
 549 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 550                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 551 {
 552         u32 temp;
 553
 554         temp = readl(port_array[port_id]);
 555         temp = xhci_port_state_to_neutral(temp);
 556
 557         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 558                 temp |= PORT_WKCONN_E;
 559         else
 560                 temp &= ~PORT_WKCONN_E;
 561
 562         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 563                 temp |= PORT_WKDISC_E;
 564         else
 565                 temp &= ~PORT_WKDISC_E;
 566
 567         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 568                 temp |= PORT_WKOC_E;
 569         else
 570                 temp &= ~PORT_WKOC_E;
 571
 572         writel(temp, port_array[port_id]);
 573 }
 574
 575 /* Test and clear port RWC bit */
 576 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 577                                 int port_id, u32 port_bit)
 578 {
 579         u32 temp;
 580
 581         temp = readl(port_array[port_id]);
 582         if (temp & port_bit) {
 583                 temp = xhci_port_state_to_neutral(temp);
 584                 temp |= port_bit;
 585                 writel(temp, port_array[port_id]);
 586         }
 587 }
 588
 589 /* Updates Link Status for USB 2.1 port */
 590 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 591 {
 592         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 593                 *status |= USB_PORT_STAT_L1;
 594 }
 595
 596 /* Updates Link Status for super Speed port */
 597 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 598                 u32 *status, u32 status_reg)
 599 {
 600         u32 pls = status_reg & PORT_PLS_MASK;
 601
 602         /* When the CAS bit is set then warm reset
 603          * should be performed on port
 604          */
 605         if (status_reg & PORT_CAS) {
 606                 /* The CAS bit can be set while the port is
 607                  * in any link state.
 608                  * Only roothubs have CAS bit, so we
 609                  * pretend to be in compliance mode
 610                  * unless we're already in compliance
 611                  * or the inactive state.
 612                  */
 613                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 614                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 615                         pls = USB_SS_PORT_LS_COMP_MOD;
 616                 }
 617                 /* Return also connection bit -
 618                  * hub state machine resets port
 619                  * when this bit is set.
 620                  */
 621                 pls |= USB_PORT_STAT_CONNECTION;
 622         } else {
 623                 /*
 624                  * Resume state is an xHCI internal state.  Do not report it to
 625                  * usb core, instead, pretend to be U3, thus usb core knows
 626                  * it's not ready for transfer.
 627                  */
 628                 if (pls == XDEV_RESUME) {
 629                         *status |= USB_SS_PORT_LS_U3;
 630                         return;
 631                 }
 632
 633                 /*
 634                  * If CAS bit isn't set but the Port is already at
 635                  * Compliance Mode, fake a connection so the USB core
 636                  * notices the Compliance state and resets the port.
 637                  * This resolves an issue generated by the SN65LVPE502CP
 638                  * in which sometimes the port enters compliance mode
 639                  * caused by a delay on the host-device negotiation.
 640                  */
 641                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 642                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 643                         pls |= USB_PORT_STAT_CONNECTION;
 644         }
 645
 646         /* update status field */
 647         *status |= pls;
 648 }
 649
 650 /*
 651  * Function for Compliance Mode Quirk.
 652  *
 653  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 654  * the compliance mode timer is deleted. A port won't enter
 655  * compliance mode if it has previously entered U0.
 656  */
 657 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 658                                     u16 wIndex)
 659 {
 660         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 661         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 662
 663         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 664                 return;
 665
 666         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 667                 xhci->port_status_u0 |= 1 << wIndex;
 668                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 669                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 670                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 671                                 "All USB3 ports have entered U0 already!");
 672                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 673                                 "Compliance Mode Recovery Timer Deleted.");
 674                 }
 675         }
 676 }
 677
 678 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 679 {
 680         u32 ext_stat = 0;
 681         int speed_id;
 682
 683         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 684         speed_id = DEV_PORT_SPEED(raw_port_status);
 685         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 686         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 687
 688         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 689         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 690
 691         return ext_stat;
 692 }
 693
 694 /*
 695  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 696  * 3.0 hubs use.
 697  *
 698  * Possible side effects:
 699  *  - Mark a port as being done with device resume,
 700  *    and ring the endpoint doorbells.
 701  *  - Stop the Synopsys redriver Compliance Mode polling.
 702  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 703  */
 704 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 705                 struct xhci_bus_state *bus_state,
 706                 __le32 __iomem **port_array,
 707                 u16 wIndex, u32 raw_port_status,
 708                 unsigned long *flags)
 709         __releases(&xhci->lock)
 710         __acquires(&xhci->lock)
 711 {
 712         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 713         u32 status = 0;
 714         int slot_id;
 715
 716         /* wPortChange bits */
 717         if (raw_port_status & PORT_CSC)
 718                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 719         if (raw_port_status & PORT_PEC)
 720                 status |= USB_PORT_STAT_C_ENABLE << 16;
 721         if ((raw_port_status & PORT_OCC))
 722                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 723         if ((raw_port_status & PORT_RC))
 724                 status |= USB_PORT_STAT_C_RESET << 16;
 725         /* USB3.0 only */
 726         if (hcd->speed >= HCD_USB3) {
 727                 /* Port link change with port in resume state should not be
 728                  * reported to usbcore, as this is an internal state to be
 729                  * handled by xhci driver. Reporting PLC to usbcore may
 730                  * cause usbcore clearing PLC first and port change event
 731                  * irq won't be generated.
 732                  */
 733                 if ((raw_port_status & PORT_PLC) &&
 734                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 735                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 736                 if ((raw_port_status & PORT_WRC))
 737                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 738                 if ((raw_port_status & PORT_CEC))
 739                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 740
 741                 /* USB3 remote wake resume signaling completed */
 742                 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
 743                     (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
 744                     (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
 745                         bus_state->port_remote_wakeup &= ~(1 << wIndex);
 746                         usb_hcd_end_port_resume(&hcd->self, wIndex);
 747                 }
 748         }
 749
 750         if (hcd->speed < HCD_USB3) {
 751                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 752                                 && (raw_port_status & PORT_POWER))
 753                         status |= USB_PORT_STAT_SUSPEND;
 754         }
 755         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 756                 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
 757                 if ((raw_port_status & PORT_RESET) ||
 758                                 !(raw_port_status & PORT_PE))
 759                         return 0xffffffff;
 760                 /* did port event handler already start resume timing? */
 761                 if (!bus_state->resume_done[wIndex]) {
 762                         /* If not, maybe we are in a host initated resume? */
 763                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 764                                 /* Host initated resume doesn't time the resume
 765                                  * signalling using resume_done[].
 766                                  * It manually sets RESUME state, sleeps 20ms
 767                                  * and sets U0 state. This should probably be
 768                                  * changed, but not right now.
 769                                  */
 770                         } else {
 771                                 /* port resume was discovered now and here,
 772                                  * start resume timing
 773                                  */
 774                                 unsigned long timeout = jiffies +
 775                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 776
 777                                 set_bit(wIndex, &bus_state->resuming_ports);
 778                                 bus_state->resume_done[wIndex] = timeout;
 779                                 mod_timer(&hcd->rh_timer, timeout);
 780                         }
 781                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 782                 } else if (time_after_eq(jiffies,
 783                                          bus_state->resume_done[wIndex])) {
 784                         int time_left;
 785
 786                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 787                                         wIndex + 1);
 788                         bus_state->resume_done[wIndex] = 0;
 789                         clear_bit(wIndex, &bus_state->resuming_ports);
 790
 791                         set_bit(wIndex, &bus_state->rexit_ports);
 792
 793                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 794                                                 PORT_PLC);
 795                         xhci_set_link_state(xhci, port_array, wIndex,
 796                                         XDEV_U0);
 797
 798                         spin_unlock_irqrestore(&xhci->lock, *flags);
 799                         time_left = wait_for_completion_timeout(
 800                                         &bus_state->rexit_done[wIndex],
 801                                         msecs_to_jiffies(
 802                                                 XHCI_MAX_REXIT_TIMEOUT_MS));
 803                         spin_lock_irqsave(&xhci->lock, *flags);
 804
 805                         if (time_left) {
 806                                 slot_id = xhci_find_slot_id_by_port(hcd,
 807                                                 xhci, wIndex + 1);
 808                                 if (!slot_id) {
 809                                         xhci_dbg(xhci, "slot_id is zero\n");
 810                                         return 0xffffffff;
 811                                 }
 812                                 xhci_ring_device(xhci, slot_id);
 813                         } else {
 814                                 int port_status = readl(port_array[wIndex]);
 815                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 816                                                 XHCI_MAX_REXIT_TIMEOUT_MS,
 817                                                 port_status);
 818                                 status |= USB_PORT_STAT_SUSPEND;
 819                                 clear_bit(wIndex, &bus_state->rexit_ports);
 820                         }
 821
 822                         bus_state->port_c_suspend |= 1 << wIndex;
 823                         bus_state->suspended_ports &= ~(1 << wIndex);
 824                 } else {
 825                         /*
 826                          * The resume has been signaling for less than
 827                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 828                          * let the usbcore check port status again and clear
 829                          * resume signaling later.
 830                          */
 831                         status |= USB_PORT_STAT_SUSPEND;
 832                 }
 833         }
 834         /*
 835          * Clear stale usb2 resume signalling variables in case port changed
 836          * state during resume signalling. For example on error
 837          */
 838         if ((bus_state->resume_done[wIndex] ||
 839              test_bit(wIndex, &bus_state->resuming_ports)) &&
 840             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 841             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 842                 bus_state->resume_done[wIndex] = 0;
 843                 clear_bit(wIndex, &bus_state->resuming_ports);
 844         }
 845
 846
 847         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 848             (raw_port_status & PORT_POWER)) {
 849                 if (bus_state->suspended_ports & (1 << wIndex)) {
 850                         bus_state->suspended_ports &= ~(1 << wIndex);
 851                         if (hcd->speed < HCD_USB3)
 852                                 bus_state->port_c_suspend |= 1 << wIndex;
 853                 }
 854                 bus_state->resume_done[wIndex] = 0;
 855                 clear_bit(wIndex, &bus_state->resuming_ports);
 856         }
 857         if (raw_port_status & PORT_CONNECT) {
 858                 status |= USB_PORT_STAT_CONNECTION;
 859                 status |= xhci_port_speed(raw_port_status);
 860         }
 861         if (raw_port_status & PORT_PE)
 862                 status |= USB_PORT_STAT_ENABLE;
 863         if (raw_port_status & PORT_OC)
 864                 status |= USB_PORT_STAT_OVERCURRENT;
 865         if (raw_port_status & PORT_RESET)
 866                 status |= USB_PORT_STAT_RESET;
 867         if (raw_port_status & PORT_POWER) {
 868                 if (hcd->speed >= HCD_USB3)
 869                         status |= USB_SS_PORT_STAT_POWER;
 870                 else
 871                         status |= USB_PORT_STAT_POWER;
 872         }
 873         /* Update Port Link State */
 874         if (hcd->speed >= HCD_USB3) {
 875                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
 876                 /*
 877                  * Verify if all USB3 Ports Have entered U0 already.
 878                  * Delete Compliance Mode Timer if so.
 879                  */
 880                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
 881         } else {
 882                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
 883         }
 884         if (bus_state->port_c_suspend & (1 << wIndex))
 885                 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
 886
 887         return status;
 888 }
 889
 890 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 891                 u16 wIndex, char *buf, u16 wLength)
 892 {
 893         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 894         int max_ports;
 895         unsigned long flags;
 896         u32 temp, status;
 897         int retval = 0;
 898         __le32 __iomem **port_array;
 899         int slot_id;
 900         struct xhci_bus_state *bus_state;
 901         u16 link_state = 0;
 902         u16 wake_mask = 0;
 903         u16 timeout = 0;
 904
 905         max_ports = xhci_get_ports(hcd, &port_array);
 906         bus_state = &xhci->bus_state[hcd_index(hcd)];
 907
 908         spin_lock_irqsave(&xhci->lock, flags);
 909         switch (typeReq) {
 910         case GetHubStatus:
 911                 /* No power source, over-current reported per port */
 912                 memset(buf, 0, 4);
 913                 break;
 914         case GetHubDescriptor:
 915                 /* Check to make sure userspace is asking for the USB 3.0 hub
 916                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 917                  * endpoint, like external hubs do.
 918                  */
 919                 if (hcd->speed >= HCD_USB3 &&
 920                                 (wLength < USB_DT_SS_HUB_SIZE ||
 921                                  wValue != (USB_DT_SS_HUB << 8))) {
 922                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 923                                         "USB 3.0 roothub.\n");
 924                         goto error;
 925                 }
 926                 xhci_hub_descriptor(hcd, xhci,
 927                                 (struct usb_hub_descriptor *) buf);
 928                 break;
 929         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 930                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 931                         goto error;
 932
 933                 if (hcd->speed < HCD_USB3)
 934                         goto error;
 935
 936                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
 937                 spin_unlock_irqrestore(&xhci->lock, flags);
 938                 return retval;
 939         case GetPortStatus:
 940                 if (!wIndex || wIndex > max_ports)
 941                         goto error;
 942                 wIndex--;
 943                 temp = readl(port_array[wIndex]);
 944                 if (temp == 0xffffffff) {
 945                         retval = -ENODEV;
 946                         break;
 947                 }
 948                 status = xhci_get_port_status(hcd, bus_state, port_array,
 949                                 wIndex, temp, &flags);
 950                 if (status == 0xffffffff)
 951                         goto error;
 952
 953                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
 954                                 wIndex, temp);
 955                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 956
 957                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 958                 /* if USB 3.1 extended port status return additional 4 bytes */
 959                 if (wValue == 0x02) {
 960                         u32 port_li;
 961
 962                         if (hcd->speed < HCD_USB31 || wLength != 8) {
 963                                 xhci_err(xhci, "get ext port status invalid parameter\n");
 964                                 retval = -EINVAL;
 965                                 break;
 966                         }
 967                         port_li = readl(port_array[wIndex] + PORTLI);
 968                         status = xhci_get_ext_port_status(temp, port_li);
 969                         put_unaligned_le32(status, &buf[4]);
 970                 }
 971                 break;
 972         case SetPortFeature:
 973                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 974                         link_state = (wIndex & 0xff00) >> 3;
 975                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 976                         wake_mask = wIndex & 0xff00;
 977                 /* The MSB of wIndex is the U1/U2 timeout */
 978                 timeout = (wIndex & 0xff00) >> 8;
 979                 wIndex &= 0xff;
 980                 if (!wIndex || wIndex > max_ports)
 981                         goto error;
 982                 wIndex--;
 983                 temp = readl(port_array[wIndex]);
 984                 if (temp == 0xffffffff) {
 985                         retval = -ENODEV;
 986                         break;
 987                 }
 988                 temp = xhci_port_state_to_neutral(temp);
 989                 /* FIXME: What new port features do we need to support? */
 990                 switch (wValue) {
 991                 case USB_PORT_FEAT_SUSPEND:
 992                         temp = readl(port_array[wIndex]);
 993                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 994                                 /* Resume the port to U0 first */
 995                                 xhci_set_link_state(xhci, port_array, wIndex,
 996                                                         XDEV_U0);
 997                                 spin_unlock_irqrestore(&xhci->lock, flags);
 998                                 msleep(10);
 999                                 spin_lock_irqsave(&xhci->lock, flags);
1000                         }
1001                         /* In spec software should not attempt to suspend
1002                          * a port unless the port reports that it is in the
1003                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1004                          */
1005                         temp = readl(port_array[wIndex]);
1006                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1007                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1008                                 xhci_warn(xhci, "USB core suspending device "
1009                                           "not in U0/U1/U2.\n");
1010                                 goto error;
1011                         }
1012
1013                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1014                                         wIndex + 1);
1015                         if (!slot_id) {
1016                                 xhci_warn(xhci, "slot_id is zero\n");
1017                                 goto error;
1018                         }
1019                         /* unlock to execute stop endpoint commands */
1020                         spin_unlock_irqrestore(&xhci->lock, flags);
1021                         xhci_stop_device(xhci, slot_id, 1);
1022                         spin_lock_irqsave(&xhci->lock, flags);
1023
1024                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1025
1026                         spin_unlock_irqrestore(&xhci->lock, flags);
1027                         msleep(10); /* wait device to enter */
1028                         spin_lock_irqsave(&xhci->lock, flags);
1029
1030                         temp = readl(port_array[wIndex]);
1031                         bus_state->suspended_ports |= 1 << wIndex;
1032                         break;
1033                 case USB_PORT_FEAT_LINK_STATE:
1034                         temp = readl(port_array[wIndex]);
1035
1036                         /* Disable port */
1037                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1038                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1039                                 temp = xhci_port_state_to_neutral(temp);
1040                                 /*
1041                                  * Clear all change bits, so that we get a new
1042                                  * connection event.
1043                                  */
1044                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1045                                         PORT_OCC | PORT_RC | PORT_PLC |
1046                                         PORT_CEC;
1047                                 writel(temp | PORT_PE, port_array[wIndex]);
1048                                 temp = readl(port_array[wIndex]);
1049                                 break;
1050                         }
1051
1052                         /* Put link in RxDetect (enable port) */
1053                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1054                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1055                                 xhci_set_link_state(xhci, port_array, wIndex,
1056                                                 link_state);
1057                                 temp = readl(port_array[wIndex]);
1058                                 break;
1059                         }
1060                         /* Port must be enabled */
1061                         if (!(temp & PORT_PE)) {
1062                                 retval = -ENODEV;
1063                                 break;
1064                         }
1065                         /* Can't set port link state above '3' (U3) */
1066                         if (link_state > USB_SS_PORT_LS_U3) {
1067                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1068                                          wIndex, link_state);
1069                                 goto error;
1070                         }
1071                         if (link_state == USB_SS_PORT_LS_U3) {
1072                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1073                                                 wIndex + 1);
1074                                 if (slot_id) {
1075                                         /* unlock to execute stop endpoint
1076                                          * commands */
1077                                         spin_unlock_irqrestore(&xhci->lock,
1078                                                                 flags);
1079                                         xhci_stop_device(xhci, slot_id, 1);
1080                                         spin_lock_irqsave(&xhci->lock, flags);
1081                                 }
1082                         }
1083
1084                         xhci_set_link_state(xhci, port_array, wIndex,
1085                                                 link_state);
1086
1087                         spin_unlock_irqrestore(&xhci->lock, flags);
1088                         msleep(20); /* wait device to enter */
1089                         spin_lock_irqsave(&xhci->lock, flags);
1090
1091                         temp = readl(port_array[wIndex]);
1092                         if (link_state == USB_SS_PORT_LS_U3)
1093                                 bus_state->suspended_ports |= 1 << wIndex;
1094                         break;
1095                 case USB_PORT_FEAT_POWER:
1096                         /*
1097                          * Turn on ports, even if there isn't per-port switching.
1098                          * HC will report connect events even before this is set.
1099                          * However, hub_wq will ignore the roothub events until
1100                          * the roothub is registered.
1101                          */
1102                         writel(temp | PORT_POWER, port_array[wIndex]);
1103
1104                         temp = readl(port_array[wIndex]);
1105                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
1106
1107                         spin_unlock_irqrestore(&xhci->lock, flags);
1108                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1109                                         wIndex);
1110                         if (temp)
1111                                 usb_acpi_set_power_state(hcd->self.root_hub,
1112                                                 wIndex, true);
1113                         spin_lock_irqsave(&xhci->lock, flags);
1114                         break;
1115                 case USB_PORT_FEAT_RESET:
1116                         temp = (temp | PORT_RESET);
1117                         writel(temp, port_array[wIndex]);
1118
1119                         temp = readl(port_array[wIndex]);
1120                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1121                         break;
1122                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1123                         xhci_set_remote_wake_mask(xhci, port_array,
1124                                         wIndex, wake_mask);
1125                         temp = readl(port_array[wIndex]);
1126                         xhci_dbg(xhci, "set port remote wake mask, "
1127                                         "actual port %d status  = 0x%x\n",
1128                                         wIndex, temp);
1129                         break;
1130                 case USB_PORT_FEAT_BH_PORT_RESET:
1131                         temp |= PORT_WR;
1132                         writel(temp, port_array[wIndex]);
1133
1134                         temp = readl(port_array[wIndex]);
1135                         break;
1136                 case USB_PORT_FEAT_U1_TIMEOUT:
1137                         if (hcd->speed < HCD_USB3)
1138                                 goto error;
1139                         temp = readl(port_array[wIndex] + PORTPMSC);
1140                         temp &= ~PORT_U1_TIMEOUT_MASK;
1141                         temp |= PORT_U1_TIMEOUT(timeout);
1142                         writel(temp, port_array[wIndex] + PORTPMSC);
1143                         break;
1144                 case USB_PORT_FEAT_U2_TIMEOUT:
1145                         if (hcd->speed < HCD_USB3)
1146                                 goto error;
1147                         temp = readl(port_array[wIndex] + PORTPMSC);
1148                         temp &= ~PORT_U2_TIMEOUT_MASK;
1149                         temp |= PORT_U2_TIMEOUT(timeout);
1150                         writel(temp, port_array[wIndex] + PORTPMSC);
1151                         break;
1152                 default:
1153                         goto error;
1154                 }
1155                 /* unblock any posted writes */
1156                 temp = readl(port_array[wIndex]);
1157                 break;
1158         case ClearPortFeature:
1159                 if (!wIndex || wIndex > max_ports)
1160                         goto error;
1161                 wIndex--;
1162                 temp = readl(port_array[wIndex]);
1163                 if (temp == 0xffffffff) {
1164                         retval = -ENODEV;
1165                         break;
1166                 }
1167                 /* FIXME: What new port features do we need to support? */
1168                 temp = xhci_port_state_to_neutral(temp);
1169                 switch (wValue) {
1170                 case USB_PORT_FEAT_SUSPEND:
1171                         temp = readl(port_array[wIndex]);
1172                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1173                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1174                         if (temp & PORT_RESET)
1175                                 goto error;
1176                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1177                                 if ((temp & PORT_PE) == 0)
1178                                         goto error;
1179
1180                                 set_bit(wIndex, &bus_state->resuming_ports);
1181                                 xhci_set_link_state(xhci, port_array, wIndex,
1182                                                         XDEV_RESUME);
1183                                 spin_unlock_irqrestore(&xhci->lock, flags);
1184                                 msleep(USB_RESUME_TIMEOUT);
1185                                 spin_lock_irqsave(&xhci->lock, flags);
1186                                 xhci_set_link_state(xhci, port_array, wIndex,
1187                                                         XDEV_U0);
1188                                 clear_bit(wIndex, &bus_state->resuming_ports);
1189                         }
1190                         bus_state->port_c_suspend |= 1 << wIndex;
1191
1192                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1193                                         wIndex + 1);
1194                         if (!slot_id) {
1195                                 xhci_dbg(xhci, "slot_id is zero\n");
1196                                 goto error;
1197                         }
1198                         xhci_ring_device(xhci, slot_id);
1199                         break;
1200                 case USB_PORT_FEAT_C_SUSPEND:
1201                         bus_state->port_c_suspend &= ~(1 << wIndex);
1202                 case USB_PORT_FEAT_C_RESET:
1203                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1204                 case USB_PORT_FEAT_C_CONNECTION:
1205                 case USB_PORT_FEAT_C_OVER_CURRENT:
1206                 case USB_PORT_FEAT_C_ENABLE:
1207                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1208                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1209                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1210                                         port_array[wIndex], temp);
1211                         break;
1212                 case USB_PORT_FEAT_ENABLE:
1213                         xhci_disable_port(hcd, xhci, wIndex,
1214                                         port_array[wIndex], temp);
1215                         break;
1216                 case USB_PORT_FEAT_POWER:
1217                         writel(temp & ~PORT_POWER, port_array[wIndex]);
1218
1219                         spin_unlock_irqrestore(&xhci->lock, flags);
1220                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1221                                         wIndex);
1222                         if (temp)
1223                                 usb_acpi_set_power_state(hcd->self.root_hub,
1224                                                 wIndex, false);
1225                         spin_lock_irqsave(&xhci->lock, flags);
1226                         break;
1227                 default:
1228                         goto error;
1229                 }
1230                 break;
1231         default:
1232 error:
1233                 /* "stall" on error */
1234                 retval = -EPIPE;
1235         }
1236         spin_unlock_irqrestore(&xhci->lock, flags);
1237         return retval;
1238 }
1239
1240 /*
1241  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1242  * Ports are 0-indexed from the HCD point of view,
1243  * and 1-indexed from the USB core pointer of view.
1244  *
1245  * Note that the status change bits will be cleared as soon as a port status
1246  * change event is generated, so we use the saved status from that event.
1247  */
1248 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1249 {
1250         unsigned long flags;
1251         u32 temp, status;
1252         u32 mask;
1253         int i, retval;
1254         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1255         int max_ports;
1256         __le32 __iomem **port_array;
1257         struct xhci_bus_state *bus_state;
1258         bool reset_change = false;
1259
1260         max_ports = xhci_get_ports(hcd, &port_array);
1261         bus_state = &xhci->bus_state[hcd_index(hcd)];
1262
1263         /* Initial status is no changes */
1264         retval = (max_ports + 8) / 8;
1265         memset(buf, 0, retval);
1266
1267         /*
1268          * Inform the usbcore about resume-in-progress by returning
1269          * a non-zero value even if there are no status changes.
1270          */
1271         spin_lock_irqsave(&xhci->lock, flags);
1272
1273         status = bus_state->resuming_ports;
1274
1275         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1276
1277         /* For each port, did anything change?  If so, set that bit in buf. */
1278         for (i = 0; i < max_ports; i++) {
1279                 temp = readl(port_array[i]);
1280                 if (temp == 0xffffffff) {
1281                         retval = -ENODEV;
1282                         break;
1283                 }
1284                 if ((temp & mask) != 0 ||
1285                         (bus_state->port_c_suspend & 1 << i) ||
1286                         (bus_state->resume_done[i] && time_after_eq(
1287                             jiffies, bus_state->resume_done[i]))) {
1288                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1289                         status = 1;
1290                 }
1291                 if ((temp & PORT_RC))
1292                         reset_change = true;
1293         }
1294         if (!status && !reset_change) {
1295                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1296                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1297         }
1298         spin_unlock_irqrestore(&xhci->lock, flags);
1299         return status ? retval : 0;
1300 }
1301
1302 #ifdef CONFIG_PM
1303
1304 int xhci_bus_suspend(struct usb_hcd *hcd)
1305 {
1306         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1307         int max_ports, port_index;
1308         __le32 __iomem **port_array;
1309         struct xhci_bus_state *bus_state;
1310         unsigned long flags;
1311         u32 portsc_buf[USB_MAXCHILDREN];
1312         bool wake_enabled;
1313
1314         max_ports = xhci_get_ports(hcd, &port_array);
1315         bus_state = &xhci->bus_state[hcd_index(hcd)];
1316         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1317
1318         spin_lock_irqsave(&xhci->lock, flags);
1319
1320         if (wake_enabled) {
1321                 if (bus_state->resuming_ports ||        /* USB2 */
1322                     bus_state->port_remote_wakeup) {    /* USB3 */
1323                         spin_unlock_irqrestore(&xhci->lock, flags);
1324                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1325                         return -EBUSY;
1326                 }
1327         }
1328         /*
1329          * Prepare ports for suspend, but don't write anything before all ports
1330          * are checked and we know bus suspend can proceed
1331          */
1332         bus_state->bus_suspended = 0;
1333         port_index = max_ports;
1334         while (port_index--) {
1335                 u32 t1, t2;
1336
1337                 t1 = readl(port_array[port_index]);
1338                 t2 = xhci_port_state_to_neutral(t1);
1339                 portsc_buf[port_index] = 0;
1340
1341                 /* Bail out if a USB3 port has a new device in link training */
1342                 if ((hcd->speed >= HCD_USB3) &&
1343                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1344                         bus_state->bus_suspended = 0;
1345                         spin_unlock_irqrestore(&xhci->lock, flags);
1346                         xhci_dbg(xhci, "Bus suspend bailout, port in polling\n");
1347                         return -EBUSY;
1348                 }
1349
1350                 /* suspend ports in U0, or bail out for new connect changes */
1351                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1352                         if ((t1 & PORT_CSC) && wake_enabled) {
1353                                 bus_state->bus_suspended = 0;
1354                                 spin_unlock_irqrestore(&xhci->lock, flags);
1355                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1356                                 return -EBUSY;
1357                         }
1358                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1359                         t2 &= ~PORT_PLS_MASK;
1360                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1361                         set_bit(port_index, &bus_state->bus_suspended);
1362                 }
1363                 /* USB core sets remote wake mask for USB 3.0 hubs,
1364                  * including the USB 3.0 roothub, but only if CONFIG_PM
1365                  * is enabled, so also enable remote wake here.
1366                  */
1367                 if (wake_enabled) {
1368                         if (t1 & PORT_CONNECT) {
1369                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1370                                 t2 &= ~PORT_WKCONN_E;
1371                         } else {
1372                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1373                                 t2 &= ~PORT_WKDISC_E;
1374                         }
1375                 } else
1376                         t2 &= ~PORT_WAKE_BITS;
1377
1378                 t1 = xhci_port_state_to_neutral(t1);
1379                 if (t1 != t2)
1380                         portsc_buf[port_index] = t2;
1381         }
1382
1383         /* write port settings, stopping and suspending ports if needed */
1384         port_index = max_ports;
1385         while (port_index--) {
1386                 if (!portsc_buf[port_index])
1387                         continue;
1388                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1389                         int slot_id;
1390
1391                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1392                                                             port_index + 1);
1393                         if (slot_id) {
1394                                 spin_unlock_irqrestore(&xhci->lock, flags);
1395                                 xhci_stop_device(xhci, slot_id, 1);
1396                                 spin_lock_irqsave(&xhci->lock, flags);
1397                         }
1398                 }
1399                 writel(portsc_buf[port_index], port_array[port_index]);
1400         }
1401         hcd->state = HC_STATE_SUSPENDED;
1402         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1403         spin_unlock_irqrestore(&xhci->lock, flags);
1404
1405         if (bus_state->bus_suspended)
1406                 usleep_range(5000, 10000);
1407
1408         return 0;
1409 }
1410
1411 /*
1412  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1413  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1414  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1415  */
1416 static bool xhci_port_missing_cas_quirk(int port_index,
1417                                              __le32 __iomem **port_array)
1418 {
1419         u32 portsc;
1420
1421         portsc = readl(port_array[port_index]);
1422
1423         /* if any of these are set we are not stuck */
1424         if (portsc & (PORT_CONNECT | PORT_CAS))
1425                 return false;
1426
1427         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1428             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1429                 return false;
1430
1431         /* clear wakeup/change bits, and do a warm port reset */
1432         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1433         portsc |= PORT_WR;
1434         writel(portsc, port_array[port_index]);
1435         /* flush write */
1436         readl(port_array[port_index]);
1437         return true;
1438 }
1439
1440 int xhci_bus_resume(struct usb_hcd *hcd)
1441 {
1442         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1443         int max_ports, port_index;
1444         __le32 __iomem **port_array;
1445         struct xhci_bus_state *bus_state;
1446         u32 temp;
1447         unsigned long flags;
1448         unsigned long port_was_suspended = 0;
1449         bool need_usb2_u3_exit = false;
1450         int slot_id;
1451         int sret;
1452
1453         max_ports = xhci_get_ports(hcd, &port_array);
1454         bus_state = &xhci->bus_state[hcd_index(hcd)];
1455
1456         if (time_before(jiffies, bus_state->next_statechange))
1457                 msleep(5);
1458
1459         spin_lock_irqsave(&xhci->lock, flags);
1460         if (!HCD_HW_ACCESSIBLE(hcd)) {
1461                 spin_unlock_irqrestore(&xhci->lock, flags);
1462                 return -ESHUTDOWN;
1463         }
1464
1465         /* delay the irqs */
1466         temp = readl(&xhci->op_regs->command);
1467         temp &= ~CMD_EIE;
1468         writel(temp, &xhci->op_regs->command);
1469
1470         port_index = max_ports;
1471         while (port_index--) {
1472                 /* Check whether need resume ports. If needed
1473                    resume port and disable remote wakeup */
1474                 u32 temp;
1475
1476                 temp = readl(port_array[port_index]);
1477
1478                 /* warm reset CAS limited ports stuck in polling/compliance */
1479                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1480                     (hcd->speed >= HCD_USB3) &&
1481                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1482                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1483                         continue;
1484                 }
1485                 if (DEV_SUPERSPEED_ANY(temp))
1486                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1487                 else
1488                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1489                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1490                     (temp & PORT_PLS_MASK)) {
1491                         set_bit(port_index, &port_was_suspended);
1492                         if (!DEV_SUPERSPEED_ANY(temp)) {
1493                                 xhci_set_link_state(xhci, port_array,
1494                                                 port_index, XDEV_RESUME);
1495                                 need_usb2_u3_exit = true;
1496                         }
1497                 } else
1498                         writel(temp, port_array[port_index]);
1499         }
1500
1501         if (need_usb2_u3_exit) {
1502                 spin_unlock_irqrestore(&xhci->lock, flags);
1503                 msleep(USB_RESUME_TIMEOUT);
1504                 spin_lock_irqsave(&xhci->lock, flags);
1505         }
1506
1507         port_index = max_ports;
1508         while (port_index--) {
1509                 if (!(port_was_suspended & BIT(port_index)))
1510                         continue;
1511                 /* Clear PLC to poll it later after XDEV_U0 */
1512                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1513                 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1514         }
1515
1516         port_index = max_ports;
1517         while (port_index--) {
1518                 if (!(port_was_suspended & BIT(port_index)))
1519                         continue;
1520                 /* Poll and Clear PLC */
1521                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1522                                       PORT_PLC, 10 * 1000);
1523                 if (sret)
1524                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1525                                   port_index);
1526                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1527                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1528                 if (slot_id)
1529                         xhci_ring_device(xhci, slot_id);
1530         }
1531
1532         (void) readl(&xhci->op_regs->command);
1533
1534         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1535         /* re-enable irqs */
1536         temp = readl(&xhci->op_regs->command);
1537         temp |= CMD_EIE;
1538         writel(temp, &xhci->op_regs->command);
1539         temp = readl(&xhci->op_regs->command);
1540
1541         spin_unlock_irqrestore(&xhci->lock, flags);
1542         return 0;
1543 }
1544
1545 #endif  /* CONFIG_PM */