drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18
  19 #define SSIC_PORT_NUM           2
  20 #define SSIC_PORT_CFG2          0x880c
  21 #define SSIC_PORT_CFG2_OFFSET   0x30
  22 #define PROG_DONE               (1 << 30)
  23 #define SSIC_PORT_UNUSED        (1 << 31)
  24 #define SPARSE_DISABLE_BIT      17
  25 #define SPARSE_CNTL_ENABLE      0xC12C
  26
  27 /* Device for a quirk */
  28 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  29 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  30 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  33
  34 #define PCI_VENDOR_ID_ETRON             0x1b6f
  35 #define PCI_DEVICE_ID_EJ168             0x7023
  36
  37 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  39 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  40 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  41 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  42 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  43 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  44 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  45 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  46 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  47 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  48
  49 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  50 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  51 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  52 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  53 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  54 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  55 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  56 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  57 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  58
  59 static const char hcd_name[] = "xhci_hcd";
  60
  61 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  62
  63 static int xhci_pci_setup(struct usb_hcd *hcd);
  64
  65 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  66         .reset = xhci_pci_setup,
  67 };
  68
  69 /* called after powerup, by probe or system-pm "wakeup" */
  70 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  71 {
  72         /*
  73          * TODO: Implement finding debug ports later.
  74          * TODO: see if there are any quirks that need to be added to handle
  75          * new extended capabilities.
  76          */
  77
  78         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  79         if (!pci_set_mwi(pdev))
  80                 xhci_dbg(xhci, "MWI active\n");
  81
  82         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  83         return 0;
  84 }
  85
  86 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  87 {
  88         struct pci_dev          *pdev = to_pci_dev(dev);
  89
  90         /* Look for vendor-specific quirks */
  91         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  92                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  93                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  94                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  95                                 pdev->revision == 0x0) {
  96                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  97                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  98                                 "QUIRK: Fresco Logic xHC needs configure"
  99                                 " endpoint cmd after reset endpoint");
 100                 }
 101                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 102                                 pdev->revision == 0x4) {
 103                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 104                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 105                                 "QUIRK: Fresco Logic xHC revision %u"
 106                                 "must be suspended extra slowly",
 107                                 pdev->revision);
 108                 }
 109                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 110                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 111                 /* Fresco Logic confirms: all revisions of this chip do not
 112                  * support MSI, even though some of them claim to in their PCI
 113                  * capabilities.
 114                  */
 115                 xhci->quirks |= XHCI_BROKEN_MSI;
 116                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 117                                 "QUIRK: Fresco Logic revision %u "
 118                                 "has broken MSI implementation",
 119                                 pdev->revision);
 120                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 121         }
 122
 123         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 124                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 125                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 126
 127         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 128                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
 129                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 130
 131         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 132                 xhci->quirks |= XHCI_NEC_HOST;
 133
 134         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 135                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 136
 137         /* AMD PLL quirk */
 138         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 139                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 140
 141         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 142                 (pdev->device == 0x145c ||
 143                  pdev->device == 0x15e0 ||
 144                  pdev->device == 0x15e1 ||
 145                  pdev->device == 0x43bb))
 146                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 147
 148         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 149             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 150                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 151
 152         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 153                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 154                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 155         }
 156
 157         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 158                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 159
 160         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 161                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 162                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 163                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 164                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 165                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 166
 167         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 168                 xhci->quirks |= XHCI_LPM_SUPPORT;
 169                 xhci->quirks |= XHCI_INTEL_HOST;
 170                 xhci->quirks |= XHCI_AVOID_BEI;
 171         }
 172         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 173                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 174                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 175                 xhci->limit_active_eps = 64;
 176                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 177                 /*
 178                  * PPT desktop boards DH77EB and DH77DF will power back on after
 179                  * a few seconds of being shutdown.  The fix for this is to
 180                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 181                  * DMI information to find those particular boards (since each
 182                  * vendor will change the board name), so we have to key off all
 183                  * PPT chipsets.
 184                  */
 185                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 186         }
 187         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 188                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 189                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 190                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 191                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 192         }
 193         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 194                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 195                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 196                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 197                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 198                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 199                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 200                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 201                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 202                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 203         }
 204         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 205             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 206                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 207         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 208             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 209              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 210              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 211                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 212         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 213             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 214              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 215              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 216              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 217              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 218                 xhci->quirks |= XHCI_MISSING_CAS;
 219
 220         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 221                         pdev->device == PCI_DEVICE_ID_EJ168) {
 222                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 223                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 224                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 225         }
 226         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 227             pdev->device == 0x0014) {
 228                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 229                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 230         }
 231         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 232             pdev->device == 0x0015) {
 233                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 234                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 235         }
 236         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 237                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 238
 239         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 240         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 241                         pdev->device == 0x3432)
 242                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 243
 244         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 245                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
 246                 /*
 247                  * try to tame the ASMedia 1042 controller which reports 0.96
 248                  * but appears to behave more like 1.0
 249                  */
 250                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 251                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 252         }
 253         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 254                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 255                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 256                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 257         }
 258         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 259             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 260              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 261              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 262                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 263
 264         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 265                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 266                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 267
 268         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 269                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 270
 271         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 272              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 273              pdev->device == 0x9026)
 274                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 275
 276         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 277                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 278                                 "QUIRK: Resetting on resume");
 279 }
 280
 281 #ifdef CONFIG_ACPI
 282 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 283 {
 284         static const guid_t intel_dsm_guid =
 285                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 286                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 287         union acpi_object *obj;
 288
 289         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 290                                 NULL);
 291         ACPI_FREE(obj);
 292 }
 293 #else
 294 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 295 #endif /* CONFIG_ACPI */
 296
 297 /* called during probe() after chip reset completes */
 298 static int xhci_pci_setup(struct usb_hcd *hcd)
 299 {
 300         struct xhci_hcd         *xhci;
 301         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 302         int                     retval;
 303
 304         xhci = hcd_to_xhci(hcd);
 305         if (!xhci->sbrn)
 306                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 307
 308         /* imod_interval is the interrupt moderation value in nanoseconds. */
 309         xhci->imod_interval = 40000;
 310
 311         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 312         if (retval)
 313                 return retval;
 314
 315         if (!usb_hcd_is_primary_hcd(hcd))
 316                 return 0;
 317
 318         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 319                 xhci_pme_acpi_rtd3_enable(pdev);
 320
 321         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 322
 323         /* Find any debug ports */
 324         return xhci_pci_reinit(xhci, pdev);
 325 }
 326
 327 /*
 328  * We need to register our own PCI probe function (instead of the USB core's
 329  * function) in order to create a second roothub under xHCI.
 330  */
 331 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 332 {
 333         int retval;
 334         struct xhci_hcd *xhci;
 335         struct hc_driver *driver;
 336         struct usb_hcd *hcd;
 337
 338         driver = (struct hc_driver *)id->driver_data;
 339
 340         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 341         pm_runtime_get_noresume(&dev->dev);
 342
 343         /* Register the USB 2.0 roothub.
 344          * FIXME: USB core must know to register the USB 2.0 roothub first.
 345          * This is sort of silly, because we could just set the HCD driver flags
 346          * to say USB 2.0, but I'm not sure what the implications would be in
 347          * the other parts of the HCD code.
 348          */
 349         retval = usb_hcd_pci_probe(dev, id);
 350
 351         if (retval)
 352                 goto put_runtime_pm;
 353
 354         /* USB 2.0 roothub is stored in the PCI device now. */
 355         hcd = dev_get_drvdata(&dev->dev);
 356         xhci = hcd_to_xhci(hcd);
 357         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 358                                 pci_name(dev), hcd);
 359         if (!xhci->shared_hcd) {
 360                 retval = -ENOMEM;
 361                 goto dealloc_usb2_hcd;
 362         }
 363
 364         retval = xhci_ext_cap_init(xhci);
 365         if (retval)
 366                 goto put_usb3_hcd;
 367
 368         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 369                         IRQF_SHARED);
 370         if (retval)
 371                 goto put_usb3_hcd;
 372         /* Roothub already marked as USB 3.0 speed */
 373
 374         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 375                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 376                 xhci->shared_hcd->can_do_streams = 1;
 377
 378         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 379         pm_runtime_put_noidle(&dev->dev);
 380
 381         dma_set_max_seg_size(&dev->dev, UINT_MAX);
 382
 383         return 0;
 384
 385 put_usb3_hcd:
 386         usb_put_hcd(xhci->shared_hcd);
 387 dealloc_usb2_hcd:
 388         usb_hcd_pci_remove(dev);
 389 put_runtime_pm:
 390         pm_runtime_put_noidle(&dev->dev);
 391         return retval;
 392 }
 393
 394 static void xhci_pci_remove(struct pci_dev *dev)
 395 {
 396         struct xhci_hcd *xhci;
 397
 398         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 399         xhci->xhc_state |= XHCI_STATE_REMOVING;
 400         if (xhci->shared_hcd) {
 401                 usb_remove_hcd(xhci->shared_hcd);
 402                 usb_put_hcd(xhci->shared_hcd);
 403                 xhci->shared_hcd = NULL;
 404         }
 405
 406         /* Workaround for spurious wakeups at shutdown with HSW */
 407         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 408                 pci_set_power_state(dev, PCI_D3hot);
 409
 410         usb_hcd_pci_remove(dev);
 411 }
 412
 413 #ifdef CONFIG_PM
 414 /*
 415  * In some Intel xHCI controllers, in order to get D3 working,
 416  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 417  * SSIC PORT need to be marked as "unused" before putting xHCI
 418  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 419  * Without this change, xHCI might not enter D3 state.
 420  */
 421 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 422 {
 423         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 424         u32 val;
 425         void __iomem *reg;
 426         int i;
 427
 428         for (i = 0; i < SSIC_PORT_NUM; i++) {
 429                 reg = (void __iomem *) xhci->cap_regs +
 430                                 SSIC_PORT_CFG2 +
 431                                 i * SSIC_PORT_CFG2_OFFSET;
 432
 433                 /* Notify SSIC that SSIC profile programming is not done. */
 434                 val = readl(reg) & ~PROG_DONE;
 435                 writel(val, reg);
 436
 437                 /* Mark SSIC port as unused(suspend) or used(resume) */
 438                 val = readl(reg);
 439                 if (suspend)
 440                         val |= SSIC_PORT_UNUSED;
 441                 else
 442                         val &= ~SSIC_PORT_UNUSED;
 443                 writel(val, reg);
 444
 445                 /* Notify SSIC that SSIC profile programming is done */
 446                 val = readl(reg) | PROG_DONE;
 447                 writel(val, reg);
 448                 readl(reg);
 449         }
 450 }
 451
 452 /*
 453  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 454  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 455  */
 456 static void xhci_pme_quirk(struct usb_hcd *hcd)
 457 {
 458         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 459         void __iomem *reg;
 460         u32 val;
 461
 462         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 463         val = readl(reg);
 464         writel(val | BIT(28), reg);
 465         readl(reg);
 466 }
 467
 468 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 469 {
 470         u32 reg;
 471
 472         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 473         reg &= ~BIT(SPARSE_DISABLE_BIT);
 474         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 475 }
 476
 477 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 478 {
 479         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 480         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 481         int                     ret;
 482
 483         /*
 484          * Systems with the TI redriver that loses port status change events
 485          * need to have the registers polled during D3, so avoid D3cold.
 486          */
 487         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 488                 pci_d3cold_disable(pdev);
 489
 490         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 491                 xhci_pme_quirk(hcd);
 492
 493         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 494                 xhci_ssic_port_unused_quirk(hcd, true);
 495
 496         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 497                 xhci_sparse_control_quirk(hcd);
 498
 499         ret = xhci_suspend(xhci, do_wakeup);
 500         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 501                 xhci_ssic_port_unused_quirk(hcd, false);
 502
 503         return ret;
 504 }
 505
 506 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 507 {
 508         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 509         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 510         int                     retval = 0;
 511
 512         /* The BIOS on systems with the Intel Panther Point chipset may or may
 513          * not support xHCI natively.  That means that during system resume, it
 514          * may switch the ports back to EHCI so that users can use their
 515          * keyboard to select a kernel from GRUB after resume from hibernate.
 516          *
 517          * The BIOS is supposed to remember whether the OS had xHCI ports
 518          * enabled before resume, and switch the ports back to xHCI when the
 519          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 520          * writers.
 521          *
 522          * Unconditionally switch the ports back to xHCI after a system resume.
 523          * It should not matter whether the EHCI or xHCI controller is
 524          * resumed first. It's enough to do the switchover in xHCI because
 525          * USB core won't notice anything as the hub driver doesn't start
 526          * running again until after all the devices (including both EHCI and
 527          * xHCI host controllers) have been resumed.
 528          */
 529
 530         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 531                 usb_enable_intel_xhci_ports(pdev);
 532
 533         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 534                 xhci_ssic_port_unused_quirk(hcd, false);
 535
 536         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 537                 xhci_pme_quirk(hcd);
 538
 539         retval = xhci_resume(xhci, hibernated);
 540         return retval;
 541 }
 542
 543 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 544 {
 545         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 546         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 547
 548         xhci_shutdown(hcd);
 549
 550         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 551         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 552                 pci_set_power_state(pdev, PCI_D3hot);
 553 }
 554 #endif /* CONFIG_PM */
 555
 556 /*-------------------------------------------------------------------------*/
 557
 558 /* PCI driver selection metadata; PCI hotplugging uses this */
 559 static const struct pci_device_id pci_ids[] = { {
 560         /* handle any USB 3.0 xHCI controller */
 561         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 562         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 563         },
 564         { /* end: all zeroes */ }
 565 };
 566 MODULE_DEVICE_TABLE(pci, pci_ids);
 567
 568 /* pci driver glue; this is a "new style" PCI driver module */
 569 static struct pci_driver xhci_pci_driver = {
 570         .name =         (char *) hcd_name,
 571         .id_table =     pci_ids,
 572
 573         .probe =        xhci_pci_probe,
 574         .remove =       xhci_pci_remove,
 575         /* suspend and resume implemented later */
 576
 577         .shutdown =     usb_hcd_pci_shutdown,
 578 #ifdef CONFIG_PM
 579         .driver = {
 580                 .pm = &usb_hcd_pci_pm_ops
 581         },
 582 #endif
 583 };
 584
 585 static int __init xhci_pci_init(void)
 586 {
 587         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 588 #ifdef CONFIG_PM
 589         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 590         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 591         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 592 #endif
 593         return pci_register_driver(&xhci_pci_driver);
 594 }
 595 module_init(xhci_pci_init);
 596
 597 static void __exit xhci_pci_exit(void)
 598 {
 599         pci_unregister_driver(&xhci_pci_driver);
 600 }
 601 module_exit(xhci_pci_exit);
 602
 603 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 604 MODULE_LICENSE("GPL");