drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/acpi.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define SSIC_PORT_NUM           2
  32 #define SSIC_PORT_CFG2          0x880c
  33 #define SSIC_PORT_CFG2_OFFSET   0x30
  34 #define PROG_DONE               (1 << 30)
  35 #define SSIC_PORT_UNUSED        (1 << 31)
  36
  37 /* Device for a quirk */
  38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  42
  43 #define PCI_VENDOR_ID_ETRON             0x1b6f
  44 #define PCI_DEVICE_ID_EJ168             0x7023
  45
  46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  54 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  55 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  56 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  57
  58 static const char hcd_name[] = "xhci_hcd";
  59
  60 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  61
  62 static int xhci_pci_setup(struct usb_hcd *hcd);
  63
  64 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  65         .extra_priv_size = sizeof(struct xhci_hcd),
  66         .reset = xhci_pci_setup,
  67 };
  68
  69 /* called after powerup, by probe or system-pm "wakeup" */
  70 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  71 {
  72         /*
  73          * TODO: Implement finding debug ports later.
  74          * TODO: see if there are any quirks that need to be added to handle
  75          * new extended capabilities.
  76          */
  77
  78         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  79         if (!pci_set_mwi(pdev))
  80                 xhci_dbg(xhci, "MWI active\n");
  81
  82         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  83         return 0;
  84 }
  85
  86 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  87 {
  88         struct pci_dev          *pdev = to_pci_dev(dev);
  89
  90         /* Look for vendor-specific quirks */
  91         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  92                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  93                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  94                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  95                                 pdev->revision == 0x0) {
  96                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  97                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  98                                 "QUIRK: Fresco Logic xHC needs configure"
  99                                 " endpoint cmd after reset endpoint");
 100                 }
 101                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 102                                 pdev->revision == 0x4) {
 103                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 104                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 105                                 "QUIRK: Fresco Logic xHC revision %u"
 106                                 "must be suspended extra slowly",
 107                                 pdev->revision);
 108                 }
 109                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 110                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 111                 /* Fresco Logic confirms: all revisions of this chip do not
 112                  * support MSI, even though some of them claim to in their PCI
 113                  * capabilities.
 114                  */
 115                 xhci->quirks |= XHCI_BROKEN_MSI;
 116                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 117                                 "QUIRK: Fresco Logic revision %u "
 118                                 "has broken MSI implementation",
 119                                 pdev->revision);
 120                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 121         }
 122
 123         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 124                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 125                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 126
 127         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 128                 xhci->quirks |= XHCI_NEC_HOST;
 129
 130         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 131                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 132
 133         /* AMD PLL quirk */
 134         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 135                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 136
 137         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 138                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 139
 140         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 141                 xhci->quirks |= XHCI_LPM_SUPPORT;
 142                 xhci->quirks |= XHCI_INTEL_HOST;
 143                 xhci->quirks |= XHCI_AVOID_BEI;
 144         }
 145         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 146                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 147                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 148                 xhci->limit_active_eps = 64;
 149                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 150                 /*
 151                  * PPT desktop boards DH77EB and DH77DF will power back on after
 152                  * a few seconds of being shutdown.  The fix for this is to
 153                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 154                  * DMI information to find those particular boards (since each
 155                  * vendor will change the board name), so we have to key off all
 156                  * PPT chipsets.
 157                  */
 158                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 159         }
 160         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 161                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 162                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 163                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 164                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 165         }
 166         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 167                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 168                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 169                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 170                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 171                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 172                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 173                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 174                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 175                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 176         }
 177         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 178             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 179              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 180              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 181              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 182              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 183                 xhci->quirks |= XHCI_MISSING_CAS;
 184
 185         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 186                         pdev->device == PCI_DEVICE_ID_EJ168) {
 187                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 188                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 189                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 190         }
 191         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 192                         pdev->device == 0x0014)
 193                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 194         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 195                         pdev->device == 0x0015)
 196                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 197         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 198                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 199
 200         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 201         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 202                         pdev->device == 0x3432)
 203                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 204
 205         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 206                         pdev->device == 0x1042)
 207                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 208         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 209                         pdev->device == 0x1142)
 210                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 211
 212         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 213                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 214                                 "QUIRK: Resetting on resume");
 215 }
 216
 217 #ifdef CONFIG_ACPI
 218 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 219 {
 220         static const u8 intel_dsm_uuid[] = {
 221                 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
 222                 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
 223         };
 224         union acpi_object *obj;
 225
 226         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
 227                                 NULL);
 228         ACPI_FREE(obj);
 229 }
 230 #else
 231 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 232 #endif /* CONFIG_ACPI */
 233
 234 /* called during probe() after chip reset completes */
 235 static int xhci_pci_setup(struct usb_hcd *hcd)
 236 {
 237         struct xhci_hcd         *xhci;
 238         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 239         int                     retval;
 240
 241         xhci = hcd_to_xhci(hcd);
 242         if (!xhci->sbrn)
 243                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 244
 245         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 246         if (retval)
 247                 return retval;
 248
 249         if (!usb_hcd_is_primary_hcd(hcd))
 250                 return 0;
 251
 252         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 253
 254         /* Find any debug ports */
 255         retval = xhci_pci_reinit(xhci, pdev);
 256         if (!retval)
 257                 return retval;
 258
 259         return retval;
 260 }
 261
 262 /*
 263  * We need to register our own PCI probe function (instead of the USB core's
 264  * function) in order to create a second roothub under xHCI.
 265  */
 266 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 267 {
 268         int retval;
 269         struct xhci_hcd *xhci;
 270         struct hc_driver *driver;
 271         struct usb_hcd *hcd;
 272
 273         driver = (struct hc_driver *)id->driver_data;
 274
 275         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 276         pm_runtime_get_noresume(&dev->dev);
 277
 278         /* Register the USB 2.0 roothub.
 279          * FIXME: USB core must know to register the USB 2.0 roothub first.
 280          * This is sort of silly, because we could just set the HCD driver flags
 281          * to say USB 2.0, but I'm not sure what the implications would be in
 282          * the other parts of the HCD code.
 283          */
 284         retval = usb_hcd_pci_probe(dev, id);
 285
 286         if (retval)
 287                 goto put_runtime_pm;
 288
 289         /* USB 2.0 roothub is stored in the PCI device now. */
 290         hcd = dev_get_drvdata(&dev->dev);
 291         xhci = hcd_to_xhci(hcd);
 292         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 293                                 pci_name(dev), hcd);
 294         if (!xhci->shared_hcd) {
 295                 retval = -ENOMEM;
 296                 goto dealloc_usb2_hcd;
 297         }
 298
 299         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 300                         IRQF_SHARED);
 301         if (retval)
 302                 goto put_usb3_hcd;
 303         /* Roothub already marked as USB 3.0 speed */
 304
 305         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 306                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 307                 xhci->shared_hcd->can_do_streams = 1;
 308
 309         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 310                 xhci_pme_acpi_rtd3_enable(dev);
 311
 312         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 313         pm_runtime_put_noidle(&dev->dev);
 314
 315         return 0;
 316
 317 put_usb3_hcd:
 318         usb_put_hcd(xhci->shared_hcd);
 319 dealloc_usb2_hcd:
 320         usb_hcd_pci_remove(dev);
 321 put_runtime_pm:
 322         pm_runtime_put_noidle(&dev->dev);
 323         return retval;
 324 }
 325
 326 static void xhci_pci_remove(struct pci_dev *dev)
 327 {
 328         struct xhci_hcd *xhci;
 329
 330         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 331         xhci->xhc_state |= XHCI_STATE_REMOVING;
 332         if (xhci->shared_hcd) {
 333                 usb_remove_hcd(xhci->shared_hcd);
 334                 usb_put_hcd(xhci->shared_hcd);
 335         }
 336
 337         /* Workaround for spurious wakeups at shutdown with HSW */
 338         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 339                 pci_set_power_state(dev, PCI_D3hot);
 340
 341         usb_hcd_pci_remove(dev);
 342 }
 343
 344 #ifdef CONFIG_PM
 345 /*
 346  * In some Intel xHCI controllers, in order to get D3 working,
 347  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 348  * SSIC PORT need to be marked as "unused" before putting xHCI
 349  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 350  * Without this change, xHCI might not enter D3 state.
 351  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 352  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 353  */
 354 static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)
 355 {
 356         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 357         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 358         u32 val;
 359         void __iomem *reg;
 360         int i;
 361
 362         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 363                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 364
 365                 for (i = 0; i < SSIC_PORT_NUM; i++) {
 366                         reg = (void __iomem *) xhci->cap_regs +
 367                                         SSIC_PORT_CFG2 +
 368                                         i * SSIC_PORT_CFG2_OFFSET;
 369
 370                         /*
 371                          * Notify SSIC that SSIC profile programming
 372                          * is not done.
 373                          */
 374                         val = readl(reg) & ~PROG_DONE;
 375                         writel(val, reg);
 376
 377                         /* Mark SSIC port as unused(suspend) or used(resume) */
 378                         val = readl(reg);
 379                         if (suspend)
 380                                 val |= SSIC_PORT_UNUSED;
 381                         else
 382                                 val &= ~SSIC_PORT_UNUSED;
 383                         writel(val, reg);
 384
 385                         /* Notify SSIC that SSIC profile programming is done */
 386                         val = readl(reg) | PROG_DONE;
 387                         writel(val, reg);
 388                         readl(reg);
 389                 }
 390         }
 391
 392         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 393         val = readl(reg);
 394         writel(val | BIT(28), reg);
 395         readl(reg);
 396 }
 397
 398 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 399 {
 400         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 401         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 402
 403         /*
 404          * Systems with the TI redriver that loses port status change events
 405          * need to have the registers polled during D3, so avoid D3cold.
 406          */
 407         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 408                 pdev->no_d3cold = true;
 409
 410         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 411                 xhci_pme_quirk(hcd, true);
 412
 413         return xhci_suspend(xhci, do_wakeup);
 414 }
 415
 416 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 417 {
 418         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 419         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 420         int                     retval = 0;
 421
 422         /* The BIOS on systems with the Intel Panther Point chipset may or may
 423          * not support xHCI natively.  That means that during system resume, it
 424          * may switch the ports back to EHCI so that users can use their
 425          * keyboard to select a kernel from GRUB after resume from hibernate.
 426          *
 427          * The BIOS is supposed to remember whether the OS had xHCI ports
 428          * enabled before resume, and switch the ports back to xHCI when the
 429          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 430          * writers.
 431          *
 432          * Unconditionally switch the ports back to xHCI after a system resume.
 433          * It should not matter whether the EHCI or xHCI controller is
 434          * resumed first. It's enough to do the switchover in xHCI because
 435          * USB core won't notice anything as the hub driver doesn't start
 436          * running again until after all the devices (including both EHCI and
 437          * xHCI host controllers) have been resumed.
 438          */
 439
 440         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 441                 usb_enable_intel_xhci_ports(pdev);
 442
 443         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 444                 xhci_pme_quirk(hcd, false);
 445
 446         retval = xhci_resume(xhci, hibernated);
 447         return retval;
 448 }
 449
 450 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 451 {
 452         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 453         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 454
 455         xhci_shutdown(hcd);
 456
 457         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 458         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 459                 pci_set_power_state(pdev, PCI_D3hot);
 460 }
 461 #endif /* CONFIG_PM */
 462
 463 /*-------------------------------------------------------------------------*/
 464
 465 /* PCI driver selection metadata; PCI hotplugging uses this */
 466 static const struct pci_device_id pci_ids[] = { {
 467         /* handle any USB 3.0 xHCI controller */
 468         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 469         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 470         },
 471         { /* end: all zeroes */ }
 472 };
 473 MODULE_DEVICE_TABLE(pci, pci_ids);
 474
 475 /* pci driver glue; this is a "new style" PCI driver module */
 476 static struct pci_driver xhci_pci_driver = {
 477         .name =         (char *) hcd_name,
 478         .id_table =     pci_ids,
 479
 480         .probe =        xhci_pci_probe,
 481         .remove =       xhci_pci_remove,
 482         /* suspend and resume implemented later */
 483
 484         .shutdown =     usb_hcd_pci_shutdown,
 485 #ifdef CONFIG_PM
 486         .driver = {
 487                 .pm = &usb_hcd_pci_pm_ops
 488         },
 489 #endif
 490 };
 491
 492 static int __init xhci_pci_init(void)
 493 {
 494         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 495 #ifdef CONFIG_PM
 496         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 497         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 498         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 499 #endif
 500         return pci_register_driver(&xhci_pci_driver);
 501 }
 502 module_init(xhci_pci_init);
 503
 504 static void __exit xhci_pci_exit(void)
 505 {
 506         pci_unregister_driver(&xhci_pci_driver);
 507 }
 508 module_exit(xhci_pci_exit);
 509
 510 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 511 MODULE_LICENSE("GPL");