2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
69 #include <linux/dma-mapping.h>
71 #include "xhci-trace.h"
75 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
78 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
81 unsigned long segment_offset;
83 if (!seg || !trb || trb < seg->trbs)
86 segment_offset = trb - seg->trbs;
87 if (segment_offset >= TRBS_PER_SEGMENT)
89 return seg->dma + (segment_offset * sizeof(*trb));
92 static bool trb_is_noop(union xhci_trb *trb)
94 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
97 static bool trb_is_link(union xhci_trb *trb)
99 return TRB_TYPE_LINK_LE32(trb->link.control);
102 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
104 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
107 static bool last_trb_on_ring(struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
113 static bool link_trb_toggles_cycle(union xhci_trb *trb)
115 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
118 static bool last_td_in_urb(struct xhci_td *td)
120 struct urb_priv *urb_priv = td->urb->hcpriv;
122 return urb_priv->num_tds_done == urb_priv->num_tds;
125 static void inc_td_cnt(struct urb *urb)
127 struct urb_priv *urb_priv = urb->hcpriv;
129 urb_priv->num_tds_done++;
132 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
134 if (trb_is_link(trb)) {
135 /* unchain chained link TRBs */
136 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
138 trb->generic.field[0] = 0;
139 trb->generic.field[1] = 0;
140 trb->generic.field[2] = 0;
141 /* Preserve only the cycle bit of this TRB */
142 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
143 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
147 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
148 * TRB is in a new segment. This does not skip over link TRBs, and it does not
149 * effect the ring dequeue or enqueue pointers.
151 static void next_trb(struct xhci_hcd *xhci,
152 struct xhci_ring *ring,
153 struct xhci_segment **seg,
154 union xhci_trb **trb)
156 if (trb_is_link(*trb)) {
158 *trb = ((*seg)->trbs);
165 * See Cycle bit rules. SW is the consumer for the event ring only.
166 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
168 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
170 /* event ring doesn't have link trbs, check for last trb */
171 if (ring->type == TYPE_EVENT) {
172 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
176 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
177 ring->cycle_state ^= 1;
178 ring->deq_seg = ring->deq_seg->next;
179 ring->dequeue = ring->deq_seg->trbs;
183 /* All other rings have link trbs */
184 if (!trb_is_link(ring->dequeue)) {
186 ring->num_trbs_free++;
188 while (trb_is_link(ring->dequeue)) {
189 ring->deq_seg = ring->deq_seg->next;
190 ring->dequeue = ring->deq_seg->trbs;
193 trace_xhci_inc_deq(ring);
199 * See Cycle bit rules. SW is the consumer for the event ring only.
200 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
202 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
203 * chain bit is set), then set the chain bit in all the following link TRBs.
204 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
205 * have their chain bit cleared (so that each Link TRB is a separate TD).
207 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
208 * set, but other sections talk about dealing with the chain bit set. This was
209 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
210 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
212 * @more_trbs_coming: Will you enqueue more TRBs before calling
213 * prepare_transfer()?
215 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
216 bool more_trbs_coming)
219 union xhci_trb *next;
221 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
222 /* If this is not event ring, there is one less usable TRB */
223 if (!trb_is_link(ring->enqueue))
224 ring->num_trbs_free--;
225 next = ++(ring->enqueue);
227 /* Update the dequeue pointer further if that was a link TRB */
228 while (trb_is_link(next)) {
231 * If the caller doesn't plan on enqueueing more TDs before
232 * ringing the doorbell, then we don't want to give the link TRB
233 * to the hardware just yet. We'll give the link TRB back in
234 * prepare_ring() just before we enqueue the TD at the top of
237 if (!chain && !more_trbs_coming)
240 /* If we're not dealing with 0.95 hardware or isoc rings on
241 * AMD 0.96 host, carry over the chain bit of the previous TRB
242 * (which may mean the chain bit is cleared).
244 if (!(ring->type == TYPE_ISOC &&
245 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
246 !xhci_link_trb_quirk(xhci)) {
247 next->link.control &= cpu_to_le32(~TRB_CHAIN);
248 next->link.control |= cpu_to_le32(chain);
250 /* Give this link TRB to the hardware */
252 next->link.control ^= cpu_to_le32(TRB_CYCLE);
254 /* Toggle the cycle bit after the last ring segment. */
255 if (link_trb_toggles_cycle(next))
256 ring->cycle_state ^= 1;
258 ring->enq_seg = ring->enq_seg->next;
259 ring->enqueue = ring->enq_seg->trbs;
260 next = ring->enqueue;
263 trace_xhci_inc_enq(ring);
267 * Check to see if there's room to enqueue num_trbs on the ring and make sure
268 * enqueue pointer will not advance into dequeue segment. See rules above.
270 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
271 unsigned int num_trbs)
273 int num_trbs_in_deq_seg;
275 if (ring->num_trbs_free < num_trbs)
278 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
279 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
280 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
287 /* Ring the host controller doorbell after placing a command on the ring */
288 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
290 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
293 xhci_dbg(xhci, "// Ding dong!\n");
294 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
295 /* Flush PCI posted writes */
296 readl(&xhci->dba->doorbell[0]);
299 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
301 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
304 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
306 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
311 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
312 * If there are other commands waiting then restart the ring and kick the timer.
313 * This must be called with command ring stopped and xhci->lock held.
315 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
316 struct xhci_command *cur_cmd)
318 struct xhci_command *i_cmd;
320 /* Turn all aborted commands in list to no-ops, then restart */
321 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
323 if (i_cmd->status != COMP_COMMAND_ABORTED)
326 i_cmd->status = COMP_COMMAND_RING_STOPPED;
328 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
331 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
334 * caller waiting for completion is called when command
335 * completion event is received for these no-op commands
339 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
341 /* ring command ring doorbell to restart the command ring */
342 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
343 !(xhci->xhc_state & XHCI_STATE_DYING)) {
344 xhci->current_cmd = cur_cmd;
345 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
346 xhci_ring_cmd_db(xhci);
350 /* Must be called with xhci->lock held, releases and aquires lock back */
351 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
353 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
354 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
358 xhci_dbg(xhci, "Abort command ring\n");
360 reinit_completion(&xhci->cmd_ring_stop_completion);
363 * The control bits like command stop, abort are located in lower
364 * dword of the command ring control register.
365 * Some controllers require all 64 bits to be written to abort the ring.
366 * Make sure the upper dword is valid, pointing to the next command,
367 * avoiding corrupting the command ring pointer in case the command ring
368 * is stopped by the time the upper dword is written.
370 next_trb(xhci, NULL, &new_seg, &new_deq);
371 if (trb_is_link(new_deq))
372 next_trb(xhci, NULL, &new_seg, &new_deq);
374 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
375 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
377 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
378 * completion of the Command Abort operation. If CRR is not negated in 5
379 * seconds then driver handles it as if host died (-ENODEV).
380 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
381 * and try to recover a -ETIMEDOUT with a host controller reset.
383 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
384 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
386 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
392 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
393 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
394 * but the completion event in never sent. Wait 2 secs (arbitrary
395 * number) to handle those cases after negation of CMD_RING_RUNNING.
397 spin_unlock_irqrestore(&xhci->lock, flags);
398 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
399 msecs_to_jiffies(2000));
400 spin_lock_irqsave(&xhci->lock, flags);
402 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
403 xhci_cleanup_command_queue(xhci);
405 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
410 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
411 unsigned int slot_id,
412 unsigned int ep_index,
413 unsigned int stream_id)
415 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
416 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
417 unsigned int ep_state = ep->ep_state;
419 /* Don't ring the doorbell for this endpoint if there are pending
420 * cancellations because we don't want to interrupt processing.
421 * We don't want to restart any stream rings if there's a set dequeue
422 * pointer command pending because the device can choose to start any
423 * stream once the endpoint is on the HW schedule.
425 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
426 (ep_state & EP_HALTED))
428 writel(DB_VALUE(ep_index, stream_id), db_addr);
429 /* The CPU has better things to do at this point than wait for a
430 * write-posting flush. It'll get there soon enough.
434 /* Ring the doorbell for any rings with pending URBs */
435 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
436 unsigned int slot_id,
437 unsigned int ep_index)
439 unsigned int stream_id;
440 struct xhci_virt_ep *ep;
442 ep = &xhci->devs[slot_id]->eps[ep_index];
444 /* A ring has pending URBs if its TD list is not empty */
445 if (!(ep->ep_state & EP_HAS_STREAMS)) {
446 if (ep->ring && !(list_empty(&ep->ring->td_list)))
447 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
451 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
453 struct xhci_stream_info *stream_info = ep->stream_info;
454 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
455 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
460 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
461 unsigned int slot_id,
462 unsigned int ep_index)
464 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
465 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
468 if (ep_index >= EP_CTX_PER_DEV) {
469 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
472 if (!xhci->devs[slot_id]) {
473 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
477 return &xhci->devs[slot_id]->eps[ep_index];
480 /* Get the right ring for the given slot_id, ep_index and stream_id.
481 * If the endpoint supports streams, boundary check the URB's stream ID.
482 * If the endpoint doesn't support streams, return the singular endpoint ring.
484 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
485 unsigned int slot_id, unsigned int ep_index,
486 unsigned int stream_id)
488 struct xhci_virt_ep *ep;
490 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
494 /* Common case: no streams */
495 if (!(ep->ep_state & EP_HAS_STREAMS))
498 if (stream_id == 0) {
500 "WARN: Slot ID %u, ep index %u has streams, "
501 "but URB has no stream ID.\n",
506 if (stream_id < ep->stream_info->num_streams)
507 return ep->stream_info->stream_rings[stream_id];
510 "WARN: Slot ID %u, ep index %u has "
511 "stream IDs 1 to %u allocated, "
512 "but stream ID %u is requested.\n",
514 ep->stream_info->num_streams - 1,
521 * Get the hw dequeue pointer xHC stopped on, either directly from the
522 * endpoint context, or if streams are in use from the stream context.
523 * The returned hw_dequeue contains the lowest four bits with cycle state
524 * and possbile stream context type.
526 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
527 unsigned int ep_index, unsigned int stream_id)
529 struct xhci_ep_ctx *ep_ctx;
530 struct xhci_stream_ctx *st_ctx;
531 struct xhci_virt_ep *ep;
533 ep = &vdev->eps[ep_index];
535 if (ep->ep_state & EP_HAS_STREAMS) {
536 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
537 return le64_to_cpu(st_ctx->stream_ring);
539 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
540 return le64_to_cpu(ep_ctx->deq);
544 * Move the xHC's endpoint ring dequeue pointer past cur_td.
545 * Record the new state of the xHC's endpoint ring dequeue segment,
546 * dequeue pointer, stream id, and new consumer cycle state in state.
547 * Update our internal representation of the ring's dequeue pointer.
549 * We do this in three jumps:
550 * - First we update our new ring state to be the same as when the xHC stopped.
551 * - Then we traverse the ring to find the segment that contains
552 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
553 * any link TRBs with the toggle cycle bit set.
554 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
555 * if we've moved it past a link TRB with the toggle cycle bit set.
557 * Some of the uses of xhci_generic_trb are grotty, but if they're done
558 * with correct __le32 accesses they should work fine. Only users of this are
561 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
562 unsigned int slot_id, unsigned int ep_index,
563 unsigned int stream_id, struct xhci_td *cur_td,
564 struct xhci_dequeue_state *state)
566 struct xhci_virt_device *dev = xhci->devs[slot_id];
567 struct xhci_virt_ep *ep = &dev->eps[ep_index];
568 struct xhci_ring *ep_ring;
569 struct xhci_segment *new_seg;
570 union xhci_trb *new_deq;
573 bool cycle_found = false;
574 bool td_last_trb_found = false;
576 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
577 ep_index, stream_id);
579 xhci_warn(xhci, "WARN can't find new dequeue state "
580 "for invalid stream ID %u.\n",
584 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
585 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
586 "Finding endpoint context");
588 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
589 new_seg = ep_ring->deq_seg;
590 new_deq = ep_ring->dequeue;
591 state->new_cycle_state = hw_dequeue & 0x1;
592 state->stream_id = stream_id;
595 * We want to find the pointer, segment and cycle state of the new trb
596 * (the one after current TD's last_trb). We know the cycle state at
597 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
601 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
602 == (dma_addr_t)(hw_dequeue & ~0xf)) {
604 if (td_last_trb_found)
607 if (new_deq == cur_td->last_trb)
608 td_last_trb_found = true;
610 if (cycle_found && trb_is_link(new_deq) &&
611 link_trb_toggles_cycle(new_deq))
612 state->new_cycle_state ^= 0x1;
614 next_trb(xhci, ep_ring, &new_seg, &new_deq);
616 /* Search wrapped around, bail out */
617 if (new_deq == ep->ring->dequeue) {
618 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
619 state->new_deq_seg = NULL;
620 state->new_deq_ptr = NULL;
624 } while (!cycle_found || !td_last_trb_found);
626 state->new_deq_seg = new_seg;
627 state->new_deq_ptr = new_deq;
629 /* Don't update the ring cycle state for the producer (us). */
630 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
631 "Cycle state = 0x%x", state->new_cycle_state);
633 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
634 "New dequeue segment = %p (virtual)",
636 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
637 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
638 "New dequeue pointer = 0x%llx (DMA)",
639 (unsigned long long) addr);
642 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
643 * (The last TRB actually points to the ring enqueue pointer, which is not part
644 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
646 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
647 struct xhci_td *td, bool flip_cycle)
649 struct xhci_segment *seg = td->start_seg;
650 union xhci_trb *trb = td->first_trb;
653 trb_to_noop(trb, TRB_TR_NOOP);
655 /* flip cycle if asked to */
656 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
657 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
659 if (trb == td->last_trb)
662 next_trb(xhci, ep_ring, &seg, &trb);
666 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
667 struct xhci_virt_ep *ep)
669 ep->ep_state &= ~EP_STOP_CMD_PENDING;
670 /* Can't del_timer_sync in interrupt */
671 del_timer(&ep->stop_cmd_timer);
675 * Must be called with xhci->lock held in interrupt context,
676 * releases and re-acquires xhci->lock
678 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
679 struct xhci_td *cur_td, int status)
681 struct urb *urb = cur_td->urb;
682 struct urb_priv *urb_priv = urb->hcpriv;
683 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
685 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
686 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
687 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
688 if (xhci->quirks & XHCI_AMD_PLL_FIX)
689 usb_amd_quirk_pll_enable();
692 xhci_urb_free_priv(urb_priv);
693 usb_hcd_unlink_urb_from_ep(hcd, urb);
694 spin_unlock(&xhci->lock);
695 trace_xhci_urb_giveback(urb);
696 usb_hcd_giveback_urb(hcd, urb, status);
697 spin_lock(&xhci->lock);
700 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
701 struct xhci_ring *ring, struct xhci_td *td)
703 struct device *dev = xhci_to_hcd(xhci)->self.controller;
704 struct xhci_segment *seg = td->bounce_seg;
705 struct urb *urb = td->urb;
708 if (!ring || !seg || !urb)
711 if (usb_urb_dir_out(urb)) {
712 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
717 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
719 /* for in tranfers we need to copy the data from bounce to sg */
721 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
722 seg->bounce_len, seg->bounce_offs);
723 if (len != seg->bounce_len)
724 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
725 len, seg->bounce_len);
727 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
731 seg->bounce_offs = 0;
735 * When we get a command completion for a Stop Endpoint Command, we need to
736 * unlink any cancelled TDs from the ring. There are two ways to do that:
738 * 1. If the HW was in the middle of processing the TD that needs to be
739 * cancelled, then we must move the ring's dequeue pointer past the last TRB
740 * in the TD with a Set Dequeue Pointer Command.
741 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
742 * bit cleared) so that the HW will skip over them.
744 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
745 union xhci_trb *trb, struct xhci_event_cmd *event)
747 unsigned int ep_index;
748 struct xhci_ring *ep_ring;
749 struct xhci_virt_ep *ep;
750 struct xhci_td *cur_td = NULL;
751 struct xhci_td *last_unlinked_td;
752 struct xhci_ep_ctx *ep_ctx;
753 struct xhci_virt_device *vdev;
755 struct xhci_dequeue_state deq_state;
757 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
758 if (!xhci->devs[slot_id])
759 xhci_warn(xhci, "Stop endpoint command "
760 "completion for disabled slot %u\n",
765 memset(&deq_state, 0, sizeof(deq_state));
766 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
768 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
772 vdev = xhci->devs[slot_id];
773 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
774 trace_xhci_handle_cmd_stop_ep(ep_ctx);
776 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
777 struct xhci_td, cancelled_td_list);
779 if (list_empty(&ep->cancelled_td_list)) {
780 xhci_stop_watchdog_timer_in_irq(xhci, ep);
781 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
785 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
786 * We have the xHCI lock, so nothing can modify this list until we drop
787 * it. We're also in the event handler, so we can't get re-interrupted
788 * if another Stop Endpoint command completes
790 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
791 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
792 "Removing canceled TD starting at 0x%llx (dma).",
793 (unsigned long long)xhci_trb_virt_to_dma(
794 cur_td->start_seg, cur_td->first_trb));
795 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
797 /* This shouldn't happen unless a driver is mucking
798 * with the stream ID after submission. This will
799 * leave the TD on the hardware ring, and the hardware
800 * will try to execute it, and may access a buffer
801 * that has already been freed. In the best case, the
802 * hardware will execute it, and the event handler will
803 * ignore the completion event for that TD, since it was
804 * removed from the td_list for that endpoint. In
805 * short, don't muck with the stream ID after
808 xhci_warn(xhci, "WARN Cancelled URB %p "
809 "has invalid stream ID %u.\n",
811 cur_td->urb->stream_id);
812 goto remove_finished_td;
815 * If we stopped on the TD we need to cancel, then we have to
816 * move the xHC endpoint ring dequeue pointer past this TD.
818 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
819 cur_td->urb->stream_id);
822 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
823 cur_td->last_trb, hw_deq, false)) {
824 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
825 cur_td->urb->stream_id,
828 td_to_noop(xhci, ep_ring, cur_td, false);
833 * The event handler won't see a completion for this TD anymore,
834 * so remove it from the endpoint ring's TD list. Keep it in
835 * the cancelled TD list for URB completion later.
837 list_del_init(&cur_td->td_list);
840 xhci_stop_watchdog_timer_in_irq(xhci, ep);
842 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
843 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
844 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
846 xhci_ring_cmd_db(xhci);
848 /* Otherwise ring the doorbell(s) to restart queued transfers */
849 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
853 * Drop the lock and complete the URBs in the cancelled TD list.
854 * New TDs to be cancelled might be added to the end of the list before
855 * we can complete all the URBs for the TDs we already unlinked.
856 * So stop when we've completed the URB for the last TD we unlinked.
859 cur_td = list_first_entry(&ep->cancelled_td_list,
860 struct xhci_td, cancelled_td_list);
861 list_del_init(&cur_td->cancelled_td_list);
863 /* Clean up the cancelled URB */
864 /* Doesn't matter what we pass for status, since the core will
865 * just overwrite it (because the URB has been unlinked).
867 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
868 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
869 inc_td_cnt(cur_td->urb);
870 if (last_td_in_urb(cur_td))
871 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
873 /* Stop processing the cancelled list if the watchdog timer is
876 if (xhci->xhc_state & XHCI_STATE_DYING)
878 } while (cur_td != last_unlinked_td);
880 /* Return to the event handler with xhci->lock re-acquired */
883 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
885 struct xhci_td *cur_td;
888 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
889 list_del_init(&cur_td->td_list);
891 if (!list_empty(&cur_td->cancelled_td_list))
892 list_del_init(&cur_td->cancelled_td_list);
894 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
896 inc_td_cnt(cur_td->urb);
897 if (last_td_in_urb(cur_td))
898 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
902 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
903 int slot_id, int ep_index)
905 struct xhci_td *cur_td;
907 struct xhci_virt_ep *ep;
908 struct xhci_ring *ring;
910 ep = &xhci->devs[slot_id]->eps[ep_index];
911 if ((ep->ep_state & EP_HAS_STREAMS) ||
912 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
915 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
917 ring = ep->stream_info->stream_rings[stream_id];
921 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
922 "Killing URBs for slot ID %u, ep index %u, stream %u",
923 slot_id, ep_index, stream_id);
924 xhci_kill_ring_urbs(xhci, ring);
930 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
931 "Killing URBs for slot ID %u, ep index %u",
933 xhci_kill_ring_urbs(xhci, ring);
936 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
938 list_del_init(&cur_td->cancelled_td_list);
939 inc_td_cnt(cur_td->urb);
941 if (last_td_in_urb(cur_td))
942 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
947 * host controller died, register read returns 0xffffffff
948 * Complete pending commands, mark them ABORTED.
949 * URBs need to be given back as usb core might be waiting with device locks
950 * held for the URBs to finish during device disconnect, blocking host remove.
952 * Call with xhci->lock held.
953 * lock is relased and re-acquired while giving back urb.
955 void xhci_hc_died(struct xhci_hcd *xhci)
959 if (xhci->xhc_state & XHCI_STATE_DYING)
962 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
963 xhci->xhc_state |= XHCI_STATE_DYING;
965 xhci_cleanup_command_queue(xhci);
967 /* return any pending urbs, remove may be waiting for them */
968 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
971 for (j = 0; j < 31; j++)
972 xhci_kill_endpoint_urbs(xhci, i, j);
975 /* inform usb core hc died if PCI remove isn't already handling it */
976 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
977 usb_hc_died(xhci_to_hcd(xhci));
980 /* Watchdog timer function for when a stop endpoint command fails to complete.
981 * In this case, we assume the host controller is broken or dying or dead. The
982 * host may still be completing some other events, so we have to be careful to
983 * let the event ring handler and the URB dequeueing/enqueueing functions know
984 * through xhci->state.
986 * The timer may also fire if the host takes a very long time to respond to the
987 * command, and the stop endpoint command completion handler cannot delete the
988 * timer before the timer function is called. Another endpoint cancellation may
989 * sneak in before the timer function can grab the lock, and that may queue
990 * another stop endpoint command and add the timer back. So we cannot use a
991 * simple flag to say whether there is a pending stop endpoint command for a
992 * particular endpoint.
994 * Instead we use a combination of that flag and checking if a new timer is
997 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
999 struct xhci_hcd *xhci;
1000 struct xhci_virt_ep *ep;
1001 unsigned long flags;
1003 ep = (struct xhci_virt_ep *) arg;
1006 spin_lock_irqsave(&xhci->lock, flags);
1008 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
1009 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
1010 timer_pending(&ep->stop_cmd_timer)) {
1011 spin_unlock_irqrestore(&xhci->lock, flags);
1012 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
1016 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1017 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1022 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1023 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1024 * and try to recover a -ETIMEDOUT with a host controller reset
1028 spin_unlock_irqrestore(&xhci->lock, flags);
1029 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1030 "xHCI host controller is dead.");
1033 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1034 struct xhci_virt_device *dev,
1035 struct xhci_ring *ep_ring,
1036 unsigned int ep_index)
1038 union xhci_trb *dequeue_temp;
1039 int num_trbs_free_temp;
1040 bool revert = false;
1042 num_trbs_free_temp = ep_ring->num_trbs_free;
1043 dequeue_temp = ep_ring->dequeue;
1045 /* If we get two back-to-back stalls, and the first stalled transfer
1046 * ends just before a link TRB, the dequeue pointer will be left on
1047 * the link TRB by the code in the while loop. So we have to update
1048 * the dequeue pointer one segment further, or we'll jump off
1049 * the segment into la-la-land.
1051 if (trb_is_link(ep_ring->dequeue)) {
1052 ep_ring->deq_seg = ep_ring->deq_seg->next;
1053 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1056 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1057 /* We have more usable TRBs */
1058 ep_ring->num_trbs_free++;
1060 if (trb_is_link(ep_ring->dequeue)) {
1061 if (ep_ring->dequeue ==
1062 dev->eps[ep_index].queued_deq_ptr)
1064 ep_ring->deq_seg = ep_ring->deq_seg->next;
1065 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1067 if (ep_ring->dequeue == dequeue_temp) {
1074 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1075 ep_ring->num_trbs_free = num_trbs_free_temp;
1080 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1081 * we need to clear the set deq pending flag in the endpoint ring state, so that
1082 * the TD queueing code can ring the doorbell again. We also need to ring the
1083 * endpoint doorbell to restart the ring, but only if there aren't more
1084 * cancellations pending.
1086 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1087 union xhci_trb *trb, u32 cmd_comp_code)
1089 unsigned int ep_index;
1090 unsigned int stream_id;
1091 struct xhci_ring *ep_ring;
1092 struct xhci_virt_device *dev;
1093 struct xhci_virt_ep *ep;
1094 struct xhci_ep_ctx *ep_ctx;
1095 struct xhci_slot_ctx *slot_ctx;
1097 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1098 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1099 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1103 dev = xhci->devs[slot_id];
1104 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1106 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1108 /* XXX: Harmless??? */
1112 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1113 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1114 trace_xhci_handle_cmd_set_deq(slot_ctx);
1115 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1117 if (cmd_comp_code != COMP_SUCCESS) {
1118 unsigned int ep_state;
1119 unsigned int slot_state;
1121 switch (cmd_comp_code) {
1122 case COMP_TRB_ERROR:
1123 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1125 case COMP_CONTEXT_STATE_ERROR:
1126 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1127 ep_state = GET_EP_CTX_STATE(ep_ctx);
1128 slot_state = le32_to_cpu(slot_ctx->dev_state);
1129 slot_state = GET_SLOT_STATE(slot_state);
1130 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1131 "Slot state = %u, EP state = %u",
1132 slot_state, ep_state);
1134 case COMP_SLOT_NOT_ENABLED_ERROR:
1135 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1139 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1143 /* OK what do we do now? The endpoint state is hosed, and we
1144 * should never get to this point if the synchronization between
1145 * queueing, and endpoint state are correct. This might happen
1146 * if the device gets disconnected after we've finished
1147 * cancelling URBs, which might not be an error...
1151 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1152 if (ep->ep_state & EP_HAS_STREAMS) {
1153 struct xhci_stream_ctx *ctx =
1154 &ep->stream_info->stream_ctx_array[stream_id];
1155 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1157 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1159 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1160 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1161 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1162 ep->queued_deq_ptr) == deq) {
1163 /* Update the ring's dequeue segment and dequeue pointer
1164 * to reflect the new position.
1166 update_ring_for_set_deq_completion(xhci, dev,
1169 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1170 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1171 ep->queued_deq_seg, ep->queued_deq_ptr);
1176 ep->ep_state &= ~SET_DEQ_PENDING;
1177 ep->queued_deq_seg = NULL;
1178 ep->queued_deq_ptr = NULL;
1179 /* Restart any rings with pending URBs */
1180 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1183 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1184 union xhci_trb *trb, u32 cmd_comp_code)
1186 struct xhci_virt_device *vdev;
1187 struct xhci_virt_ep *ep;
1188 struct xhci_ep_ctx *ep_ctx;
1189 unsigned int ep_index;
1191 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1192 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1196 vdev = xhci->devs[slot_id];
1197 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1198 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1200 /* This command will only fail if the endpoint wasn't halted,
1201 * but we don't care.
1203 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1204 "Ignoring reset ep completion code of %u", cmd_comp_code);
1206 /* HW with the reset endpoint quirk needs to have a configure endpoint
1207 * command complete before the endpoint can be used. Queue that here
1208 * because the HW can't handle two commands being queued in a row.
1210 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1211 struct xhci_command *command;
1213 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1217 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1218 "Queueing configure endpoint command");
1219 xhci_queue_configure_endpoint(xhci, command,
1220 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1222 xhci_ring_cmd_db(xhci);
1224 /* Clear our internal halted state */
1225 ep->ep_state &= ~EP_HALTED;
1229 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1230 struct xhci_command *command, u32 cmd_comp_code)
1232 if (cmd_comp_code == COMP_SUCCESS)
1233 command->slot_id = slot_id;
1235 command->slot_id = 0;
1238 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1240 struct xhci_virt_device *virt_dev;
1241 struct xhci_slot_ctx *slot_ctx;
1243 virt_dev = xhci->devs[slot_id];
1247 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1248 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1250 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1251 /* Delete default control endpoint resources */
1252 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1253 xhci_free_virt_device(xhci, slot_id);
1256 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1257 struct xhci_event_cmd *event, u32 cmd_comp_code)
1259 struct xhci_virt_device *virt_dev;
1260 struct xhci_input_control_ctx *ctrl_ctx;
1261 struct xhci_ep_ctx *ep_ctx;
1262 unsigned int ep_index;
1263 unsigned int ep_state;
1264 u32 add_flags, drop_flags;
1267 * Configure endpoint commands can come from the USB core
1268 * configuration or alt setting changes, or because the HW
1269 * needed an extra configure endpoint command after a reset
1270 * endpoint command or streams were being configured.
1271 * If the command was for a halted endpoint, the xHCI driver
1272 * is not waiting on the configure endpoint command.
1274 virt_dev = xhci->devs[slot_id];
1275 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1277 xhci_warn(xhci, "Could not get input context, bad type.\n");
1281 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1282 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1283 /* Input ctx add_flags are the endpoint index plus one */
1284 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1286 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1287 trace_xhci_handle_cmd_config_ep(ep_ctx);
1289 /* A usb_set_interface() call directly after clearing a halted
1290 * condition may race on this quirky hardware. Not worth
1291 * worrying about, since this is prototype hardware. Not sure
1292 * if this will work for streams, but streams support was
1293 * untested on this prototype.
1295 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1296 ep_index != (unsigned int) -1 &&
1297 add_flags - SLOT_FLAG == drop_flags) {
1298 ep_state = virt_dev->eps[ep_index].ep_state;
1299 if (!(ep_state & EP_HALTED))
1301 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1302 "Completed config ep cmd - "
1303 "last ep index = %d, state = %d",
1304 ep_index, ep_state);
1305 /* Clear internal halted state and restart ring(s) */
1306 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1307 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1313 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1315 struct xhci_virt_device *vdev;
1316 struct xhci_slot_ctx *slot_ctx;
1318 vdev = xhci->devs[slot_id];
1319 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1320 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1323 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1324 struct xhci_event_cmd *event)
1326 struct xhci_virt_device *vdev;
1327 struct xhci_slot_ctx *slot_ctx;
1329 vdev = xhci->devs[slot_id];
1330 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1331 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1333 xhci_dbg(xhci, "Completed reset device command.\n");
1334 if (!xhci->devs[slot_id])
1335 xhci_warn(xhci, "Reset device command completion "
1336 "for disabled slot %u\n", slot_id);
1339 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1340 struct xhci_event_cmd *event)
1342 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1343 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1346 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1347 "NEC firmware version %2x.%02x",
1348 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1349 NEC_FW_MINOR(le32_to_cpu(event->status)));
1352 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1354 list_del(&cmd->cmd_list);
1356 if (cmd->completion) {
1357 cmd->status = status;
1358 complete(cmd->completion);
1364 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1366 struct xhci_command *cur_cmd, *tmp_cmd;
1367 xhci->current_cmd = NULL;
1368 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1369 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1372 void xhci_handle_command_timeout(struct work_struct *work)
1374 struct xhci_hcd *xhci;
1375 unsigned long flags;
1378 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1380 spin_lock_irqsave(&xhci->lock, flags);
1383 * If timeout work is pending, or current_cmd is NULL, it means we
1384 * raced with command completion. Command is handled so just return.
1386 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1387 spin_unlock_irqrestore(&xhci->lock, flags);
1390 /* mark this command to be cancelled */
1391 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1393 /* Make sure command ring is running before aborting it */
1394 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1395 if (hw_ring_state == ~(u64)0) {
1397 goto time_out_completed;
1400 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1401 (hw_ring_state & CMD_RING_RUNNING)) {
1402 /* Prevent new doorbell, and start command abort */
1403 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1404 xhci_dbg(xhci, "Command timeout\n");
1405 xhci_abort_cmd_ring(xhci, flags);
1406 goto time_out_completed;
1409 /* host removed. Bail out */
1410 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1411 xhci_dbg(xhci, "host removed, ring start fail?\n");
1412 xhci_cleanup_command_queue(xhci);
1414 goto time_out_completed;
1417 /* command timeout on stopped ring, ring can't be aborted */
1418 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1419 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1422 spin_unlock_irqrestore(&xhci->lock, flags);
1426 static void handle_cmd_completion(struct xhci_hcd *xhci,
1427 struct xhci_event_cmd *event)
1429 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1431 dma_addr_t cmd_dequeue_dma;
1433 union xhci_trb *cmd_trb;
1434 struct xhci_command *cmd;
1437 cmd_dma = le64_to_cpu(event->cmd_trb);
1438 cmd_trb = xhci->cmd_ring->dequeue;
1440 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1442 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1445 * Check whether the completion event is for our internal kept
1448 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1450 "ERROR mismatched command completion event\n");
1454 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1456 cancel_delayed_work(&xhci->cmd_timer);
1458 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1460 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1461 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1462 complete_all(&xhci->cmd_ring_stop_completion);
1466 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1468 "Command completion event does not match command\n");
1473 * Host aborted the command ring, check if the current command was
1474 * supposed to be aborted, otherwise continue normally.
1475 * The command ring is stopped now, but the xHC will issue a Command
1476 * Ring Stopped event which will cause us to restart it.
1478 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1479 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1480 if (cmd->status == COMP_COMMAND_ABORTED) {
1481 if (xhci->current_cmd == cmd)
1482 xhci->current_cmd = NULL;
1487 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1489 case TRB_ENABLE_SLOT:
1490 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1492 case TRB_DISABLE_SLOT:
1493 xhci_handle_cmd_disable_slot(xhci, slot_id);
1496 if (!cmd->completion)
1497 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1500 case TRB_EVAL_CONTEXT:
1503 xhci_handle_cmd_addr_dev(xhci, slot_id);
1506 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1507 le32_to_cpu(cmd_trb->generic.field[3])));
1508 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1511 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1512 le32_to_cpu(cmd_trb->generic.field[3])));
1513 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1516 /* Is this an aborted command turned to NO-OP? */
1517 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1518 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1521 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1522 le32_to_cpu(cmd_trb->generic.field[3])));
1523 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1526 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1527 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1529 slot_id = TRB_TO_SLOT_ID(
1530 le32_to_cpu(cmd_trb->generic.field[3]));
1531 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1533 case TRB_NEC_GET_FW:
1534 xhci_handle_cmd_nec_get_fw(xhci, event);
1537 /* Skip over unknown commands on the event ring */
1538 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1542 /* restart timer if this wasn't the last command */
1543 if (!list_is_singular(&xhci->cmd_list)) {
1544 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1545 struct xhci_command, cmd_list);
1546 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1547 } else if (xhci->current_cmd == cmd) {
1548 xhci->current_cmd = NULL;
1552 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1554 inc_deq(xhci, xhci->cmd_ring);
1557 static void handle_vendor_event(struct xhci_hcd *xhci,
1558 union xhci_trb *event)
1562 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1563 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1564 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1565 handle_cmd_completion(xhci, &event->event_cmd);
1568 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1569 * port registers -- USB 3.0 and USB 2.0).
1571 * Returns a zero-based port number, which is suitable for indexing into each of
1572 * the split roothubs' port arrays and bus state arrays.
1573 * Add one to it in order to call xhci_find_slot_id_by_port.
1575 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1576 struct xhci_hcd *xhci, u32 port_id)
1579 unsigned int num_similar_speed_ports = 0;
1581 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1582 * and usb2_ports are 0-based indexes. Count the number of similar
1583 * speed ports, up to 1 port before this port.
1585 for (i = 0; i < (port_id - 1); i++) {
1586 u8 port_speed = xhci->port_array[i];
1589 * Skip ports that don't have known speeds, or have duplicate
1590 * Extended Capabilities port speed entries.
1592 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1596 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1597 * 1.1 ports are under the USB 2.0 hub. If the port speed
1598 * matches the device speed, it's a similar speed port.
1600 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1601 num_similar_speed_ports++;
1603 return num_similar_speed_ports;
1606 static void handle_device_notification(struct xhci_hcd *xhci,
1607 union xhci_trb *event)
1610 struct usb_device *udev;
1612 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1613 if (!xhci->devs[slot_id]) {
1614 xhci_warn(xhci, "Device Notification event for "
1615 "unused slot %u\n", slot_id);
1619 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1621 udev = xhci->devs[slot_id]->udev;
1622 if (udev && udev->parent)
1623 usb_wakeup_notification(udev->parent, udev->portnum);
1627 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1629 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1630 * If a connection to a USB 1 device is followed by another connection
1631 * to a USB 2 device.
1633 * Reset the PHY after the USB device is disconnected if device speed
1634 * is less than HCD_USB3.
1635 * Retry the reset sequence max of 4 times checking the PLL lock status.
1638 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1640 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1642 u32 retry_count = 4;
1645 /* Assert PHY reset */
1646 writel(0x6F, hcd->regs + 0x1048);
1648 /* De-assert the PHY reset */
1649 writel(0x7F, hcd->regs + 0x1048);
1651 pll_lock_check = readl(hcd->regs + 0x1070);
1652 } while (!(pll_lock_check & 0x1) && --retry_count);
1655 static void handle_port_status(struct xhci_hcd *xhci,
1656 union xhci_trb *event)
1658 struct usb_hcd *hcd;
1660 u32 portsc, cmd_reg;
1663 unsigned int faked_port_index;
1665 struct xhci_bus_state *bus_state;
1666 __le32 __iomem **port_array;
1667 bool bogus_port_status = false;
1669 /* Port status change events always have a successful completion code */
1670 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1672 "WARN: xHC returned failed port status event\n");
1674 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1675 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1677 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1678 if ((port_id <= 0) || (port_id > max_ports)) {
1679 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1680 inc_deq(xhci, xhci->event_ring);
1684 /* Figure out which usb_hcd this port is attached to:
1685 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1687 major_revision = xhci->port_array[port_id - 1];
1689 /* Find the right roothub. */
1690 hcd = xhci_to_hcd(xhci);
1691 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1692 hcd = xhci->shared_hcd;
1695 xhci_dbg(xhci, "No hcd found for port %u event\n", port_id);
1696 bogus_port_status = true;
1700 if (major_revision == 0) {
1701 xhci_warn(xhci, "Event for port %u not in "
1702 "Extended Capabilities, ignoring.\n",
1704 bogus_port_status = true;
1707 if (major_revision == DUPLICATE_ENTRY) {
1708 xhci_warn(xhci, "Event for port %u duplicated in"
1709 "Extended Capabilities, ignoring.\n",
1711 bogus_port_status = true;
1716 * Hardware port IDs reported by a Port Status Change Event include USB
1717 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1718 * resume event, but we first need to translate the hardware port ID
1719 * into the index into the ports on the correct split roothub, and the
1720 * correct bus_state structure.
1722 bus_state = &xhci->bus_state[hcd_index(hcd)];
1723 if (hcd->speed >= HCD_USB3)
1724 port_array = xhci->usb3_ports;
1726 port_array = xhci->usb2_ports;
1727 /* Find the faked port hub number */
1728 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1730 portsc = readl(port_array[faked_port_index]);
1732 trace_xhci_handle_port_status(faked_port_index, portsc);
1734 if (hcd->state == HC_STATE_SUSPENDED) {
1735 xhci_dbg(xhci, "resume root hub\n");
1736 usb_hcd_resume_root_hub(hcd);
1739 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1740 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1742 cmd_reg = readl(&xhci->op_regs->command);
1743 if (!(cmd_reg & CMD_RUN)) {
1744 xhci_warn(xhci, "xHC is not running.\n");
1748 if (DEV_SUPERSPEED_ANY(portsc)) {
1749 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1750 /* Set a flag to say the port signaled remote wakeup,
1751 * so we can tell the difference between the end of
1752 * device and host initiated resume.
1754 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1755 xhci_test_and_clear_bit(xhci, port_array,
1756 faked_port_index, PORT_PLC);
1757 usb_hcd_start_port_resume(&hcd->self, faked_port_index);
1758 xhci_set_link_state(xhci, port_array, faked_port_index,
1760 /* Need to wait until the next link state change
1761 * indicates the device is actually in U0.
1763 bogus_port_status = true;
1765 } else if (!test_bit(faked_port_index,
1766 &bus_state->resuming_ports)) {
1767 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1768 bus_state->resume_done[faked_port_index] = jiffies +
1769 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1770 set_bit(faked_port_index, &bus_state->resuming_ports);
1771 mod_timer(&hcd->rh_timer,
1772 bus_state->resume_done[faked_port_index]);
1773 /* Do the rest in GetPortStatus */
1777 if ((portsc & PORT_PLC) &&
1778 DEV_SUPERSPEED_ANY(portsc) &&
1779 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1780 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1781 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1782 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1783 /* We've just brought the device into U0/1/2 through either the
1784 * Resume state after a device remote wakeup, or through the
1785 * U3Exit state after a host-initiated resume. If it's a device
1786 * initiated remote wake, don't pass up the link state change,
1787 * so the roothub behavior is consistent with external
1788 * USB 3.0 hub behavior.
1790 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1791 faked_port_index + 1);
1792 if (slot_id && xhci->devs[slot_id])
1793 xhci_ring_device(xhci, slot_id);
1794 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1795 xhci_test_and_clear_bit(xhci, port_array,
1796 faked_port_index, PORT_PLC);
1797 usb_wakeup_notification(hcd->self.root_hub,
1798 faked_port_index + 1);
1799 bogus_port_status = true;
1805 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1806 * RExit to a disconnect state). If so, let the the driver know it's
1807 * out of the RExit state.
1809 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1810 test_and_clear_bit(faked_port_index,
1811 &bus_state->rexit_ports)) {
1812 complete(&bus_state->rexit_done[faked_port_index]);
1813 bogus_port_status = true;
1817 if (hcd->speed < HCD_USB3) {
1818 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1820 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1821 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1822 xhci_cavium_reset_phy_quirk(xhci);
1826 /* Update event ring dequeue pointer before dropping the lock */
1827 inc_deq(xhci, xhci->event_ring);
1829 /* Don't make the USB core poll the roothub if we got a bad port status
1830 * change event. Besides, at that point we can't tell which roothub
1831 * (USB 2.0 or USB 3.0) to kick.
1833 if (bogus_port_status)
1837 * xHCI port-status-change events occur when the "or" of all the
1838 * status-change bits in the portsc register changes from 0 to 1.
1839 * New status changes won't cause an event if any other change
1840 * bits are still set. When an event occurs, switch over to
1841 * polling to avoid losing status changes.
1843 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1844 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1845 spin_unlock(&xhci->lock);
1846 /* Pass this up to the core */
1847 usb_hcd_poll_rh_status(hcd);
1848 spin_lock(&xhci->lock);
1852 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1853 * at end_trb, which may be in another segment. If the suspect DMA address is a
1854 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1857 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1858 struct xhci_segment *start_seg,
1859 union xhci_trb *start_trb,
1860 union xhci_trb *end_trb,
1861 dma_addr_t suspect_dma,
1864 dma_addr_t start_dma;
1865 dma_addr_t end_seg_dma;
1866 dma_addr_t end_trb_dma;
1867 struct xhci_segment *cur_seg;
1869 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1870 cur_seg = start_seg;
1875 /* We may get an event for a Link TRB in the middle of a TD */
1876 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1877 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1878 /* If the end TRB isn't in this segment, this is set to 0 */
1879 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1883 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1884 (unsigned long long)suspect_dma,
1885 (unsigned long long)start_dma,
1886 (unsigned long long)end_trb_dma,
1887 (unsigned long long)cur_seg->dma,
1888 (unsigned long long)end_seg_dma);
1890 if (end_trb_dma > 0) {
1891 /* The end TRB is in this segment, so suspect should be here */
1892 if (start_dma <= end_trb_dma) {
1893 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1896 /* Case for one segment with
1897 * a TD wrapped around to the top
1899 if ((suspect_dma >= start_dma &&
1900 suspect_dma <= end_seg_dma) ||
1901 (suspect_dma >= cur_seg->dma &&
1902 suspect_dma <= end_trb_dma))
1907 /* Might still be somewhere in this segment */
1908 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1911 cur_seg = cur_seg->next;
1912 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1913 } while (cur_seg != start_seg);
1918 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1919 unsigned int slot_id, unsigned int ep_index,
1920 unsigned int stream_id,
1921 struct xhci_td *td, union xhci_trb *ep_trb,
1922 enum xhci_ep_reset_type reset_type)
1924 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1925 struct xhci_command *command;
1926 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1930 ep->ep_state |= EP_HALTED;
1932 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1934 if (reset_type == EP_HARD_RESET)
1935 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1937 xhci_ring_cmd_db(xhci);
1940 /* Check if an error has halted the endpoint ring. The class driver will
1941 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1942 * However, a babble and other errors also halt the endpoint ring, and the class
1943 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1944 * Ring Dequeue Pointer command manually.
1946 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1947 struct xhci_ep_ctx *ep_ctx,
1948 unsigned int trb_comp_code)
1950 /* TRB completion codes that may require a manual halt cleanup */
1951 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1952 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1953 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1954 /* The 0.95 spec says a babbling control endpoint
1955 * is not halted. The 0.96 spec says it is. Some HW
1956 * claims to be 0.95 compliant, but it halts the control
1957 * endpoint anyway. Check if a babble halted the
1960 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1966 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1968 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1969 /* Vendor defined "informational" completion code,
1970 * treat as not-an-error.
1972 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1974 xhci_dbg(xhci, "Treating code as success.\n");
1980 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1981 struct xhci_ring *ep_ring, int *status)
1983 struct urb_priv *urb_priv;
1984 struct urb *urb = NULL;
1986 /* Clean up the endpoint's TD list */
1988 urb_priv = urb->hcpriv;
1990 /* if a bounce buffer was used to align this td then unmap it */
1991 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1993 /* Do one last check of the actual transfer length.
1994 * If the host controller said we transferred more data than the buffer
1995 * length, urb->actual_length will be a very big number (since it's
1996 * unsigned). Play it safe and say we didn't transfer anything.
1998 if (urb->actual_length > urb->transfer_buffer_length) {
1999 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
2000 urb->transfer_buffer_length, urb->actual_length);
2001 urb->actual_length = 0;
2004 list_del_init(&td->td_list);
2005 /* Was this TD slated to be cancelled but completed anyway? */
2006 if (!list_empty(&td->cancelled_td_list))
2007 list_del_init(&td->cancelled_td_list);
2010 /* Giveback the urb when all the tds are completed */
2011 if (last_td_in_urb(td)) {
2012 if ((urb->actual_length != urb->transfer_buffer_length &&
2013 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
2014 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2015 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
2016 urb, urb->actual_length,
2017 urb->transfer_buffer_length, *status);
2019 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
2020 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2022 xhci_giveback_urb_in_irq(xhci, td, *status);
2028 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
2029 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2030 struct xhci_virt_ep *ep, int *status)
2032 struct xhci_virt_device *xdev;
2033 struct xhci_ep_ctx *ep_ctx;
2034 struct xhci_ring *ep_ring;
2035 unsigned int slot_id;
2039 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2040 xdev = xhci->devs[slot_id];
2041 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2042 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2043 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2044 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2046 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2047 trb_comp_code == COMP_STOPPED ||
2048 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
2049 /* The Endpoint Stop Command completion will take care of any
2050 * stopped TDs. A stopped TD may be restarted, so don't update
2051 * the ring dequeue pointer or take this TD off any lists yet.
2055 if (trb_comp_code == COMP_STALL_ERROR ||
2056 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2058 /* Issue a reset endpoint command to clear the host side
2059 * halt, followed by a set dequeue command to move the
2060 * dequeue pointer past the TD.
2061 * The class driver clears the device side halt later.
2063 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2064 ep_ring->stream_id, td, ep_trb,
2067 /* Update ring dequeue pointer */
2068 while (ep_ring->dequeue != td->last_trb)
2069 inc_deq(xhci, ep_ring);
2070 inc_deq(xhci, ep_ring);
2073 return xhci_td_cleanup(xhci, td, ep_ring, status);
2076 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2077 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2078 union xhci_trb *stop_trb)
2081 union xhci_trb *trb = ring->dequeue;
2082 struct xhci_segment *seg = ring->deq_seg;
2084 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2085 if (!trb_is_noop(trb) && !trb_is_link(trb))
2086 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2092 * Process control tds, update urb status and actual_length.
2094 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2095 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2096 struct xhci_virt_ep *ep, int *status)
2098 struct xhci_virt_device *xdev;
2099 struct xhci_ring *ep_ring;
2100 unsigned int slot_id;
2102 struct xhci_ep_ctx *ep_ctx;
2104 u32 remaining, requested;
2107 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2108 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2109 xdev = xhci->devs[slot_id];
2110 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2111 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2112 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2113 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2114 requested = td->urb->transfer_buffer_length;
2115 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2117 switch (trb_comp_code) {
2119 if (trb_type != TRB_STATUS) {
2120 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2121 (trb_type == TRB_DATA) ? "data" : "setup");
2122 *status = -ESHUTDOWN;
2127 case COMP_SHORT_PACKET:
2130 case COMP_STOPPED_SHORT_PACKET:
2131 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2132 td->urb->actual_length = remaining;
2134 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2139 td->urb->actual_length = 0;
2143 td->urb->actual_length = requested - remaining;
2146 td->urb->actual_length = requested;
2149 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2153 case COMP_STOPPED_LENGTH_INVALID:
2156 if (!xhci_requires_manual_halt_cleanup(xhci,
2157 ep_ctx, trb_comp_code))
2159 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2160 trb_comp_code, ep_index);
2161 /* else fall through */
2162 case COMP_STALL_ERROR:
2163 /* Did we transfer part of the data (middle) phase? */
2164 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2165 td->urb->actual_length = requested - remaining;
2166 else if (!td->urb_length_set)
2167 td->urb->actual_length = 0;
2171 /* stopped at setup stage, no data transferred */
2172 if (trb_type == TRB_SETUP)
2176 * if on data stage then update the actual_length of the URB and flag it
2177 * as set, so it won't be overwritten in the event for the last TRB.
2179 if (trb_type == TRB_DATA ||
2180 trb_type == TRB_NORMAL) {
2181 td->urb_length_set = true;
2182 td->urb->actual_length = requested - remaining;
2183 xhci_dbg(xhci, "Waiting for status stage event\n");
2187 /* at status stage */
2188 if (!td->urb_length_set)
2189 td->urb->actual_length = requested;
2192 return finish_td(xhci, td, ep_trb, event, ep, status);
2196 * Process isochronous tds, update urb packet status and actual_length.
2198 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2199 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2200 struct xhci_virt_ep *ep, int *status)
2202 struct xhci_ring *ep_ring;
2203 struct urb_priv *urb_priv;
2205 struct usb_iso_packet_descriptor *frame;
2207 bool sum_trbs_for_length = false;
2208 u32 remaining, requested, ep_trb_len;
2209 int short_framestatus;
2211 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2212 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2213 urb_priv = td->urb->hcpriv;
2214 idx = urb_priv->num_tds_done;
2215 frame = &td->urb->iso_frame_desc[idx];
2216 requested = frame->length;
2217 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2218 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2219 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2222 /* handle completion code */
2223 switch (trb_comp_code) {
2226 frame->status = short_framestatus;
2227 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2228 sum_trbs_for_length = true;
2233 case COMP_SHORT_PACKET:
2234 frame->status = short_framestatus;
2235 sum_trbs_for_length = true;
2237 case COMP_BANDWIDTH_OVERRUN_ERROR:
2238 frame->status = -ECOMM;
2240 case COMP_ISOCH_BUFFER_OVERRUN:
2241 case COMP_BABBLE_DETECTED_ERROR:
2242 frame->status = -EOVERFLOW;
2244 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2245 case COMP_STALL_ERROR:
2246 frame->status = -EPROTO;
2248 case COMP_USB_TRANSACTION_ERROR:
2249 frame->status = -EPROTO;
2250 if (ep_trb != td->last_trb)
2254 sum_trbs_for_length = true;
2256 case COMP_STOPPED_SHORT_PACKET:
2257 /* field normally containing residue now contains tranferred */
2258 frame->status = short_framestatus;
2259 requested = remaining;
2261 case COMP_STOPPED_LENGTH_INVALID:
2266 sum_trbs_for_length = true;
2271 if (sum_trbs_for_length)
2272 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2273 ep_trb_len - remaining;
2275 frame->actual_length = requested;
2277 td->urb->actual_length += frame->actual_length;
2279 return finish_td(xhci, td, ep_trb, event, ep, status);
2282 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2283 struct xhci_transfer_event *event,
2284 struct xhci_virt_ep *ep, int *status)
2286 struct xhci_ring *ep_ring;
2287 struct urb_priv *urb_priv;
2288 struct usb_iso_packet_descriptor *frame;
2291 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2292 urb_priv = td->urb->hcpriv;
2293 idx = urb_priv->num_tds_done;
2294 frame = &td->urb->iso_frame_desc[idx];
2296 /* The transfer is partly done. */
2297 frame->status = -EXDEV;
2299 /* calc actual length */
2300 frame->actual_length = 0;
2302 /* Update ring dequeue pointer */
2303 while (ep_ring->dequeue != td->last_trb)
2304 inc_deq(xhci, ep_ring);
2305 inc_deq(xhci, ep_ring);
2307 return xhci_td_cleanup(xhci, td, ep_ring, status);
2311 * Process bulk and interrupt tds, update urb status and actual_length.
2313 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2314 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2315 struct xhci_virt_ep *ep, int *status)
2317 struct xhci_ring *ep_ring;
2319 u32 remaining, requested, ep_trb_len;
2321 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2322 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2323 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2324 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2325 requested = td->urb->transfer_buffer_length;
2327 switch (trb_comp_code) {
2329 /* handle success with untransferred data as short packet */
2330 if (ep_trb != td->last_trb || remaining) {
2331 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2332 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2333 td->urb->ep->desc.bEndpointAddress,
2334 requested, remaining);
2338 case COMP_SHORT_PACKET:
2339 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2340 td->urb->ep->desc.bEndpointAddress,
2341 requested, remaining);
2344 case COMP_STOPPED_SHORT_PACKET:
2345 td->urb->actual_length = remaining;
2347 case COMP_STOPPED_LENGTH_INVALID:
2348 /* stopped on ep trb with invalid length, exclude it */
2357 if (ep_trb == td->last_trb)
2358 td->urb->actual_length = requested - remaining;
2360 td->urb->actual_length =
2361 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2362 ep_trb_len - remaining;
2364 if (remaining > requested) {
2365 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2367 td->urb->actual_length = 0;
2369 return finish_td(xhci, td, ep_trb, event, ep, status);
2373 * If this function returns an error condition, it means it got a Transfer
2374 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2375 * At this point, the host controller is probably hosed and should be reset.
2377 static int handle_tx_event(struct xhci_hcd *xhci,
2378 struct xhci_transfer_event *event)
2380 struct xhci_virt_device *xdev;
2381 struct xhci_virt_ep *ep;
2382 struct xhci_ring *ep_ring;
2383 unsigned int slot_id;
2385 struct xhci_td *td = NULL;
2386 dma_addr_t ep_trb_dma;
2387 struct xhci_segment *ep_seg;
2388 union xhci_trb *ep_trb;
2389 int status = -EINPROGRESS;
2390 struct xhci_ep_ctx *ep_ctx;
2391 struct list_head *tmp;
2394 bool handling_skipped_tds = false;
2396 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2397 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2398 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2399 ep_trb_dma = le64_to_cpu(event->buffer);
2401 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2403 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2407 xdev = xhci->devs[slot_id];
2408 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2409 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2411 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2413 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2418 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2420 switch (trb_comp_code) {
2421 case COMP_STALL_ERROR:
2422 case COMP_USB_TRANSACTION_ERROR:
2423 case COMP_INVALID_STREAM_TYPE_ERROR:
2424 case COMP_INVALID_STREAM_ID_ERROR:
2425 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2426 NULL, NULL, EP_SOFT_RESET);
2428 case COMP_RING_UNDERRUN:
2429 case COMP_RING_OVERRUN:
2430 case COMP_STOPPED_LENGTH_INVALID:
2433 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2439 /* Count current td numbers if ep->skip is set */
2441 list_for_each(tmp, &ep_ring->td_list)
2445 /* Look for common error cases */
2446 switch (trb_comp_code) {
2447 /* Skip codes that require special handling depending on
2451 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2453 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2454 ep_ring->last_td_was_short)
2455 trb_comp_code = COMP_SHORT_PACKET;
2457 xhci_warn_ratelimited(xhci,
2458 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2460 case COMP_SHORT_PACKET:
2462 /* Completion codes for endpoint stopped state */
2464 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2467 case COMP_STOPPED_LENGTH_INVALID:
2469 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2472 case COMP_STOPPED_SHORT_PACKET:
2474 "Stopped with short packet transfer detected for slot %u ep %u\n",
2477 /* Completion codes for endpoint halted state */
2478 case COMP_STALL_ERROR:
2479 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2481 ep->ep_state |= EP_HALTED;
2484 case COMP_SPLIT_TRANSACTION_ERROR:
2485 case COMP_USB_TRANSACTION_ERROR:
2486 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2490 case COMP_BABBLE_DETECTED_ERROR:
2491 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2493 status = -EOVERFLOW;
2495 /* Completion codes for endpoint error state */
2496 case COMP_TRB_ERROR:
2498 "WARN: TRB error for slot %u ep %u on endpoint\n",
2502 /* completion codes not indicating endpoint state change */
2503 case COMP_DATA_BUFFER_ERROR:
2505 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2509 case COMP_BANDWIDTH_OVERRUN_ERROR:
2511 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2514 case COMP_ISOCH_BUFFER_OVERRUN:
2516 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2519 case COMP_RING_UNDERRUN:
2521 * When the Isoch ring is empty, the xHC will generate
2522 * a Ring Overrun Event for IN Isoch endpoint or Ring
2523 * Underrun Event for OUT Isoch endpoint.
2525 xhci_dbg(xhci, "underrun event on endpoint\n");
2526 if (!list_empty(&ep_ring->td_list))
2527 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2528 "still with TDs queued?\n",
2529 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2532 case COMP_RING_OVERRUN:
2533 xhci_dbg(xhci, "overrun event on endpoint\n");
2534 if (!list_empty(&ep_ring->td_list))
2535 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2536 "still with TDs queued?\n",
2537 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2540 case COMP_MISSED_SERVICE_ERROR:
2542 * When encounter missed service error, one or more isoc tds
2543 * may be missed by xHC.
2544 * Set skip flag of the ep_ring; Complete the missed tds as
2545 * short transfer when process the ep_ring next time.
2549 "Miss service interval error for slot %u ep %u, set skip flag\n",
2552 case COMP_NO_PING_RESPONSE_ERROR:
2555 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2559 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2560 /* needs disable slot command to recover */
2562 "WARN: detect an incompatible device for slot %u ep %u",
2567 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2572 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2573 trb_comp_code, slot_id, ep_index);
2578 /* This TRB should be in the TD at the head of this ring's
2581 if (list_empty(&ep_ring->td_list)) {
2583 * Don't print wanings if it's due to a stopped endpoint
2584 * generating an extra completion event if the device
2585 * was suspended. Or, a event for the last TRB of a
2586 * short TD we already got a short event for.
2587 * The short TD is already removed from the TD list.
2590 if (!(trb_comp_code == COMP_STOPPED ||
2591 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2592 ep_ring->last_td_was_short)) {
2593 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2594 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2599 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2605 /* We've skipped all the TDs on the ep ring when ep->skip set */
2606 if (ep->skip && td_num == 0) {
2608 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2613 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2618 /* Is this a TRB in the currently executing TD? */
2619 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2620 td->last_trb, ep_trb_dma, false);
2623 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2624 * is not in the current TD pointed by ep_ring->dequeue because
2625 * that the hardware dequeue pointer still at the previous TRB
2626 * of the current TD. The previous TRB maybe a Link TD or the
2627 * last TRB of the previous TD. The command completion handle
2628 * will take care the rest.
2630 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2631 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2637 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2638 /* Some host controllers give a spurious
2639 * successful event after a short transfer.
2642 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2643 ep_ring->last_td_was_short) {
2644 ep_ring->last_td_was_short = false;
2647 /* HC is busted, give up! */
2649 "ERROR Transfer event TRB DMA ptr not "
2650 "part of current TD ep_index %d "
2651 "comp_code %u\n", ep_index,
2653 trb_in_td(xhci, ep_ring->deq_seg,
2654 ep_ring->dequeue, td->last_trb,
2659 skip_isoc_td(xhci, td, event, ep, &status);
2662 if (trb_comp_code == COMP_SHORT_PACKET)
2663 ep_ring->last_td_was_short = true;
2665 ep_ring->last_td_was_short = false;
2669 "Found td. Clear skip flag for slot %u ep %u.\n",
2674 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2677 trace_xhci_handle_transfer(ep_ring,
2678 (struct xhci_generic_trb *) ep_trb);
2681 * No-op TRB could trigger interrupts in a case where
2682 * a URB was killed and a STALL_ERROR happens right
2683 * after the endpoint ring stopped. Reset the halted
2684 * endpoint. Otherwise, the endpoint remains stalled
2687 if (trb_is_noop(ep_trb)) {
2688 if (trb_comp_code == COMP_STALL_ERROR ||
2689 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2691 xhci_cleanup_halted_endpoint(xhci, slot_id,
2699 /* update the urb's actual_length and give back to the core */
2700 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2701 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2702 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2703 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2705 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2708 handling_skipped_tds = ep->skip &&
2709 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2710 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2713 * Do not update event ring dequeue pointer if we're in a loop
2714 * processing missed tds.
2716 if (!handling_skipped_tds)
2717 inc_deq(xhci, xhci->event_ring);
2720 * If ep->skip is set, it means there are missed tds on the
2721 * endpoint ring need to take care of.
2722 * Process them as short transfer until reach the td pointed by
2725 } while (handling_skipped_tds);
2730 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2731 (unsigned long long) xhci_trb_virt_to_dma(
2732 xhci->event_ring->deq_seg,
2733 xhci->event_ring->dequeue),
2734 lower_32_bits(le64_to_cpu(event->buffer)),
2735 upper_32_bits(le64_to_cpu(event->buffer)),
2736 le32_to_cpu(event->transfer_len),
2737 le32_to_cpu(event->flags));
2742 * This function handles all OS-owned events on the event ring. It may drop
2743 * xhci->lock between event processing (e.g. to pass up port status changes).
2744 * Returns >0 for "possibly more events to process" (caller should call again),
2745 * otherwise 0 if done. In future, <0 returns should indicate error code.
2747 static int xhci_handle_event(struct xhci_hcd *xhci)
2749 union xhci_trb *event;
2750 int update_ptrs = 1;
2753 /* Event ring hasn't been allocated yet. */
2754 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2755 xhci_err(xhci, "ERROR event ring not ready\n");
2759 event = xhci->event_ring->dequeue;
2760 /* Does the HC or OS own the TRB? */
2761 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2762 xhci->event_ring->cycle_state)
2765 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2768 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2769 * speculative reads of the event's flags/data below.
2772 /* FIXME: Handle more event types. */
2773 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2774 case TRB_TYPE(TRB_COMPLETION):
2775 handle_cmd_completion(xhci, &event->event_cmd);
2777 case TRB_TYPE(TRB_PORT_STATUS):
2778 handle_port_status(xhci, event);
2781 case TRB_TYPE(TRB_TRANSFER):
2782 ret = handle_tx_event(xhci, &event->trans_event);
2786 case TRB_TYPE(TRB_DEV_NOTE):
2787 handle_device_notification(xhci, event);
2790 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2792 handle_vendor_event(xhci, event);
2794 xhci_warn(xhci, "ERROR unknown event type %d\n",
2796 le32_to_cpu(event->event_cmd.flags)));
2798 /* Any of the above functions may drop and re-acquire the lock, so check
2799 * to make sure a watchdog timer didn't mark the host as non-responsive.
2801 if (xhci->xhc_state & XHCI_STATE_DYING) {
2802 xhci_dbg(xhci, "xHCI host dying, returning from "
2803 "event handler.\n");
2808 /* Update SW event ring dequeue pointer */
2809 inc_deq(xhci, xhci->event_ring);
2811 /* Are there more items on the event ring? Caller will call us again to
2818 * Update Event Ring Dequeue Pointer:
2819 * - When all events have finished
2820 * - To avoid "Event Ring Full Error" condition
2822 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2823 union xhci_trb *event_ring_deq)
2828 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2829 /* If necessary, update the HW's version of the event ring deq ptr. */
2830 if (event_ring_deq != xhci->event_ring->dequeue) {
2831 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2832 xhci->event_ring->dequeue);
2834 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2836 * Per 4.9.4, Software writes to the ERDP register shall
2837 * always advance the Event Ring Dequeue Pointer value.
2839 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2840 ((u64) deq & (u64) ~ERST_PTR_MASK))
2843 /* Update HC event ring dequeue pointer */
2844 temp_64 &= ERST_PTR_MASK;
2845 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2848 /* Clear the event handler busy flag (RW1C) */
2849 temp_64 |= ERST_EHB;
2850 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2854 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2855 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2856 * indicators of an event TRB error, but we check the status *first* to be safe.
2858 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2860 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2861 union xhci_trb *event_ring_deq;
2862 irqreturn_t ret = IRQ_NONE;
2863 unsigned long flags;
2868 spin_lock_irqsave(&xhci->lock, flags);
2869 /* Check if the xHC generated the interrupt, or the irq is shared */
2870 status = readl(&xhci->op_regs->status);
2871 if (status == ~(u32)0) {
2877 if (!(status & STS_EINT))
2880 if (status & STS_FATAL) {
2881 xhci_warn(xhci, "WARNING: Host System Error\n");
2888 * Clear the op reg interrupt status first,
2889 * so we can receive interrupts from other MSI-X interrupters.
2890 * Write 1 to clear the interrupt status.
2893 writel(status, &xhci->op_regs->status);
2895 if (!hcd->msi_enabled) {
2897 irq_pending = readl(&xhci->ir_set->irq_pending);
2898 irq_pending |= IMAN_IP;
2899 writel(irq_pending, &xhci->ir_set->irq_pending);
2902 if (xhci->xhc_state & XHCI_STATE_DYING ||
2903 xhci->xhc_state & XHCI_STATE_HALTED) {
2904 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2905 "Shouldn't IRQs be disabled?\n");
2906 /* Clear the event handler busy flag (RW1C);
2907 * the event ring should be empty.
2909 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2910 xhci_write_64(xhci, temp_64 | ERST_EHB,
2911 &xhci->ir_set->erst_dequeue);
2916 event_ring_deq = xhci->event_ring->dequeue;
2917 /* FIXME this should be a delayed service routine
2918 * that clears the EHB.
2920 while (xhci_handle_event(xhci) > 0) {
2921 if (event_loop++ < TRBS_PER_SEGMENT / 2)
2923 xhci_update_erst_dequeue(xhci, event_ring_deq);
2927 xhci_update_erst_dequeue(xhci, event_ring_deq);
2931 spin_unlock_irqrestore(&xhci->lock, flags);
2936 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2938 return xhci_irq(hcd);
2941 /**** Endpoint Ring Operations ****/
2944 * Generic function for queueing a TRB on a ring.
2945 * The caller must have checked to make sure there's room on the ring.
2947 * @more_trbs_coming: Will you enqueue more TRBs before calling
2948 * prepare_transfer()?
2950 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2951 bool more_trbs_coming,
2952 u32 field1, u32 field2, u32 field3, u32 field4)
2954 struct xhci_generic_trb *trb;
2956 trb = &ring->enqueue->generic;
2957 trb->field[0] = cpu_to_le32(field1);
2958 trb->field[1] = cpu_to_le32(field2);
2959 trb->field[2] = cpu_to_le32(field3);
2960 /* make sure TRB is fully written before giving it to the controller */
2962 trb->field[3] = cpu_to_le32(field4);
2964 trace_xhci_queue_trb(ring, trb);
2966 inc_enq(xhci, ring, more_trbs_coming);
2970 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2971 * FIXME allocate segments if the ring is full.
2973 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2974 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2976 unsigned int num_trbs_needed;
2978 /* Make sure the endpoint has been added to xHC schedule */
2980 case EP_STATE_DISABLED:
2982 * USB core changed config/interfaces without notifying us,
2983 * or hardware is reporting the wrong state.
2985 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2987 case EP_STATE_ERROR:
2988 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2989 /* FIXME event handling code for error needs to clear it */
2990 /* XXX not sure if this should be -ENOENT or not */
2992 case EP_STATE_HALTED:
2993 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2994 case EP_STATE_STOPPED:
2995 case EP_STATE_RUNNING:
2998 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3000 * FIXME issue Configure Endpoint command to try to get the HC
3001 * back into a known state.
3007 if (room_on_ring(xhci, ep_ring, num_trbs))
3010 if (ep_ring == xhci->cmd_ring) {
3011 xhci_err(xhci, "Do not support expand command ring\n");
3015 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3016 "ERROR no room on ep ring, try ring expansion");
3017 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3018 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3020 xhci_err(xhci, "Ring expansion failed\n");
3025 while (trb_is_link(ep_ring->enqueue)) {
3026 /* If we're not dealing with 0.95 hardware or isoc rings
3027 * on AMD 0.96 host, clear the chain bit.
3029 if (!xhci_link_trb_quirk(xhci) &&
3030 !(ep_ring->type == TYPE_ISOC &&
3031 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3032 ep_ring->enqueue->link.control &=
3033 cpu_to_le32(~TRB_CHAIN);
3035 ep_ring->enqueue->link.control |=
3036 cpu_to_le32(TRB_CHAIN);
3039 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3041 /* Toggle the cycle bit after the last ring segment. */
3042 if (link_trb_toggles_cycle(ep_ring->enqueue))
3043 ep_ring->cycle_state ^= 1;
3045 ep_ring->enq_seg = ep_ring->enq_seg->next;
3046 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3051 static int prepare_transfer(struct xhci_hcd *xhci,
3052 struct xhci_virt_device *xdev,
3053 unsigned int ep_index,
3054 unsigned int stream_id,
3055 unsigned int num_trbs,
3057 unsigned int td_index,
3061 struct urb_priv *urb_priv;
3063 struct xhci_ring *ep_ring;
3064 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3066 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3068 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3073 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3074 num_trbs, mem_flags);
3078 urb_priv = urb->hcpriv;
3079 td = &urb_priv->td[td_index];
3081 INIT_LIST_HEAD(&td->td_list);
3082 INIT_LIST_HEAD(&td->cancelled_td_list);
3084 if (td_index == 0) {
3085 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3091 /* Add this TD to the tail of the endpoint ring's TD list */
3092 list_add_tail(&td->td_list, &ep_ring->td_list);
3093 td->start_seg = ep_ring->enq_seg;
3094 td->first_trb = ep_ring->enqueue;
3099 static unsigned int count_trbs(u64 addr, u64 len)
3101 unsigned int num_trbs;
3103 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3111 static inline unsigned int count_trbs_needed(struct urb *urb)
3113 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3116 static unsigned int count_sg_trbs_needed(struct urb *urb)
3118 struct scatterlist *sg;
3119 unsigned int i, len, full_len, num_trbs = 0;
3121 full_len = urb->transfer_buffer_length;
3123 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3124 len = sg_dma_len(sg);
3125 num_trbs += count_trbs(sg_dma_address(sg), len);
3126 len = min_t(unsigned int, len, full_len);
3135 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3139 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3140 len = urb->iso_frame_desc[i].length;
3142 return count_trbs(addr, len);
3145 static void check_trb_math(struct urb *urb, int running_total)
3147 if (unlikely(running_total != urb->transfer_buffer_length))
3148 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3149 "queued %#x (%d), asked for %#x (%d)\n",
3151 urb->ep->desc.bEndpointAddress,
3152 running_total, running_total,
3153 urb->transfer_buffer_length,
3154 urb->transfer_buffer_length);
3157 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3158 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3159 struct xhci_generic_trb *start_trb)
3162 * Pass all the TRBs to the hardware at once and make sure this write
3167 start_trb->field[3] |= cpu_to_le32(start_cycle);
3169 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3170 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3173 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3174 struct xhci_ep_ctx *ep_ctx)
3179 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3180 ep_interval = urb->interval;
3182 /* Convert to microframes */
3183 if (urb->dev->speed == USB_SPEED_LOW ||
3184 urb->dev->speed == USB_SPEED_FULL)
3187 /* FIXME change this to a warning and a suggestion to use the new API
3188 * to set the polling interval (once the API is added).
3190 if (xhci_interval != ep_interval) {
3191 dev_dbg_ratelimited(&urb->dev->dev,
3192 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3193 ep_interval, ep_interval == 1 ? "" : "s",
3194 xhci_interval, xhci_interval == 1 ? "" : "s");
3195 urb->interval = xhci_interval;
3196 /* Convert back to frames for LS/FS devices */
3197 if (urb->dev->speed == USB_SPEED_LOW ||
3198 urb->dev->speed == USB_SPEED_FULL)
3204 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3205 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3206 * (comprised of sg list entries) can take several service intervals to
3209 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3210 struct urb *urb, int slot_id, unsigned int ep_index)
3212 struct xhci_ep_ctx *ep_ctx;
3214 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3215 check_interval(xhci, urb, ep_ctx);
3217 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3221 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3222 * packets remaining in the TD (*not* including this TRB).
3224 * Total TD packet count = total_packet_count =
3225 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3227 * Packets transferred up to and including this TRB = packets_transferred =
3228 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3230 * TD size = total_packet_count - packets_transferred
3232 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3233 * including this TRB, right shifted by 10
3235 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3236 * This is taken care of in the TRB_TD_SIZE() macro
3238 * The last TRB in a TD must have the TD size set to zero.
3240 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3241 int trb_buff_len, unsigned int td_total_len,
3242 struct urb *urb, bool more_trbs_coming)
3244 u32 maxp, total_packet_count;
3246 /* MTK xHCI 0.96 contains some features from 1.0 */
3247 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3248 return ((td_total_len - transferred) >> 10);
3250 /* One TRB with a zero-length data packet. */
3251 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3252 trb_buff_len == td_total_len)
3255 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3256 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3259 maxp = usb_endpoint_maxp(&urb->ep->desc);
3260 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3262 /* Queueing functions don't count the current TRB into transferred */
3263 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3267 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3268 u32 *trb_buff_len, struct xhci_segment *seg)
3270 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3271 unsigned int unalign;
3272 unsigned int max_pkt;
3276 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3277 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3279 /* we got lucky, last normal TRB data on segment is packet aligned */
3283 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3284 unalign, *trb_buff_len);
3286 /* is the last nornal TRB alignable by splitting it */
3287 if (*trb_buff_len > unalign) {
3288 *trb_buff_len -= unalign;
3289 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3294 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3295 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3296 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3298 new_buff_len = max_pkt - (enqd_len % max_pkt);
3300 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3301 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3303 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3304 if (usb_urb_dir_out(urb)) {
3306 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3307 seg->bounce_buf, new_buff_len, enqd_len);
3308 if (len != new_buff_len)
3309 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3312 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3315 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3316 max_pkt, DMA_TO_DEVICE);
3318 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3319 max_pkt, DMA_FROM_DEVICE);
3322 if (dma_mapping_error(dev, seg->bounce_dma)) {
3323 /* try without aligning. Some host controllers survive */
3324 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3327 *trb_buff_len = new_buff_len;
3328 seg->bounce_len = new_buff_len;
3329 seg->bounce_offs = enqd_len;
3331 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3336 /* This is very similar to what ehci-q.c qtd_fill() does */
3337 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3338 struct urb *urb, int slot_id, unsigned int ep_index)
3340 struct xhci_ring *ring;
3341 struct urb_priv *urb_priv;
3343 struct xhci_generic_trb *start_trb;
3344 struct scatterlist *sg = NULL;
3345 bool more_trbs_coming = true;
3346 bool need_zero_pkt = false;
3347 bool first_trb = true;
3348 unsigned int num_trbs;
3349 unsigned int start_cycle, num_sgs = 0;
3350 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3352 u32 field, length_field, remainder;
3353 u64 addr, send_addr;
3355 ring = xhci_urb_to_transfer_ring(xhci, urb);
3359 full_len = urb->transfer_buffer_length;
3360 /* If we have scatter/gather list, we use it. */
3362 num_sgs = urb->num_mapped_sgs;
3364 addr = (u64) sg_dma_address(sg);
3365 block_len = sg_dma_len(sg);
3366 num_trbs = count_sg_trbs_needed(urb);
3368 num_trbs = count_trbs_needed(urb);
3369 addr = (u64) urb->transfer_dma;
3370 block_len = full_len;
3372 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3373 ep_index, urb->stream_id,
3374 num_trbs, urb, 0, mem_flags);
3375 if (unlikely(ret < 0))
3378 urb_priv = urb->hcpriv;
3380 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3381 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3382 need_zero_pkt = true;
3384 td = &urb_priv->td[0];
3387 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3388 * until we've finished creating all the other TRBs. The ring's cycle
3389 * state may change as we enqueue the other TRBs, so save it too.
3391 start_trb = &ring->enqueue->generic;
3392 start_cycle = ring->cycle_state;
3395 /* Queue the TRBs, even if they are zero-length */
3396 for (enqd_len = 0; first_trb || enqd_len < full_len;
3397 enqd_len += trb_buff_len) {
3398 field = TRB_TYPE(TRB_NORMAL);
3400 /* TRB buffer should not cross 64KB boundaries */
3401 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3402 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3404 if (enqd_len + trb_buff_len > full_len)
3405 trb_buff_len = full_len - enqd_len;
3407 /* Don't change the cycle bit of the first TRB until later */
3410 if (start_cycle == 0)
3413 field |= ring->cycle_state;
3415 /* Chain all the TRBs together; clear the chain bit in the last
3416 * TRB to indicate it's the last TRB in the chain.
3418 if (enqd_len + trb_buff_len < full_len) {
3420 if (trb_is_link(ring->enqueue + 1)) {
3421 if (xhci_align_td(xhci, urb, enqd_len,
3424 send_addr = ring->enq_seg->bounce_dma;
3425 /* assuming TD won't span 2 segs */
3426 td->bounce_seg = ring->enq_seg;
3430 if (enqd_len + trb_buff_len >= full_len) {
3431 field &= ~TRB_CHAIN;
3433 more_trbs_coming = false;
3434 td->last_trb = ring->enqueue;
3437 /* Only set interrupt on short packet for IN endpoints */
3438 if (usb_urb_dir_in(urb))
3441 /* Set the TRB length, TD size, and interrupter fields. */
3442 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3443 full_len, urb, more_trbs_coming);
3445 length_field = TRB_LEN(trb_buff_len) |
3446 TRB_TD_SIZE(remainder) |
3449 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3450 lower_32_bits(send_addr),
3451 upper_32_bits(send_addr),
3455 addr += trb_buff_len;
3456 sent_len = trb_buff_len;
3458 while (sg && sent_len >= block_len) {
3461 sent_len -= block_len;
3463 if (num_sgs != 0 && sg) {
3464 block_len = sg_dma_len(sg);
3465 addr = (u64) sg_dma_address(sg);
3469 block_len -= sent_len;
3473 if (need_zero_pkt) {
3474 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3475 ep_index, urb->stream_id,
3476 1, urb, 1, mem_flags);
3477 urb_priv->td[1].last_trb = ring->enqueue;
3478 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3479 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3482 check_trb_math(urb, enqd_len);
3483 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3484 start_cycle, start_trb);
3488 /* Caller must have locked xhci->lock */
3489 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3490 struct urb *urb, int slot_id, unsigned int ep_index)
3492 struct xhci_ring *ep_ring;
3495 struct usb_ctrlrequest *setup;
3496 struct xhci_generic_trb *start_trb;
3499 struct urb_priv *urb_priv;
3502 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3507 * Need to copy setup packet into setup TRB, so we can't use the setup
3510 if (!urb->setup_packet)
3513 /* 1 TRB for setup, 1 for status */
3516 * Don't need to check if we need additional event data and normal TRBs,
3517 * since data in control transfers will never get bigger than 16MB
3518 * XXX: can we get a buffer that crosses 64KB boundaries?
3520 if (urb->transfer_buffer_length > 0)
3522 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3523 ep_index, urb->stream_id,
3524 num_trbs, urb, 0, mem_flags);
3528 urb_priv = urb->hcpriv;
3529 td = &urb_priv->td[0];
3532 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3533 * until we've finished creating all the other TRBs. The ring's cycle
3534 * state may change as we enqueue the other TRBs, so save it too.
3536 start_trb = &ep_ring->enqueue->generic;
3537 start_cycle = ep_ring->cycle_state;
3539 /* Queue setup TRB - see section 6.4.1.2.1 */
3540 /* FIXME better way to translate setup_packet into two u32 fields? */
3541 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3543 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3544 if (start_cycle == 0)
3547 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3548 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3549 if (urb->transfer_buffer_length > 0) {
3550 if (setup->bRequestType & USB_DIR_IN)
3551 field |= TRB_TX_TYPE(TRB_DATA_IN);
3553 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3557 queue_trb(xhci, ep_ring, true,
3558 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3559 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3560 TRB_LEN(8) | TRB_INTR_TARGET(0),
3561 /* Immediate data in pointer */
3564 /* If there's data, queue data TRBs */
3565 /* Only set interrupt on short packet for IN endpoints */
3566 if (usb_urb_dir_in(urb))
3567 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3569 field = TRB_TYPE(TRB_DATA);
3571 if (urb->transfer_buffer_length > 0) {
3572 u32 length_field, remainder;
3574 remainder = xhci_td_remainder(xhci, 0,
3575 urb->transfer_buffer_length,
3576 urb->transfer_buffer_length,
3578 length_field = TRB_LEN(urb->transfer_buffer_length) |
3579 TRB_TD_SIZE(remainder) |
3581 if (setup->bRequestType & USB_DIR_IN)
3582 field |= TRB_DIR_IN;
3583 queue_trb(xhci, ep_ring, true,
3584 lower_32_bits(urb->transfer_dma),
3585 upper_32_bits(urb->transfer_dma),
3587 field | ep_ring->cycle_state);
3590 /* Save the DMA address of the last TRB in the TD */
3591 td->last_trb = ep_ring->enqueue;
3593 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3594 /* If the device sent data, the status stage is an OUT transfer */
3595 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3599 queue_trb(xhci, ep_ring, false,
3603 /* Event on completion */
3604 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3606 giveback_first_trb(xhci, slot_id, ep_index, 0,
3607 start_cycle, start_trb);
3612 * The transfer burst count field of the isochronous TRB defines the number of
3613 * bursts that are required to move all packets in this TD. Only SuperSpeed
3614 * devices can burst up to bMaxBurst number of packets per service interval.
3615 * This field is zero based, meaning a value of zero in the field means one
3616 * burst. Basically, for everything but SuperSpeed devices, this field will be
3617 * zero. Only xHCI 1.0 host controllers support this field.
3619 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3620 struct urb *urb, unsigned int total_packet_count)
3622 unsigned int max_burst;
3624 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3627 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3628 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3632 * Returns the number of packets in the last "burst" of packets. This field is
3633 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3634 * the last burst packet count is equal to the total number of packets in the
3635 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3636 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3637 * contain 1 to (bMaxBurst + 1) packets.
3639 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3640 struct urb *urb, unsigned int total_packet_count)
3642 unsigned int max_burst;
3643 unsigned int residue;
3645 if (xhci->hci_version < 0x100)
3648 if (urb->dev->speed >= USB_SPEED_SUPER) {
3649 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3650 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3651 residue = total_packet_count % (max_burst + 1);
3652 /* If residue is zero, the last burst contains (max_burst + 1)
3653 * number of packets, but the TLBPC field is zero-based.
3659 if (total_packet_count == 0)
3661 return total_packet_count - 1;
3665 * Calculates Frame ID field of the isochronous TRB identifies the
3666 * target frame that the Interval associated with this Isochronous
3667 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3669 * Returns actual frame id on success, negative value on error.
3671 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3672 struct urb *urb, int index)
3674 int start_frame, ist, ret = 0;
3675 int start_frame_id, end_frame_id, current_frame_id;
3677 if (urb->dev->speed == USB_SPEED_LOW ||
3678 urb->dev->speed == USB_SPEED_FULL)
3679 start_frame = urb->start_frame + index * urb->interval;
3681 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3683 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3685 * If bit [3] of IST is cleared to '0', software can add a TRB no
3686 * later than IST[2:0] Microframes before that TRB is scheduled to
3688 * If bit [3] of IST is set to '1', software can add a TRB no later
3689 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3691 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3692 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3695 /* Software shall not schedule an Isoch TD with a Frame ID value that
3696 * is less than the Start Frame ID or greater than the End Frame ID,
3699 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3700 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3702 * Both the End Frame ID and Start Frame ID values are calculated
3703 * in microframes. When software determines the valid Frame ID value;
3704 * The End Frame ID value should be rounded down to the nearest Frame
3705 * boundary, and the Start Frame ID value should be rounded up to the
3706 * nearest Frame boundary.
3708 current_frame_id = readl(&xhci->run_regs->microframe_index);
3709 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3710 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3712 start_frame &= 0x7ff;
3713 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3714 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3716 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3717 __func__, index, readl(&xhci->run_regs->microframe_index),
3718 start_frame_id, end_frame_id, start_frame);
3720 if (start_frame_id < end_frame_id) {
3721 if (start_frame > end_frame_id ||
3722 start_frame < start_frame_id)
3724 } else if (start_frame_id > end_frame_id) {
3725 if ((start_frame > end_frame_id &&
3726 start_frame < start_frame_id))
3733 if (ret == -EINVAL || start_frame == start_frame_id) {
3734 start_frame = start_frame_id + 1;
3735 if (urb->dev->speed == USB_SPEED_LOW ||
3736 urb->dev->speed == USB_SPEED_FULL)
3737 urb->start_frame = start_frame;
3739 urb->start_frame = start_frame << 3;
3745 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3746 start_frame, current_frame_id, index,
3747 start_frame_id, end_frame_id);
3748 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3755 /* This is for isoc transfer */
3756 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3757 struct urb *urb, int slot_id, unsigned int ep_index)
3759 struct xhci_ring *ep_ring;
3760 struct urb_priv *urb_priv;
3762 int num_tds, trbs_per_td;
3763 struct xhci_generic_trb *start_trb;
3766 u32 field, length_field;
3767 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3768 u64 start_addr, addr;
3770 bool more_trbs_coming;
3771 struct xhci_virt_ep *xep;
3774 xep = &xhci->devs[slot_id]->eps[ep_index];
3775 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3777 num_tds = urb->number_of_packets;
3779 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3782 start_addr = (u64) urb->transfer_dma;
3783 start_trb = &ep_ring->enqueue->generic;
3784 start_cycle = ep_ring->cycle_state;
3786 urb_priv = urb->hcpriv;
3787 /* Queue the TRBs for each TD, even if they are zero-length */
3788 for (i = 0; i < num_tds; i++) {
3789 unsigned int total_pkt_count, max_pkt;
3790 unsigned int burst_count, last_burst_pkt_count;
3795 addr = start_addr + urb->iso_frame_desc[i].offset;
3796 td_len = urb->iso_frame_desc[i].length;
3797 td_remain_len = td_len;
3798 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3799 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3801 /* A zero-length transfer still involves at least one packet. */
3802 if (total_pkt_count == 0)
3804 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3805 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3806 urb, total_pkt_count);
3808 trbs_per_td = count_isoc_trbs_needed(urb, i);
3810 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3811 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3817 td = &urb_priv->td[i];
3819 /* use SIA as default, if frame id is used overwrite it */
3820 sia_frame_id = TRB_SIA;
3821 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3822 HCC_CFC(xhci->hcc_params)) {
3823 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3825 sia_frame_id = TRB_FRAME_ID(frame_id);
3828 * Set isoc specific data for the first TRB in a TD.
3829 * Prevent HW from getting the TRBs by keeping the cycle state
3830 * inverted in the first TDs isoc TRB.
3832 field = TRB_TYPE(TRB_ISOC) |
3833 TRB_TLBPC(last_burst_pkt_count) |
3835 (i ? ep_ring->cycle_state : !start_cycle);
3837 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3838 if (!xep->use_extended_tbc)
3839 field |= TRB_TBC(burst_count);
3841 /* fill the rest of the TRB fields, and remaining normal TRBs */
3842 for (j = 0; j < trbs_per_td; j++) {
3845 /* only first TRB is isoc, overwrite otherwise */
3847 field = TRB_TYPE(TRB_NORMAL) |
3848 ep_ring->cycle_state;
3850 /* Only set interrupt on short packet for IN EPs */
3851 if (usb_urb_dir_in(urb))
3854 /* Set the chain bit for all except the last TRB */
3855 if (j < trbs_per_td - 1) {
3856 more_trbs_coming = true;
3859 more_trbs_coming = false;
3860 td->last_trb = ep_ring->enqueue;
3862 /* set BEI, except for the last TD */
3863 if (xhci->hci_version >= 0x100 &&
3864 !(xhci->quirks & XHCI_AVOID_BEI) &&
3868 /* Calculate TRB length */
3869 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3870 if (trb_buff_len > td_remain_len)
3871 trb_buff_len = td_remain_len;
3873 /* Set the TRB length, TD size, & interrupter fields. */
3874 remainder = xhci_td_remainder(xhci, running_total,
3875 trb_buff_len, td_len,
3876 urb, more_trbs_coming);
3878 length_field = TRB_LEN(trb_buff_len) |
3881 /* xhci 1.1 with ETE uses TD Size field for TBC */
3882 if (first_trb && xep->use_extended_tbc)
3883 length_field |= TRB_TD_SIZE_TBC(burst_count);
3885 length_field |= TRB_TD_SIZE(remainder);
3888 queue_trb(xhci, ep_ring, more_trbs_coming,
3889 lower_32_bits(addr),
3890 upper_32_bits(addr),
3893 running_total += trb_buff_len;
3895 addr += trb_buff_len;
3896 td_remain_len -= trb_buff_len;
3899 /* Check TD length */
3900 if (running_total != td_len) {
3901 xhci_err(xhci, "ISOC TD length unmatch\n");
3907 /* store the next frame id */
3908 if (HCC_CFC(xhci->hcc_params))
3909 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3911 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3912 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3913 usb_amd_quirk_pll_disable();
3915 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3917 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3918 start_cycle, start_trb);
3921 /* Clean up a partially enqueued isoc transfer. */
3923 for (i--; i >= 0; i--)
3924 list_del_init(&urb_priv->td[i].td_list);
3926 /* Use the first TD as a temporary variable to turn the TDs we've queued
3927 * into No-ops with a software-owned cycle bit. That way the hardware
3928 * won't accidentally start executing bogus TDs when we partially
3929 * overwrite them. td->first_trb and td->start_seg are already set.
3931 urb_priv->td[0].last_trb = ep_ring->enqueue;
3932 /* Every TRB except the first & last will have its cycle bit flipped. */
3933 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3935 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3936 ep_ring->enqueue = urb_priv->td[0].first_trb;
3937 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3938 ep_ring->cycle_state = start_cycle;
3939 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3940 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3945 * Check transfer ring to guarantee there is enough room for the urb.
3946 * Update ISO URB start_frame and interval.
3947 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3948 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3949 * Contiguous Frame ID is not supported by HC.
3951 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3952 struct urb *urb, int slot_id, unsigned int ep_index)
3954 struct xhci_virt_device *xdev;
3955 struct xhci_ring *ep_ring;
3956 struct xhci_ep_ctx *ep_ctx;
3958 int num_tds, num_trbs, i;
3960 struct xhci_virt_ep *xep;
3963 xdev = xhci->devs[slot_id];
3964 xep = &xhci->devs[slot_id]->eps[ep_index];
3965 ep_ring = xdev->eps[ep_index].ring;
3966 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3969 num_tds = urb->number_of_packets;
3970 for (i = 0; i < num_tds; i++)
3971 num_trbs += count_isoc_trbs_needed(urb, i);
3973 /* Check the ring to guarantee there is enough room for the whole urb.
3974 * Do not insert any td of the urb to the ring if the check failed.
3976 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3977 num_trbs, mem_flags);
3982 * Check interval value. This should be done before we start to
3983 * calculate the start frame value.
3985 check_interval(xhci, urb, ep_ctx);
3987 /* Calculate the start frame and put it in urb->start_frame. */
3988 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3989 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3990 urb->start_frame = xep->next_frame_id;
3991 goto skip_start_over;
3995 start_frame = readl(&xhci->run_regs->microframe_index);
3996 start_frame &= 0x3fff;
3998 * Round up to the next frame and consider the time before trb really
3999 * gets scheduled by hardare.
4001 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4002 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4004 start_frame += ist + XHCI_CFC_DELAY;
4005 start_frame = roundup(start_frame, 8);
4008 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4009 * is greate than 8 microframes.
4011 if (urb->dev->speed == USB_SPEED_LOW ||
4012 urb->dev->speed == USB_SPEED_FULL) {
4013 start_frame = roundup(start_frame, urb->interval << 3);
4014 urb->start_frame = start_frame >> 3;
4016 start_frame = roundup(start_frame, urb->interval);
4017 urb->start_frame = start_frame;
4021 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4023 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4026 /**** Command Ring Operations ****/
4028 /* Generic function for queueing a command TRB on the command ring.
4029 * Check to make sure there's room on the command ring for one command TRB.
4030 * Also check that there's room reserved for commands that must not fail.
4031 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4032 * then only check for the number of reserved spots.
4033 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4034 * because the command event handler may want to resubmit a failed command.
4036 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4037 u32 field1, u32 field2,
4038 u32 field3, u32 field4, bool command_must_succeed)
4040 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4043 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4044 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4045 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4049 if (!command_must_succeed)
4052 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4053 reserved_trbs, GFP_ATOMIC);
4055 xhci_err(xhci, "ERR: No room for command on command ring\n");
4056 if (command_must_succeed)
4057 xhci_err(xhci, "ERR: Reserved TRB counting for "
4058 "unfailable commands failed.\n");
4062 cmd->command_trb = xhci->cmd_ring->enqueue;
4064 /* if there are no other commands queued we start the timeout timer */
4065 if (list_empty(&xhci->cmd_list)) {
4066 xhci->current_cmd = cmd;
4067 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4070 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4072 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4073 field4 | xhci->cmd_ring->cycle_state);
4077 /* Queue a slot enable or disable request on the command ring */
4078 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4079 u32 trb_type, u32 slot_id)
4081 return queue_command(xhci, cmd, 0, 0, 0,
4082 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4085 /* Queue an address device command TRB */
4086 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4087 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4089 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4090 upper_32_bits(in_ctx_ptr), 0,
4091 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4092 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4095 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4096 u32 field1, u32 field2, u32 field3, u32 field4)
4098 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4101 /* Queue a reset device command TRB */
4102 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4105 return queue_command(xhci, cmd, 0, 0, 0,
4106 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4110 /* Queue a configure endpoint command TRB */
4111 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4112 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4113 u32 slot_id, bool command_must_succeed)
4115 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4116 upper_32_bits(in_ctx_ptr), 0,
4117 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4118 command_must_succeed);
4121 /* Queue an evaluate context command TRB */
4122 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4123 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4125 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4126 upper_32_bits(in_ctx_ptr), 0,
4127 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4128 command_must_succeed);
4132 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4133 * activity on an endpoint that is about to be suspended.
4135 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4136 int slot_id, unsigned int ep_index, int suspend)
4138 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4139 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4140 u32 type = TRB_TYPE(TRB_STOP_RING);
4141 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4143 return queue_command(xhci, cmd, 0, 0, 0,
4144 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4147 /* Set Transfer Ring Dequeue Pointer command */
4148 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4149 unsigned int slot_id, unsigned int ep_index,
4150 struct xhci_dequeue_state *deq_state)
4153 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4154 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4155 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4157 u32 type = TRB_TYPE(TRB_SET_DEQ);
4158 struct xhci_virt_ep *ep;
4159 struct xhci_command *cmd;
4162 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4163 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4164 deq_state->new_deq_seg,
4165 (unsigned long long)deq_state->new_deq_seg->dma,
4166 deq_state->new_deq_ptr,
4167 (unsigned long long)xhci_trb_virt_to_dma(
4168 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4169 deq_state->new_cycle_state);
4171 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4172 deq_state->new_deq_ptr);
4174 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4175 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4176 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4179 ep = &xhci->devs[slot_id]->eps[ep_index];
4180 if ((ep->ep_state & SET_DEQ_PENDING)) {
4181 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4182 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4186 /* This function gets called from contexts where it cannot sleep */
4187 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
4191 ep->queued_deq_seg = deq_state->new_deq_seg;
4192 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4193 if (deq_state->stream_id)
4194 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4195 ret = queue_command(xhci, cmd,
4196 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4197 upper_32_bits(addr), trb_stream_id,
4198 trb_slot_id | trb_ep_index | type, false);
4200 xhci_free_command(xhci, cmd);
4204 /* Stop the TD queueing code from ringing the doorbell until
4205 * this command completes. The HC won't set the dequeue pointer
4206 * if the ring is running, and ringing the doorbell starts the
4209 ep->ep_state |= SET_DEQ_PENDING;
4212 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4213 int slot_id, unsigned int ep_index,
4214 enum xhci_ep_reset_type reset_type)
4216 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4217 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4218 u32 type = TRB_TYPE(TRB_RESET_EP);
4220 if (reset_type == EP_SOFT_RESET)
4223 return queue_command(xhci, cmd, 0, 0, 0,
4224 trb_slot_id | trb_ep_index | type, false);