drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70 #include "xhci-trace.h"
  71
  72 /*
  73  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  74  * address of the TRB.
  75  */
  76 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  77                 union xhci_trb *trb)
  78 {
  79         unsigned long segment_offset;
  80
  81         if (!seg || !trb || trb < seg->trbs)
  82                 return 0;
  83         /* offset in TRBs */
  84         segment_offset = trb - seg->trbs;
  85         if (segment_offset >= TRBS_PER_SEGMENT)
  86                 return 0;
  87         return seg->dma + (segment_offset * sizeof(*trb));
  88 }
  89
  90 /* Does this link TRB point to the first segment in a ring,
  91  * or was the previous TRB the last TRB on the last segment in the ERST?
  92  */
  93 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  94                 struct xhci_segment *seg, union xhci_trb *trb)
  95 {
  96         if (ring == xhci->event_ring)
  97                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  98                         (seg->next == xhci->event_ring->first_seg);
  99         else
 100                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 101 }
 102
 103 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 104  * segment?  I.e. would the updated event TRB pointer step off the end of the
 105  * event seg?
 106  */
 107 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 108                 struct xhci_segment *seg, union xhci_trb *trb)
 109 {
 110         if (ring == xhci->event_ring)
 111                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 112         else
 113                 return TRB_TYPE_LINK_LE32(trb->link.control);
 114 }
 115
 116 static int enqueue_is_link_trb(struct xhci_ring *ring)
 117 {
 118         struct xhci_link_trb *link = &ring->enqueue->link;
 119         return TRB_TYPE_LINK_LE32(link->control);
 120 }
 121
 122 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 123  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 124  * effect the ring dequeue or enqueue pointers.
 125  */
 126 static void next_trb(struct xhci_hcd *xhci,
 127                 struct xhci_ring *ring,
 128                 struct xhci_segment **seg,
 129                 union xhci_trb **trb)
 130 {
 131         if (last_trb(xhci, ring, *seg, *trb)) {
 132                 *seg = (*seg)->next;
 133                 *trb = ((*seg)->trbs);
 134         } else {
 135                 (*trb)++;
 136         }
 137 }
 138
 139 /*
 140  * See Cycle bit rules. SW is the consumer for the event ring only.
 141  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 142  */
 143 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 144 {
 145         ring->deq_updates++;
 146
 147         /*
 148          * If this is not event ring, and the dequeue pointer
 149          * is not on a link TRB, there is one more usable TRB
 150          */
 151         if (ring->type != TYPE_EVENT &&
 152                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 153                 ring->num_trbs_free++;
 154
 155         do {
 156                 /*
 157                  * Update the dequeue pointer further if that was a link TRB or
 158                  * we're at the end of an event ring segment (which doesn't have
 159                  * link TRBS)
 160                  */
 161                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 162                         if (ring->type == TYPE_EVENT &&
 163                                         last_trb_on_last_seg(xhci, ring,
 164                                                 ring->deq_seg, ring->dequeue)) {
 165                                 ring->cycle_state ^= 1;
 166                         }
 167                         ring->deq_seg = ring->deq_seg->next;
 168                         ring->dequeue = ring->deq_seg->trbs;
 169                 } else {
 170                         ring->dequeue++;
 171                 }
 172         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 173 }
 174
 175 /*
 176  * See Cycle bit rules. SW is the consumer for the event ring only.
 177  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 178  *
 179  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 180  * chain bit is set), then set the chain bit in all the following link TRBs.
 181  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 182  * have their chain bit cleared (so that each Link TRB is a separate TD).
 183  *
 184  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 185  * set, but other sections talk about dealing with the chain bit set.  This was
 186  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 187  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 188  *
 189  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 190  *                      prepare_transfer()?
 191  */
 192 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 193                         bool more_trbs_coming)
 194 {
 195         u32 chain;
 196         union xhci_trb *next;
 197
 198         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 199         /* If this is not event ring, there is one less usable TRB */
 200         if (ring->type != TYPE_EVENT &&
 201                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 202                 ring->num_trbs_free--;
 203         next = ++(ring->enqueue);
 204
 205         ring->enq_updates++;
 206         /* Update the dequeue pointer further if that was a link TRB or we're at
 207          * the end of an event ring segment (which doesn't have link TRBS)
 208          */
 209         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 210                 if (ring->type != TYPE_EVENT) {
 211                         /*
 212                          * If the caller doesn't plan on enqueueing more
 213                          * TDs before ringing the doorbell, then we
 214                          * don't want to give the link TRB to the
 215                          * hardware just yet.  We'll give the link TRB
 216                          * back in prepare_ring() just before we enqueue
 217                          * the TD at the top of the ring.
 218                          */
 219                         if (!chain && !more_trbs_coming)
 220                                 break;
 221
 222                         /* If we're not dealing with 0.95 hardware or
 223                          * isoc rings on AMD 0.96 host,
 224                          * carry over the chain bit of the previous TRB
 225                          * (which may mean the chain bit is cleared).
 226                          */
 227                         if (!(ring->type == TYPE_ISOC &&
 228                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 229                                                 && !xhci_link_trb_quirk(xhci)) {
 230                                 next->link.control &=
 231                                         cpu_to_le32(~TRB_CHAIN);
 232                                 next->link.control |=
 233                                         cpu_to_le32(chain);
 234                         }
 235                         /* Give this link TRB to the hardware */
 236                         wmb();
 237                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 238
 239                         /* Toggle the cycle bit after the last ring segment. */
 240                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 241                                 ring->cycle_state ^= 1;
 242                         }
 243                 }
 244                 ring->enq_seg = ring->enq_seg->next;
 245                 ring->enqueue = ring->enq_seg->trbs;
 246                 next = ring->enqueue;
 247         }
 248 }
 249
 250 /*
 251  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 252  * enqueue pointer will not advance into dequeue segment. See rules above.
 253  */
 254 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 255                 unsigned int num_trbs)
 256 {
 257         int num_trbs_in_deq_seg;
 258
 259         if (ring->num_trbs_free < num_trbs)
 260                 return 0;
 261
 262         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 263                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 264                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 265                         return 0;
 266         }
 267
 268         return 1;
 269 }
 270
 271 /* Ring the host controller doorbell after placing a command on the ring */
 272 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 273 {
 274         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 275                 return;
 276
 277         xhci_dbg(xhci, "// Ding dong!\n");
 278         writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 279         /* Flush PCI posted writes */
 280         readl(&xhci->dba->doorbell[0]);
 281 }
 282
 283 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
 284 {
 285         return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
 286 }
 287
 288 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
 289 {
 290         return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
 291                                         cmd_list);
 292 }
 293
 294 /*
 295  * Turn all commands on command ring with status set to "aborted" to no-op trbs.
 296  * If there are other commands waiting then restart the ring and kick the timer.
 297  * This must be called with command ring stopped and xhci->lock held.
 298  */
 299 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
 300                                          struct xhci_command *cur_cmd)
 301 {
 302         struct xhci_command *i_cmd;
 303         u32 cycle_state;
 304
 305         /* Turn all aborted commands in list to no-ops, then restart */
 306         list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
 307
 308                 if (i_cmd->status != COMP_CMD_ABORT)
 309                         continue;
 310
 311                 i_cmd->status = COMP_CMD_STOP;
 312
 313                 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
 314                          i_cmd->command_trb);
 315                 /* get cycle state from the original cmd trb */
 316                 cycle_state = le32_to_cpu(
 317                         i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
 318                 /* modify the command trb to no-op command */
 319                 i_cmd->command_trb->generic.field[0] = 0;
 320                 i_cmd->command_trb->generic.field[1] = 0;
 321                 i_cmd->command_trb->generic.field[2] = 0;
 322                 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
 323                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
 324
 325                 /*
 326                  * caller waiting for completion is called when command
 327                  *  completion event is received for these no-op commands
 328                  */
 329         }
 330
 331         xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
 332
 333         /* ring command ring doorbell to restart the command ring */
 334         if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
 335             !(xhci->xhc_state & XHCI_STATE_DYING)) {
 336                 xhci->current_cmd = cur_cmd;
 337                 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
 338                 xhci_ring_cmd_db(xhci);
 339         }
 340 }
 341
 342 /* Must be called with xhci->lock held, releases and aquires lock back */
 343 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
 344 {
 345         u64 temp_64;
 346         int ret;
 347
 348         xhci_dbg(xhci, "Abort command ring\n");
 349
 350         reinit_completion(&xhci->cmd_ring_stop_completion);
 351
 352         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 353         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 354                         &xhci->op_regs->cmd_ring);
 355
 356         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 357          * time the completion od all xHCI commands, including
 358          * the Command Abort operation. If software doesn't see
 359          * CRR negated in a timely manner (e.g. longer than 5
 360          * seconds), then it should assume that the there are
 361          * larger problems with the xHC and assert HCRST.
 362          */
 363         ret = xhci_handshake(&xhci->op_regs->cmd_ring,
 364                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 365         if (ret < 0) {
 366                 /* we are about to kill xhci, give it one more chance */
 367                 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 368                               &xhci->op_regs->cmd_ring);
 369                 udelay(1000);
 370                 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
 371                                      CMD_RING_RUNNING, 0, 3 * 1000 * 1000);
 372                 if (ret < 0) {
 373                         xhci_err(xhci, "Stopped the command ring failed, "
 374                                  "maybe the host is dead\n");
 375                         xhci->xhc_state |= XHCI_STATE_DYING;
 376                         xhci_quiesce(xhci);
 377                         xhci_halt(xhci);
 378                         return -ESHUTDOWN;
 379                 }
 380         }
 381         /*
 382          * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
 383          * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
 384          * but the completion event in never sent. Wait 2 secs (arbitrary
 385          * number) to handle those cases after negation of CMD_RING_RUNNING.
 386          */
 387         spin_unlock_irqrestore(&xhci->lock, flags);
 388         ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
 389                                           msecs_to_jiffies(2000));
 390         spin_lock_irqsave(&xhci->lock, flags);
 391         if (!ret) {
 392                 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
 393                 xhci_cleanup_command_queue(xhci);
 394         } else {
 395                 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
 396         }
 397
 398         return 0;
 399 }
 400
 401 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 402                 unsigned int slot_id,
 403                 unsigned int ep_index,
 404                 unsigned int stream_id)
 405 {
 406         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 407         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 408         unsigned int ep_state = ep->ep_state;
 409
 410         /* Don't ring the doorbell for this endpoint if there are pending
 411          * cancellations because we don't want to interrupt processing.
 412          * We don't want to restart any stream rings if there's a set dequeue
 413          * pointer command pending because the device can choose to start any
 414          * stream once the endpoint is on the HW schedule.
 415          */
 416         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 417             (ep_state & EP_HALTED))
 418                 return;
 419         writel(DB_VALUE(ep_index, stream_id), db_addr);
 420         /* The CPU has better things to do at this point than wait for a
 421          * write-posting flush.  It'll get there soon enough.
 422          */
 423 }
 424
 425 /* Ring the doorbell for any rings with pending URBs */
 426 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 427                 unsigned int slot_id,
 428                 unsigned int ep_index)
 429 {
 430         unsigned int stream_id;
 431         struct xhci_virt_ep *ep;
 432
 433         ep = &xhci->devs[slot_id]->eps[ep_index];
 434
 435         /* A ring has pending URBs if its TD list is not empty */
 436         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 437                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 438                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 439                 return;
 440         }
 441
 442         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 443                         stream_id++) {
 444                 struct xhci_stream_info *stream_info = ep->stream_info;
 445                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 446                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 447                                                 stream_id);
 448         }
 449 }
 450
 451 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 452                 unsigned int slot_id, unsigned int ep_index,
 453                 unsigned int stream_id)
 454 {
 455         struct xhci_virt_ep *ep;
 456
 457         ep = &xhci->devs[slot_id]->eps[ep_index];
 458         /* Common case: no streams */
 459         if (!(ep->ep_state & EP_HAS_STREAMS))
 460                 return ep->ring;
 461
 462         if (stream_id == 0) {
 463                 xhci_warn(xhci,
 464                                 "WARN: Slot ID %u, ep index %u has streams, "
 465                                 "but URB has no stream ID.\n",
 466                                 slot_id, ep_index);
 467                 return NULL;
 468         }
 469
 470         if (stream_id < ep->stream_info->num_streams)
 471                 return ep->stream_info->stream_rings[stream_id];
 472
 473         xhci_warn(xhci,
 474                         "WARN: Slot ID %u, ep index %u has "
 475                         "stream IDs 1 to %u allocated, "
 476                         "but stream ID %u is requested.\n",
 477                         slot_id, ep_index,
 478                         ep->stream_info->num_streams - 1,
 479                         stream_id);
 480         return NULL;
 481 }
 482
 483 /* Get the right ring for the given URB.
 484  * If the endpoint supports streams, boundary check the URB's stream ID.
 485  * If the endpoint doesn't support streams, return the singular endpoint ring.
 486  */
 487 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 488                 struct urb *urb)
 489 {
 490         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 491                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 492 }
 493
 494 /*
 495  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 496  * Record the new state of the xHC's endpoint ring dequeue segment,
 497  * dequeue pointer, and new consumer cycle state in state.
 498  * Update our internal representation of the ring's dequeue pointer.
 499  *
 500  * We do this in three jumps:
 501  *  - First we update our new ring state to be the same as when the xHC stopped.
 502  *  - Then we traverse the ring to find the segment that contains
 503  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 504  *    any link TRBs with the toggle cycle bit set.
 505  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 506  *    if we've moved it past a link TRB with the toggle cycle bit set.
 507  *
 508  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 509  * with correct __le32 accesses they should work fine.  Only users of this are
 510  * in here.
 511  */
 512 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 513                 unsigned int slot_id, unsigned int ep_index,
 514                 unsigned int stream_id, struct xhci_td *cur_td,
 515                 struct xhci_dequeue_state *state)
 516 {
 517         struct xhci_virt_device *dev = xhci->devs[slot_id];
 518         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 519         struct xhci_ring *ep_ring;
 520         struct xhci_segment *new_seg;
 521         union xhci_trb *new_deq;
 522         dma_addr_t addr;
 523         u64 hw_dequeue;
 524         bool cycle_found = false;
 525         bool td_last_trb_found = false;
 526
 527         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 528                         ep_index, stream_id);
 529         if (!ep_ring) {
 530                 xhci_warn(xhci, "WARN can't find new dequeue state "
 531                                 "for invalid stream ID %u.\n",
 532                                 stream_id);
 533                 return;
 534         }
 535
 536         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 537         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 538                         "Finding endpoint context");
 539         /* 4.6.9 the css flag is written to the stream context for streams */
 540         if (ep->ep_state & EP_HAS_STREAMS) {
 541                 struct xhci_stream_ctx *ctx =
 542                         &ep->stream_info->stream_ctx_array[stream_id];
 543                 hw_dequeue = le64_to_cpu(ctx->stream_ring);
 544         } else {
 545                 struct xhci_ep_ctx *ep_ctx
 546                         = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 547                 hw_dequeue = le64_to_cpu(ep_ctx->deq);
 548         }
 549
 550         new_seg = ep_ring->deq_seg;
 551         new_deq = ep_ring->dequeue;
 552         state->new_cycle_state = hw_dequeue & 0x1;
 553
 554         /*
 555          * We want to find the pointer, segment and cycle state of the new trb
 556          * (the one after current TD's last_trb). We know the cycle state at
 557          * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
 558          * found.
 559          */
 560         do {
 561                 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
 562                     == (dma_addr_t)(hw_dequeue & ~0xf)) {
 563                         cycle_found = true;
 564                         if (td_last_trb_found)
 565                                 break;
 566                 }
 567                 if (new_deq == cur_td->last_trb)
 568                         td_last_trb_found = true;
 569
 570                 if (cycle_found &&
 571                     TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
 572                     new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
 573                         state->new_cycle_state ^= 0x1;
 574
 575                 next_trb(xhci, ep_ring, &new_seg, &new_deq);
 576
 577                 /* Search wrapped around, bail out */
 578                 if (new_deq == ep->ring->dequeue) {
 579                         xhci_err(xhci, "Error: Failed finding new dequeue state\n");
 580                         state->new_deq_seg = NULL;
 581                         state->new_deq_ptr = NULL;
 582                         return;
 583                 }
 584
 585         } while (!cycle_found || !td_last_trb_found);
 586
 587         state->new_deq_seg = new_seg;
 588         state->new_deq_ptr = new_deq;
 589
 590         /* Don't update the ring cycle state for the producer (us). */
 591         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 592                         "Cycle state = 0x%x", state->new_cycle_state);
 593
 594         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 595                         "New dequeue segment = %p (virtual)",
 596                         state->new_deq_seg);
 597         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 598         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 599                         "New dequeue pointer = 0x%llx (DMA)",
 600                         (unsigned long long) addr);
 601 }
 602
 603 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 604  * (The last TRB actually points to the ring enqueue pointer, which is not part
 605  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 606  */
 607 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 608                 struct xhci_td *cur_td, bool flip_cycle)
 609 {
 610         struct xhci_segment *cur_seg;
 611         union xhci_trb *cur_trb;
 612
 613         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 614                         true;
 615                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 616                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 617                         /* Unchain any chained Link TRBs, but
 618                          * leave the pointers intact.
 619                          */
 620                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 621                         /* Flip the cycle bit (link TRBs can't be the first
 622                          * or last TRB).
 623                          */
 624                         if (flip_cycle)
 625                                 cur_trb->generic.field[3] ^=
 626                                         cpu_to_le32(TRB_CYCLE);
 627                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 628                                         "Cancel (unchain) link TRB");
 629                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 630                                         "Address = %p (0x%llx dma); "
 631                                         "in seg %p (0x%llx dma)",
 632                                         cur_trb,
 633                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 634                                         cur_seg,
 635                                         (unsigned long long)cur_seg->dma);
 636                 } else {
 637                         cur_trb->generic.field[0] = 0;
 638                         cur_trb->generic.field[1] = 0;
 639                         cur_trb->generic.field[2] = 0;
 640                         /* Preserve only the cycle bit of this TRB */
 641                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 642                         /* Flip the cycle bit except on the first or last TRB */
 643                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 644                                         cur_trb != cur_td->last_trb)
 645                                 cur_trb->generic.field[3] ^=
 646                                         cpu_to_le32(TRB_CYCLE);
 647                         cur_trb->generic.field[3] |= cpu_to_le32(
 648                                 TRB_TYPE(TRB_TR_NOOP));
 649                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 650                                         "TRB to noop at offset 0x%llx",
 651                                         (unsigned long long)
 652                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 653                 }
 654                 if (cur_trb == cur_td->last_trb)
 655                         break;
 656         }
 657 }
 658
 659 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 660                 struct xhci_virt_ep *ep)
 661 {
 662         ep->ep_state &= ~EP_HALT_PENDING;
 663         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 664          * timer is running on another CPU, we don't decrement stop_cmds_pending
 665          * (since we didn't successfully stop the watchdog timer).
 666          */
 667         if (del_timer(&ep->stop_cmd_timer))
 668                 ep->stop_cmds_pending--;
 669 }
 670
 671 /* Must be called with xhci->lock held in interrupt context */
 672 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 673                 struct xhci_td *cur_td, int status)
 674 {
 675         struct usb_hcd *hcd;
 676         struct urb      *urb;
 677         struct urb_priv *urb_priv;
 678
 679         urb = cur_td->urb;
 680         urb_priv = urb->hcpriv;
 681         urb_priv->td_cnt++;
 682         hcd = bus_to_hcd(urb->dev->bus);
 683
 684         /* Only giveback urb when this is the last td in urb */
 685         if (urb_priv->td_cnt == urb_priv->length) {
 686                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 687                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 688                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 689                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 690                                         usb_amd_quirk_pll_enable();
 691                         }
 692                 }
 693                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 694
 695                 spin_unlock(&xhci->lock);
 696                 usb_hcd_giveback_urb(hcd, urb, status);
 697                 xhci_urb_free_priv(urb_priv);
 698                 spin_lock(&xhci->lock);
 699         }
 700 }
 701
 702 /*
 703  * When we get a command completion for a Stop Endpoint Command, we need to
 704  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 705  *
 706  *  1. If the HW was in the middle of processing the TD that needs to be
 707  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 708  *     in the TD with a Set Dequeue Pointer Command.
 709  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 710  *     bit cleared) so that the HW will skip over them.
 711  */
 712 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
 713                 union xhci_trb *trb, struct xhci_event_cmd *event)
 714 {
 715         unsigned int ep_index;
 716         struct xhci_ring *ep_ring;
 717         struct xhci_virt_ep *ep;
 718         struct list_head *entry;
 719         struct xhci_td *cur_td = NULL;
 720         struct xhci_td *last_unlinked_td;
 721
 722         struct xhci_dequeue_state deq_state;
 723
 724         if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
 725                 if (!xhci->devs[slot_id])
 726                         xhci_warn(xhci, "Stop endpoint command "
 727                                 "completion for disabled slot %u\n",
 728                                 slot_id);
 729                 return;
 730         }
 731
 732         memset(&deq_state, 0, sizeof(deq_state));
 733         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 734         ep = &xhci->devs[slot_id]->eps[ep_index];
 735
 736         if (list_empty(&ep->cancelled_td_list)) {
 737                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 738                 ep->stopped_td = NULL;
 739                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 740                 return;
 741         }
 742
 743         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 744          * We have the xHCI lock, so nothing can modify this list until we drop
 745          * it.  We're also in the event handler, so we can't get re-interrupted
 746          * if another Stop Endpoint command completes
 747          */
 748         list_for_each(entry, &ep->cancelled_td_list) {
 749                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 750                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 751                                 "Removing canceled TD starting at 0x%llx (dma).",
 752                                 (unsigned long long)xhci_trb_virt_to_dma(
 753                                         cur_td->start_seg, cur_td->first_trb));
 754                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 755                 if (!ep_ring) {
 756                         /* This shouldn't happen unless a driver is mucking
 757                          * with the stream ID after submission.  This will
 758                          * leave the TD on the hardware ring, and the hardware
 759                          * will try to execute it, and may access a buffer
 760                          * that has already been freed.  In the best case, the
 761                          * hardware will execute it, and the event handler will
 762                          * ignore the completion event for that TD, since it was
 763                          * removed from the td_list for that endpoint.  In
 764                          * short, don't muck with the stream ID after
 765                          * submission.
 766                          */
 767                         xhci_warn(xhci, "WARN Cancelled URB %p "
 768                                         "has invalid stream ID %u.\n",
 769                                         cur_td->urb,
 770                                         cur_td->urb->stream_id);
 771                         goto remove_finished_td;
 772                 }
 773                 /*
 774                  * If we stopped on the TD we need to cancel, then we have to
 775                  * move the xHC endpoint ring dequeue pointer past this TD.
 776                  */
 777                 if (cur_td == ep->stopped_td)
 778                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 779                                         cur_td->urb->stream_id,
 780                                         cur_td, &deq_state);
 781                 else
 782                         td_to_noop(xhci, ep_ring, cur_td, false);
 783 remove_finished_td:
 784                 /*
 785                  * The event handler won't see a completion for this TD anymore,
 786                  * so remove it from the endpoint ring's TD list.  Keep it in
 787                  * the cancelled TD list for URB completion later.
 788                  */
 789                 list_del_init(&cur_td->td_list);
 790         }
 791         last_unlinked_td = cur_td;
 792         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 793
 794         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 795         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 796                 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
 797                                 ep->stopped_td->urb->stream_id, &deq_state);
 798                 xhci_ring_cmd_db(xhci);
 799         } else {
 800                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 801                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 802         }
 803
 804         ep->stopped_td = NULL;
 805
 806         /*
 807          * Drop the lock and complete the URBs in the cancelled TD list.
 808          * New TDs to be cancelled might be added to the end of the list before
 809          * we can complete all the URBs for the TDs we already unlinked.
 810          * So stop when we've completed the URB for the last TD we unlinked.
 811          */
 812         do {
 813                 cur_td = list_entry(ep->cancelled_td_list.next,
 814                                 struct xhci_td, cancelled_td_list);
 815                 list_del_init(&cur_td->cancelled_td_list);
 816
 817                 /* Clean up the cancelled URB */
 818                 /* Doesn't matter what we pass for status, since the core will
 819                  * just overwrite it (because the URB has been unlinked).
 820                  */
 821                 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
 822
 823                 /* Stop processing the cancelled list if the watchdog timer is
 824                  * running.
 825                  */
 826                 if (xhci->xhc_state & XHCI_STATE_DYING)
 827                         return;
 828         } while (cur_td != last_unlinked_td);
 829
 830         /* Return to the event handler with xhci->lock re-acquired */
 831 }
 832
 833 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
 834 {
 835         struct xhci_td *cur_td;
 836
 837         while (!list_empty(&ring->td_list)) {
 838                 cur_td = list_first_entry(&ring->td_list,
 839                                 struct xhci_td, td_list);
 840                 list_del_init(&cur_td->td_list);
 841                 if (!list_empty(&cur_td->cancelled_td_list))
 842                         list_del_init(&cur_td->cancelled_td_list);
 843                 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
 844         }
 845 }
 846
 847 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
 848                 int slot_id, int ep_index)
 849 {
 850         struct xhci_td *cur_td;
 851         struct xhci_virt_ep *ep;
 852         struct xhci_ring *ring;
 853
 854         ep = &xhci->devs[slot_id]->eps[ep_index];
 855         if ((ep->ep_state & EP_HAS_STREAMS) ||
 856                         (ep->ep_state & EP_GETTING_NO_STREAMS)) {
 857                 int stream_id;
 858
 859                 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 860                                 stream_id++) {
 861                         ring = ep->stream_info->stream_rings[stream_id];
 862                         if (!ring)
 863                                 continue;
 864
 865                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 866                                         "Killing URBs for slot ID %u, ep index %u, stream %u",
 867                                         slot_id, ep_index, stream_id);
 868                         xhci_kill_ring_urbs(xhci, ring);
 869                 }
 870         } else {
 871                 ring = ep->ring;
 872                 if (!ring)
 873                         return;
 874                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 875                                 "Killing URBs for slot ID %u, ep index %u",
 876                                 slot_id, ep_index);
 877                 xhci_kill_ring_urbs(xhci, ring);
 878         }
 879         while (!list_empty(&ep->cancelled_td_list)) {
 880                 cur_td = list_first_entry(&ep->cancelled_td_list,
 881                                 struct xhci_td, cancelled_td_list);
 882                 list_del_init(&cur_td->cancelled_td_list);
 883                 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
 884         }
 885 }
 886
 887 /* Watchdog timer function for when a stop endpoint command fails to complete.
 888  * In this case, we assume the host controller is broken or dying or dead.  The
 889  * host may still be completing some other events, so we have to be careful to
 890  * let the event ring handler and the URB dequeueing/enqueueing functions know
 891  * through xhci->state.
 892  *
 893  * The timer may also fire if the host takes a very long time to respond to the
 894  * command, and the stop endpoint command completion handler cannot delete the
 895  * timer before the timer function is called.  Another endpoint cancellation may
 896  * sneak in before the timer function can grab the lock, and that may queue
 897  * another stop endpoint command and add the timer back.  So we cannot use a
 898  * simple flag to say whether there is a pending stop endpoint command for a
 899  * particular endpoint.
 900  *
 901  * Instead we use a combination of that flag and a counter for the number of
 902  * pending stop endpoint commands.  If the timer is the tail end of the last
 903  * stop endpoint command, and the endpoint's command is still pending, we assume
 904  * the host is dying.
 905  */
 906 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 907 {
 908         struct xhci_hcd *xhci;
 909         struct xhci_virt_ep *ep;
 910         int ret, i, j;
 911         unsigned long flags;
 912
 913         ep = (struct xhci_virt_ep *) arg;
 914         xhci = ep->xhci;
 915
 916         spin_lock_irqsave(&xhci->lock, flags);
 917
 918         ep->stop_cmds_pending--;
 919         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 920                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 921                                 "Stop EP timer ran, but no command pending, "
 922                                 "exiting.");
 923                 spin_unlock_irqrestore(&xhci->lock, flags);
 924                 return;
 925         }
 926
 927         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 928         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 929         /* Oops, HC is dead or dying or at least not responding to the stop
 930          * endpoint command.
 931          */
 932         xhci->xhc_state |= XHCI_STATE_DYING;
 933         /* Disable interrupts from the host controller and start halting it */
 934         xhci_quiesce(xhci);
 935         spin_unlock_irqrestore(&xhci->lock, flags);
 936
 937         ret = xhci_halt(xhci);
 938
 939         spin_lock_irqsave(&xhci->lock, flags);
 940         if (ret < 0) {
 941                 /* This is bad; the host is not responding to commands and it's
 942                  * not allowing itself to be halted.  At least interrupts are
 943                  * disabled. If we call usb_hc_died(), it will attempt to
 944                  * disconnect all device drivers under this host.  Those
 945                  * disconnect() methods will wait for all URBs to be unlinked,
 946                  * so we must complete them.
 947                  */
 948                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 949                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 950                 /* We could turn all TDs on the rings to no-ops.  This won't
 951                  * help if the host has cached part of the ring, and is slow if
 952                  * we want to preserve the cycle bit.  Skip it and hope the host
 953                  * doesn't touch the memory.
 954                  */
 955         }
 956         for (i = 0; i < MAX_HC_SLOTS; i++) {
 957                 if (!xhci->devs[i])
 958                         continue;
 959                 for (j = 0; j < 31; j++)
 960                         xhci_kill_endpoint_urbs(xhci, i, j);
 961         }
 962         spin_unlock_irqrestore(&xhci->lock, flags);
 963         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 964                         "Calling usb_hc_died()");
 965         usb_hc_died(xhci_to_hcd(xhci));
 966         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 967                         "xHCI host controller is dead.");
 968 }
 969
 970
 971 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
 972                 struct xhci_virt_device *dev,
 973                 struct xhci_ring *ep_ring,
 974                 unsigned int ep_index)
 975 {
 976         union xhci_trb *dequeue_temp;
 977         int num_trbs_free_temp;
 978         bool revert = false;
 979
 980         num_trbs_free_temp = ep_ring->num_trbs_free;
 981         dequeue_temp = ep_ring->dequeue;
 982
 983         /* If we get two back-to-back stalls, and the first stalled transfer
 984          * ends just before a link TRB, the dequeue pointer will be left on
 985          * the link TRB by the code in the while loop.  So we have to update
 986          * the dequeue pointer one segment further, or we'll jump off
 987          * the segment into la-la-land.
 988          */
 989         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
 990                 ep_ring->deq_seg = ep_ring->deq_seg->next;
 991                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
 992         }
 993
 994         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
 995                 /* We have more usable TRBs */
 996                 ep_ring->num_trbs_free++;
 997                 ep_ring->dequeue++;
 998                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
 999                                 ep_ring->dequeue)) {
1000                         if (ep_ring->dequeue ==
1001                                         dev->eps[ep_index].queued_deq_ptr)
1002                                 break;
1003                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1004                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1005                 }
1006                 if (ep_ring->dequeue == dequeue_temp) {
1007                         revert = true;
1008                         break;
1009                 }
1010         }
1011
1012         if (revert) {
1013                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1014                 ep_ring->num_trbs_free = num_trbs_free_temp;
1015         }
1016 }
1017
1018 /*
1019  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1020  * we need to clear the set deq pending flag in the endpoint ring state, so that
1021  * the TD queueing code can ring the doorbell again.  We also need to ring the
1022  * endpoint doorbell to restart the ring, but only if there aren't more
1023  * cancellations pending.
1024  */
1025 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1026                 union xhci_trb *trb, u32 cmd_comp_code)
1027 {
1028         unsigned int ep_index;
1029         unsigned int stream_id;
1030         struct xhci_ring *ep_ring;
1031         struct xhci_virt_device *dev;
1032         struct xhci_virt_ep *ep;
1033         struct xhci_ep_ctx *ep_ctx;
1034         struct xhci_slot_ctx *slot_ctx;
1035
1036         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1037         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1038         dev = xhci->devs[slot_id];
1039         ep = &dev->eps[ep_index];
1040
1041         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1042         if (!ep_ring) {
1043                 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1044                                 stream_id);
1045                 /* XXX: Harmless??? */
1046                 goto cleanup;
1047         }
1048
1049         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1050         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1051
1052         if (cmd_comp_code != COMP_SUCCESS) {
1053                 unsigned int ep_state;
1054                 unsigned int slot_state;
1055
1056                 switch (cmd_comp_code) {
1057                 case COMP_TRB_ERR:
1058                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1059                         break;
1060                 case COMP_CTX_STATE:
1061                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1062                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1063                         ep_state &= EP_STATE_MASK;
1064                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1065                         slot_state = GET_SLOT_STATE(slot_state);
1066                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1067                                         "Slot state = %u, EP state = %u",
1068                                         slot_state, ep_state);
1069                         break;
1070                 case COMP_EBADSLT:
1071                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1072                                         slot_id);
1073                         break;
1074                 default:
1075                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1076                                         cmd_comp_code);
1077                         break;
1078                 }
1079                 /* OK what do we do now?  The endpoint state is hosed, and we
1080                  * should never get to this point if the synchronization between
1081                  * queueing, and endpoint state are correct.  This might happen
1082                  * if the device gets disconnected after we've finished
1083                  * cancelling URBs, which might not be an error...
1084                  */
1085         } else {
1086                 u64 deq;
1087                 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1088                 if (ep->ep_state & EP_HAS_STREAMS) {
1089                         struct xhci_stream_ctx *ctx =
1090                                 &ep->stream_info->stream_ctx_array[stream_id];
1091                         deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1092                 } else {
1093                         deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1094                 }
1095                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1096                         "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1097                 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1098                                          ep->queued_deq_ptr) == deq) {
1099                         /* Update the ring's dequeue segment and dequeue pointer
1100                          * to reflect the new position.
1101                          */
1102                         update_ring_for_set_deq_completion(xhci, dev,
1103                                 ep_ring, ep_index);
1104                 } else {
1105                         xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1106                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1107                                   ep->queued_deq_seg, ep->queued_deq_ptr);
1108                 }
1109         }
1110
1111 cleanup:
1112         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1113         dev->eps[ep_index].queued_deq_seg = NULL;
1114         dev->eps[ep_index].queued_deq_ptr = NULL;
1115         /* Restart any rings with pending URBs */
1116         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1117 }
1118
1119 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1120                 union xhci_trb *trb, u32 cmd_comp_code)
1121 {
1122         unsigned int ep_index;
1123
1124         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1125         /* This command will only fail if the endpoint wasn't halted,
1126          * but we don't care.
1127          */
1128         xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1129                 "Ignoring reset ep completion code of %u", cmd_comp_code);
1130
1131         /* HW with the reset endpoint quirk needs to have a configure endpoint
1132          * command complete before the endpoint can be used.  Queue that here
1133          * because the HW can't handle two commands being queued in a row.
1134          */
1135         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1136                 struct xhci_command *command;
1137                 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1138                 if (!command) {
1139                         xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1140                         return;
1141                 }
1142                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1143                                 "Queueing configure endpoint command");
1144                 xhci_queue_configure_endpoint(xhci, command,
1145                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1146                                 false);
1147                 xhci_ring_cmd_db(xhci);
1148         } else {
1149                 /* Clear our internal halted state */
1150                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1151         }
1152 }
1153
1154 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1155                 u32 cmd_comp_code)
1156 {
1157         if (cmd_comp_code == COMP_SUCCESS)
1158                 xhci->slot_id = slot_id;
1159         else
1160                 xhci->slot_id = 0;
1161 }
1162
1163 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1164 {
1165         struct xhci_virt_device *virt_dev;
1166
1167         virt_dev = xhci->devs[slot_id];
1168         if (!virt_dev)
1169                 return;
1170         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1171                 /* Delete default control endpoint resources */
1172                 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1173         xhci_free_virt_device(xhci, slot_id);
1174 }
1175
1176 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1177                 struct xhci_event_cmd *event, u32 cmd_comp_code)
1178 {
1179         struct xhci_virt_device *virt_dev;
1180         struct xhci_input_control_ctx *ctrl_ctx;
1181         unsigned int ep_index;
1182         unsigned int ep_state;
1183         u32 add_flags, drop_flags;
1184
1185         /*
1186          * Configure endpoint commands can come from the USB core
1187          * configuration or alt setting changes, or because the HW
1188          * needed an extra configure endpoint command after a reset
1189          * endpoint command or streams were being configured.
1190          * If the command was for a halted endpoint, the xHCI driver
1191          * is not waiting on the configure endpoint command.
1192          */
1193         virt_dev = xhci->devs[slot_id];
1194         ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1195         if (!ctrl_ctx) {
1196                 xhci_warn(xhci, "Could not get input context, bad type.\n");
1197                 return;
1198         }
1199
1200         add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1201         drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1202         /* Input ctx add_flags are the endpoint index plus one */
1203         ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1204
1205         /* A usb_set_interface() call directly after clearing a halted
1206          * condition may race on this quirky hardware.  Not worth
1207          * worrying about, since this is prototype hardware.  Not sure
1208          * if this will work for streams, but streams support was
1209          * untested on this prototype.
1210          */
1211         if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1212                         ep_index != (unsigned int) -1 &&
1213                         add_flags - SLOT_FLAG == drop_flags) {
1214                 ep_state = virt_dev->eps[ep_index].ep_state;
1215                 if (!(ep_state & EP_HALTED))
1216                         return;
1217                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1218                                 "Completed config ep cmd - "
1219                                 "last ep index = %d, state = %d",
1220                                 ep_index, ep_state);
1221                 /* Clear internal halted state and restart ring(s) */
1222                 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1223                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1224                 return;
1225         }
1226         return;
1227 }
1228
1229 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1230                 struct xhci_event_cmd *event)
1231 {
1232         xhci_dbg(xhci, "Completed reset device command.\n");
1233         if (!xhci->devs[slot_id])
1234                 xhci_warn(xhci, "Reset device command completion "
1235                                 "for disabled slot %u\n", slot_id);
1236 }
1237
1238 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1239                 struct xhci_event_cmd *event)
1240 {
1241         if (!(xhci->quirks & XHCI_NEC_HOST)) {
1242                 xhci->error_bitmask |= 1 << 6;
1243                 return;
1244         }
1245         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1246                         "NEC firmware version %2x.%02x",
1247                         NEC_FW_MAJOR(le32_to_cpu(event->status)),
1248                         NEC_FW_MINOR(le32_to_cpu(event->status)));
1249 }
1250
1251 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1252 {
1253         list_del(&cmd->cmd_list);
1254
1255         if (cmd->completion) {
1256                 cmd->status = status;
1257                 complete(cmd->completion);
1258         } else {
1259                 kfree(cmd);
1260         }
1261 }
1262
1263 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1264 {
1265         struct xhci_command *cur_cmd, *tmp_cmd;
1266         list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1267                 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1268 }
1269
1270 void xhci_handle_command_timeout(struct work_struct *work)
1271 {
1272         struct xhci_hcd *xhci;
1273         int ret;
1274         unsigned long flags;
1275         u64 hw_ring_state;
1276
1277         xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1278
1279         spin_lock_irqsave(&xhci->lock, flags);
1280
1281         /*
1282          * If timeout work is pending, or current_cmd is NULL, it means we
1283          * raced with command completion. Command is handled so just return.
1284          */
1285         if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1286                 spin_unlock_irqrestore(&xhci->lock, flags);
1287                 return;
1288         }
1289         /* mark this command to be cancelled */
1290         xhci->current_cmd->status = COMP_CMD_ABORT;
1291
1292         /* Make sure command ring is running before aborting it */
1293         hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1294         if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1295             (hw_ring_state & CMD_RING_RUNNING))  {
1296                 /* Prevent new doorbell, and start command abort */
1297                 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1298                 xhci_dbg(xhci, "Command timeout\n");
1299                 ret = xhci_abort_cmd_ring(xhci, flags);
1300                 if (unlikely(ret == -ESHUTDOWN)) {
1301                         xhci_err(xhci, "Abort command ring failed\n");
1302                         xhci_cleanup_command_queue(xhci);
1303                         spin_unlock_irqrestore(&xhci->lock, flags);
1304                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1305                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1306
1307                         return;
1308                 }
1309
1310                 goto time_out_completed;
1311         }
1312
1313         /* host removed. Bail out */
1314         if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1315                 xhci_dbg(xhci, "host removed, ring start fail?\n");
1316                 xhci_cleanup_command_queue(xhci);
1317
1318                 goto time_out_completed;
1319         }
1320
1321         /* command timeout on stopped ring, ring can't be aborted */
1322         xhci_dbg(xhci, "Command timeout on stopped ring\n");
1323         xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1324
1325 time_out_completed:
1326         spin_unlock_irqrestore(&xhci->lock, flags);
1327         return;
1328 }
1329
1330 static void handle_cmd_completion(struct xhci_hcd *xhci,
1331                 struct xhci_event_cmd *event)
1332 {
1333         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1334         u64 cmd_dma;
1335         dma_addr_t cmd_dequeue_dma;
1336         u32 cmd_comp_code;
1337         union xhci_trb *cmd_trb;
1338         struct xhci_command *cmd;
1339         u32 cmd_type;
1340
1341         cmd_dma = le64_to_cpu(event->cmd_trb);
1342         cmd_trb = xhci->cmd_ring->dequeue;
1343         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1344                         cmd_trb);
1345         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1346         if (cmd_dequeue_dma == 0) {
1347                 xhci->error_bitmask |= 1 << 4;
1348                 return;
1349         }
1350         /* Does the DMA address match our internal dequeue pointer address? */
1351         if (cmd_dma != (u64) cmd_dequeue_dma) {
1352                 xhci->error_bitmask |= 1 << 5;
1353                 return;
1354         }
1355
1356         cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1357
1358         cancel_delayed_work(&xhci->cmd_timer);
1359
1360         trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1361
1362         cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1363
1364         /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1365         if (cmd_comp_code == COMP_CMD_STOP) {
1366                 complete_all(&xhci->cmd_ring_stop_completion);
1367                 return;
1368         }
1369
1370         if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1371                 xhci_err(xhci,
1372                          "Command completion event does not match command\n");
1373                 return;
1374         }
1375
1376         /*
1377          * Host aborted the command ring, check if the current command was
1378          * supposed to be aborted, otherwise continue normally.
1379          * The command ring is stopped now, but the xHC will issue a Command
1380          * Ring Stopped event which will cause us to restart it.
1381          */
1382         if (cmd_comp_code == COMP_CMD_ABORT) {
1383                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1384                 if (cmd->status == COMP_CMD_ABORT) {
1385                         if (xhci->current_cmd == cmd)
1386                                 xhci->current_cmd = NULL;
1387                         goto event_handled;
1388                 }
1389         }
1390
1391         cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1392         switch (cmd_type) {
1393         case TRB_ENABLE_SLOT:
1394                 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1395                 break;
1396         case TRB_DISABLE_SLOT:
1397                 xhci_handle_cmd_disable_slot(xhci, slot_id);
1398                 break;
1399         case TRB_CONFIG_EP:
1400                 if (!cmd->completion)
1401                         xhci_handle_cmd_config_ep(xhci, slot_id, event,
1402                                                   cmd_comp_code);
1403                 break;
1404         case TRB_EVAL_CONTEXT:
1405                 break;
1406         case TRB_ADDR_DEV:
1407                 break;
1408         case TRB_STOP_RING:
1409                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1410                                 le32_to_cpu(cmd_trb->generic.field[3])));
1411                 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1412                 break;
1413         case TRB_SET_DEQ:
1414                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1415                                 le32_to_cpu(cmd_trb->generic.field[3])));
1416                 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1417                 break;
1418         case TRB_CMD_NOOP:
1419                 /* Is this an aborted command turned to NO-OP? */
1420                 if (cmd->status == COMP_CMD_STOP)
1421                         cmd_comp_code = COMP_CMD_STOP;
1422                 break;
1423         case TRB_RESET_EP:
1424                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1425                                 le32_to_cpu(cmd_trb->generic.field[3])));
1426                 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1427                 break;
1428         case TRB_RESET_DEV:
1429                 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1430                  * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1431                  */
1432                 slot_id = TRB_TO_SLOT_ID(
1433                                 le32_to_cpu(cmd_trb->generic.field[3]));
1434                 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1435                 break;
1436         case TRB_NEC_GET_FW:
1437                 xhci_handle_cmd_nec_get_fw(xhci, event);
1438                 break;
1439         default:
1440                 /* Skip over unknown commands on the event ring */
1441                 xhci->error_bitmask |= 1 << 6;
1442                 break;
1443         }
1444
1445         /* restart timer if this wasn't the last command */
1446         if (cmd->cmd_list.next != &xhci->cmd_list) {
1447                 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1448                                                struct xhci_command, cmd_list);
1449                 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1450         } else if (xhci->current_cmd == cmd) {
1451                 xhci->current_cmd = NULL;
1452         }
1453
1454 event_handled:
1455         xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1456
1457         inc_deq(xhci, xhci->cmd_ring);
1458 }
1459
1460 static void handle_vendor_event(struct xhci_hcd *xhci,
1461                 union xhci_trb *event)
1462 {
1463         u32 trb_type;
1464
1465         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1466         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1467         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1468                 handle_cmd_completion(xhci, &event->event_cmd);
1469 }
1470
1471 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1472  * port registers -- USB 3.0 and USB 2.0).
1473  *
1474  * Returns a zero-based port number, which is suitable for indexing into each of
1475  * the split roothubs' port arrays and bus state arrays.
1476  * Add one to it in order to call xhci_find_slot_id_by_port.
1477  */
1478 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1479                 struct xhci_hcd *xhci, u32 port_id)
1480 {
1481         unsigned int i;
1482         unsigned int num_similar_speed_ports = 0;
1483
1484         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1485          * and usb2_ports are 0-based indexes.  Count the number of similar
1486          * speed ports, up to 1 port before this port.
1487          */
1488         for (i = 0; i < (port_id - 1); i++) {
1489                 u8 port_speed = xhci->port_array[i];
1490
1491                 /*
1492                  * Skip ports that don't have known speeds, or have duplicate
1493                  * Extended Capabilities port speed entries.
1494                  */
1495                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1496                         continue;
1497
1498                 /*
1499                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1500                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1501                  * matches the device speed, it's a similar speed port.
1502                  */
1503                 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1504                         num_similar_speed_ports++;
1505         }
1506         return num_similar_speed_ports;
1507 }
1508
1509 static void handle_device_notification(struct xhci_hcd *xhci,
1510                 union xhci_trb *event)
1511 {
1512         u32 slot_id;
1513         struct usb_device *udev;
1514
1515         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1516         if (!xhci->devs[slot_id]) {
1517                 xhci_warn(xhci, "Device Notification event for "
1518                                 "unused slot %u\n", slot_id);
1519                 return;
1520         }
1521
1522         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1523                         slot_id);
1524         udev = xhci->devs[slot_id]->udev;
1525         if (udev && udev->parent)
1526                 usb_wakeup_notification(udev->parent, udev->portnum);
1527 }
1528
1529 static void handle_port_status(struct xhci_hcd *xhci,
1530                 union xhci_trb *event)
1531 {
1532         struct usb_hcd *hcd;
1533         u32 port_id;
1534         u32 temp, temp1;
1535         int max_ports;
1536         int slot_id;
1537         unsigned int faked_port_index;
1538         u8 major_revision;
1539         struct xhci_bus_state *bus_state;
1540         __le32 __iomem **port_array;
1541         bool bogus_port_status = false;
1542
1543         /* Port status change events always have a successful completion code */
1544         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1545                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1546                 xhci->error_bitmask |= 1 << 8;
1547         }
1548         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1549         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1550
1551         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1552         if ((port_id <= 0) || (port_id > max_ports)) {
1553                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1554                 inc_deq(xhci, xhci->event_ring);
1555                 return;
1556         }
1557
1558         /* Figure out which usb_hcd this port is attached to:
1559          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1560          */
1561         major_revision = xhci->port_array[port_id - 1];
1562
1563         /* Find the right roothub. */
1564         hcd = xhci_to_hcd(xhci);
1565         if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1566                 hcd = xhci->shared_hcd;
1567
1568         if (major_revision == 0) {
1569                 xhci_warn(xhci, "Event for port %u not in "
1570                                 "Extended Capabilities, ignoring.\n",
1571                                 port_id);
1572                 bogus_port_status = true;
1573                 goto cleanup;
1574         }
1575         if (major_revision == DUPLICATE_ENTRY) {
1576                 xhci_warn(xhci, "Event for port %u duplicated in"
1577                                 "Extended Capabilities, ignoring.\n",
1578                                 port_id);
1579                 bogus_port_status = true;
1580                 goto cleanup;
1581         }
1582
1583         /*
1584          * Hardware port IDs reported by a Port Status Change Event include USB
1585          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1586          * resume event, but we first need to translate the hardware port ID
1587          * into the index into the ports on the correct split roothub, and the
1588          * correct bus_state structure.
1589          */
1590         bus_state = &xhci->bus_state[hcd_index(hcd)];
1591         if (hcd->speed >= HCD_USB3)
1592                 port_array = xhci->usb3_ports;
1593         else
1594                 port_array = xhci->usb2_ports;
1595         /* Find the faked port hub number */
1596         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1597                         port_id);
1598
1599         temp = readl(port_array[faked_port_index]);
1600         if (hcd->state == HC_STATE_SUSPENDED) {
1601                 xhci_dbg(xhci, "resume root hub\n");
1602                 usb_hcd_resume_root_hub(hcd);
1603         }
1604
1605         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1606                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1607
1608                 temp1 = readl(&xhci->op_regs->command);
1609                 if (!(temp1 & CMD_RUN)) {
1610                         xhci_warn(xhci, "xHC is not running.\n");
1611                         goto cleanup;
1612                 }
1613
1614                 if (DEV_SUPERSPEED_ANY(temp)) {
1615                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1616                         /* Set a flag to say the port signaled remote wakeup,
1617                          * so we can tell the difference between the end of
1618                          * device and host initiated resume.
1619                          */
1620                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1621                         xhci_test_and_clear_bit(xhci, port_array,
1622                                         faked_port_index, PORT_PLC);
1623                         usb_hcd_start_port_resume(&hcd->self, faked_port_index);
1624                         xhci_set_link_state(xhci, port_array, faked_port_index,
1625                                                 XDEV_U0);
1626                         /* Need to wait until the next link state change
1627                          * indicates the device is actually in U0.
1628                          */
1629                         bogus_port_status = true;
1630                         goto cleanup;
1631                 } else if (!test_bit(faked_port_index,
1632                                      &bus_state->resuming_ports)) {
1633                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1634                         bus_state->resume_done[faked_port_index] = jiffies +
1635                                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1636                         set_bit(faked_port_index, &bus_state->resuming_ports);
1637                         mod_timer(&hcd->rh_timer,
1638                                   bus_state->resume_done[faked_port_index]);
1639                         /* Do the rest in GetPortStatus */
1640                 }
1641         }
1642
1643         if ((temp & PORT_PLC) &&
1644             DEV_SUPERSPEED_ANY(temp) &&
1645             ((temp & PORT_PLS_MASK) == XDEV_U0 ||
1646              (temp & PORT_PLS_MASK) == XDEV_U1 ||
1647              (temp & PORT_PLS_MASK) == XDEV_U2)) {
1648                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1649                 /* We've just brought the device into U0/1/2 through either the
1650                  * Resume state after a device remote wakeup, or through the
1651                  * U3Exit state after a host-initiated resume.  If it's a device
1652                  * initiated remote wake, don't pass up the link state change,
1653                  * so the roothub behavior is consistent with external
1654                  * USB 3.0 hub behavior.
1655                  */
1656                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1657                                 faked_port_index + 1);
1658                 if (slot_id && xhci->devs[slot_id])
1659                         xhci_ring_device(xhci, slot_id);
1660                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1661                         xhci_test_and_clear_bit(xhci, port_array,
1662                                         faked_port_index, PORT_PLC);
1663                         usb_wakeup_notification(hcd->self.root_hub,
1664                                         faked_port_index + 1);
1665                         bogus_port_status = true;
1666                         goto cleanup;
1667                 }
1668         }
1669
1670         /*
1671          * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1672          * RExit to a disconnect state).  If so, let the the driver know it's
1673          * out of the RExit state.
1674          */
1675         if (!DEV_SUPERSPEED_ANY(temp) && hcd->speed < HCD_USB3 &&
1676                         test_and_clear_bit(faked_port_index,
1677                                 &bus_state->rexit_ports)) {
1678                 complete(&bus_state->rexit_done[faked_port_index]);
1679                 bogus_port_status = true;
1680                 goto cleanup;
1681         }
1682
1683         if (hcd->speed < HCD_USB3)
1684                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1685                                         PORT_PLC);
1686
1687 cleanup:
1688         /* Update event ring dequeue pointer before dropping the lock */
1689         inc_deq(xhci, xhci->event_ring);
1690
1691         /* Don't make the USB core poll the roothub if we got a bad port status
1692          * change event.  Besides, at that point we can't tell which roothub
1693          * (USB 2.0 or USB 3.0) to kick.
1694          */
1695         if (bogus_port_status)
1696                 return;
1697
1698         /*
1699          * xHCI port-status-change events occur when the "or" of all the
1700          * status-change bits in the portsc register changes from 0 to 1.
1701          * New status changes won't cause an event if any other change
1702          * bits are still set.  When an event occurs, switch over to
1703          * polling to avoid losing status changes.
1704          */
1705         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1706         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1707         spin_unlock(&xhci->lock);
1708         /* Pass this up to the core */
1709         usb_hcd_poll_rh_status(hcd);
1710         spin_lock(&xhci->lock);
1711 }
1712
1713 /*
1714  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1715  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1716  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1717  * returns 0.
1718  */
1719 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1720                 struct xhci_segment *start_seg,
1721                 union xhci_trb  *start_trb,
1722                 union xhci_trb  *end_trb,
1723                 dma_addr_t      suspect_dma,
1724                 bool            debug)
1725 {
1726         dma_addr_t start_dma;
1727         dma_addr_t end_seg_dma;
1728         dma_addr_t end_trb_dma;
1729         struct xhci_segment *cur_seg;
1730
1731         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1732         cur_seg = start_seg;
1733
1734         do {
1735                 if (start_dma == 0)
1736                         return NULL;
1737                 /* We may get an event for a Link TRB in the middle of a TD */
1738                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1739                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1740                 /* If the end TRB isn't in this segment, this is set to 0 */
1741                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1742
1743                 if (debug)
1744                         xhci_warn(xhci,
1745                                 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1746                                 (unsigned long long)suspect_dma,
1747                                 (unsigned long long)start_dma,
1748                                 (unsigned long long)end_trb_dma,
1749                                 (unsigned long long)cur_seg->dma,
1750                                 (unsigned long long)end_seg_dma);
1751
1752                 if (end_trb_dma > 0) {
1753                         /* The end TRB is in this segment, so suspect should be here */
1754                         if (start_dma <= end_trb_dma) {
1755                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1756                                         return cur_seg;
1757                         } else {
1758                                 /* Case for one segment with
1759                                  * a TD wrapped around to the top
1760                                  */
1761                                 if ((suspect_dma >= start_dma &&
1762                                                         suspect_dma <= end_seg_dma) ||
1763                                                 (suspect_dma >= cur_seg->dma &&
1764                                                  suspect_dma <= end_trb_dma))
1765                                         return cur_seg;
1766                         }
1767                         return NULL;
1768                 } else {
1769                         /* Might still be somewhere in this segment */
1770                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1771                                 return cur_seg;
1772                 }
1773                 cur_seg = cur_seg->next;
1774                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1775         } while (cur_seg != start_seg);
1776
1777         return NULL;
1778 }
1779
1780 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1781                 unsigned int slot_id, unsigned int ep_index,
1782                 unsigned int stream_id,
1783                 struct xhci_td *td, union xhci_trb *event_trb)
1784 {
1785         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1786         struct xhci_command *command;
1787         command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1788         if (!command)
1789                 return;
1790
1791         ep->ep_state |= EP_HALTED;
1792         ep->stopped_stream = stream_id;
1793
1794         xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1795         xhci_cleanup_stalled_ring(xhci, ep_index, td);
1796
1797         ep->stopped_stream = 0;
1798
1799         xhci_ring_cmd_db(xhci);
1800 }
1801
1802 /* Check if an error has halted the endpoint ring.  The class driver will
1803  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1804  * However, a babble and other errors also halt the endpoint ring, and the class
1805  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1806  * Ring Dequeue Pointer command manually.
1807  */
1808 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1809                 struct xhci_ep_ctx *ep_ctx,
1810                 unsigned int trb_comp_code)
1811 {
1812         /* TRB completion codes that may require a manual halt cleanup */
1813         if (trb_comp_code == COMP_TX_ERR ||
1814                         trb_comp_code == COMP_BABBLE ||
1815                         trb_comp_code == COMP_SPLIT_ERR)
1816                 /* The 0.96 spec says a babbling control endpoint
1817                  * is not halted. The 0.96 spec says it is.  Some HW
1818                  * claims to be 0.95 compliant, but it halts the control
1819                  * endpoint anyway.  Check if a babble halted the
1820                  * endpoint.
1821                  */
1822                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1823                     cpu_to_le32(EP_STATE_HALTED))
1824                         return 1;
1825
1826         return 0;
1827 }
1828
1829 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1830 {
1831         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1832                 /* Vendor defined "informational" completion code,
1833                  * treat as not-an-error.
1834                  */
1835                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1836                                 trb_comp_code);
1837                 xhci_dbg(xhci, "Treating code as success.\n");
1838                 return 1;
1839         }
1840         return 0;
1841 }
1842
1843 /*
1844  * Finish the td processing, remove the td from td list;
1845  * Return 1 if the urb can be given back.
1846  */
1847 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1848         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1849         struct xhci_virt_ep *ep, int *status, bool skip)
1850 {
1851         struct xhci_virt_device *xdev;
1852         struct xhci_ring *ep_ring;
1853         unsigned int slot_id;
1854         int ep_index;
1855         struct urb *urb = NULL;
1856         struct xhci_ep_ctx *ep_ctx;
1857         int ret = 0;
1858         struct urb_priv *urb_priv;
1859         u32 trb_comp_code;
1860
1861         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1862         xdev = xhci->devs[slot_id];
1863         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1864         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1865         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1866         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1867
1868         if (skip)
1869                 goto td_cleanup;
1870
1871         if (trb_comp_code == COMP_STOP_INVAL ||
1872                         trb_comp_code == COMP_STOP ||
1873                         trb_comp_code == COMP_STOP_SHORT) {
1874                 /* The Endpoint Stop Command completion will take care of any
1875                  * stopped TDs.  A stopped TD may be restarted, so don't update
1876                  * the ring dequeue pointer or take this TD off any lists yet.
1877                  */
1878                 ep->stopped_td = td;
1879                 return 0;
1880         }
1881         if (trb_comp_code == COMP_STALL ||
1882                 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1883                                                 trb_comp_code)) {
1884                 /* Issue a reset endpoint command to clear the host side
1885                  * halt, followed by a set dequeue command to move the
1886                  * dequeue pointer past the TD.
1887                  * The class driver clears the device side halt later.
1888                  */
1889                 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1890                                         ep_ring->stream_id, td, event_trb);
1891         } else {
1892                 /* Update ring dequeue pointer */
1893                 while (ep_ring->dequeue != td->last_trb)
1894                         inc_deq(xhci, ep_ring);
1895                 inc_deq(xhci, ep_ring);
1896         }
1897
1898 td_cleanup:
1899         /* Clean up the endpoint's TD list */
1900         urb = td->urb;
1901         urb_priv = urb->hcpriv;
1902
1903         /* Do one last check of the actual transfer length.
1904          * If the host controller said we transferred more data than the buffer
1905          * length, urb->actual_length will be a very big number (since it's
1906          * unsigned).  Play it safe and say we didn't transfer anything.
1907          */
1908         if (urb->actual_length > urb->transfer_buffer_length) {
1909                 xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1910                         urb->transfer_buffer_length,
1911                         urb->actual_length);
1912                 urb->actual_length = 0;
1913                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1914                         *status = -EREMOTEIO;
1915                 else
1916                         *status = 0;
1917         }
1918         list_del_init(&td->td_list);
1919         /* Was this TD slated to be cancelled but completed anyway? */
1920         if (!list_empty(&td->cancelled_td_list))
1921                 list_del_init(&td->cancelled_td_list);
1922
1923         urb_priv->td_cnt++;
1924         /* Giveback the urb when all the tds are completed */
1925         if (urb_priv->td_cnt == urb_priv->length) {
1926                 ret = 1;
1927                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1928                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1929                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
1930                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1931                                         usb_amd_quirk_pll_enable();
1932                         }
1933                 }
1934         }
1935
1936         return ret;
1937 }
1938
1939 /*
1940  * Process control tds, update urb status and actual_length.
1941  */
1942 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1943         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1944         struct xhci_virt_ep *ep, int *status)
1945 {
1946         struct xhci_virt_device *xdev;
1947         struct xhci_ring *ep_ring;
1948         unsigned int slot_id;
1949         int ep_index;
1950         struct xhci_ep_ctx *ep_ctx;
1951         u32 trb_comp_code;
1952
1953         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1954         xdev = xhci->devs[slot_id];
1955         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1956         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1957         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1958         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1959
1960         switch (trb_comp_code) {
1961         case COMP_SUCCESS:
1962                 if (event_trb == ep_ring->dequeue) {
1963                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1964                                         "without IOC set??\n");
1965                         *status = -ESHUTDOWN;
1966                 } else if (event_trb != td->last_trb) {
1967                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1968                                         "without IOC set??\n");
1969                         *status = -ESHUTDOWN;
1970                 } else {
1971                         *status = 0;
1972                 }
1973                 break;
1974         case COMP_SHORT_TX:
1975                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1976                         *status = -EREMOTEIO;
1977                 else
1978                         *status = 0;
1979                 break;
1980         case COMP_STOP_SHORT:
1981                 if (event_trb == ep_ring->dequeue || event_trb == td->last_trb)
1982                         xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
1983                 else
1984                         td->urb->actual_length =
1985                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1986
1987                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1988         case COMP_STOP:
1989                 /* Did we stop at data stage? */
1990                 if (event_trb != ep_ring->dequeue && event_trb != td->last_trb)
1991                         td->urb->actual_length =
1992                                 td->urb->transfer_buffer_length -
1993                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1994                 /* fall through */
1995         case COMP_STOP_INVAL:
1996                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1997         default:
1998                 if (!xhci_requires_manual_halt_cleanup(xhci,
1999                                         ep_ctx, trb_comp_code))
2000                         break;
2001                 xhci_dbg(xhci, "TRB error code %u, "
2002                                 "halted endpoint index = %u\n",
2003                                 trb_comp_code, ep_index);
2004                 /* else fall through */
2005         case COMP_STALL:
2006                 /* Did we transfer part of the data (middle) phase? */
2007                 if (event_trb != ep_ring->dequeue &&
2008                                 event_trb != td->last_trb)
2009                         td->urb->actual_length =
2010                                 td->urb->transfer_buffer_length -
2011                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2012                 else if (!td->urb_length_set)
2013                         td->urb->actual_length = 0;
2014
2015                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2016         }
2017         /*
2018          * Did we transfer any data, despite the errors that might have
2019          * happened?  I.e. did we get past the setup stage?
2020          */
2021         if (event_trb != ep_ring->dequeue) {
2022                 /* The event was for the status stage */
2023                 if (event_trb == td->last_trb) {
2024                         if (td->urb_length_set) {
2025                                 /* Don't overwrite a previously set error code
2026                                  */
2027                                 if ((*status == -EINPROGRESS || *status == 0) &&
2028                                                 (td->urb->transfer_flags
2029                                                  & URB_SHORT_NOT_OK))
2030                                         /* Did we already see a short data
2031                                          * stage? */
2032                                         *status = -EREMOTEIO;
2033                         } else {
2034                                 td->urb->actual_length =
2035                                         td->urb->transfer_buffer_length;
2036                         }
2037                 } else {
2038                         /*
2039                          * Maybe the event was for the data stage? If so, update
2040                          * already the actual_length of the URB and flag it as
2041                          * set, so that it is not overwritten in the event for
2042                          * the last TRB.
2043                          */
2044                         td->urb_length_set = true;
2045                         td->urb->actual_length =
2046                                 td->urb->transfer_buffer_length -
2047                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2048                         xhci_dbg(xhci, "Waiting for status "
2049                                         "stage event\n");
2050                         return 0;
2051                 }
2052         }
2053
2054         return finish_td(xhci, td, event_trb, event, ep, status, false);
2055 }
2056
2057 /*
2058  * Process isochronous tds, update urb packet status and actual_length.
2059  */
2060 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2061         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2062         struct xhci_virt_ep *ep, int *status)
2063 {
2064         struct xhci_ring *ep_ring;
2065         struct urb_priv *urb_priv;
2066         int idx;
2067         int len = 0;
2068         union xhci_trb *cur_trb;
2069         struct xhci_segment *cur_seg;
2070         struct usb_iso_packet_descriptor *frame;
2071         u32 trb_comp_code;
2072         bool skip_td = false;
2073
2074         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2075         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2076         urb_priv = td->urb->hcpriv;
2077         idx = urb_priv->td_cnt;
2078         frame = &td->urb->iso_frame_desc[idx];
2079
2080         /* handle completion code */
2081         switch (trb_comp_code) {
2082         case COMP_SUCCESS:
2083                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2084                         frame->status = 0;
2085                         break;
2086                 }
2087                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2088                         trb_comp_code = COMP_SHORT_TX;
2089         /* fallthrough */
2090         case COMP_STOP_SHORT:
2091         case COMP_SHORT_TX:
2092                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2093                                 -EREMOTEIO : 0;
2094                 break;
2095         case COMP_BW_OVER:
2096                 frame->status = -ECOMM;
2097                 skip_td = true;
2098                 break;
2099         case COMP_BUFF_OVER:
2100         case COMP_BABBLE:
2101                 frame->status = -EOVERFLOW;
2102                 skip_td = true;
2103                 break;
2104         case COMP_DEV_ERR:
2105         case COMP_STALL:
2106                 frame->status = -EPROTO;
2107                 skip_td = true;
2108                 break;
2109         case COMP_TX_ERR:
2110                 frame->status = -EPROTO;
2111                 if (event_trb != td->last_trb)
2112                         return 0;
2113                 skip_td = true;
2114                 break;
2115         case COMP_STOP:
2116         case COMP_STOP_INVAL:
2117                 break;
2118         default:
2119                 frame->status = -1;
2120                 break;
2121         }
2122
2123         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2124                 frame->actual_length = frame->length;
2125                 td->urb->actual_length += frame->length;
2126         } else if (trb_comp_code == COMP_STOP_SHORT) {
2127                 frame->actual_length =
2128                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2129                 td->urb->actual_length += frame->actual_length;
2130         } else {
2131                 for (cur_trb = ep_ring->dequeue,
2132                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2133                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2134                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2135                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2136                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2137                 }
2138                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2139                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2140
2141                 if (trb_comp_code != COMP_STOP_INVAL) {
2142                         frame->actual_length = len;
2143                         td->urb->actual_length += len;
2144                 }
2145         }
2146
2147         return finish_td(xhci, td, event_trb, event, ep, status, false);
2148 }
2149
2150 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2151                         struct xhci_transfer_event *event,
2152                         struct xhci_virt_ep *ep, int *status)
2153 {
2154         struct xhci_ring *ep_ring;
2155         struct urb_priv *urb_priv;
2156         struct usb_iso_packet_descriptor *frame;
2157         int idx;
2158
2159         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2160         urb_priv = td->urb->hcpriv;
2161         idx = urb_priv->td_cnt;
2162         frame = &td->urb->iso_frame_desc[idx];
2163
2164         /* The transfer is partly done. */
2165         frame->status = -EXDEV;
2166
2167         /* calc actual length */
2168         frame->actual_length = 0;
2169
2170         /* Update ring dequeue pointer */
2171         while (ep_ring->dequeue != td->last_trb)
2172                 inc_deq(xhci, ep_ring);
2173         inc_deq(xhci, ep_ring);
2174
2175         return finish_td(xhci, td, NULL, event, ep, status, true);
2176 }
2177
2178 /*
2179  * Process bulk and interrupt tds, update urb status and actual_length.
2180  */
2181 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2182         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2183         struct xhci_virt_ep *ep, int *status)
2184 {
2185         struct xhci_ring *ep_ring;
2186         union xhci_trb *cur_trb;
2187         struct xhci_segment *cur_seg;
2188         u32 trb_comp_code;
2189
2190         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2191         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2192
2193         switch (trb_comp_code) {
2194         case COMP_SUCCESS:
2195                 /* Double check that the HW transferred everything. */
2196                 if (event_trb != td->last_trb ||
2197                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2198                         xhci_warn(xhci, "WARN Successful completion "
2199                                         "on short TX\n");
2200                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2201                                 *status = -EREMOTEIO;
2202                         else
2203                                 *status = 0;
2204                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2205                                 trb_comp_code = COMP_SHORT_TX;
2206                 } else {
2207                         *status = 0;
2208                 }
2209                 break;
2210         case COMP_STOP_SHORT:
2211         case COMP_SHORT_TX:
2212                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2213                         *status = -EREMOTEIO;
2214                 else
2215                         *status = 0;
2216                 break;
2217         default:
2218                 /* Others already handled above */
2219                 break;
2220         }
2221         if (trb_comp_code == COMP_SHORT_TX)
2222                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2223                                 "%d bytes untransferred\n",
2224                                 td->urb->ep->desc.bEndpointAddress,
2225                                 td->urb->transfer_buffer_length,
2226                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2227         /* Stopped - short packet completion */
2228         if (trb_comp_code == COMP_STOP_SHORT) {
2229                 td->urb->actual_length =
2230                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2231
2232                 if (td->urb->transfer_buffer_length <
2233                                 td->urb->actual_length) {
2234                         xhci_warn(xhci, "HC gave bad length of %d bytes txed\n",
2235                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2236                         td->urb->actual_length = 0;
2237                          /* status will be set by usb core for canceled urbs */
2238                 }
2239         /* Fast path - was this the last TRB in the TD for this URB? */
2240         } else if (event_trb == td->last_trb) {
2241                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2242                         td->urb->actual_length =
2243                                 td->urb->transfer_buffer_length -
2244                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2245                         if (td->urb->transfer_buffer_length <
2246                                         td->urb->actual_length) {
2247                                 xhci_warn(xhci, "HC gave bad length "
2248                                                 "of %d bytes left\n",
2249                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2250                                 td->urb->actual_length = 0;
2251                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2252                                         *status = -EREMOTEIO;
2253                                 else
2254                                         *status = 0;
2255                         }
2256                         /* Don't overwrite a previously set error code */
2257                         if (*status == -EINPROGRESS) {
2258                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2259                                         *status = -EREMOTEIO;
2260                                 else
2261                                         *status = 0;
2262                         }
2263                 } else {
2264                         td->urb->actual_length =
2265                                 td->urb->transfer_buffer_length;
2266                         /* Ignore a short packet completion if the
2267                          * untransferred length was zero.
2268                          */
2269                         if (*status == -EREMOTEIO)
2270                                 *status = 0;
2271                 }
2272         } else {
2273                 /* Slow path - walk the list, starting from the dequeue
2274                  * pointer, to get the actual length transferred.
2275                  */
2276                 td->urb->actual_length = 0;
2277                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2278                                 cur_trb != event_trb;
2279                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2280                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2281                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2282                                 td->urb->actual_length +=
2283                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2284                 }
2285                 /* If the ring didn't stop on a Link or No-op TRB, add
2286                  * in the actual bytes transferred from the Normal TRB
2287                  */
2288                 if (trb_comp_code != COMP_STOP_INVAL)
2289                         td->urb->actual_length +=
2290                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2291                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2292         }
2293
2294         return finish_td(xhci, td, event_trb, event, ep, status, false);
2295 }
2296
2297 /*
2298  * If this function returns an error condition, it means it got a Transfer
2299  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2300  * At this point, the host controller is probably hosed and should be reset.
2301  */
2302 static int handle_tx_event(struct xhci_hcd *xhci,
2303                 struct xhci_transfer_event *event)
2304         __releases(&xhci->lock)
2305         __acquires(&xhci->lock)
2306 {
2307         struct xhci_virt_device *xdev;
2308         struct xhci_virt_ep *ep;
2309         struct xhci_ring *ep_ring;
2310         unsigned int slot_id;
2311         int ep_index;
2312         struct xhci_td *td = NULL;
2313         dma_addr_t event_dma;
2314         struct xhci_segment *event_seg;
2315         union xhci_trb *event_trb;
2316         struct urb *urb = NULL;
2317         int status = -EINPROGRESS;
2318         struct urb_priv *urb_priv;
2319         struct xhci_ep_ctx *ep_ctx;
2320         struct list_head *tmp;
2321         u32 trb_comp_code;
2322         int ret = 0;
2323         int td_num = 0;
2324         bool handling_skipped_tds = false;
2325
2326         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2327         xdev = xhci->devs[slot_id];
2328         if (!xdev) {
2329                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2330                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2331                          (unsigned long long) xhci_trb_virt_to_dma(
2332                                  xhci->event_ring->deq_seg,
2333                                  xhci->event_ring->dequeue),
2334                          lower_32_bits(le64_to_cpu(event->buffer)),
2335                          upper_32_bits(le64_to_cpu(event->buffer)),
2336                          le32_to_cpu(event->transfer_len),
2337                          le32_to_cpu(event->flags));
2338                 xhci_dbg(xhci, "Event ring:\n");
2339                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2340                 return -ENODEV;
2341         }
2342
2343         /* Endpoint ID is 1 based, our index is zero based */
2344         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2345         ep = &xdev->eps[ep_index];
2346         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2347         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2348         if (!ep_ring ||
2349             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2350             EP_STATE_DISABLED) {
2351                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2352                                 "or incorrect stream ring\n");
2353                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2354                          (unsigned long long) xhci_trb_virt_to_dma(
2355                                  xhci->event_ring->deq_seg,
2356                                  xhci->event_ring->dequeue),
2357                          lower_32_bits(le64_to_cpu(event->buffer)),
2358                          upper_32_bits(le64_to_cpu(event->buffer)),
2359                          le32_to_cpu(event->transfer_len),
2360                          le32_to_cpu(event->flags));
2361                 xhci_dbg(xhci, "Event ring:\n");
2362                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2363                 return -ENODEV;
2364         }
2365
2366         /* Count current td numbers if ep->skip is set */
2367         if (ep->skip) {
2368                 list_for_each(tmp, &ep_ring->td_list)
2369                         td_num++;
2370         }
2371
2372         event_dma = le64_to_cpu(event->buffer);
2373         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2374         /* Look for common error cases */
2375         switch (trb_comp_code) {
2376         /* Skip codes that require special handling depending on
2377          * transfer type
2378          */
2379         case COMP_SUCCESS:
2380                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2381                         break;
2382                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2383                         trb_comp_code = COMP_SHORT_TX;
2384                 else
2385                         xhci_warn_ratelimited(xhci,
2386                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2387         case COMP_SHORT_TX:
2388                 break;
2389         case COMP_STOP:
2390                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2391                 break;
2392         case COMP_STOP_INVAL:
2393                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2394                 break;
2395         case COMP_STOP_SHORT:
2396                 xhci_dbg(xhci, "Stopped with short packet transfer detected\n");
2397                 break;
2398         case COMP_STALL:
2399                 xhci_dbg(xhci, "Stalled endpoint\n");
2400                 ep->ep_state |= EP_HALTED;
2401                 status = -EPIPE;
2402                 break;
2403         case COMP_TRB_ERR:
2404                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2405                 status = -EILSEQ;
2406                 break;
2407         case COMP_SPLIT_ERR:
2408         case COMP_TX_ERR:
2409                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2410                 status = -EPROTO;
2411                 break;
2412         case COMP_BABBLE:
2413                 xhci_dbg(xhci, "Babble error on endpoint\n");
2414                 status = -EOVERFLOW;
2415                 break;
2416         case COMP_DB_ERR:
2417                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2418                 status = -ENOSR;
2419                 break;
2420         case COMP_BW_OVER:
2421                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2422                 break;
2423         case COMP_BUFF_OVER:
2424                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2425                 break;
2426         case COMP_UNDERRUN:
2427                 /*
2428                  * When the Isoch ring is empty, the xHC will generate
2429                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2430                  * Underrun Event for OUT Isoch endpoint.
2431                  */
2432                 xhci_dbg(xhci, "underrun event on endpoint\n");
2433                 if (!list_empty(&ep_ring->td_list))
2434                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2435                                         "still with TDs queued?\n",
2436                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2437                                  ep_index);
2438                 goto cleanup;
2439         case COMP_OVERRUN:
2440                 xhci_dbg(xhci, "overrun event on endpoint\n");
2441                 if (!list_empty(&ep_ring->td_list))
2442                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2443                                         "still with TDs queued?\n",
2444                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2445                                  ep_index);
2446                 goto cleanup;
2447         case COMP_DEV_ERR:
2448                 xhci_warn(xhci, "WARN: detect an incompatible device");
2449                 status = -EPROTO;
2450                 break;
2451         case COMP_MISSED_INT:
2452                 /*
2453                  * When encounter missed service error, one or more isoc tds
2454                  * may be missed by xHC.
2455                  * Set skip flag of the ep_ring; Complete the missed tds as
2456                  * short transfer when process the ep_ring next time.
2457                  */
2458                 ep->skip = true;
2459                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2460                 goto cleanup;
2461         case COMP_PING_ERR:
2462                 ep->skip = true;
2463                 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2464                 goto cleanup;
2465         default:
2466                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2467                         status = 0;
2468                         break;
2469                 }
2470                 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n",
2471                           trb_comp_code);
2472                 goto cleanup;
2473         }
2474
2475         do {
2476                 /* This TRB should be in the TD at the head of this ring's
2477                  * TD list.
2478                  */
2479                 if (list_empty(&ep_ring->td_list)) {
2480                         /*
2481                          * A stopped endpoint may generate an extra completion
2482                          * event if the device was suspended.  Don't print
2483                          * warnings.
2484                          */
2485                         if (!(trb_comp_code == COMP_STOP ||
2486                                                 trb_comp_code == COMP_STOP_INVAL)) {
2487                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2488                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2489                                                 ep_index);
2490                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2491                                                 (le32_to_cpu(event->flags) &
2492                                                  TRB_TYPE_BITMASK)>>10);
2493                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2494                         }
2495                         if (ep->skip) {
2496                                 ep->skip = false;
2497                                 xhci_dbg(xhci, "td_list is empty while skip "
2498                                                 "flag set. Clear skip flag.\n");
2499                         }
2500                         ret = 0;
2501                         goto cleanup;
2502                 }
2503
2504                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2505                 if (ep->skip && td_num == 0) {
2506                         ep->skip = false;
2507                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2508                                                 "Clear skip flag.\n");
2509                         ret = 0;
2510                         goto cleanup;
2511                 }
2512
2513                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2514                 if (ep->skip)
2515                         td_num--;
2516
2517                 /* Is this a TRB in the currently executing TD? */
2518                 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2519                                 td->last_trb, event_dma, false);
2520
2521                 /*
2522                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2523                  * is not in the current TD pointed by ep_ring->dequeue because
2524                  * that the hardware dequeue pointer still at the previous TRB
2525                  * of the current TD. The previous TRB maybe a Link TD or the
2526                  * last TRB of the previous TD. The command completion handle
2527                  * will take care the rest.
2528                  */
2529                 if (!event_seg && (trb_comp_code == COMP_STOP ||
2530                                    trb_comp_code == COMP_STOP_INVAL)) {
2531                         ret = 0;
2532                         goto cleanup;
2533                 }
2534
2535                 if (!event_seg) {
2536                         if (!ep->skip ||
2537                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2538                                 /* Some host controllers give a spurious
2539                                  * successful event after a short transfer.
2540                                  * Ignore it.
2541                                  */
2542                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2543                                                 ep_ring->last_td_was_short) {
2544                                         ep_ring->last_td_was_short = false;
2545                                         ret = 0;
2546                                         goto cleanup;
2547                                 }
2548                                 /* HC is busted, give up! */
2549                                 xhci_err(xhci,
2550                                         "ERROR Transfer event TRB DMA ptr not "
2551                                         "part of current TD ep_index %d "
2552                                         "comp_code %u\n", ep_index,
2553                                         trb_comp_code);
2554                                 trb_in_td(xhci, ep_ring->deq_seg,
2555                                           ep_ring->dequeue, td->last_trb,
2556                                           event_dma, true);
2557                                 return -ESHUTDOWN;
2558                         }
2559
2560                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2561                         goto cleanup;
2562                 }
2563                 if (trb_comp_code == COMP_SHORT_TX)
2564                         ep_ring->last_td_was_short = true;
2565                 else
2566                         ep_ring->last_td_was_short = false;
2567
2568                 if (ep->skip) {
2569                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2570                         ep->skip = false;
2571                 }
2572
2573                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2574                                                 sizeof(*event_trb)];
2575                 /*
2576                  * No-op TRB should not trigger interrupts.
2577                  * If event_trb is a no-op TRB, it means the
2578                  * corresponding TD has been cancelled. Just ignore
2579                  * the TD.
2580                  */
2581                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2582                         xhci_dbg(xhci,
2583                                  "event_trb is a no-op TRB. Skip it\n");
2584                         goto cleanup;
2585                 }
2586
2587                 /* Now update the urb's actual_length and give back to
2588                  * the core
2589                  */
2590                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2591                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2592                                                  &status);
2593                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2594                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2595                                                  &status);
2596                 else
2597                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2598                                                  ep, &status);
2599
2600 cleanup:
2601
2602
2603                 handling_skipped_tds = ep->skip &&
2604                         trb_comp_code != COMP_MISSED_INT &&
2605                         trb_comp_code != COMP_PING_ERR;
2606
2607                 /*
2608                  * Do not update event ring dequeue pointer if we're in a loop
2609                  * processing missed tds.
2610                  */
2611                 if (!handling_skipped_tds)
2612                         inc_deq(xhci, xhci->event_ring);
2613
2614                 if (ret) {
2615                         urb = td->urb;
2616                         urb_priv = urb->hcpriv;
2617
2618                         xhci_urb_free_priv(urb_priv);
2619
2620                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2621                         if ((urb->actual_length != urb->transfer_buffer_length &&
2622                                                 (urb->transfer_flags &
2623                                                  URB_SHORT_NOT_OK)) ||
2624                                         (status != 0 &&
2625                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2626                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2627                                                 "expected = %d, status = %d\n",
2628                                                 urb, urb->actual_length,
2629                                                 urb->transfer_buffer_length,
2630                                                 status);
2631                         spin_unlock(&xhci->lock);
2632                         /* EHCI, UHCI, and OHCI always unconditionally set the
2633                          * urb->status of an isochronous endpoint to 0.
2634                          */
2635                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2636                                 status = 0;
2637                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2638                         spin_lock(&xhci->lock);
2639                 }
2640
2641         /*
2642          * If ep->skip is set, it means there are missed tds on the
2643          * endpoint ring need to take care of.
2644          * Process them as short transfer until reach the td pointed by
2645          * the event.
2646          */
2647         } while (handling_skipped_tds);
2648
2649         return 0;
2650 }
2651
2652 /*
2653  * This function handles all OS-owned events on the event ring.  It may drop
2654  * xhci->lock between event processing (e.g. to pass up port status changes).
2655  * Returns >0 for "possibly more events to process" (caller should call again),
2656  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2657  */
2658 static int xhci_handle_event(struct xhci_hcd *xhci)
2659 {
2660         union xhci_trb *event;
2661         int update_ptrs = 1;
2662         int ret;
2663
2664         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2665                 xhci->error_bitmask |= 1 << 1;
2666                 return 0;
2667         }
2668
2669         event = xhci->event_ring->dequeue;
2670         /* Does the HC or OS own the TRB? */
2671         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2672             xhci->event_ring->cycle_state) {
2673                 xhci->error_bitmask |= 1 << 2;
2674                 return 0;
2675         }
2676
2677         /*
2678          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2679          * speculative reads of the event's flags/data below.
2680          */
2681         rmb();
2682         /* FIXME: Handle more event types. */
2683         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2684         case TRB_TYPE(TRB_COMPLETION):
2685                 handle_cmd_completion(xhci, &event->event_cmd);
2686                 break;
2687         case TRB_TYPE(TRB_PORT_STATUS):
2688                 handle_port_status(xhci, event);
2689                 update_ptrs = 0;
2690                 break;
2691         case TRB_TYPE(TRB_TRANSFER):
2692                 ret = handle_tx_event(xhci, &event->trans_event);
2693                 if (ret < 0)
2694                         xhci->error_bitmask |= 1 << 9;
2695                 else
2696                         update_ptrs = 0;
2697                 break;
2698         case TRB_TYPE(TRB_DEV_NOTE):
2699                 handle_device_notification(xhci, event);
2700                 break;
2701         default:
2702                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2703                     TRB_TYPE(48))
2704                         handle_vendor_event(xhci, event);
2705                 else
2706                         xhci->error_bitmask |= 1 << 3;
2707         }
2708         /* Any of the above functions may drop and re-acquire the lock, so check
2709          * to make sure a watchdog timer didn't mark the host as non-responsive.
2710          */
2711         if (xhci->xhc_state & XHCI_STATE_DYING) {
2712                 xhci_dbg(xhci, "xHCI host dying, returning from "
2713                                 "event handler.\n");
2714                 return 0;
2715         }
2716
2717         if (update_ptrs)
2718                 /* Update SW event ring dequeue pointer */
2719                 inc_deq(xhci, xhci->event_ring);
2720
2721         /* Are there more items on the event ring?  Caller will call us again to
2722          * check.
2723          */
2724         return 1;
2725 }
2726
2727 /*
2728  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2729  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2730  * indicators of an event TRB error, but we check the status *first* to be safe.
2731  */
2732 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2733 {
2734         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2735         u32 status;
2736         u64 temp_64;
2737         union xhci_trb *event_ring_deq;
2738         dma_addr_t deq;
2739
2740         spin_lock(&xhci->lock);
2741         /* Check if the xHC generated the interrupt, or the irq is shared */
2742         status = readl(&xhci->op_regs->status);
2743         if (status == 0xffffffff)
2744                 goto hw_died;
2745
2746         if (!(status & STS_EINT)) {
2747                 spin_unlock(&xhci->lock);
2748                 return IRQ_NONE;
2749         }
2750         if (status & STS_FATAL) {
2751                 xhci_warn(xhci, "WARNING: Host System Error\n");
2752                 xhci_halt(xhci);
2753 hw_died:
2754                 spin_unlock(&xhci->lock);
2755                 return IRQ_HANDLED;
2756         }
2757
2758         /*
2759          * Clear the op reg interrupt status first,
2760          * so we can receive interrupts from other MSI-X interrupters.
2761          * Write 1 to clear the interrupt status.
2762          */
2763         status |= STS_EINT;
2764         writel(status, &xhci->op_regs->status);
2765         /* FIXME when MSI-X is supported and there are multiple vectors */
2766         /* Clear the MSI-X event interrupt status */
2767
2768         if (hcd->irq) {
2769                 u32 irq_pending;
2770                 /* Acknowledge the PCI interrupt */
2771                 irq_pending = readl(&xhci->ir_set->irq_pending);
2772                 irq_pending |= IMAN_IP;
2773                 writel(irq_pending, &xhci->ir_set->irq_pending);
2774         }
2775
2776         if (xhci->xhc_state & XHCI_STATE_DYING ||
2777             xhci->xhc_state & XHCI_STATE_HALTED) {
2778                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2779                                 "Shouldn't IRQs be disabled?\n");
2780                 /* Clear the event handler busy flag (RW1C);
2781                  * the event ring should be empty.
2782                  */
2783                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2784                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2785                                 &xhci->ir_set->erst_dequeue);
2786                 spin_unlock(&xhci->lock);
2787
2788                 return IRQ_HANDLED;
2789         }
2790
2791         event_ring_deq = xhci->event_ring->dequeue;
2792         /* FIXME this should be a delayed service routine
2793          * that clears the EHB.
2794          */
2795         while (xhci_handle_event(xhci) > 0) {}
2796
2797         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2798         /* If necessary, update the HW's version of the event ring deq ptr. */
2799         if (event_ring_deq != xhci->event_ring->dequeue) {
2800                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2801                                 xhci->event_ring->dequeue);
2802                 if (deq == 0)
2803                         xhci_warn(xhci, "WARN something wrong with SW event "
2804                                         "ring dequeue ptr.\n");
2805                 /* Update HC event ring dequeue pointer */
2806                 temp_64 &= ERST_PTR_MASK;
2807                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2808         }
2809
2810         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2811         temp_64 |= ERST_EHB;
2812         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2813
2814         spin_unlock(&xhci->lock);
2815
2816         return IRQ_HANDLED;
2817 }
2818
2819 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2820 {
2821         return xhci_irq(hcd);
2822 }
2823
2824 /****           Endpoint Ring Operations        ****/
2825
2826 /*
2827  * Generic function for queueing a TRB on a ring.
2828  * The caller must have checked to make sure there's room on the ring.
2829  *
2830  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2831  *                      prepare_transfer()?
2832  */
2833 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2834                 bool more_trbs_coming,
2835                 u32 field1, u32 field2, u32 field3, u32 field4)
2836 {
2837         struct xhci_generic_trb *trb;
2838
2839         trb = &ring->enqueue->generic;
2840         trb->field[0] = cpu_to_le32(field1);
2841         trb->field[1] = cpu_to_le32(field2);
2842         trb->field[2] = cpu_to_le32(field3);
2843         /* make sure TRB is fully written before giving it to the controller */
2844         wmb();
2845         trb->field[3] = cpu_to_le32(field4);
2846         inc_enq(xhci, ring, more_trbs_coming);
2847 }
2848
2849 /*
2850  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2851  * FIXME allocate segments if the ring is full.
2852  */
2853 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2854                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2855 {
2856         unsigned int num_trbs_needed;
2857
2858         /* Make sure the endpoint has been added to xHC schedule */
2859         switch (ep_state) {
2860         case EP_STATE_DISABLED:
2861                 /*
2862                  * USB core changed config/interfaces without notifying us,
2863                  * or hardware is reporting the wrong state.
2864                  */
2865                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2866                 return -ENOENT;
2867         case EP_STATE_ERROR:
2868                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2869                 /* FIXME event handling code for error needs to clear it */
2870                 /* XXX not sure if this should be -ENOENT or not */
2871                 return -EINVAL;
2872         case EP_STATE_HALTED:
2873                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2874         case EP_STATE_STOPPED:
2875         case EP_STATE_RUNNING:
2876                 break;
2877         default:
2878                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2879                 /*
2880                  * FIXME issue Configure Endpoint command to try to get the HC
2881                  * back into a known state.
2882                  */
2883                 return -EINVAL;
2884         }
2885
2886         while (1) {
2887                 if (room_on_ring(xhci, ep_ring, num_trbs))
2888                         break;
2889
2890                 if (ep_ring == xhci->cmd_ring) {
2891                         xhci_err(xhci, "Do not support expand command ring\n");
2892                         return -ENOMEM;
2893                 }
2894
2895                 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2896                                 "ERROR no room on ep ring, try ring expansion");
2897                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2898                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2899                                         mem_flags)) {
2900                         xhci_err(xhci, "Ring expansion failed\n");
2901                         return -ENOMEM;
2902                 }
2903         }
2904
2905         if (enqueue_is_link_trb(ep_ring)) {
2906                 struct xhci_ring *ring = ep_ring;
2907                 union xhci_trb *next;
2908
2909                 next = ring->enqueue;
2910
2911                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2912                         /* If we're not dealing with 0.95 hardware or isoc rings
2913                          * on AMD 0.96 host, clear the chain bit.
2914                          */
2915                         if (!xhci_link_trb_quirk(xhci) &&
2916                                         !(ring->type == TYPE_ISOC &&
2917                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
2918                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2919                         else
2920                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2921
2922                         wmb();
2923                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2924
2925                         /* Toggle the cycle bit after the last ring segment. */
2926                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2927                                 ring->cycle_state ^= 1;
2928                         }
2929                         ring->enq_seg = ring->enq_seg->next;
2930                         ring->enqueue = ring->enq_seg->trbs;
2931                         next = ring->enqueue;
2932                 }
2933         }
2934
2935         return 0;
2936 }
2937
2938 static int prepare_transfer(struct xhci_hcd *xhci,
2939                 struct xhci_virt_device *xdev,
2940                 unsigned int ep_index,
2941                 unsigned int stream_id,
2942                 unsigned int num_trbs,
2943                 struct urb *urb,
2944                 unsigned int td_index,
2945                 gfp_t mem_flags)
2946 {
2947         int ret;
2948         struct urb_priv *urb_priv;
2949         struct xhci_td  *td;
2950         struct xhci_ring *ep_ring;
2951         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2952
2953         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2954         if (!ep_ring) {
2955                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2956                                 stream_id);
2957                 return -EINVAL;
2958         }
2959
2960         ret = prepare_ring(xhci, ep_ring,
2961                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2962                            num_trbs, mem_flags);
2963         if (ret)
2964                 return ret;
2965
2966         urb_priv = urb->hcpriv;
2967         td = urb_priv->td[td_index];
2968
2969         INIT_LIST_HEAD(&td->td_list);
2970         INIT_LIST_HEAD(&td->cancelled_td_list);
2971
2972         if (td_index == 0) {
2973                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2974                 if (unlikely(ret))
2975                         return ret;
2976         }
2977
2978         td->urb = urb;
2979         /* Add this TD to the tail of the endpoint ring's TD list */
2980         list_add_tail(&td->td_list, &ep_ring->td_list);
2981         td->start_seg = ep_ring->enq_seg;
2982         td->first_trb = ep_ring->enqueue;
2983
2984         urb_priv->td[td_index] = td;
2985
2986         return 0;
2987 }
2988
2989 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2990 {
2991         int num_sgs, num_trbs, running_total, temp, i;
2992         struct scatterlist *sg;
2993
2994         sg = NULL;
2995         num_sgs = urb->num_mapped_sgs;
2996         temp = urb->transfer_buffer_length;
2997
2998         num_trbs = 0;
2999         for_each_sg(urb->sg, sg, num_sgs, i) {
3000                 unsigned int len = sg_dma_len(sg);
3001
3002                 /* Scatter gather list entries may cross 64KB boundaries */
3003                 running_total = TRB_MAX_BUFF_SIZE -
3004                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3005                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3006                 if (running_total != 0)
3007                         num_trbs++;
3008
3009                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3010                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3011                         num_trbs++;
3012                         running_total += TRB_MAX_BUFF_SIZE;
3013                 }
3014                 len = min_t(int, len, temp);
3015                 temp -= len;
3016                 if (temp == 0)
3017                         break;
3018         }
3019         return num_trbs;
3020 }
3021
3022 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3023 {
3024         if (num_trbs != 0)
3025                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3026                                 "TRBs, %d left\n", __func__,
3027                                 urb->ep->desc.bEndpointAddress, num_trbs);
3028         if (running_total != urb->transfer_buffer_length)
3029                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3030                                 "queued %#x (%d), asked for %#x (%d)\n",
3031                                 __func__,
3032                                 urb->ep->desc.bEndpointAddress,
3033                                 running_total, running_total,
3034                                 urb->transfer_buffer_length,
3035                                 urb->transfer_buffer_length);
3036 }
3037
3038 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3039                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3040                 struct xhci_generic_trb *start_trb)
3041 {
3042         /*
3043          * Pass all the TRBs to the hardware at once and make sure this write
3044          * isn't reordered.
3045          */
3046         wmb();
3047         if (start_cycle)
3048                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3049         else
3050                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3051         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3052 }
3053
3054 /*
3055  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3056  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3057  * (comprised of sg list entries) can take several service intervals to
3058  * transmit.
3059  */
3060 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3061                 struct urb *urb, int slot_id, unsigned int ep_index)
3062 {
3063         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3064                         xhci->devs[slot_id]->out_ctx, ep_index);
3065         int xhci_interval;
3066         int ep_interval;
3067
3068         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3069         ep_interval = urb->interval;
3070         /* Convert to microframes */
3071         if (urb->dev->speed == USB_SPEED_LOW ||
3072                         urb->dev->speed == USB_SPEED_FULL)
3073                 ep_interval *= 8;
3074         /* FIXME change this to a warning and a suggestion to use the new API
3075          * to set the polling interval (once the API is added).
3076          */
3077         if (xhci_interval != ep_interval) {
3078                 dev_dbg_ratelimited(&urb->dev->dev,
3079                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3080                                 ep_interval, ep_interval == 1 ? "" : "s",
3081                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3082                 urb->interval = xhci_interval;
3083                 /* Convert back to frames for LS/FS devices */
3084                 if (urb->dev->speed == USB_SPEED_LOW ||
3085                                 urb->dev->speed == USB_SPEED_FULL)
3086                         urb->interval /= 8;
3087         }
3088         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3089 }
3090
3091 /*
3092  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3093  * packets remaining in the TD (*not* including this TRB).
3094  *
3095  * Total TD packet count = total_packet_count =
3096  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3097  *
3098  * Packets transferred up to and including this TRB = packets_transferred =
3099  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3100  *
3101  * TD size = total_packet_count - packets_transferred
3102  *
3103  * For xHCI 0.96 and older, TD size field should be the remaining bytes
3104  * including this TRB, right shifted by 10
3105  *
3106  * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3107  * This is taken care of in the TRB_TD_SIZE() macro
3108  *
3109  * The last TRB in a TD must have the TD size set to zero.
3110  */
3111 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3112                               int trb_buff_len, unsigned int td_total_len,
3113                               struct urb *urb, unsigned int num_trbs_left)
3114 {
3115         u32 maxp, total_packet_count;
3116
3117         if (xhci->hci_version < 0x100)
3118                 return ((td_total_len - transferred) >> 10);
3119
3120         maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3121         total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3122
3123         /* One TRB with a zero-length data packet. */
3124         if (num_trbs_left == 0 || (transferred == 0 && trb_buff_len == 0) ||
3125             trb_buff_len == td_total_len)
3126                 return 0;
3127
3128         /* Queueing functions don't count the current TRB into transferred */
3129         return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3130 }
3131
3132
3133 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3134                 struct urb *urb, int slot_id, unsigned int ep_index)
3135 {
3136         struct xhci_ring *ep_ring;
3137         unsigned int num_trbs;
3138         struct urb_priv *urb_priv;
3139         struct xhci_td *td;
3140         struct scatterlist *sg;
3141         int num_sgs;
3142         int trb_buff_len, this_sg_len, running_total, ret;
3143         unsigned int total_packet_count;
3144         bool zero_length_needed;
3145         bool first_trb;
3146         int last_trb_num;
3147         u64 addr;
3148         bool more_trbs_coming;
3149
3150         struct xhci_generic_trb *start_trb;
3151         int start_cycle;
3152
3153         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3154         if (!ep_ring)
3155                 return -EINVAL;
3156
3157         num_trbs = count_sg_trbs_needed(xhci, urb);
3158         num_sgs = urb->num_mapped_sgs;
3159         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3160                         usb_endpoint_maxp(&urb->ep->desc));
3161
3162         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3163                         ep_index, urb->stream_id,
3164                         num_trbs, urb, 0, mem_flags);
3165         if (ret < 0)
3166                 return ret;
3167
3168         urb_priv = urb->hcpriv;
3169
3170         /* Deal with URB_ZERO_PACKET - need one more td/trb */
3171         zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3172                 urb_priv->length == 2;
3173         if (zero_length_needed) {
3174                 num_trbs++;
3175                 xhci_dbg(xhci, "Creating zero length td.\n");
3176                 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3177                                 ep_index, urb->stream_id,
3178                                 1, urb, 1, mem_flags);
3179                 if (ret < 0)
3180                         return ret;
3181         }
3182
3183         td = urb_priv->td[0];
3184
3185         /*
3186          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3187          * until we've finished creating all the other TRBs.  The ring's cycle
3188          * state may change as we enqueue the other TRBs, so save it too.
3189          */
3190         start_trb = &ep_ring->enqueue->generic;
3191         start_cycle = ep_ring->cycle_state;
3192
3193         running_total = 0;
3194         /*
3195          * How much data is in the first TRB?
3196          *
3197          * There are three forces at work for TRB buffer pointers and lengths:
3198          * 1. We don't want to walk off the end of this sg-list entry buffer.
3199          * 2. The transfer length that the driver requested may be smaller than
3200          *    the amount of memory allocated for this scatter-gather list.
3201          * 3. TRBs buffers can't cross 64KB boundaries.
3202          */
3203         sg = urb->sg;
3204         addr = (u64) sg_dma_address(sg);
3205         this_sg_len = sg_dma_len(sg);
3206         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3207         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3208         if (trb_buff_len > urb->transfer_buffer_length)
3209                 trb_buff_len = urb->transfer_buffer_length;
3210
3211         first_trb = true;
3212         last_trb_num = zero_length_needed ? 2 : 1;
3213         /* Queue the first TRB, even if it's zero-length */
3214         do {
3215                 u32 field = 0;
3216                 u32 length_field = 0;
3217                 u32 remainder = 0;
3218
3219                 /* Don't change the cycle bit of the first TRB until later */
3220                 if (first_trb) {
3221                         first_trb = false;
3222                         if (start_cycle == 0)
3223                                 field |= 0x1;
3224                 } else
3225                         field |= ep_ring->cycle_state;
3226
3227                 /* Chain all the TRBs together; clear the chain bit in the last
3228                  * TRB to indicate it's the last TRB in the chain.
3229                  */
3230                 if (num_trbs > last_trb_num) {
3231                         field |= TRB_CHAIN;
3232                 } else if (num_trbs == last_trb_num) {
3233                         td->last_trb = ep_ring->enqueue;
3234                         field |= TRB_IOC;
3235                 } else if (zero_length_needed && num_trbs == 1) {
3236                         trb_buff_len = 0;
3237                         urb_priv->td[1]->last_trb = ep_ring->enqueue;
3238                         field |= TRB_IOC;
3239                 }
3240
3241                 /* Only set interrupt on short packet for IN endpoints */
3242                 if (usb_urb_dir_in(urb))
3243                         field |= TRB_ISP;
3244
3245                 if (TRB_MAX_BUFF_SIZE -
3246                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3247                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3248                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3249                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3250                                         (unsigned int) addr + trb_buff_len);
3251                 }
3252
3253                 /* Set the TRB length, TD size, and interrupter fields. */
3254                 remainder = xhci_td_remainder(xhci, running_total, trb_buff_len,
3255                                            urb->transfer_buffer_length,
3256                                            urb, num_trbs - 1);
3257
3258                 length_field = TRB_LEN(trb_buff_len) |
3259                         TRB_TD_SIZE(remainder) |
3260                         TRB_INTR_TARGET(0);
3261
3262                 if (num_trbs > 1)
3263                         more_trbs_coming = true;
3264                 else
3265                         more_trbs_coming = false;
3266                 queue_trb(xhci, ep_ring, more_trbs_coming,
3267                                 lower_32_bits(addr),
3268                                 upper_32_bits(addr),
3269                                 length_field,
3270                                 field | TRB_TYPE(TRB_NORMAL));
3271                 --num_trbs;
3272                 running_total += trb_buff_len;
3273
3274                 /* Calculate length for next transfer --
3275                  * Are we done queueing all the TRBs for this sg entry?
3276                  */
3277                 this_sg_len -= trb_buff_len;
3278                 if (this_sg_len == 0) {
3279                         --num_sgs;
3280                         if (num_sgs == 0)
3281                                 break;
3282                         sg = sg_next(sg);
3283                         addr = (u64) sg_dma_address(sg);
3284                         this_sg_len = sg_dma_len(sg);
3285                 } else {
3286                         addr += trb_buff_len;
3287                 }
3288
3289                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3290                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3291                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3292                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3293                         trb_buff_len =
3294                                 urb->transfer_buffer_length - running_total;
3295         } while (num_trbs > 0);
3296
3297         check_trb_math(urb, num_trbs, running_total);
3298         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3299                         start_cycle, start_trb);
3300         return 0;
3301 }
3302
3303 /* This is very similar to what ehci-q.c qtd_fill() does */
3304 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3305                 struct urb *urb, int slot_id, unsigned int ep_index)
3306 {
3307         struct xhci_ring *ep_ring;
3308         struct urb_priv *urb_priv;
3309         struct xhci_td *td;
3310         int num_trbs;
3311         struct xhci_generic_trb *start_trb;
3312         bool first_trb;
3313         int last_trb_num;
3314         bool more_trbs_coming;
3315         bool zero_length_needed;
3316         int start_cycle;
3317         u32 field, length_field;
3318
3319         int running_total, trb_buff_len, ret;
3320         unsigned int total_packet_count;
3321         u64 addr;
3322
3323         if (urb->num_sgs)
3324                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3325
3326         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3327         if (!ep_ring)
3328                 return -EINVAL;
3329
3330         num_trbs = 0;
3331         /* How much data is (potentially) left before the 64KB boundary? */
3332         running_total = TRB_MAX_BUFF_SIZE -
3333                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3334         running_total &= TRB_MAX_BUFF_SIZE - 1;
3335
3336         /* If there's some data on this 64KB chunk, or we have to send a
3337          * zero-length transfer, we need at least one TRB
3338          */
3339         if (running_total != 0 || urb->transfer_buffer_length == 0)
3340                 num_trbs++;
3341         /* How many more 64KB chunks to transfer, how many more TRBs? */
3342         while (running_total < urb->transfer_buffer_length) {
3343                 num_trbs++;
3344                 running_total += TRB_MAX_BUFF_SIZE;
3345         }
3346
3347         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3348                         ep_index, urb->stream_id,
3349                         num_trbs, urb, 0, mem_flags);
3350         if (ret < 0)
3351                 return ret;
3352
3353         urb_priv = urb->hcpriv;
3354
3355         /* Deal with URB_ZERO_PACKET - need one more td/trb */
3356         zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3357                 urb_priv->length == 2;
3358         if (zero_length_needed) {
3359                 num_trbs++;
3360                 xhci_dbg(xhci, "Creating zero length td.\n");
3361                 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3362                                 ep_index, urb->stream_id,
3363                                 1, urb, 1, mem_flags);
3364                 if (ret < 0)
3365                         return ret;
3366         }
3367
3368         td = urb_priv->td[0];
3369
3370         /*
3371          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3372          * until we've finished creating all the other TRBs.  The ring's cycle
3373          * state may change as we enqueue the other TRBs, so save it too.
3374          */
3375         start_trb = &ep_ring->enqueue->generic;
3376         start_cycle = ep_ring->cycle_state;
3377
3378         running_total = 0;
3379         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3380                         usb_endpoint_maxp(&urb->ep->desc));
3381         /* How much data is in the first TRB? */
3382         addr = (u64) urb->transfer_dma;
3383         trb_buff_len = TRB_MAX_BUFF_SIZE -
3384                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3385         if (trb_buff_len > urb->transfer_buffer_length)
3386                 trb_buff_len = urb->transfer_buffer_length;
3387
3388         first_trb = true;
3389         last_trb_num = zero_length_needed ? 2 : 1;
3390         /* Queue the first TRB, even if it's zero-length */
3391         do {
3392                 u32 remainder = 0;
3393                 field = 0;
3394
3395                 /* Don't change the cycle bit of the first TRB until later */
3396                 if (first_trb) {
3397                         first_trb = false;
3398                         if (start_cycle == 0)
3399                                 field |= 0x1;
3400                 } else
3401                         field |= ep_ring->cycle_state;
3402
3403                 /* Chain all the TRBs together; clear the chain bit in the last
3404                  * TRB to indicate it's the last TRB in the chain.
3405                  */
3406                 if (num_trbs > last_trb_num) {
3407                         field |= TRB_CHAIN;
3408                 } else if (num_trbs == last_trb_num) {
3409                         td->last_trb = ep_ring->enqueue;
3410                         field |= TRB_IOC;
3411                 } else if (zero_length_needed && num_trbs == 1) {
3412                         trb_buff_len = 0;
3413                         urb_priv->td[1]->last_trb = ep_ring->enqueue;
3414                         field |= TRB_IOC;
3415                 }
3416
3417                 /* Only set interrupt on short packet for IN endpoints */
3418                 if (usb_urb_dir_in(urb))
3419                         field |= TRB_ISP;
3420
3421                 /* Set the TRB length, TD size, and interrupter fields. */
3422                 remainder = xhci_td_remainder(xhci, running_total, trb_buff_len,
3423                                            urb->transfer_buffer_length,
3424                                            urb, num_trbs - 1);
3425
3426                 length_field = TRB_LEN(trb_buff_len) |
3427                         TRB_TD_SIZE(remainder) |
3428                         TRB_INTR_TARGET(0);
3429
3430                 if (num_trbs > 1)
3431                         more_trbs_coming = true;
3432                 else
3433                         more_trbs_coming = false;
3434                 queue_trb(xhci, ep_ring, more_trbs_coming,
3435                                 lower_32_bits(addr),
3436                                 upper_32_bits(addr),
3437                                 length_field,
3438                                 field | TRB_TYPE(TRB_NORMAL));
3439                 --num_trbs;
3440                 running_total += trb_buff_len;
3441
3442                 /* Calculate length for next transfer */
3443                 addr += trb_buff_len;
3444                 trb_buff_len = urb->transfer_buffer_length - running_total;
3445                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3446                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3447         } while (num_trbs > 0);
3448
3449         check_trb_math(urb, num_trbs, running_total);
3450         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3451                         start_cycle, start_trb);
3452         return 0;
3453 }
3454
3455 /* Caller must have locked xhci->lock */
3456 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3457                 struct urb *urb, int slot_id, unsigned int ep_index)
3458 {
3459         struct xhci_ring *ep_ring;
3460         int num_trbs;
3461         int ret;
3462         struct usb_ctrlrequest *setup;
3463         struct xhci_generic_trb *start_trb;
3464         int start_cycle;
3465         u32 field, length_field, remainder;
3466         struct urb_priv *urb_priv;
3467         struct xhci_td *td;
3468
3469         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3470         if (!ep_ring)
3471                 return -EINVAL;
3472
3473         /*
3474          * Need to copy setup packet into setup TRB, so we can't use the setup
3475          * DMA address.
3476          */
3477         if (!urb->setup_packet)
3478                 return -EINVAL;
3479
3480         /* 1 TRB for setup, 1 for status */
3481         num_trbs = 2;
3482         /*
3483          * Don't need to check if we need additional event data and normal TRBs,
3484          * since data in control transfers will never get bigger than 16MB
3485          * XXX: can we get a buffer that crosses 64KB boundaries?
3486          */
3487         if (urb->transfer_buffer_length > 0)
3488                 num_trbs++;
3489         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3490                         ep_index, urb->stream_id,
3491                         num_trbs, urb, 0, mem_flags);
3492         if (ret < 0)
3493                 return ret;
3494
3495         urb_priv = urb->hcpriv;
3496         td = urb_priv->td[0];
3497
3498         /*
3499          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3500          * until we've finished creating all the other TRBs.  The ring's cycle
3501          * state may change as we enqueue the other TRBs, so save it too.
3502          */
3503         start_trb = &ep_ring->enqueue->generic;
3504         start_cycle = ep_ring->cycle_state;
3505
3506         /* Queue setup TRB - see section 6.4.1.2.1 */
3507         /* FIXME better way to translate setup_packet into two u32 fields? */
3508         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3509         field = 0;
3510         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3511         if (start_cycle == 0)
3512                 field |= 0x1;
3513
3514         /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3515         if (xhci->hci_version >= 0x100) {
3516                 if (urb->transfer_buffer_length > 0) {
3517                         if (setup->bRequestType & USB_DIR_IN)
3518                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3519                         else
3520                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3521                 }
3522         }
3523
3524         queue_trb(xhci, ep_ring, true,
3525                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3526                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3527                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3528                   /* Immediate data in pointer */
3529                   field);
3530
3531         /* If there's data, queue data TRBs */
3532         /* Only set interrupt on short packet for IN endpoints */
3533         if (usb_urb_dir_in(urb))
3534                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3535         else
3536                 field = TRB_TYPE(TRB_DATA);
3537
3538         remainder = xhci_td_remainder(xhci, 0,
3539                                    urb->transfer_buffer_length,
3540                                    urb->transfer_buffer_length,
3541                                    urb, 1);
3542
3543         length_field = TRB_LEN(urb->transfer_buffer_length) |
3544                 TRB_TD_SIZE(remainder) |
3545                 TRB_INTR_TARGET(0);
3546
3547         if (urb->transfer_buffer_length > 0) {
3548                 if (setup->bRequestType & USB_DIR_IN)
3549                         field |= TRB_DIR_IN;
3550                 queue_trb(xhci, ep_ring, true,
3551                                 lower_32_bits(urb->transfer_dma),
3552                                 upper_32_bits(urb->transfer_dma),
3553                                 length_field,
3554                                 field | ep_ring->cycle_state);
3555         }
3556
3557         /* Save the DMA address of the last TRB in the TD */
3558         td->last_trb = ep_ring->enqueue;
3559
3560         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3561         /* If the device sent data, the status stage is an OUT transfer */
3562         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3563                 field = 0;
3564         else
3565                 field = TRB_DIR_IN;
3566         queue_trb(xhci, ep_ring, false,
3567                         0,
3568                         0,
3569                         TRB_INTR_TARGET(0),
3570                         /* Event on completion */
3571                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3572
3573         giveback_first_trb(xhci, slot_id, ep_index, 0,
3574                         start_cycle, start_trb);
3575         return 0;
3576 }
3577
3578 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3579                 struct urb *urb, int i)
3580 {
3581         int num_trbs = 0;
3582         u64 addr, td_len;
3583
3584         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3585         td_len = urb->iso_frame_desc[i].length;
3586
3587         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3588                         TRB_MAX_BUFF_SIZE);
3589         if (num_trbs == 0)
3590                 num_trbs++;
3591
3592         return num_trbs;
3593 }
3594
3595 /*
3596  * The transfer burst count field of the isochronous TRB defines the number of
3597  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3598  * devices can burst up to bMaxBurst number of packets per service interval.
3599  * This field is zero based, meaning a value of zero in the field means one
3600  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3601  * zero.  Only xHCI 1.0 host controllers support this field.
3602  */
3603 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3604                 struct usb_device *udev,
3605                 struct urb *urb, unsigned int total_packet_count)
3606 {
3607         unsigned int max_burst;
3608
3609         if (xhci->hci_version < 0x100 || udev->speed < USB_SPEED_SUPER)
3610                 return 0;
3611
3612         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3613         return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3614 }
3615
3616 /*
3617  * Returns the number of packets in the last "burst" of packets.  This field is
3618  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3619  * the last burst packet count is equal to the total number of packets in the
3620  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3621  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3622  * contain 1 to (bMaxBurst + 1) packets.
3623  */
3624 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3625                 struct usb_device *udev,
3626                 struct urb *urb, unsigned int total_packet_count)
3627 {
3628         unsigned int max_burst;
3629         unsigned int residue;
3630
3631         if (xhci->hci_version < 0x100)
3632                 return 0;
3633
3634         switch (udev->speed) {
3635         case USB_SPEED_SUPER_PLUS:
3636         case USB_SPEED_SUPER:
3637                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3638                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3639                 residue = total_packet_count % (max_burst + 1);
3640                 /* If residue is zero, the last burst contains (max_burst + 1)
3641                  * number of packets, but the TLBPC field is zero-based.
3642                  */
3643                 if (residue == 0)
3644                         return max_burst;
3645                 return residue - 1;
3646         default:
3647                 if (total_packet_count == 0)
3648                         return 0;
3649                 return total_packet_count - 1;
3650         }
3651 }
3652
3653 /*
3654  * Calculates Frame ID field of the isochronous TRB identifies the
3655  * target frame that the Interval associated with this Isochronous
3656  * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3657  *
3658  * Returns actual frame id on success, negative value on error.
3659  */
3660 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3661                 struct urb *urb, int index)
3662 {
3663         int start_frame, ist, ret = 0;
3664         int start_frame_id, end_frame_id, current_frame_id;
3665
3666         if (urb->dev->speed == USB_SPEED_LOW ||
3667                         urb->dev->speed == USB_SPEED_FULL)
3668                 start_frame = urb->start_frame + index * urb->interval;
3669         else
3670                 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3671
3672         /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3673          *
3674          * If bit [3] of IST is cleared to '0', software can add a TRB no
3675          * later than IST[2:0] Microframes before that TRB is scheduled to
3676          * be executed.
3677          * If bit [3] of IST is set to '1', software can add a TRB no later
3678          * than IST[2:0] Frames before that TRB is scheduled to be executed.
3679          */
3680         ist = HCS_IST(xhci->hcs_params2) & 0x7;
3681         if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3682                 ist <<= 3;
3683
3684         /* Software shall not schedule an Isoch TD with a Frame ID value that
3685          * is less than the Start Frame ID or greater than the End Frame ID,
3686          * where:
3687          *
3688          * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3689          * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3690          *
3691          * Both the End Frame ID and Start Frame ID values are calculated
3692          * in microframes. When software determines the valid Frame ID value;
3693          * The End Frame ID value should be rounded down to the nearest Frame
3694          * boundary, and the Start Frame ID value should be rounded up to the
3695          * nearest Frame boundary.
3696          */
3697         current_frame_id = readl(&xhci->run_regs->microframe_index);
3698         start_frame_id = roundup(current_frame_id + ist + 1, 8);
3699         end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3700
3701         start_frame &= 0x7ff;
3702         start_frame_id = (start_frame_id >> 3) & 0x7ff;
3703         end_frame_id = (end_frame_id >> 3) & 0x7ff;
3704
3705         xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3706                  __func__, index, readl(&xhci->run_regs->microframe_index),
3707                  start_frame_id, end_frame_id, start_frame);
3708
3709         if (start_frame_id < end_frame_id) {
3710                 if (start_frame > end_frame_id ||
3711                                 start_frame < start_frame_id)
3712                         ret = -EINVAL;
3713         } else if (start_frame_id > end_frame_id) {
3714                 if ((start_frame > end_frame_id &&
3715                                 start_frame < start_frame_id))
3716                         ret = -EINVAL;
3717         } else {
3718                         ret = -EINVAL;
3719         }
3720
3721         if (index == 0) {
3722                 if (ret == -EINVAL || start_frame == start_frame_id) {
3723                         start_frame = start_frame_id + 1;
3724                         if (urb->dev->speed == USB_SPEED_LOW ||
3725                                         urb->dev->speed == USB_SPEED_FULL)
3726                                 urb->start_frame = start_frame;
3727                         else
3728                                 urb->start_frame = start_frame << 3;
3729                         ret = 0;
3730                 }
3731         }
3732
3733         if (ret) {
3734                 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3735                                 start_frame, current_frame_id, index,
3736                                 start_frame_id, end_frame_id);
3737                 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3738                 return ret;
3739         }
3740
3741         return start_frame;
3742 }
3743
3744 /* This is for isoc transfer */
3745 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3746                 struct urb *urb, int slot_id, unsigned int ep_index)
3747 {
3748         struct xhci_ring *ep_ring;
3749         struct urb_priv *urb_priv;
3750         struct xhci_td *td;
3751         int num_tds, trbs_per_td;
3752         struct xhci_generic_trb *start_trb;
3753         bool first_trb;
3754         int start_cycle;
3755         u32 field, length_field;
3756         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3757         u64 start_addr, addr;
3758         int i, j;
3759         bool more_trbs_coming;
3760         struct xhci_virt_ep *xep;
3761
3762         xep = &xhci->devs[slot_id]->eps[ep_index];
3763         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3764
3765         num_tds = urb->number_of_packets;
3766         if (num_tds < 1) {
3767                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3768                 return -EINVAL;
3769         }
3770
3771         start_addr = (u64) urb->transfer_dma;
3772         start_trb = &ep_ring->enqueue->generic;
3773         start_cycle = ep_ring->cycle_state;
3774
3775         urb_priv = urb->hcpriv;
3776         /* Queue the first TRB, even if it's zero-length */
3777         for (i = 0; i < num_tds; i++) {
3778                 unsigned int total_packet_count;
3779                 unsigned int burst_count;
3780                 unsigned int residue;
3781
3782                 first_trb = true;
3783                 running_total = 0;
3784                 addr = start_addr + urb->iso_frame_desc[i].offset;
3785                 td_len = urb->iso_frame_desc[i].length;
3786                 td_remain_len = td_len;
3787                 total_packet_count = DIV_ROUND_UP(td_len,
3788                                 GET_MAX_PACKET(
3789                                         usb_endpoint_maxp(&urb->ep->desc)));
3790                 /* A zero-length transfer still involves at least one packet. */
3791                 if (total_packet_count == 0)
3792                         total_packet_count++;
3793                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3794                                 total_packet_count);
3795                 residue = xhci_get_last_burst_packet_count(xhci,
3796                                 urb->dev, urb, total_packet_count);
3797
3798                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3799
3800                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3801                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3802                 if (ret < 0) {
3803                         if (i == 0)
3804                                 return ret;
3805                         goto cleanup;
3806                 }
3807
3808                 td = urb_priv->td[i];
3809                 for (j = 0; j < trbs_per_td; j++) {
3810                         int frame_id = 0;
3811                         u32 remainder = 0;
3812                         field = 0;
3813
3814                         if (first_trb) {
3815                                 field = TRB_TBC(burst_count) |
3816                                         TRB_TLBPC(residue);
3817                                 /* Queue the isoc TRB */
3818                                 field |= TRB_TYPE(TRB_ISOC);
3819
3820                                 /* Calculate Frame ID and SIA fields */
3821                                 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3822                                                 HCC_CFC(xhci->hcc_params)) {
3823                                         frame_id = xhci_get_isoc_frame_id(xhci,
3824                                                                           urb,
3825                                                                           i);
3826                                         if (frame_id >= 0)
3827                                                 field |= TRB_FRAME_ID(frame_id);
3828                                         else
3829                                                 field |= TRB_SIA;
3830                                 } else
3831                                         field |= TRB_SIA;
3832
3833                                 if (i == 0) {
3834                                         if (start_cycle == 0)
3835                                                 field |= 0x1;
3836                                 } else
3837                                         field |= ep_ring->cycle_state;
3838                                 first_trb = false;
3839                         } else {
3840                                 /* Queue other normal TRBs */
3841                                 field |= TRB_TYPE(TRB_NORMAL);
3842                                 field |= ep_ring->cycle_state;
3843                         }
3844
3845                         /* Only set interrupt on short packet for IN EPs */
3846                         if (usb_urb_dir_in(urb))
3847                                 field |= TRB_ISP;
3848
3849                         /* Chain all the TRBs together; clear the chain bit in
3850                          * the last TRB to indicate it's the last TRB in the
3851                          * chain.
3852                          */
3853                         if (j < trbs_per_td - 1) {
3854                                 field |= TRB_CHAIN;
3855                                 more_trbs_coming = true;
3856                         } else {
3857                                 td->last_trb = ep_ring->enqueue;
3858                                 field |= TRB_IOC;
3859                                 if (xhci->hci_version == 0x100 &&
3860                                                 !(xhci->quirks &
3861                                                         XHCI_AVOID_BEI)) {
3862                                         /* Set BEI bit except for the last td */
3863                                         if (i < num_tds - 1)
3864                                                 field |= TRB_BEI;
3865                                 }
3866                                 more_trbs_coming = false;
3867                         }
3868
3869                         /* Calculate TRB length */
3870                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3871                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3872                         if (trb_buff_len > td_remain_len)
3873                                 trb_buff_len = td_remain_len;
3874
3875                         /* Set the TRB length, TD size, & interrupter fields. */
3876                         remainder = xhci_td_remainder(xhci, running_total,
3877                                                    trb_buff_len, td_len,
3878                                                    urb, trbs_per_td - j - 1);
3879
3880                         length_field = TRB_LEN(trb_buff_len) |
3881                                 TRB_TD_SIZE(remainder) |
3882                                 TRB_INTR_TARGET(0);
3883
3884                         queue_trb(xhci, ep_ring, more_trbs_coming,
3885                                 lower_32_bits(addr),
3886                                 upper_32_bits(addr),
3887                                 length_field,
3888                                 field);
3889                         running_total += trb_buff_len;
3890
3891                         addr += trb_buff_len;
3892                         td_remain_len -= trb_buff_len;
3893                 }
3894
3895                 /* Check TD length */
3896                 if (running_total != td_len) {
3897                         xhci_err(xhci, "ISOC TD length unmatch\n");
3898                         ret = -EINVAL;
3899                         goto cleanup;
3900                 }
3901         }
3902
3903         /* store the next frame id */
3904         if (HCC_CFC(xhci->hcc_params))
3905                 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3906
3907         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3908                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3909                         usb_amd_quirk_pll_disable();
3910         }
3911         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3912
3913         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3914                         start_cycle, start_trb);
3915         return 0;
3916 cleanup:
3917         /* Clean up a partially enqueued isoc transfer. */
3918
3919         for (i--; i >= 0; i--)
3920                 list_del_init(&urb_priv->td[i]->td_list);
3921
3922         /* Use the first TD as a temporary variable to turn the TDs we've queued
3923          * into No-ops with a software-owned cycle bit. That way the hardware
3924          * won't accidentally start executing bogus TDs when we partially
3925          * overwrite them.  td->first_trb and td->start_seg are already set.
3926          */
3927         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3928         /* Every TRB except the first & last will have its cycle bit flipped. */
3929         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3930
3931         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3932         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3933         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3934         ep_ring->cycle_state = start_cycle;
3935         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3936         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3937         return ret;
3938 }
3939
3940 /*
3941  * Check transfer ring to guarantee there is enough room for the urb.
3942  * Update ISO URB start_frame and interval.
3943  * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3944  * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3945  * Contiguous Frame ID is not supported by HC.
3946  */
3947 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3948                 struct urb *urb, int slot_id, unsigned int ep_index)
3949 {
3950         struct xhci_virt_device *xdev;
3951         struct xhci_ring *ep_ring;
3952         struct xhci_ep_ctx *ep_ctx;
3953         int start_frame;
3954         int xhci_interval;
3955         int ep_interval;
3956         int num_tds, num_trbs, i;
3957         int ret;
3958         struct xhci_virt_ep *xep;
3959         int ist;
3960
3961         xdev = xhci->devs[slot_id];
3962         xep = &xhci->devs[slot_id]->eps[ep_index];
3963         ep_ring = xdev->eps[ep_index].ring;
3964         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3965
3966         num_trbs = 0;
3967         num_tds = urb->number_of_packets;
3968         for (i = 0; i < num_tds; i++)
3969                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3970
3971         /* Check the ring to guarantee there is enough room for the whole urb.
3972          * Do not insert any td of the urb to the ring if the check failed.
3973          */
3974         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3975                            num_trbs, mem_flags);
3976         if (ret)
3977                 return ret;
3978
3979         /*
3980          * Check interval value. This should be done before we start to
3981          * calculate the start frame value.
3982          */
3983         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3984         ep_interval = urb->interval;
3985         /* Convert to microframes */
3986         if (urb->dev->speed == USB_SPEED_LOW ||
3987                         urb->dev->speed == USB_SPEED_FULL)
3988                 ep_interval *= 8;
3989         /* FIXME change this to a warning and a suggestion to use the new API
3990          * to set the polling interval (once the API is added).
3991          */
3992         if (xhci_interval != ep_interval) {
3993                 dev_dbg_ratelimited(&urb->dev->dev,
3994                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3995                                 ep_interval, ep_interval == 1 ? "" : "s",
3996                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3997                 urb->interval = xhci_interval;
3998                 /* Convert back to frames for LS/FS devices */
3999                 if (urb->dev->speed == USB_SPEED_LOW ||
4000                                 urb->dev->speed == USB_SPEED_FULL)
4001                         urb->interval /= 8;
4002         }
4003
4004         /* Calculate the start frame and put it in urb->start_frame. */
4005         if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4006                 if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
4007                                 EP_STATE_RUNNING) {
4008                         urb->start_frame = xep->next_frame_id;
4009                         goto skip_start_over;
4010                 }
4011         }
4012
4013         start_frame = readl(&xhci->run_regs->microframe_index);
4014         start_frame &= 0x3fff;
4015         /*
4016          * Round up to the next frame and consider the time before trb really
4017          * gets scheduled by hardare.
4018          */
4019         ist = HCS_IST(xhci->hcs_params2) & 0x7;
4020         if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4021                 ist <<= 3;
4022         start_frame += ist + XHCI_CFC_DELAY;
4023         start_frame = roundup(start_frame, 8);
4024
4025         /*
4026          * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4027          * is greate than 8 microframes.
4028          */
4029         if (urb->dev->speed == USB_SPEED_LOW ||
4030                         urb->dev->speed == USB_SPEED_FULL) {
4031                 start_frame = roundup(start_frame, urb->interval << 3);
4032                 urb->start_frame = start_frame >> 3;
4033         } else {
4034                 start_frame = roundup(start_frame, urb->interval);
4035                 urb->start_frame = start_frame;
4036         }
4037
4038 skip_start_over:
4039         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4040
4041         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4042 }
4043
4044 /****           Command Ring Operations         ****/
4045
4046 /* Generic function for queueing a command TRB on the command ring.
4047  * Check to make sure there's room on the command ring for one command TRB.
4048  * Also check that there's room reserved for commands that must not fail.
4049  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4050  * then only check for the number of reserved spots.
4051  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4052  * because the command event handler may want to resubmit a failed command.
4053  */
4054 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4055                          u32 field1, u32 field2,
4056                          u32 field3, u32 field4, bool command_must_succeed)
4057 {
4058         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4059         int ret;
4060
4061         if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4062                 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4063                 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4064                 return -ESHUTDOWN;
4065         }
4066
4067         if (!command_must_succeed)
4068                 reserved_trbs++;
4069
4070         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4071                         reserved_trbs, GFP_ATOMIC);
4072         if (ret < 0) {
4073                 xhci_err(xhci, "ERR: No room for command on command ring\n");
4074                 if (command_must_succeed)
4075                         xhci_err(xhci, "ERR: Reserved TRB counting for "
4076                                         "unfailable commands failed.\n");
4077                 return ret;
4078         }
4079
4080         cmd->command_trb = xhci->cmd_ring->enqueue;
4081         list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4082
4083         /* if there are no other commands queued we start the timeout timer */
4084         if (xhci->cmd_list.next == &cmd->cmd_list &&
4085             !delayed_work_pending(&xhci->cmd_timer)) {
4086                 xhci->current_cmd = cmd;
4087                 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4088         }
4089
4090         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4091                         field4 | xhci->cmd_ring->cycle_state);
4092         return 0;
4093 }
4094
4095 /* Queue a slot enable or disable request on the command ring */
4096 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4097                 u32 trb_type, u32 slot_id)
4098 {
4099         return queue_command(xhci, cmd, 0, 0, 0,
4100                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4101 }
4102
4103 /* Queue an address device command TRB */
4104 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4105                 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4106 {
4107         return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4108                         upper_32_bits(in_ctx_ptr), 0,
4109                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4110                         | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4111 }
4112
4113 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4114                 u32 field1, u32 field2, u32 field3, u32 field4)
4115 {
4116         return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4117 }
4118
4119 /* Queue a reset device command TRB */
4120 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4121                 u32 slot_id)
4122 {
4123         return queue_command(xhci, cmd, 0, 0, 0,
4124                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4125                         false);
4126 }
4127
4128 /* Queue a configure endpoint command TRB */
4129 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4130                 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4131                 u32 slot_id, bool command_must_succeed)
4132 {
4133         return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4134                         upper_32_bits(in_ctx_ptr), 0,
4135                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4136                         command_must_succeed);
4137 }
4138
4139 /* Queue an evaluate context command TRB */
4140 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4141                 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4142 {
4143         return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4144                         upper_32_bits(in_ctx_ptr), 0,
4145                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4146                         command_must_succeed);
4147 }
4148
4149 /*
4150  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4151  * activity on an endpoint that is about to be suspended.
4152  */
4153 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4154                              int slot_id, unsigned int ep_index, int suspend)
4155 {
4156         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4157         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4158         u32 type = TRB_TYPE(TRB_STOP_RING);
4159         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4160
4161         return queue_command(xhci, cmd, 0, 0, 0,
4162                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
4163 }
4164
4165 /* Set Transfer Ring Dequeue Pointer command */
4166 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4167                 unsigned int slot_id, unsigned int ep_index,
4168                 unsigned int stream_id,
4169                 struct xhci_dequeue_state *deq_state)
4170 {
4171         dma_addr_t addr;
4172         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4173         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4174         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4175         u32 trb_sct = 0;
4176         u32 type = TRB_TYPE(TRB_SET_DEQ);
4177         struct xhci_virt_ep *ep;
4178         struct xhci_command *cmd;
4179         int ret;
4180
4181         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4182                 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4183                 deq_state->new_deq_seg,
4184                 (unsigned long long)deq_state->new_deq_seg->dma,
4185                 deq_state->new_deq_ptr,
4186                 (unsigned long long)xhci_trb_virt_to_dma(
4187                         deq_state->new_deq_seg, deq_state->new_deq_ptr),
4188                 deq_state->new_cycle_state);
4189
4190         addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4191                                     deq_state->new_deq_ptr);
4192         if (addr == 0) {
4193                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4194                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4195                           deq_state->new_deq_seg, deq_state->new_deq_ptr);
4196                 return;
4197         }
4198         ep = &xhci->devs[slot_id]->eps[ep_index];
4199         if ((ep->ep_state & SET_DEQ_PENDING)) {
4200                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4201                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4202                 return;
4203         }
4204
4205         /* This function gets called from contexts where it cannot sleep */
4206         cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
4207         if (!cmd) {
4208                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
4209                 return;
4210         }
4211
4212         ep->queued_deq_seg = deq_state->new_deq_seg;
4213         ep->queued_deq_ptr = deq_state->new_deq_ptr;
4214         if (stream_id)
4215                 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4216         ret = queue_command(xhci, cmd,
4217                 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4218                 upper_32_bits(addr), trb_stream_id,
4219                 trb_slot_id | trb_ep_index | type, false);
4220         if (ret < 0) {
4221                 xhci_free_command(xhci, cmd);
4222                 return;
4223         }
4224
4225         /* Stop the TD queueing code from ringing the doorbell until
4226          * this command completes.  The HC won't set the dequeue pointer
4227          * if the ring is running, and ringing the doorbell starts the
4228          * ring running.
4229          */
4230         ep->ep_state |= SET_DEQ_PENDING;
4231 }
4232
4233 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4234                         int slot_id, unsigned int ep_index)
4235 {
4236         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4237         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4238         u32 type = TRB_TYPE(TRB_RESET_EP);
4239
4240         return queue_command(xhci, cmd, 0, 0, 0,
4241                         trb_slot_id | trb_ep_index | type, false);
4242 }