drivers/usb/host/xhci-tegra.c

   1 /*
   2  * NVIDIA Tegra xHCI host controller driver
   3  *
   4  * Copyright (C) 2014 NVIDIA Corporation
   5  * Copyright (C) 2014 Google, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/firmware.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of_device.h>
  20 #include <linux/phy/phy.h>
  21 #include <linux/phy/tegra/xusb.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/reset.h>
  26 #include <linux/slab.h>
  27
  28 #include "xhci.h"
  29
  30 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
  31 #define TEGRA_XHCI_SS_LOW_SPEED   12000000
  32
  33 /* FPCI CFG registers */
  34 #define XUSB_CFG_1                              0x004
  35 #define  XUSB_IO_SPACE_EN                       BIT(0)
  36 #define  XUSB_MEM_SPACE_EN                      BIT(1)
  37 #define  XUSB_BUS_MASTER_EN                     BIT(2)
  38 #define XUSB_CFG_4                              0x010
  39 #define  XUSB_BASE_ADDR_SHIFT                   15
  40 #define  XUSB_BASE_ADDR_MASK                    0x1ffff
  41 #define XUSB_CFG_ARU_C11_CSBRANGE               0x41c
  42 #define XUSB_CFG_CSB_BASE_ADDR                  0x800
  43
  44 /* FPCI mailbox registers */
  45 #define XUSB_CFG_ARU_MBOX_CMD                   0x0e4
  46 #define  MBOX_DEST_FALC                         BIT(27)
  47 #define  MBOX_DEST_PME                          BIT(28)
  48 #define  MBOX_DEST_SMI                          BIT(29)
  49 #define  MBOX_DEST_XHCI                         BIT(30)
  50 #define  MBOX_INT_EN                            BIT(31)
  51 #define XUSB_CFG_ARU_MBOX_DATA_IN               0x0e8
  52 #define  CMD_DATA_SHIFT                         0
  53 #define  CMD_DATA_MASK                          0xffffff
  54 #define  CMD_TYPE_SHIFT                         24
  55 #define  CMD_TYPE_MASK                          0xff
  56 #define XUSB_CFG_ARU_MBOX_DATA_OUT              0x0ec
  57 #define XUSB_CFG_ARU_MBOX_OWNER                 0x0f0
  58 #define  MBOX_OWNER_NONE                        0
  59 #define  MBOX_OWNER_FW                          1
  60 #define  MBOX_OWNER_SW                          2
  61 #define XUSB_CFG_ARU_SMI_INTR                   0x428
  62 #define  MBOX_SMI_INTR_FW_HANG                  BIT(1)
  63 #define  MBOX_SMI_INTR_EN                       BIT(3)
  64
  65 /* IPFS registers */
  66 #define IPFS_XUSB_HOST_CONFIGURATION_0          0x180
  67 #define  IPFS_EN_FPCI                           BIT(0)
  68 #define IPFS_XUSB_HOST_INTR_MASK_0              0x188
  69 #define  IPFS_IP_INT_MASK                       BIT(16)
  70 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0     0x1bc
  71
  72 #define CSB_PAGE_SELECT_MASK                    0x7fffff
  73 #define CSB_PAGE_SELECT_SHIFT                   9
  74 #define CSB_PAGE_OFFSET_MASK                    0x1ff
  75 #define CSB_PAGE_SELECT(addr)   ((addr) >> (CSB_PAGE_SELECT_SHIFT) &    \
  76                                  CSB_PAGE_SELECT_MASK)
  77 #define CSB_PAGE_OFFSET(addr)   ((addr) & CSB_PAGE_OFFSET_MASK)
  78
  79 /* Falcon CSB registers */
  80 #define XUSB_FALC_CPUCTL                        0x100
  81 #define  CPUCTL_STARTCPU                        BIT(1)
  82 #define  CPUCTL_STATE_HALTED                    BIT(4)
  83 #define  CPUCTL_STATE_STOPPED                   BIT(5)
  84 #define XUSB_FALC_BOOTVEC                       0x104
  85 #define XUSB_FALC_DMACTL                        0x10c
  86 #define XUSB_FALC_IMFILLRNG1                    0x154
  87 #define  IMFILLRNG1_TAG_MASK                    0xffff
  88 #define  IMFILLRNG1_TAG_LO_SHIFT                0
  89 #define  IMFILLRNG1_TAG_HI_SHIFT                16
  90 #define XUSB_FALC_IMFILLCTL                     0x158
  91
  92 /* MP CSB registers */
  93 #define XUSB_CSB_MP_ILOAD_ATTR                  0x101a00
  94 #define XUSB_CSB_MP_ILOAD_BASE_LO               0x101a04
  95 #define XUSB_CSB_MP_ILOAD_BASE_HI               0x101a08
  96 #define XUSB_CSB_MP_L2IMEMOP_SIZE               0x101a10
  97 #define  L2IMEMOP_SIZE_SRC_OFFSET_SHIFT         8
  98 #define  L2IMEMOP_SIZE_SRC_OFFSET_MASK          0x3ff
  99 #define  L2IMEMOP_SIZE_SRC_COUNT_SHIFT          24
 100 #define  L2IMEMOP_SIZE_SRC_COUNT_MASK           0xff
 101 #define XUSB_CSB_MP_L2IMEMOP_TRIG               0x101a14
 102 #define  L2IMEMOP_ACTION_SHIFT                  24
 103 #define  L2IMEMOP_INVALIDATE_ALL                (0x40 << L2IMEMOP_ACTION_SHIFT)
 104 #define  L2IMEMOP_LOAD_LOCKED_RESULT            (0x11 << L2IMEMOP_ACTION_SHIFT)
 105 #define XUSB_CSB_MP_APMAP                       0x10181c
 106 #define  APMAP_BOOTPATH                         BIT(31)
 107
 108 #define IMEM_BLOCK_SIZE                         256
 109
 110 struct tegra_xusb_fw_header {
 111         u32 boot_loadaddr_in_imem;
 112         u32 boot_codedfi_offset;
 113         u32 boot_codetag;
 114         u32 boot_codesize;
 115         u32 phys_memaddr;
 116         u16 reqphys_memsize;
 117         u16 alloc_phys_memsize;
 118         u32 rodata_img_offset;
 119         u32 rodata_section_start;
 120         u32 rodata_section_end;
 121         u32 main_fnaddr;
 122         u32 fwimg_cksum;
 123         u32 fwimg_created_time;
 124         u32 imem_resident_start;
 125         u32 imem_resident_end;
 126         u32 idirect_start;
 127         u32 idirect_end;
 128         u32 l2_imem_start;
 129         u32 l2_imem_end;
 130         u32 version_id;
 131         u8 init_ddirect;
 132         u8 reserved[3];
 133         u32 phys_addr_log_buffer;
 134         u32 total_log_entries;
 135         u32 dequeue_ptr;
 136         u32 dummy_var[2];
 137         u32 fwimg_len;
 138         u8 magic[8];
 139         u32 ss_low_power_entry_timeout;
 140         u8 num_hsic_port;
 141         u8 padding[139]; /* Pad to 256 bytes */
 142 };
 143
 144 struct tegra_xusb_phy_type {
 145         const char *name;
 146         unsigned int num;
 147 };
 148
 149 struct tegra_xusb_soc {
 150         const char *firmware;
 151         const char * const *supply_names;
 152         unsigned int num_supplies;
 153         const struct tegra_xusb_phy_type *phy_types;
 154         unsigned int num_types;
 155
 156         struct {
 157                 struct {
 158                         unsigned int offset;
 159                         unsigned int count;
 160                 } usb2, ulpi, hsic, usb3;
 161         } ports;
 162
 163         bool scale_ss_clock;
 164 };
 165
 166 struct tegra_xusb {
 167         struct device *dev;
 168         void __iomem *regs;
 169         struct usb_hcd *hcd;
 170
 171         struct mutex lock;
 172
 173         int xhci_irq;
 174         int mbox_irq;
 175
 176         void __iomem *ipfs_base;
 177         void __iomem *fpci_base;
 178
 179         const struct tegra_xusb_soc *soc;
 180
 181         struct regulator_bulk_data *supplies;
 182
 183         struct tegra_xusb_padctl *padctl;
 184
 185         struct clk *host_clk;
 186         struct clk *falcon_clk;
 187         struct clk *ss_clk;
 188         struct clk *ss_src_clk;
 189         struct clk *hs_src_clk;
 190         struct clk *fs_src_clk;
 191         struct clk *pll_u_480m;
 192         struct clk *clk_m;
 193         struct clk *pll_e;
 194
 195         struct reset_control *host_rst;
 196         struct reset_control *ss_rst;
 197
 198         struct phy **phys;
 199         unsigned int num_phys;
 200
 201         /* Firmware loading related */
 202         struct {
 203                 size_t size;
 204                 void *virt;
 205                 dma_addr_t phys;
 206         } fw;
 207 };
 208
 209 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
 210
 211 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
 212 {
 213         return readl(tegra->fpci_base + offset);
 214 }
 215
 216 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
 217                                unsigned int offset)
 218 {
 219         writel(value, tegra->fpci_base + offset);
 220 }
 221
 222 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
 223 {
 224         return readl(tegra->ipfs_base + offset);
 225 }
 226
 227 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
 228                                unsigned int offset)
 229 {
 230         writel(value, tegra->ipfs_base + offset);
 231 }
 232
 233 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
 234 {
 235         u32 page = CSB_PAGE_SELECT(offset);
 236         u32 ofs = CSB_PAGE_OFFSET(offset);
 237
 238         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 239
 240         return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
 241 }
 242
 243 static void csb_writel(struct tegra_xusb *tegra, u32 value,
 244                        unsigned int offset)
 245 {
 246         u32 page = CSB_PAGE_SELECT(offset);
 247         u32 ofs = CSB_PAGE_OFFSET(offset);
 248
 249         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 250         fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
 251 }
 252
 253 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
 254                                  unsigned long rate)
 255 {
 256         unsigned long new_parent_rate, old_parent_rate;
 257         struct clk *clk = tegra->ss_src_clk;
 258         unsigned int div;
 259         int err;
 260
 261         if (clk_get_rate(clk) == rate)
 262                 return 0;
 263
 264         switch (rate) {
 265         case TEGRA_XHCI_SS_HIGH_SPEED:
 266                 /*
 267                  * Reparent to PLLU_480M. Set divider first to avoid
 268                  * overclocking.
 269                  */
 270                 old_parent_rate = clk_get_rate(clk_get_parent(clk));
 271                 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
 272                 div = new_parent_rate / rate;
 273
 274                 err = clk_set_rate(clk, old_parent_rate / div);
 275                 if (err)
 276                         return err;
 277
 278                 err = clk_set_parent(clk, tegra->pll_u_480m);
 279                 if (err)
 280                         return err;
 281
 282                 /*
 283                  * The rate should already be correct, but set it again just
 284                  * to be sure.
 285                  */
 286                 err = clk_set_rate(clk, rate);
 287                 if (err)
 288                         return err;
 289
 290                 break;
 291
 292         case TEGRA_XHCI_SS_LOW_SPEED:
 293                 /* Reparent to CLK_M */
 294                 err = clk_set_parent(clk, tegra->clk_m);
 295                 if (err)
 296                         return err;
 297
 298                 err = clk_set_rate(clk, rate);
 299                 if (err)
 300                         return err;
 301
 302                 break;
 303
 304         default:
 305                 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
 306                 return -EINVAL;
 307         }
 308
 309         if (clk_get_rate(clk) != rate) {
 310                 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
 311                 return -EINVAL;
 312         }
 313
 314         return 0;
 315 }
 316
 317 static unsigned long extract_field(u32 value, unsigned int start,
 318                                    unsigned int count)
 319 {
 320         return (value >> start) & ((1 << count) - 1);
 321 }
 322
 323 /* Command requests from the firmware */
 324 enum tegra_xusb_mbox_cmd {
 325         MBOX_CMD_MSG_ENABLED = 1,
 326         MBOX_CMD_INC_FALC_CLOCK,
 327         MBOX_CMD_DEC_FALC_CLOCK,
 328         MBOX_CMD_INC_SSPI_CLOCK,
 329         MBOX_CMD_DEC_SSPI_CLOCK,
 330         MBOX_CMD_SET_BW, /* no ACK/NAK required */
 331         MBOX_CMD_SET_SS_PWR_GATING,
 332         MBOX_CMD_SET_SS_PWR_UNGATING,
 333         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 334         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 335         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
 336         MBOX_CMD_START_HSIC_IDLE,
 337         MBOX_CMD_STOP_HSIC_IDLE,
 338         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 339         MBOX_CMD_HSIC_PRETEND_CONNECT,
 340         MBOX_CMD_RESET_SSPI,
 341         MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
 342         MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
 343
 344         MBOX_CMD_MAX,
 345
 346         /* Response message to above commands */
 347         MBOX_CMD_ACK = 128,
 348         MBOX_CMD_NAK
 349 };
 350
 351 static const char * const mbox_cmd_name[] = {
 352         [  1] = "MSG_ENABLE",
 353         [  2] = "INC_FALCON_CLOCK",
 354         [  3] = "DEC_FALCON_CLOCK",
 355         [  4] = "INC_SSPI_CLOCK",
 356         [  5] = "DEC_SSPI_CLOCK",
 357         [  6] = "SET_BW",
 358         [  7] = "SET_SS_PWR_GATING",
 359         [  8] = "SET_SS_PWR_UNGATING",
 360         [  9] = "SAVE_DFE_CTLE_CTX",
 361         [ 10] = "AIRPLANE_MODE_ENABLED",
 362         [ 11] = "AIRPLANE_MODE_DISABLED",
 363         [ 12] = "START_HSIC_IDLE",
 364         [ 13] = "STOP_HSIC_IDLE",
 365         [ 14] = "DBC_WAKE_STACK",
 366         [ 15] = "HSIC_PRETEND_CONNECT",
 367         [ 16] = "RESET_SSPI",
 368         [ 17] = "DISABLE_SS_LFPS_DETECTION",
 369         [ 18] = "ENABLE_SS_LFPS_DETECTION",
 370         [128] = "ACK",
 371         [129] = "NAK",
 372 };
 373
 374 struct tegra_xusb_mbox_msg {
 375         u32 cmd;
 376         u32 data;
 377 };
 378
 379 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
 380 {
 381         return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
 382                (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
 383 }
 384 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
 385                                           u32 value)
 386 {
 387         msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
 388         msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
 389 }
 390
 391 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
 392 {
 393         switch (cmd) {
 394         case MBOX_CMD_SET_BW:
 395         case MBOX_CMD_ACK:
 396         case MBOX_CMD_NAK:
 397                 return false;
 398
 399         default:
 400                 return true;
 401         }
 402 }
 403
 404 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
 405                                 const struct tegra_xusb_mbox_msg *msg)
 406 {
 407         bool wait_for_idle = false;
 408         u32 value;
 409
 410         /*
 411          * Acquire the mailbox. The firmware still owns the mailbox for
 412          * ACK/NAK messages.
 413          */
 414         if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
 415                 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
 416                 if (value != MBOX_OWNER_NONE) {
 417                         dev_err(tegra->dev, "mailbox is busy\n");
 418                         return -EBUSY;
 419                 }
 420
 421                 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER);
 422
 423                 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
 424                 if (value != MBOX_OWNER_SW) {
 425                         dev_err(tegra->dev, "failed to acquire mailbox\n");
 426                         return -EBUSY;
 427                 }
 428
 429                 wait_for_idle = true;
 430         }
 431
 432         value = tegra_xusb_mbox_pack(msg);
 433         fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN);
 434
 435         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
 436         value |= MBOX_INT_EN | MBOX_DEST_FALC;
 437         fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
 438
 439         if (wait_for_idle) {
 440                 unsigned long timeout = jiffies + msecs_to_jiffies(250);
 441
 442                 while (time_before(jiffies, timeout)) {
 443                         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
 444                         if (value == MBOX_OWNER_NONE)
 445                                 break;
 446
 447                         usleep_range(10, 20);
 448                 }
 449
 450                 if (time_after(jiffies, timeout))
 451                         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
 452
 453                 if (value != MBOX_OWNER_NONE)
 454                         return -ETIMEDOUT;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
 461 {
 462         struct tegra_xusb *tegra = data;
 463         u32 value;
 464
 465         /* clear mailbox interrupts */
 466         value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
 467         fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
 468
 469         if (value & MBOX_SMI_INTR_FW_HANG)
 470                 dev_err(tegra->dev, "controller firmware hang\n");
 471
 472         return IRQ_WAKE_THREAD;
 473 }
 474
 475 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 476                                    const struct tegra_xusb_mbox_msg *msg)
 477 {
 478         struct tegra_xusb_padctl *padctl = tegra->padctl;
 479         const struct tegra_xusb_soc *soc = tegra->soc;
 480         struct device *dev = tegra->dev;
 481         struct tegra_xusb_mbox_msg rsp;
 482         unsigned long mask;
 483         unsigned int port;
 484         bool idle, enable;
 485         int err = 0;
 486
 487         memset(&rsp, 0, sizeof(rsp));
 488
 489         switch (msg->cmd) {
 490         case MBOX_CMD_INC_FALC_CLOCK:
 491         case MBOX_CMD_DEC_FALC_CLOCK:
 492                 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
 493                 if (rsp.data != msg->data)
 494                         rsp.cmd = MBOX_CMD_NAK;
 495                 else
 496                         rsp.cmd = MBOX_CMD_ACK;
 497
 498                 break;
 499
 500         case MBOX_CMD_INC_SSPI_CLOCK:
 501         case MBOX_CMD_DEC_SSPI_CLOCK:
 502                 if (tegra->soc->scale_ss_clock) {
 503                         err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
 504                         if (err < 0)
 505                                 rsp.cmd = MBOX_CMD_NAK;
 506                         else
 507                                 rsp.cmd = MBOX_CMD_ACK;
 508
 509                         rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
 510                 } else {
 511                         rsp.cmd = MBOX_CMD_ACK;
 512                         rsp.data = msg->data;
 513                 }
 514
 515                 break;
 516
 517         case MBOX_CMD_SET_BW:
 518                 /*
 519                  * TODO: Request bandwidth once EMC scaling is supported.
 520                  * Ignore for now since ACK/NAK is not required for SET_BW
 521                  * messages.
 522                  */
 523                 break;
 524
 525         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
 526                 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
 527                 if (err < 0) {
 528                         dev_err(dev, "failed to save context for USB3#%u: %d\n",
 529                                 msg->data, err);
 530                         rsp.cmd = MBOX_CMD_NAK;
 531                 } else {
 532                         rsp.cmd = MBOX_CMD_ACK;
 533                 }
 534
 535                 rsp.data = msg->data;
 536                 break;
 537
 538         case MBOX_CMD_START_HSIC_IDLE:
 539         case MBOX_CMD_STOP_HSIC_IDLE:
 540                 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
 541                         idle = false;
 542                 else
 543                         idle = true;
 544
 545                 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
 546                                      soc->ports.hsic.count);
 547
 548                 for_each_set_bit(port, &mask, 32) {
 549                         err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
 550                                                               idle);
 551                         if (err < 0)
 552                                 break;
 553                 }
 554
 555                 if (err < 0) {
 556                         dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
 557                                 idle ? "idle" : "busy", err);
 558                         rsp.cmd = MBOX_CMD_NAK;
 559                 } else {
 560                         rsp.cmd = MBOX_CMD_ACK;
 561                 }
 562
 563                 rsp.data = msg->data;
 564                 break;
 565
 566         case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
 567         case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
 568                 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
 569                         enable = false;
 570                 else
 571                         enable = true;
 572
 573                 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
 574                                      soc->ports.usb3.count);
 575
 576                 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
 577                         err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
 578                                                                      port,
 579                                                                      enable);
 580                         if (err < 0)
 581                                 break;
 582
 583                         /*
 584                          * wait 500us for LFPS detector to be disabled before
 585                          * sending ACK
 586                          */
 587                         if (!enable)
 588                                 usleep_range(500, 1000);
 589                 }
 590
 591                 if (err < 0) {
 592                         dev_err(dev,
 593                                 "failed to %s LFPS detection on USB3#%u: %d\n",
 594                                 enable ? "enable" : "disable", port, err);
 595                         rsp.cmd = MBOX_CMD_NAK;
 596                 } else {
 597                         rsp.cmd = MBOX_CMD_ACK;
 598                 }
 599
 600                 rsp.data = msg->data;
 601                 break;
 602
 603         default:
 604                 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
 605                 break;
 606         }
 607
 608         if (rsp.cmd) {
 609                 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
 610
 611                 err = tegra_xusb_mbox_send(tegra, &rsp);
 612                 if (err < 0)
 613                         dev_err(dev, "failed to send %s: %d\n", cmd, err);
 614         }
 615 }
 616
 617 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
 618 {
 619         struct tegra_xusb *tegra = data;
 620         struct tegra_xusb_mbox_msg msg;
 621         u32 value;
 622
 623         mutex_lock(&tegra->lock);
 624
 625         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT);
 626         tegra_xusb_mbox_unpack(&msg, value);
 627
 628         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
 629         value &= ~MBOX_DEST_SMI;
 630         fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
 631
 632         /* clear mailbox owner if no ACK/NAK is required */
 633         if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
 634                 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
 635
 636         tegra_xusb_mbox_handle(tegra, &msg);
 637
 638         mutex_unlock(&tegra->lock);
 639         return IRQ_HANDLED;
 640 }
 641
 642 static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra,
 643                                    struct resource *regs)
 644 {
 645         u32 value;
 646
 647         value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
 648         value |= IPFS_EN_FPCI;
 649         ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
 650
 651         usleep_range(10, 20);
 652
 653         /* Program BAR0 space */
 654         value = fpci_readl(tegra, XUSB_CFG_4);
 655         value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 656         value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 657         fpci_writel(tegra, value, XUSB_CFG_4);
 658
 659         usleep_range(100, 200);
 660
 661         /* Enable bus master */
 662         value = fpci_readl(tegra, XUSB_CFG_1);
 663         value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
 664         fpci_writel(tegra, value, XUSB_CFG_1);
 665
 666         /* Enable interrupt assertion */
 667         value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
 668         value |= IPFS_IP_INT_MASK;
 669         ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
 670
 671         /* Set hysteresis */
 672         ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
 673 }
 674
 675 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
 676 {
 677         int err;
 678
 679         err = clk_prepare_enable(tegra->pll_e);
 680         if (err < 0)
 681                 return err;
 682
 683         err = clk_prepare_enable(tegra->host_clk);
 684         if (err < 0)
 685                 goto disable_plle;
 686
 687         err = clk_prepare_enable(tegra->ss_clk);
 688         if (err < 0)
 689                 goto disable_host;
 690
 691         err = clk_prepare_enable(tegra->falcon_clk);
 692         if (err < 0)
 693                 goto disable_ss;
 694
 695         err = clk_prepare_enable(tegra->fs_src_clk);
 696         if (err < 0)
 697                 goto disable_falc;
 698
 699         err = clk_prepare_enable(tegra->hs_src_clk);
 700         if (err < 0)
 701                 goto disable_fs_src;
 702
 703         if (tegra->soc->scale_ss_clock) {
 704                 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
 705                 if (err < 0)
 706                         goto disable_hs_src;
 707         }
 708
 709         return 0;
 710
 711 disable_hs_src:
 712         clk_disable_unprepare(tegra->hs_src_clk);
 713 disable_fs_src:
 714         clk_disable_unprepare(tegra->fs_src_clk);
 715 disable_falc:
 716         clk_disable_unprepare(tegra->falcon_clk);
 717 disable_ss:
 718         clk_disable_unprepare(tegra->ss_clk);
 719 disable_host:
 720         clk_disable_unprepare(tegra->host_clk);
 721 disable_plle:
 722         clk_disable_unprepare(tegra->pll_e);
 723         return err;
 724 }
 725
 726 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
 727 {
 728         clk_disable_unprepare(tegra->pll_e);
 729         clk_disable_unprepare(tegra->host_clk);
 730         clk_disable_unprepare(tegra->ss_clk);
 731         clk_disable_unprepare(tegra->falcon_clk);
 732         clk_disable_unprepare(tegra->fs_src_clk);
 733         clk_disable_unprepare(tegra->hs_src_clk);
 734 }
 735
 736 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
 737 {
 738         unsigned int i;
 739         int err;
 740
 741         for (i = 0; i < tegra->num_phys; i++) {
 742                 err = phy_init(tegra->phys[i]);
 743                 if (err)
 744                         goto disable_phy;
 745
 746                 err = phy_power_on(tegra->phys[i]);
 747                 if (err) {
 748                         phy_exit(tegra->phys[i]);
 749                         goto disable_phy;
 750                 }
 751         }
 752
 753         return 0;
 754
 755 disable_phy:
 756         while (i--) {
 757                 phy_power_off(tegra->phys[i]);
 758                 phy_exit(tegra->phys[i]);
 759         }
 760
 761         return err;
 762 }
 763
 764 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
 765 {
 766         unsigned int i;
 767
 768         for (i = 0; i < tegra->num_phys; i++) {
 769                 phy_power_off(tegra->phys[i]);
 770                 phy_exit(tegra->phys[i]);
 771         }
 772 }
 773
 774 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
 775 {
 776         unsigned int code_tag_blocks, code_size_blocks, code_blocks;
 777         struct tegra_xusb_fw_header *header;
 778         struct device *dev = tegra->dev;
 779         const struct firmware *fw;
 780         unsigned long timeout;
 781         time_t timestamp;
 782         struct tm time;
 783         u64 address;
 784         u32 value;
 785         int err;
 786
 787         err = reject_firmware(&fw, tegra->soc->firmware, tegra->dev);
 788         if (err < 0) {
 789                 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
 790                 return err;
 791         }
 792
 793         /* Load Falcon controller with its firmware. */
 794         header = (struct tegra_xusb_fw_header *)fw->data;
 795         tegra->fw.size = le32_to_cpu(header->fwimg_len);
 796
 797         tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
 798                                             &tegra->fw.phys, GFP_KERNEL);
 799         if (!tegra->fw.virt) {
 800                 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
 801                 release_firmware(fw);
 802                 return -ENOMEM;
 803         }
 804
 805         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 806         memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
 807         release_firmware(fw);
 808
 809         if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
 810                 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
 811                          csb_readl(tegra, XUSB_FALC_CPUCTL));
 812                 return 0;
 813         }
 814
 815         /* Program the size of DFI into ILOAD_ATTR. */
 816         csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
 817
 818         /*
 819          * Boot code of the firmware reads the ILOAD_BASE registers
 820          * to get to the start of the DFI in system memory.
 821          */
 822         address = tegra->fw.phys + sizeof(*header);
 823         csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
 824         csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
 825
 826         /* Set BOOTPATH to 1 in APMAP. */
 827         csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
 828
 829         /* Invalidate L2IMEM. */
 830         csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
 831
 832         /*
 833          * Initiate fetch of bootcode from system memory into L2IMEM.
 834          * Program bootcode location and size in system memory.
 835          */
 836         code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
 837                                        IMEM_BLOCK_SIZE);
 838         code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
 839                                         IMEM_BLOCK_SIZE);
 840         code_blocks = code_tag_blocks + code_size_blocks;
 841
 842         value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
 843                         L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
 844                 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
 845                         L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
 846         csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
 847
 848         /* Trigger L2IMEM load operation. */
 849         csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
 850                    XUSB_CSB_MP_L2IMEMOP_TRIG);
 851
 852         /* Setup Falcon auto-fill. */
 853         csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
 854
 855         value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
 856                         IMFILLRNG1_TAG_LO_SHIFT) |
 857                 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
 858                         IMFILLRNG1_TAG_HI_SHIFT);
 859         csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
 860
 861         csb_writel(tegra, 0, XUSB_FALC_DMACTL);
 862
 863         msleep(50);
 864
 865         csb_writel(tegra, le32_to_cpu(header->boot_codetag),
 866                    XUSB_FALC_BOOTVEC);
 867
 868         /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
 869         timeout = jiffies + msecs_to_jiffies(5);
 870
 871         csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
 872
 873         while (time_before(jiffies, timeout)) {
 874                 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
 875                         break;
 876
 877                 usleep_range(100, 200);
 878         }
 879
 880         if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
 881                 dev_err(dev, "Falcon failed to start, state: %#x\n",
 882                         csb_readl(tegra, XUSB_FALC_CPUCTL));
 883                 return -EIO;
 884         }
 885
 886         timestamp = le32_to_cpu(header->fwimg_created_time);
 887         time_to_tm(timestamp, 0, &time);
 888
 889         dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
 890                  time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
 891                  time.tm_hour, time.tm_min, time.tm_sec);
 892
 893         return 0;
 894 }
 895
 896 static int tegra_xusb_probe(struct platform_device *pdev)
 897 {
 898         struct tegra_xusb_mbox_msg msg;
 899         struct resource *res, *regs;
 900         struct tegra_xusb *tegra;
 901         struct xhci_hcd *xhci;
 902         unsigned int i, j, k;
 903         struct phy *phy;
 904         int err;
 905
 906         BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
 907
 908         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
 909         if (!tegra)
 910                 return -ENOMEM;
 911
 912         tegra->soc = of_device_get_match_data(&pdev->dev);
 913         mutex_init(&tegra->lock);
 914         tegra->dev = &pdev->dev;
 915
 916         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 917         tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
 918         if (IS_ERR(tegra->regs))
 919                 return PTR_ERR(tegra->regs);
 920
 921         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 922         tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res);
 923         if (IS_ERR(tegra->fpci_base))
 924                 return PTR_ERR(tegra->fpci_base);
 925
 926         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 927         tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
 928         if (IS_ERR(tegra->ipfs_base))
 929                 return PTR_ERR(tegra->ipfs_base);
 930
 931         tegra->xhci_irq = platform_get_irq(pdev, 0);
 932         if (tegra->xhci_irq < 0)
 933                 return tegra->xhci_irq;
 934
 935         tegra->mbox_irq = platform_get_irq(pdev, 1);
 936         if (tegra->mbox_irq < 0)
 937                 return tegra->mbox_irq;
 938
 939         tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
 940         if (IS_ERR(tegra->padctl))
 941                 return PTR_ERR(tegra->padctl);
 942
 943         tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host");
 944         if (IS_ERR(tegra->host_rst)) {
 945                 err = PTR_ERR(tegra->host_rst);
 946                 dev_err(&pdev->dev, "failed to get xusb_host reset: %d\n", err);
 947                 goto put_padctl;
 948         }
 949
 950         tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
 951         if (IS_ERR(tegra->ss_rst)) {
 952                 err = PTR_ERR(tegra->ss_rst);
 953                 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", err);
 954                 goto put_padctl;
 955         }
 956
 957         tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
 958         if (IS_ERR(tegra->host_clk)) {
 959                 err = PTR_ERR(tegra->host_clk);
 960                 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
 961                 goto put_padctl;
 962         }
 963
 964         tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
 965         if (IS_ERR(tegra->falcon_clk)) {
 966                 err = PTR_ERR(tegra->falcon_clk);
 967                 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
 968                 goto put_padctl;
 969         }
 970
 971         tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
 972         if (IS_ERR(tegra->ss_clk)) {
 973                 err = PTR_ERR(tegra->ss_clk);
 974                 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
 975                 goto put_padctl;
 976         }
 977
 978         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
 979         if (IS_ERR(tegra->ss_src_clk)) {
 980                 err = PTR_ERR(tegra->ss_src_clk);
 981                 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
 982                 goto put_padctl;
 983         }
 984
 985         tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
 986         if (IS_ERR(tegra->hs_src_clk)) {
 987                 err = PTR_ERR(tegra->hs_src_clk);
 988                 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
 989                 goto put_padctl;
 990         }
 991
 992         tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
 993         if (IS_ERR(tegra->fs_src_clk)) {
 994                 err = PTR_ERR(tegra->fs_src_clk);
 995                 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
 996                 goto put_padctl;
 997         }
 998
 999         tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1000         if (IS_ERR(tegra->pll_u_480m)) {
1001                 err = PTR_ERR(tegra->pll_u_480m);
1002                 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1003                 goto put_padctl;
1004         }
1005
1006         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1007         if (IS_ERR(tegra->clk_m)) {
1008                 err = PTR_ERR(tegra->clk_m);
1009                 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1010                 goto put_padctl;
1011         }
1012
1013         tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1014         if (IS_ERR(tegra->pll_e)) {
1015                 err = PTR_ERR(tegra->pll_e);
1016                 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1017                 goto put_padctl;
1018         }
1019
1020         tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1021                                        sizeof(*tegra->supplies), GFP_KERNEL);
1022         if (!tegra->supplies) {
1023                 err = -ENOMEM;
1024                 goto put_padctl;
1025         }
1026
1027         for (i = 0; i < tegra->soc->num_supplies; i++)
1028                 tegra->supplies[i].supply = tegra->soc->supply_names[i];
1029
1030         err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1031                                       tegra->supplies);
1032         if (err) {
1033                 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1034                 goto put_padctl;
1035         }
1036
1037         for (i = 0; i < tegra->soc->num_types; i++)
1038                 tegra->num_phys += tegra->soc->phy_types[i].num;
1039
1040         tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1041                                    sizeof(*tegra->phys), GFP_KERNEL);
1042         if (!tegra->phys) {
1043                 err = -ENOMEM;
1044                 goto put_padctl;
1045         }
1046
1047         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1048                 char prop[8];
1049
1050                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1051                         snprintf(prop, sizeof(prop), "%s-%d",
1052                                  tegra->soc->phy_types[i].name, j);
1053
1054                         phy = devm_phy_optional_get(&pdev->dev, prop);
1055                         if (IS_ERR(phy)) {
1056                                 dev_err(&pdev->dev,
1057                                         "failed to get PHY %s: %ld\n", prop,
1058                                         PTR_ERR(phy));
1059                                 err = PTR_ERR(phy);
1060                                 goto put_padctl;
1061                         }
1062
1063                         tegra->phys[k++] = phy;
1064                 }
1065         }
1066
1067         err = tegra_xusb_clk_enable(tegra);
1068         if (err) {
1069                 dev_err(&pdev->dev, "failed to enable clocks: %d\n", err);
1070                 goto put_padctl;
1071         }
1072
1073         err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1074         if (err) {
1075                 dev_err(&pdev->dev, "failed to enable regulators: %d\n", err);
1076                 goto disable_clk;
1077         }
1078
1079         err = tegra_xusb_phy_enable(tegra);
1080         if (err < 0) {
1081                 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1082                 goto disable_regulator;
1083         }
1084
1085         tegra_xusb_ipfs_config(tegra, regs);
1086
1087         err = tegra_xusb_load_firmware(tegra);
1088         if (err < 0) {
1089                 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1090                 goto disable_phy;
1091         }
1092
1093         tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1094                                     dev_name(&pdev->dev));
1095         if (!tegra->hcd) {
1096                 err = -ENOMEM;
1097                 goto disable_phy;
1098         }
1099
1100         /*
1101          * This must happen after usb_create_hcd(), because usb_create_hcd()
1102          * will overwrite the drvdata of the device with the hcd it creates.
1103          */
1104         platform_set_drvdata(pdev, tegra);
1105
1106         tegra->hcd->regs = tegra->regs;
1107         tegra->hcd->rsrc_start = regs->start;
1108         tegra->hcd->rsrc_len = resource_size(regs);
1109
1110         err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1111         if (err < 0) {
1112                 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1113                 goto put_usb2;
1114         }
1115
1116         device_wakeup_enable(tegra->hcd->self.controller);
1117
1118         xhci = hcd_to_xhci(tegra->hcd);
1119
1120         xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1121                                                  &pdev->dev,
1122                                                  dev_name(&pdev->dev),
1123                                                  tegra->hcd);
1124         if (!xhci->shared_hcd) {
1125                 dev_err(&pdev->dev, "failed to create shared HCD\n");
1126                 err = -ENOMEM;
1127                 goto remove_usb2;
1128         }
1129
1130         err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1131         if (err < 0) {
1132                 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1133                 goto put_usb3;
1134         }
1135
1136         mutex_lock(&tegra->lock);
1137
1138         /* Enable firmware messages from controller. */
1139         msg.cmd = MBOX_CMD_MSG_ENABLED;
1140         msg.data = 0;
1141
1142         err = tegra_xusb_mbox_send(tegra, &msg);
1143         if (err < 0) {
1144                 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1145                 mutex_unlock(&tegra->lock);
1146                 goto remove_usb3;
1147         }
1148
1149         mutex_unlock(&tegra->lock);
1150
1151         err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1152                                         tegra_xusb_mbox_irq,
1153                                         tegra_xusb_mbox_thread, 0,
1154                                         dev_name(&pdev->dev), tegra);
1155         if (err < 0) {
1156                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1157                 goto remove_usb3;
1158         }
1159
1160         return 0;
1161
1162 remove_usb3:
1163         usb_remove_hcd(xhci->shared_hcd);
1164 put_usb3:
1165         usb_put_hcd(xhci->shared_hcd);
1166 remove_usb2:
1167         usb_remove_hcd(tegra->hcd);
1168 put_usb2:
1169         usb_put_hcd(tegra->hcd);
1170 disable_phy:
1171         tegra_xusb_phy_disable(tegra);
1172 disable_regulator:
1173         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1174 disable_clk:
1175         tegra_xusb_clk_disable(tegra);
1176 put_padctl:
1177         tegra_xusb_padctl_put(tegra->padctl);
1178         return err;
1179 }
1180
1181 static int tegra_xusb_remove(struct platform_device *pdev)
1182 {
1183         struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1184         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1185
1186         usb_remove_hcd(xhci->shared_hcd);
1187         usb_put_hcd(xhci->shared_hcd);
1188         usb_remove_hcd(tegra->hcd);
1189         usb_put_hcd(tegra->hcd);
1190
1191         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1192                           tegra->fw.phys);
1193
1194         tegra_xusb_phy_disable(tegra);
1195         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1196         tegra_xusb_clk_disable(tegra);
1197
1198         tegra_xusb_padctl_put(tegra->padctl);
1199
1200         return 0;
1201 }
1202
1203 #ifdef CONFIG_PM_SLEEP
1204 static int tegra_xusb_suspend(struct device *dev)
1205 {
1206         struct tegra_xusb *tegra = dev_get_drvdata(dev);
1207         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1208         bool wakeup = device_may_wakeup(dev);
1209
1210         /* TODO: Powergate controller across suspend/resume. */
1211         return xhci_suspend(xhci, wakeup);
1212 }
1213
1214 static int tegra_xusb_resume(struct device *dev)
1215 {
1216         struct tegra_xusb *tegra = dev_get_drvdata(dev);
1217         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1218
1219         return xhci_resume(xhci, 0);
1220 }
1221 #endif
1222
1223 static const struct dev_pm_ops tegra_xusb_pm_ops = {
1224         SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1225 };
1226
1227 static const char * const tegra124_supply_names[] = {
1228         "avddio-pex",
1229         "dvddio-pex",
1230         "avdd-usb",
1231         "avdd-pll-utmip",
1232         "avdd-pll-erefe",
1233         "avdd-usb-ss-pll",
1234         "hvdd-usb-ss",
1235         "hvdd-usb-ss-pll-e",
1236 };
1237
1238 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1239         { .name = "usb3", .num = 2, },
1240         { .name = "usb2", .num = 3, },
1241         { .name = "hsic", .num = 2, },
1242 };
1243
1244 static const struct tegra_xusb_soc tegra124_soc = {
1245         .firmware = "/*(DEBLOBBED)*/",
1246         .supply_names = tegra124_supply_names,
1247         .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1248         .phy_types = tegra124_phy_types,
1249         .num_types = ARRAY_SIZE(tegra124_phy_types),
1250         .ports = {
1251                 .usb2 = { .offset = 4, .count = 4, },
1252                 .hsic = { .offset = 6, .count = 2, },
1253                 .usb3 = { .offset = 0, .count = 2, },
1254         },
1255         .scale_ss_clock = true,
1256 };
1257 /*(DEBLOBBED)*/
1258
1259 static const char * const tegra210_supply_names[] = {
1260         "dvddio-pex",
1261         "hvddio-pex",
1262         "avdd-usb",
1263         "avdd-pll-utmip",
1264         "avdd-pll-uerefe",
1265         "dvdd-pex-pll",
1266         "hvdd-pex-pll-e",
1267 };
1268
1269 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1270         { .name = "usb3", .num = 4, },
1271         { .name = "usb2", .num = 4, },
1272         { .name = "hsic", .num = 1, },
1273 };
1274
1275 static const struct tegra_xusb_soc tegra210_soc = {
1276         .firmware = "/*(DEBLOBBED)*/",
1277         .supply_names = tegra210_supply_names,
1278         .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1279         .phy_types = tegra210_phy_types,
1280         .num_types = ARRAY_SIZE(tegra210_phy_types),
1281         .ports = {
1282                 .usb2 = { .offset = 4, .count = 4, },
1283                 .hsic = { .offset = 8, .count = 1, },
1284                 .usb3 = { .offset = 0, .count = 4, },
1285         },
1286         .scale_ss_clock = false,
1287 };
1288 /*(DEBLOBBED)*/
1289
1290 static const struct of_device_id tegra_xusb_of_match[] = {
1291         { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
1292         { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
1293         { },
1294 };
1295 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1296
1297 static struct platform_driver tegra_xusb_driver = {
1298         .probe = tegra_xusb_probe,
1299         .remove = tegra_xusb_remove,
1300         .driver = {
1301                 .name = "tegra-xusb",
1302                 .pm = &tegra_xusb_pm_ops,
1303                 .of_match_table = tegra_xusb_of_match,
1304         },
1305 };
1306
1307 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1308 {
1309         xhci->quirks |= XHCI_PLAT;
1310 }
1311
1312 static int tegra_xhci_setup(struct usb_hcd *hcd)
1313 {
1314         return xhci_gen_setup(hcd, tegra_xhci_quirks);
1315 }
1316
1317 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
1318         .extra_priv_size = sizeof(struct xhci_hcd),
1319         .reset = tegra_xhci_setup,
1320 };
1321
1322 static int __init tegra_xusb_init(void)
1323 {
1324         xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1325
1326         return platform_driver_register(&tegra_xusb_driver);
1327 }
1328 module_init(tegra_xusb_init);
1329
1330 static void __exit tegra_xusb_exit(void)
1331 {
1332         platform_driver_unregister(&tegra_xusb_driver);
1333 }
1334 module_exit(tegra_xusb_exit);
1335
1336 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1337 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1338 MODULE_LICENSE("GPL v2");