GNU Linux-libre 4.19.264-gnu1
[releases.git] / drivers / usb / host / xhci-tegra.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * NVIDIA Tegra xHCI host controller driver
4  *
5  * Copyright (C) 2014 NVIDIA Corporation
6  * Copyright (C) 2014 Google, Inc.
7  */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/phy/phy.h>
18 #include <linux/phy/tegra/xusb.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/reset.h>
24 #include <linux/slab.h>
25 #include <soc/tegra/pmc.h>
26
27 #include "xhci.h"
28
29 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
30 #define TEGRA_XHCI_SS_LOW_SPEED   12000000
31
32 /* FPCI CFG registers */
33 #define XUSB_CFG_1                              0x004
34 #define  XUSB_IO_SPACE_EN                       BIT(0)
35 #define  XUSB_MEM_SPACE_EN                      BIT(1)
36 #define  XUSB_BUS_MASTER_EN                     BIT(2)
37 #define XUSB_CFG_4                              0x010
38 #define  XUSB_BASE_ADDR_SHIFT                   15
39 #define  XUSB_BASE_ADDR_MASK                    0x1ffff
40 #define XUSB_CFG_ARU_C11_CSBRANGE               0x41c
41 #define XUSB_CFG_CSB_BASE_ADDR                  0x800
42
43 /* FPCI mailbox registers */
44 #define XUSB_CFG_ARU_MBOX_CMD                   0x0e4
45 #define  MBOX_DEST_FALC                         BIT(27)
46 #define  MBOX_DEST_PME                          BIT(28)
47 #define  MBOX_DEST_SMI                          BIT(29)
48 #define  MBOX_DEST_XHCI                         BIT(30)
49 #define  MBOX_INT_EN                            BIT(31)
50 #define XUSB_CFG_ARU_MBOX_DATA_IN               0x0e8
51 #define  CMD_DATA_SHIFT                         0
52 #define  CMD_DATA_MASK                          0xffffff
53 #define  CMD_TYPE_SHIFT                         24
54 #define  CMD_TYPE_MASK                          0xff
55 #define XUSB_CFG_ARU_MBOX_DATA_OUT              0x0ec
56 #define XUSB_CFG_ARU_MBOX_OWNER                 0x0f0
57 #define  MBOX_OWNER_NONE                        0
58 #define  MBOX_OWNER_FW                          1
59 #define  MBOX_OWNER_SW                          2
60 #define XUSB_CFG_ARU_SMI_INTR                   0x428
61 #define  MBOX_SMI_INTR_FW_HANG                  BIT(1)
62 #define  MBOX_SMI_INTR_EN                       BIT(3)
63
64 /* IPFS registers */
65 #define IPFS_XUSB_HOST_CONFIGURATION_0          0x180
66 #define  IPFS_EN_FPCI                           BIT(0)
67 #define IPFS_XUSB_HOST_INTR_MASK_0              0x188
68 #define  IPFS_IP_INT_MASK                       BIT(16)
69 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0     0x1bc
70
71 #define CSB_PAGE_SELECT_MASK                    0x7fffff
72 #define CSB_PAGE_SELECT_SHIFT                   9
73 #define CSB_PAGE_OFFSET_MASK                    0x1ff
74 #define CSB_PAGE_SELECT(addr)   ((addr) >> (CSB_PAGE_SELECT_SHIFT) &    \
75                                  CSB_PAGE_SELECT_MASK)
76 #define CSB_PAGE_OFFSET(addr)   ((addr) & CSB_PAGE_OFFSET_MASK)
77
78 /* Falcon CSB registers */
79 #define XUSB_FALC_CPUCTL                        0x100
80 #define  CPUCTL_STARTCPU                        BIT(1)
81 #define  CPUCTL_STATE_HALTED                    BIT(4)
82 #define  CPUCTL_STATE_STOPPED                   BIT(5)
83 #define XUSB_FALC_BOOTVEC                       0x104
84 #define XUSB_FALC_DMACTL                        0x10c
85 #define XUSB_FALC_IMFILLRNG1                    0x154
86 #define  IMFILLRNG1_TAG_MASK                    0xffff
87 #define  IMFILLRNG1_TAG_LO_SHIFT                0
88 #define  IMFILLRNG1_TAG_HI_SHIFT                16
89 #define XUSB_FALC_IMFILLCTL                     0x158
90
91 /* MP CSB registers */
92 #define XUSB_CSB_MP_ILOAD_ATTR                  0x101a00
93 #define XUSB_CSB_MP_ILOAD_BASE_LO               0x101a04
94 #define XUSB_CSB_MP_ILOAD_BASE_HI               0x101a08
95 #define XUSB_CSB_MP_L2IMEMOP_SIZE               0x101a10
96 #define  L2IMEMOP_SIZE_SRC_OFFSET_SHIFT         8
97 #define  L2IMEMOP_SIZE_SRC_OFFSET_MASK          0x3ff
98 #define  L2IMEMOP_SIZE_SRC_COUNT_SHIFT          24
99 #define  L2IMEMOP_SIZE_SRC_COUNT_MASK           0xff
100 #define XUSB_CSB_MP_L2IMEMOP_TRIG               0x101a14
101 #define  L2IMEMOP_ACTION_SHIFT                  24
102 #define  L2IMEMOP_INVALIDATE_ALL                (0x40 << L2IMEMOP_ACTION_SHIFT)
103 #define  L2IMEMOP_LOAD_LOCKED_RESULT            (0x11 << L2IMEMOP_ACTION_SHIFT)
104 #define XUSB_CSB_MP_APMAP                       0x10181c
105 #define  APMAP_BOOTPATH                         BIT(31)
106
107 #define IMEM_BLOCK_SIZE                         256
108
109 struct tegra_xusb_fw_header {
110         u32 boot_loadaddr_in_imem;
111         u32 boot_codedfi_offset;
112         u32 boot_codetag;
113         u32 boot_codesize;
114         u32 phys_memaddr;
115         u16 reqphys_memsize;
116         u16 alloc_phys_memsize;
117         u32 rodata_img_offset;
118         u32 rodata_section_start;
119         u32 rodata_section_end;
120         u32 main_fnaddr;
121         u32 fwimg_cksum;
122         u32 fwimg_created_time;
123         u32 imem_resident_start;
124         u32 imem_resident_end;
125         u32 idirect_start;
126         u32 idirect_end;
127         u32 l2_imem_start;
128         u32 l2_imem_end;
129         u32 version_id;
130         u8 init_ddirect;
131         u8 reserved[3];
132         u32 phys_addr_log_buffer;
133         u32 total_log_entries;
134         u32 dequeue_ptr;
135         u32 dummy_var[2];
136         u32 fwimg_len;
137         u8 magic[8];
138         u32 ss_low_power_entry_timeout;
139         u8 num_hsic_port;
140         u8 padding[139]; /* Pad to 256 bytes */
141 };
142
143 struct tegra_xusb_phy_type {
144         const char *name;
145         unsigned int num;
146 };
147
148 struct tegra_xusb_soc {
149         const char *firmware;
150         const char * const *supply_names;
151         unsigned int num_supplies;
152         const struct tegra_xusb_phy_type *phy_types;
153         unsigned int num_types;
154
155         struct {
156                 struct {
157                         unsigned int offset;
158                         unsigned int count;
159                 } usb2, ulpi, hsic, usb3;
160         } ports;
161
162         bool scale_ss_clock;
163 };
164
165 struct tegra_xusb {
166         struct device *dev;
167         void __iomem *regs;
168         struct usb_hcd *hcd;
169
170         struct mutex lock;
171
172         int xhci_irq;
173         int mbox_irq;
174
175         void __iomem *ipfs_base;
176         void __iomem *fpci_base;
177
178         const struct tegra_xusb_soc *soc;
179
180         struct regulator_bulk_data *supplies;
181
182         struct tegra_xusb_padctl *padctl;
183
184         struct clk *host_clk;
185         struct clk *falcon_clk;
186         struct clk *ss_clk;
187         struct clk *ss_src_clk;
188         struct clk *hs_src_clk;
189         struct clk *fs_src_clk;
190         struct clk *pll_u_480m;
191         struct clk *clk_m;
192         struct clk *pll_e;
193
194         struct reset_control *host_rst;
195         struct reset_control *ss_rst;
196
197         struct phy **phys;
198         unsigned int num_phys;
199
200         /* Firmware loading related */
201         struct {
202                 size_t size;
203                 void *virt;
204                 dma_addr_t phys;
205         } fw;
206 };
207
208 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
209
210 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
211 {
212         return readl(tegra->fpci_base + offset);
213 }
214
215 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
216                                unsigned int offset)
217 {
218         writel(value, tegra->fpci_base + offset);
219 }
220
221 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
222 {
223         return readl(tegra->ipfs_base + offset);
224 }
225
226 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
227                                unsigned int offset)
228 {
229         writel(value, tegra->ipfs_base + offset);
230 }
231
232 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
233 {
234         u32 page = CSB_PAGE_SELECT(offset);
235         u32 ofs = CSB_PAGE_OFFSET(offset);
236
237         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
238
239         return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
240 }
241
242 static void csb_writel(struct tegra_xusb *tegra, u32 value,
243                        unsigned int offset)
244 {
245         u32 page = CSB_PAGE_SELECT(offset);
246         u32 ofs = CSB_PAGE_OFFSET(offset);
247
248         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
249         fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
250 }
251
252 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
253                                  unsigned long rate)
254 {
255         unsigned long new_parent_rate, old_parent_rate;
256         struct clk *clk = tegra->ss_src_clk;
257         unsigned int div;
258         int err;
259
260         if (clk_get_rate(clk) == rate)
261                 return 0;
262
263         switch (rate) {
264         case TEGRA_XHCI_SS_HIGH_SPEED:
265                 /*
266                  * Reparent to PLLU_480M. Set divider first to avoid
267                  * overclocking.
268                  */
269                 old_parent_rate = clk_get_rate(clk_get_parent(clk));
270                 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
271                 div = new_parent_rate / rate;
272
273                 err = clk_set_rate(clk, old_parent_rate / div);
274                 if (err)
275                         return err;
276
277                 err = clk_set_parent(clk, tegra->pll_u_480m);
278                 if (err)
279                         return err;
280
281                 /*
282                  * The rate should already be correct, but set it again just
283                  * to be sure.
284                  */
285                 err = clk_set_rate(clk, rate);
286                 if (err)
287                         return err;
288
289                 break;
290
291         case TEGRA_XHCI_SS_LOW_SPEED:
292                 /* Reparent to CLK_M */
293                 err = clk_set_parent(clk, tegra->clk_m);
294                 if (err)
295                         return err;
296
297                 err = clk_set_rate(clk, rate);
298                 if (err)
299                         return err;
300
301                 break;
302
303         default:
304                 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
305                 return -EINVAL;
306         }
307
308         if (clk_get_rate(clk) != rate) {
309                 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
310                 return -EINVAL;
311         }
312
313         return 0;
314 }
315
316 static unsigned long extract_field(u32 value, unsigned int start,
317                                    unsigned int count)
318 {
319         return (value >> start) & ((1 << count) - 1);
320 }
321
322 /* Command requests from the firmware */
323 enum tegra_xusb_mbox_cmd {
324         MBOX_CMD_MSG_ENABLED = 1,
325         MBOX_CMD_INC_FALC_CLOCK,
326         MBOX_CMD_DEC_FALC_CLOCK,
327         MBOX_CMD_INC_SSPI_CLOCK,
328         MBOX_CMD_DEC_SSPI_CLOCK,
329         MBOX_CMD_SET_BW, /* no ACK/NAK required */
330         MBOX_CMD_SET_SS_PWR_GATING,
331         MBOX_CMD_SET_SS_PWR_UNGATING,
332         MBOX_CMD_SAVE_DFE_CTLE_CTX,
333         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
334         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
335         MBOX_CMD_START_HSIC_IDLE,
336         MBOX_CMD_STOP_HSIC_IDLE,
337         MBOX_CMD_DBC_WAKE_STACK, /* unused */
338         MBOX_CMD_HSIC_PRETEND_CONNECT,
339         MBOX_CMD_RESET_SSPI,
340         MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
341         MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
342
343         MBOX_CMD_MAX,
344
345         /* Response message to above commands */
346         MBOX_CMD_ACK = 128,
347         MBOX_CMD_NAK
348 };
349
350 static const char * const mbox_cmd_name[] = {
351         [  1] = "MSG_ENABLE",
352         [  2] = "INC_FALCON_CLOCK",
353         [  3] = "DEC_FALCON_CLOCK",
354         [  4] = "INC_SSPI_CLOCK",
355         [  5] = "DEC_SSPI_CLOCK",
356         [  6] = "SET_BW",
357         [  7] = "SET_SS_PWR_GATING",
358         [  8] = "SET_SS_PWR_UNGATING",
359         [  9] = "SAVE_DFE_CTLE_CTX",
360         [ 10] = "AIRPLANE_MODE_ENABLED",
361         [ 11] = "AIRPLANE_MODE_DISABLED",
362         [ 12] = "START_HSIC_IDLE",
363         [ 13] = "STOP_HSIC_IDLE",
364         [ 14] = "DBC_WAKE_STACK",
365         [ 15] = "HSIC_PRETEND_CONNECT",
366         [ 16] = "RESET_SSPI",
367         [ 17] = "DISABLE_SS_LFPS_DETECTION",
368         [ 18] = "ENABLE_SS_LFPS_DETECTION",
369         [128] = "ACK",
370         [129] = "NAK",
371 };
372
373 struct tegra_xusb_mbox_msg {
374         u32 cmd;
375         u32 data;
376 };
377
378 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
379 {
380         return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
381                (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
382 }
383 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
384                                           u32 value)
385 {
386         msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
387         msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
388 }
389
390 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
391 {
392         switch (cmd) {
393         case MBOX_CMD_SET_BW:
394         case MBOX_CMD_ACK:
395         case MBOX_CMD_NAK:
396                 return false;
397
398         default:
399                 return true;
400         }
401 }
402
403 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
404                                 const struct tegra_xusb_mbox_msg *msg)
405 {
406         bool wait_for_idle = false;
407         u32 value;
408
409         /*
410          * Acquire the mailbox. The firmware still owns the mailbox for
411          * ACK/NAK messages.
412          */
413         if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
414                 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
415                 if (value != MBOX_OWNER_NONE) {
416                         dev_err(tegra->dev, "mailbox is busy\n");
417                         return -EBUSY;
418                 }
419
420                 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER);
421
422                 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
423                 if (value != MBOX_OWNER_SW) {
424                         dev_err(tegra->dev, "failed to acquire mailbox\n");
425                         return -EBUSY;
426                 }
427
428                 wait_for_idle = true;
429         }
430
431         value = tegra_xusb_mbox_pack(msg);
432         fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN);
433
434         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
435         value |= MBOX_INT_EN | MBOX_DEST_FALC;
436         fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
437
438         if (wait_for_idle) {
439                 unsigned long timeout = jiffies + msecs_to_jiffies(250);
440
441                 while (time_before(jiffies, timeout)) {
442                         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
443                         if (value == MBOX_OWNER_NONE)
444                                 break;
445
446                         usleep_range(10, 20);
447                 }
448
449                 if (time_after(jiffies, timeout))
450                         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
451
452                 if (value != MBOX_OWNER_NONE)
453                         return -ETIMEDOUT;
454         }
455
456         return 0;
457 }
458
459 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
460 {
461         struct tegra_xusb *tegra = data;
462         u32 value;
463
464         /* clear mailbox interrupts */
465         value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
466         fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
467
468         if (value & MBOX_SMI_INTR_FW_HANG)
469                 dev_err(tegra->dev, "controller firmware hang\n");
470
471         return IRQ_WAKE_THREAD;
472 }
473
474 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
475                                    const struct tegra_xusb_mbox_msg *msg)
476 {
477         struct tegra_xusb_padctl *padctl = tegra->padctl;
478         const struct tegra_xusb_soc *soc = tegra->soc;
479         struct device *dev = tegra->dev;
480         struct tegra_xusb_mbox_msg rsp;
481         unsigned long mask;
482         unsigned int port;
483         bool idle, enable;
484         int err = 0;
485
486         memset(&rsp, 0, sizeof(rsp));
487
488         switch (msg->cmd) {
489         case MBOX_CMD_INC_FALC_CLOCK:
490         case MBOX_CMD_DEC_FALC_CLOCK:
491                 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
492                 if (rsp.data != msg->data)
493                         rsp.cmd = MBOX_CMD_NAK;
494                 else
495                         rsp.cmd = MBOX_CMD_ACK;
496
497                 break;
498
499         case MBOX_CMD_INC_SSPI_CLOCK:
500         case MBOX_CMD_DEC_SSPI_CLOCK:
501                 if (tegra->soc->scale_ss_clock) {
502                         err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
503                         if (err < 0)
504                                 rsp.cmd = MBOX_CMD_NAK;
505                         else
506                                 rsp.cmd = MBOX_CMD_ACK;
507
508                         rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
509                 } else {
510                         rsp.cmd = MBOX_CMD_ACK;
511                         rsp.data = msg->data;
512                 }
513
514                 break;
515
516         case MBOX_CMD_SET_BW:
517                 /*
518                  * TODO: Request bandwidth once EMC scaling is supported.
519                  * Ignore for now since ACK/NAK is not required for SET_BW
520                  * messages.
521                  */
522                 break;
523
524         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
525                 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
526                 if (err < 0) {
527                         dev_err(dev, "failed to save context for USB3#%u: %d\n",
528                                 msg->data, err);
529                         rsp.cmd = MBOX_CMD_NAK;
530                 } else {
531                         rsp.cmd = MBOX_CMD_ACK;
532                 }
533
534                 rsp.data = msg->data;
535                 break;
536
537         case MBOX_CMD_START_HSIC_IDLE:
538         case MBOX_CMD_STOP_HSIC_IDLE:
539                 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
540                         idle = false;
541                 else
542                         idle = true;
543
544                 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
545                                      soc->ports.hsic.count);
546
547                 for_each_set_bit(port, &mask, 32) {
548                         err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
549                                                               idle);
550                         if (err < 0)
551                                 break;
552                 }
553
554                 if (err < 0) {
555                         dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
556                                 idle ? "idle" : "busy", err);
557                         rsp.cmd = MBOX_CMD_NAK;
558                 } else {
559                         rsp.cmd = MBOX_CMD_ACK;
560                 }
561
562                 rsp.data = msg->data;
563                 break;
564
565         case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
566         case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
567                 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
568                         enable = false;
569                 else
570                         enable = true;
571
572                 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
573                                      soc->ports.usb3.count);
574
575                 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
576                         err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
577                                                                      port,
578                                                                      enable);
579                         if (err < 0)
580                                 break;
581
582                         /*
583                          * wait 500us for LFPS detector to be disabled before
584                          * sending ACK
585                          */
586                         if (!enable)
587                                 usleep_range(500, 1000);
588                 }
589
590                 if (err < 0) {
591                         dev_err(dev,
592                                 "failed to %s LFPS detection on USB3#%u: %d\n",
593                                 enable ? "enable" : "disable", port, err);
594                         rsp.cmd = MBOX_CMD_NAK;
595                 } else {
596                         rsp.cmd = MBOX_CMD_ACK;
597                 }
598
599                 rsp.data = msg->data;
600                 break;
601
602         default:
603                 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
604                 break;
605         }
606
607         if (rsp.cmd) {
608                 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
609
610                 err = tegra_xusb_mbox_send(tegra, &rsp);
611                 if (err < 0)
612                         dev_err(dev, "failed to send %s: %d\n", cmd, err);
613         }
614 }
615
616 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
617 {
618         struct tegra_xusb *tegra = data;
619         struct tegra_xusb_mbox_msg msg;
620         u32 value;
621
622         mutex_lock(&tegra->lock);
623
624         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT);
625         tegra_xusb_mbox_unpack(&msg, value);
626
627         value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
628         value &= ~MBOX_DEST_SMI;
629         fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
630
631         /* clear mailbox owner if no ACK/NAK is required */
632         if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
633                 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
634
635         tegra_xusb_mbox_handle(tegra, &msg);
636
637         mutex_unlock(&tegra->lock);
638         return IRQ_HANDLED;
639 }
640
641 static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra,
642                                    struct resource *regs)
643 {
644         u32 value;
645
646         value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
647         value |= IPFS_EN_FPCI;
648         ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
649
650         usleep_range(10, 20);
651
652         /* Program BAR0 space */
653         value = fpci_readl(tegra, XUSB_CFG_4);
654         value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
655         value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
656         fpci_writel(tegra, value, XUSB_CFG_4);
657
658         usleep_range(100, 200);
659
660         /* Enable bus master */
661         value = fpci_readl(tegra, XUSB_CFG_1);
662         value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
663         fpci_writel(tegra, value, XUSB_CFG_1);
664
665         /* Enable interrupt assertion */
666         value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
667         value |= IPFS_IP_INT_MASK;
668         ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
669
670         /* Set hysteresis */
671         ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
672 }
673
674 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
675 {
676         int err;
677
678         err = clk_prepare_enable(tegra->pll_e);
679         if (err < 0)
680                 return err;
681
682         err = clk_prepare_enable(tegra->host_clk);
683         if (err < 0)
684                 goto disable_plle;
685
686         err = clk_prepare_enable(tegra->ss_clk);
687         if (err < 0)
688                 goto disable_host;
689
690         err = clk_prepare_enable(tegra->falcon_clk);
691         if (err < 0)
692                 goto disable_ss;
693
694         err = clk_prepare_enable(tegra->fs_src_clk);
695         if (err < 0)
696                 goto disable_falc;
697
698         err = clk_prepare_enable(tegra->hs_src_clk);
699         if (err < 0)
700                 goto disable_fs_src;
701
702         if (tegra->soc->scale_ss_clock) {
703                 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
704                 if (err < 0)
705                         goto disable_hs_src;
706         }
707
708         return 0;
709
710 disable_hs_src:
711         clk_disable_unprepare(tegra->hs_src_clk);
712 disable_fs_src:
713         clk_disable_unprepare(tegra->fs_src_clk);
714 disable_falc:
715         clk_disable_unprepare(tegra->falcon_clk);
716 disable_ss:
717         clk_disable_unprepare(tegra->ss_clk);
718 disable_host:
719         clk_disable_unprepare(tegra->host_clk);
720 disable_plle:
721         clk_disable_unprepare(tegra->pll_e);
722         return err;
723 }
724
725 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
726 {
727         clk_disable_unprepare(tegra->pll_e);
728         clk_disable_unprepare(tegra->host_clk);
729         clk_disable_unprepare(tegra->ss_clk);
730         clk_disable_unprepare(tegra->falcon_clk);
731         clk_disable_unprepare(tegra->fs_src_clk);
732         clk_disable_unprepare(tegra->hs_src_clk);
733 }
734
735 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
736 {
737         unsigned int i;
738         int err;
739
740         for (i = 0; i < tegra->num_phys; i++) {
741                 err = phy_init(tegra->phys[i]);
742                 if (err)
743                         goto disable_phy;
744
745                 err = phy_power_on(tegra->phys[i]);
746                 if (err) {
747                         phy_exit(tegra->phys[i]);
748                         goto disable_phy;
749                 }
750         }
751
752         return 0;
753
754 disable_phy:
755         while (i--) {
756                 phy_power_off(tegra->phys[i]);
757                 phy_exit(tegra->phys[i]);
758         }
759
760         return err;
761 }
762
763 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
764 {
765         unsigned int i;
766
767         for (i = 0; i < tegra->num_phys; i++) {
768                 phy_power_off(tegra->phys[i]);
769                 phy_exit(tegra->phys[i]);
770         }
771 }
772
773 static int tegra_xusb_runtime_suspend(struct device *dev)
774 {
775         struct tegra_xusb *tegra = dev_get_drvdata(dev);
776
777         tegra_xusb_phy_disable(tegra);
778         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
779         tegra_xusb_clk_disable(tegra);
780
781         return 0;
782 }
783
784 static int tegra_xusb_runtime_resume(struct device *dev)
785 {
786         struct tegra_xusb *tegra = dev_get_drvdata(dev);
787         int err;
788
789         err = tegra_xusb_clk_enable(tegra);
790         if (err) {
791                 dev_err(dev, "failed to enable clocks: %d\n", err);
792                 return err;
793         }
794
795         err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
796         if (err) {
797                 dev_err(dev, "failed to enable regulators: %d\n", err);
798                 goto disable_clk;
799         }
800
801         err = tegra_xusb_phy_enable(tegra);
802         if (err < 0) {
803                 dev_err(dev, "failed to enable PHYs: %d\n", err);
804                 goto disable_regulator;
805         }
806
807         return 0;
808
809 disable_regulator:
810         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
811 disable_clk:
812         tegra_xusb_clk_disable(tegra);
813         return err;
814 }
815
816 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
817 {
818         unsigned int code_tag_blocks, code_size_blocks, code_blocks;
819         struct tegra_xusb_fw_header *header;
820         struct device *dev = tegra->dev;
821         const struct firmware *fw;
822         unsigned long timeout;
823         time64_t timestamp;
824         struct tm time;
825         u64 address;
826         u32 value;
827         int err;
828
829         err = reject_firmware(&fw, tegra->soc->firmware, tegra->dev);
830         if (err < 0) {
831                 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
832                 return err;
833         }
834
835         /* Load Falcon controller with its firmware. */
836         header = (struct tegra_xusb_fw_header *)fw->data;
837         tegra->fw.size = le32_to_cpu(header->fwimg_len);
838
839         tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
840                                             &tegra->fw.phys, GFP_KERNEL);
841         if (!tegra->fw.virt) {
842                 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
843                 release_firmware(fw);
844                 return -ENOMEM;
845         }
846
847         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
848         memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
849         release_firmware(fw);
850
851         if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
852                 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
853                          csb_readl(tegra, XUSB_FALC_CPUCTL));
854                 return 0;
855         }
856
857         /* Program the size of DFI into ILOAD_ATTR. */
858         csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
859
860         /*
861          * Boot code of the firmware reads the ILOAD_BASE registers
862          * to get to the start of the DFI in system memory.
863          */
864         address = tegra->fw.phys + sizeof(*header);
865         csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
866         csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
867
868         /* Set BOOTPATH to 1 in APMAP. */
869         csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
870
871         /* Invalidate L2IMEM. */
872         csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
873
874         /*
875          * Initiate fetch of bootcode from system memory into L2IMEM.
876          * Program bootcode location and size in system memory.
877          */
878         code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
879                                        IMEM_BLOCK_SIZE);
880         code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
881                                         IMEM_BLOCK_SIZE);
882         code_blocks = code_tag_blocks + code_size_blocks;
883
884         value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
885                         L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
886                 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
887                         L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
888         csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
889
890         /* Trigger L2IMEM load operation. */
891         csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
892                    XUSB_CSB_MP_L2IMEMOP_TRIG);
893
894         /* Setup Falcon auto-fill. */
895         csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
896
897         value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
898                         IMFILLRNG1_TAG_LO_SHIFT) |
899                 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
900                         IMFILLRNG1_TAG_HI_SHIFT);
901         csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
902
903         csb_writel(tegra, 0, XUSB_FALC_DMACTL);
904
905         msleep(50);
906
907         csb_writel(tegra, le32_to_cpu(header->boot_codetag),
908                    XUSB_FALC_BOOTVEC);
909
910         /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
911         timeout = jiffies + msecs_to_jiffies(5);
912
913         csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
914
915         while (time_before(jiffies, timeout)) {
916                 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
917                         break;
918
919                 usleep_range(100, 200);
920         }
921
922         if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
923                 dev_err(dev, "Falcon failed to start, state: %#x\n",
924                         csb_readl(tegra, XUSB_FALC_CPUCTL));
925                 return -EIO;
926         }
927
928         timestamp = le32_to_cpu(header->fwimg_created_time);
929         time64_to_tm(timestamp, 0, &time);
930
931         dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
932                  time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
933                  time.tm_hour, time.tm_min, time.tm_sec);
934
935         return 0;
936 }
937
938 static int tegra_xusb_probe(struct platform_device *pdev)
939 {
940         struct tegra_xusb_mbox_msg msg;
941         struct resource *res, *regs;
942         struct tegra_xusb *tegra;
943         struct xhci_hcd *xhci;
944         unsigned int i, j, k;
945         struct phy *phy;
946         int err;
947
948         BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
949
950         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
951         if (!tegra)
952                 return -ENOMEM;
953
954         tegra->soc = of_device_get_match_data(&pdev->dev);
955         mutex_init(&tegra->lock);
956         tegra->dev = &pdev->dev;
957
958         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
959         tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
960         if (IS_ERR(tegra->regs))
961                 return PTR_ERR(tegra->regs);
962
963         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
964         tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res);
965         if (IS_ERR(tegra->fpci_base))
966                 return PTR_ERR(tegra->fpci_base);
967
968         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
969         tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
970         if (IS_ERR(tegra->ipfs_base))
971                 return PTR_ERR(tegra->ipfs_base);
972
973         tegra->xhci_irq = platform_get_irq(pdev, 0);
974         if (tegra->xhci_irq < 0)
975                 return tegra->xhci_irq;
976
977         tegra->mbox_irq = platform_get_irq(pdev, 1);
978         if (tegra->mbox_irq < 0)
979                 return tegra->mbox_irq;
980
981         tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
982         if (IS_ERR(tegra->padctl))
983                 return PTR_ERR(tegra->padctl);
984
985         tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
986         if (IS_ERR(tegra->host_clk)) {
987                 err = PTR_ERR(tegra->host_clk);
988                 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
989                 goto put_padctl;
990         }
991
992         tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
993         if (IS_ERR(tegra->falcon_clk)) {
994                 err = PTR_ERR(tegra->falcon_clk);
995                 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
996                 goto put_padctl;
997         }
998
999         tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1000         if (IS_ERR(tegra->ss_clk)) {
1001                 err = PTR_ERR(tegra->ss_clk);
1002                 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1003                 goto put_padctl;
1004         }
1005
1006         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1007         if (IS_ERR(tegra->ss_src_clk)) {
1008                 err = PTR_ERR(tegra->ss_src_clk);
1009                 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1010                 goto put_padctl;
1011         }
1012
1013         tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1014         if (IS_ERR(tegra->hs_src_clk)) {
1015                 err = PTR_ERR(tegra->hs_src_clk);
1016                 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1017                 goto put_padctl;
1018         }
1019
1020         tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1021         if (IS_ERR(tegra->fs_src_clk)) {
1022                 err = PTR_ERR(tegra->fs_src_clk);
1023                 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1024                 goto put_padctl;
1025         }
1026
1027         tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1028         if (IS_ERR(tegra->pll_u_480m)) {
1029                 err = PTR_ERR(tegra->pll_u_480m);
1030                 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1031                 goto put_padctl;
1032         }
1033
1034         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1035         if (IS_ERR(tegra->clk_m)) {
1036                 err = PTR_ERR(tegra->clk_m);
1037                 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1038                 goto put_padctl;
1039         }
1040
1041         tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1042         if (IS_ERR(tegra->pll_e)) {
1043                 err = PTR_ERR(tegra->pll_e);
1044                 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1045                 goto put_padctl;
1046         }
1047
1048         if (!pdev->dev.pm_domain) {
1049                 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1050                                                          "xusb_host");
1051                 if (IS_ERR(tegra->host_rst)) {
1052                         err = PTR_ERR(tegra->host_rst);
1053                         dev_err(&pdev->dev,
1054                                 "failed to get xusb_host reset: %d\n", err);
1055                         goto put_padctl;
1056                 }
1057
1058                 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1059                 if (IS_ERR(tegra->ss_rst)) {
1060                         err = PTR_ERR(tegra->ss_rst);
1061                         dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1062                                 err);
1063                         goto put_padctl;
1064                 }
1065
1066                 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1067                                                         tegra->ss_clk,
1068                                                         tegra->ss_rst);
1069                 if (err) {
1070                         dev_err(&pdev->dev,
1071                                 "failed to enable XUSBA domain: %d\n", err);
1072                         goto put_padctl;
1073                 }
1074
1075                 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1076                                                         tegra->host_clk,
1077                                                         tegra->host_rst);
1078                 if (err) {
1079                         dev_err(&pdev->dev,
1080                                 "failed to enable XUSBC domain: %d\n", err);
1081                         goto disable_xusba;
1082                 }
1083         }
1084
1085         tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1086                                        sizeof(*tegra->supplies), GFP_KERNEL);
1087         if (!tegra->supplies) {
1088                 err = -ENOMEM;
1089                 goto disable_xusbc;
1090         }
1091
1092         for (i = 0; i < tegra->soc->num_supplies; i++)
1093                 tegra->supplies[i].supply = tegra->soc->supply_names[i];
1094
1095         err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1096                                       tegra->supplies);
1097         if (err) {
1098                 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1099                 goto disable_xusbc;
1100         }
1101
1102         for (i = 0; i < tegra->soc->num_types; i++)
1103                 tegra->num_phys += tegra->soc->phy_types[i].num;
1104
1105         tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1106                                    sizeof(*tegra->phys), GFP_KERNEL);
1107         if (!tegra->phys) {
1108                 err = -ENOMEM;
1109                 goto disable_xusbc;
1110         }
1111
1112         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1113                 char prop[8];
1114
1115                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1116                         snprintf(prop, sizeof(prop), "%s-%d",
1117                                  tegra->soc->phy_types[i].name, j);
1118
1119                         phy = devm_phy_optional_get(&pdev->dev, prop);
1120                         if (IS_ERR(phy)) {
1121                                 dev_err(&pdev->dev,
1122                                         "failed to get PHY %s: %ld\n", prop,
1123                                         PTR_ERR(phy));
1124                                 err = PTR_ERR(phy);
1125                                 goto disable_xusbc;
1126                         }
1127
1128                         tegra->phys[k++] = phy;
1129                 }
1130         }
1131
1132         tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1133                                     dev_name(&pdev->dev));
1134         if (!tegra->hcd) {
1135                 err = -ENOMEM;
1136                 goto disable_xusbc;
1137         }
1138
1139         /*
1140          * This must happen after usb_create_hcd(), because usb_create_hcd()
1141          * will overwrite the drvdata of the device with the hcd it creates.
1142          */
1143         platform_set_drvdata(pdev, tegra);
1144
1145         pm_runtime_enable(&pdev->dev);
1146         if (pm_runtime_enabled(&pdev->dev))
1147                 err = pm_runtime_get_sync(&pdev->dev);
1148         else
1149                 err = tegra_xusb_runtime_resume(&pdev->dev);
1150
1151         if (err < 0) {
1152                 dev_err(&pdev->dev, "failed to enable device: %d\n", err);
1153                 goto disable_rpm;
1154         }
1155
1156         tegra_xusb_ipfs_config(tegra, regs);
1157
1158         /*
1159          * The XUSB Falcon microcontroller can only address 40 bits, so set
1160          * the DMA mask accordingly.
1161          */
1162         err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1163         if (err < 0) {
1164                 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1165                 goto put_rpm;
1166         }
1167
1168         err = tegra_xusb_load_firmware(tegra);
1169         if (err < 0) {
1170                 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1171                 goto put_rpm;
1172         }
1173
1174         tegra->hcd->regs = tegra->regs;
1175         tegra->hcd->rsrc_start = regs->start;
1176         tegra->hcd->rsrc_len = resource_size(regs);
1177
1178         err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1179         if (err < 0) {
1180                 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1181                 goto put_rpm;
1182         }
1183
1184         device_wakeup_enable(tegra->hcd->self.controller);
1185
1186         xhci = hcd_to_xhci(tegra->hcd);
1187
1188         xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1189                                                  &pdev->dev,
1190                                                  dev_name(&pdev->dev),
1191                                                  tegra->hcd);
1192         if (!xhci->shared_hcd) {
1193                 dev_err(&pdev->dev, "failed to create shared HCD\n");
1194                 err = -ENOMEM;
1195                 goto remove_usb2;
1196         }
1197
1198         err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1199         if (err < 0) {
1200                 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1201                 goto put_usb3;
1202         }
1203
1204         mutex_lock(&tegra->lock);
1205
1206         /* Enable firmware messages from controller. */
1207         msg.cmd = MBOX_CMD_MSG_ENABLED;
1208         msg.data = 0;
1209
1210         err = tegra_xusb_mbox_send(tegra, &msg);
1211         if (err < 0) {
1212                 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1213                 mutex_unlock(&tegra->lock);
1214                 goto remove_usb3;
1215         }
1216
1217         mutex_unlock(&tegra->lock);
1218
1219         err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1220                                         tegra_xusb_mbox_irq,
1221                                         tegra_xusb_mbox_thread, 0,
1222                                         dev_name(&pdev->dev), tegra);
1223         if (err < 0) {
1224                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1225                 goto remove_usb3;
1226         }
1227
1228         return 0;
1229
1230 remove_usb3:
1231         usb_remove_hcd(xhci->shared_hcd);
1232 put_usb3:
1233         usb_put_hcd(xhci->shared_hcd);
1234 remove_usb2:
1235         usb_remove_hcd(tegra->hcd);
1236 put_rpm:
1237         if (!pm_runtime_status_suspended(&pdev->dev))
1238                 tegra_xusb_runtime_suspend(&pdev->dev);
1239 disable_rpm:
1240         pm_runtime_disable(&pdev->dev);
1241         usb_put_hcd(tegra->hcd);
1242 disable_xusbc:
1243         if (!pdev->dev.pm_domain)
1244                 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1245 disable_xusba:
1246         if (!pdev->dev.pm_domain)
1247                 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1248 put_padctl:
1249         tegra_xusb_padctl_put(tegra->padctl);
1250         return err;
1251 }
1252
1253 static int tegra_xusb_remove(struct platform_device *pdev)
1254 {
1255         struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1256         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1257
1258         usb_remove_hcd(xhci->shared_hcd);
1259         usb_put_hcd(xhci->shared_hcd);
1260         xhci->shared_hcd = NULL;
1261         usb_remove_hcd(tegra->hcd);
1262         usb_put_hcd(tegra->hcd);
1263
1264         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1265                           tegra->fw.phys);
1266
1267         pm_runtime_put_sync(&pdev->dev);
1268         pm_runtime_disable(&pdev->dev);
1269
1270         tegra_xusb_padctl_put(tegra->padctl);
1271
1272         return 0;
1273 }
1274
1275 #ifdef CONFIG_PM_SLEEP
1276 static int tegra_xusb_suspend(struct device *dev)
1277 {
1278         struct tegra_xusb *tegra = dev_get_drvdata(dev);
1279         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1280         bool wakeup = device_may_wakeup(dev);
1281
1282         /* TODO: Powergate controller across suspend/resume. */
1283         return xhci_suspend(xhci, wakeup);
1284 }
1285
1286 static int tegra_xusb_resume(struct device *dev)
1287 {
1288         struct tegra_xusb *tegra = dev_get_drvdata(dev);
1289         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1290
1291         return xhci_resume(xhci, 0);
1292 }
1293 #endif
1294
1295 static const struct dev_pm_ops tegra_xusb_pm_ops = {
1296         SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
1297                            tegra_xusb_runtime_resume, NULL)
1298         SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1299 };
1300
1301 static const char * const tegra124_supply_names[] = {
1302         "avddio-pex",
1303         "dvddio-pex",
1304         "avdd-usb",
1305         "avdd-pll-utmip",
1306         "avdd-pll-erefe",
1307         "avdd-usb-ss-pll",
1308         "hvdd-usb-ss",
1309         "hvdd-usb-ss-pll-e",
1310 };
1311
1312 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1313         { .name = "usb3", .num = 2, },
1314         { .name = "usb2", .num = 3, },
1315         { .name = "hsic", .num = 2, },
1316 };
1317
1318 static const struct tegra_xusb_soc tegra124_soc = {
1319         .firmware = "/*(DEBLOBBED)*/",
1320         .supply_names = tegra124_supply_names,
1321         .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1322         .phy_types = tegra124_phy_types,
1323         .num_types = ARRAY_SIZE(tegra124_phy_types),
1324         .ports = {
1325                 .usb2 = { .offset = 4, .count = 4, },
1326                 .hsic = { .offset = 6, .count = 2, },
1327                 .usb3 = { .offset = 0, .count = 2, },
1328         },
1329         .scale_ss_clock = true,
1330 };
1331 /*(DEBLOBBED)*/
1332
1333 static const char * const tegra210_supply_names[] = {
1334         "dvddio-pex",
1335         "hvddio-pex",
1336         "avdd-usb",
1337         "avdd-pll-utmip",
1338         "avdd-pll-uerefe",
1339         "dvdd-pex-pll",
1340         "hvdd-pex-pll-e",
1341 };
1342
1343 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1344         { .name = "usb3", .num = 4, },
1345         { .name = "usb2", .num = 4, },
1346         { .name = "hsic", .num = 1, },
1347 };
1348
1349 static const struct tegra_xusb_soc tegra210_soc = {
1350         .firmware = "/*(DEBLOBBED)*/",
1351         .supply_names = tegra210_supply_names,
1352         .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1353         .phy_types = tegra210_phy_types,
1354         .num_types = ARRAY_SIZE(tegra210_phy_types),
1355         .ports = {
1356                 .usb2 = { .offset = 4, .count = 4, },
1357                 .hsic = { .offset = 8, .count = 1, },
1358                 .usb3 = { .offset = 0, .count = 4, },
1359         },
1360         .scale_ss_clock = false,
1361 };
1362 /*(DEBLOBBED)*/
1363
1364 static const struct of_device_id tegra_xusb_of_match[] = {
1365         { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
1366         { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
1367         { },
1368 };
1369 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1370
1371 static struct platform_driver tegra_xusb_driver = {
1372         .probe = tegra_xusb_probe,
1373         .remove = tegra_xusb_remove,
1374         .driver = {
1375                 .name = "tegra-xusb",
1376                 .pm = &tegra_xusb_pm_ops,
1377                 .of_match_table = tegra_xusb_of_match,
1378         },
1379 };
1380
1381 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1382 {
1383         xhci->quirks |= XHCI_PLAT;
1384 }
1385
1386 static int tegra_xhci_setup(struct usb_hcd *hcd)
1387 {
1388         return xhci_gen_setup(hcd, tegra_xhci_quirks);
1389 }
1390
1391 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
1392         .reset = tegra_xhci_setup,
1393 };
1394
1395 static int __init tegra_xusb_init(void)
1396 {
1397         xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1398
1399         return platform_driver_register(&tegra_xusb_driver);
1400 }
1401 module_init(tegra_xusb_init);
1402
1403 static void __exit tegra_xusb_exit(void)
1404 {
1405         platform_driver_unregister(&tegra_xusb_driver);
1406 }
1407 module_exit(tegra_xusb_exit);
1408
1409 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1410 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1411 MODULE_LICENSE("GPL v2");