2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/iopoll.h>
25 #include <linux/irq.h>
26 #include <linux/log2.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/slab.h>
30 #include <linux/dmi.h>
31 #include <linux/dma-mapping.h>
34 #include "xhci-trace.h"
37 #define DRIVER_AUTHOR "Sarah Sharp"
38 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
40 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
42 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
43 static int link_quirk;
44 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
47 static unsigned int quirks;
48 module_param(quirks, uint, S_IRUGO);
49 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
69 ret = readl_poll_timeout_atomic(ptr, result,
70 (result & mask) == done ||
73 if (result == U32_MAX) /* card removed */
80 * Disable interrupts and begin the xHCI halting process.
82 void xhci_quiesce(struct xhci_hcd *xhci)
89 halted = readl(&xhci->op_regs->status) & STS_HALT;
93 cmd = readl(&xhci->op_regs->command);
95 writel(cmd, &xhci->op_regs->command);
99 * Force HC into halt state.
101 * Disable any IRQs and clear the run/stop bit.
102 * HC will complete any current and actively pipelined transactions, and
103 * should halt within 16 ms of the run/stop bit being cleared.
104 * Read HC Halted bit in the status register to see when the HC is finished.
106 int xhci_halt(struct xhci_hcd *xhci)
109 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
112 ret = xhci_handshake(&xhci->op_regs->status,
113 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
115 xhci->xhc_state |= XHCI_STATE_HALTED;
116 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
118 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
124 * Set the run bit and wait for the host to be running.
126 static int xhci_start(struct xhci_hcd *xhci)
131 temp = readl(&xhci->op_regs->command);
133 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
135 writel(temp, &xhci->op_regs->command);
138 * Wait for the HCHalted Status bit to be 0 to indicate the host is
141 ret = xhci_handshake(&xhci->op_regs->status,
142 STS_HALT, 0, XHCI_MAX_HALT_USEC);
143 if (ret == -ETIMEDOUT)
144 xhci_err(xhci, "Host took too long to start, "
145 "waited %u microseconds.\n",
148 /* clear state flags. Including dying, halted or removing */
157 * This resets pipelines, timers, counters, state machines, etc.
158 * Transactions will be terminated immediately, and operational registers
159 * will be set to their defaults.
161 int xhci_reset(struct xhci_hcd *xhci)
167 state = readl(&xhci->op_regs->status);
168 if ((state & STS_HALT) == 0) {
169 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
173 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
174 command = readl(&xhci->op_regs->command);
175 command |= CMD_RESET;
176 writel(command, &xhci->op_regs->command);
178 /* Existing Intel xHCI controllers require a delay of 1 mS,
179 * after setting the CMD_RESET bit, and before accessing any
180 * HC registers. This allows the HC to complete the
181 * reset operation and be ready for HC register access.
182 * Without this delay, the subsequent HC register access,
183 * may result in a system hang very rarely.
185 if (xhci->quirks & XHCI_INTEL_HOST)
188 ret = xhci_handshake(&xhci->op_regs->command,
189 CMD_RESET, 0, 10 * 1000 * 1000);
193 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
194 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
196 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
197 "Wait for controller to be ready for doorbell rings");
199 * xHCI cannot write to any doorbells or operational registers other
200 * than status until the "Controller Not Ready" flag is cleared.
202 ret = xhci_handshake(&xhci->op_regs->status,
203 STS_CNR, 0, 10 * 1000 * 1000);
205 for (i = 0; i < 2; ++i) {
206 xhci->bus_state[i].port_c_suspend = 0;
207 xhci->bus_state[i].suspended_ports = 0;
208 xhci->bus_state[i].resuming_ports = 0;
215 static int xhci_free_msi(struct xhci_hcd *xhci)
219 if (!xhci->msix_entries)
222 for (i = 0; i < xhci->msix_count; i++)
223 if (xhci->msix_entries[i].vector)
224 free_irq(xhci->msix_entries[i].vector,
232 static int xhci_setup_msi(struct xhci_hcd *xhci)
235 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
237 ret = pci_enable_msi(pdev);
239 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
240 "failed to allocate MSI entry");
244 ret = request_irq(pdev->irq, xhci_msi_irq,
245 0, "xhci_hcd", xhci_to_hcd(xhci));
247 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
248 "disable MSI interrupt");
249 pci_disable_msi(pdev);
257 * free all IRQs request
259 static void xhci_free_irq(struct xhci_hcd *xhci)
261 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
264 /* return if using legacy interrupt */
265 if (xhci_to_hcd(xhci)->irq > 0)
268 ret = xhci_free_msi(xhci);
272 free_irq(pdev->irq, xhci_to_hcd(xhci));
280 static int xhci_setup_msix(struct xhci_hcd *xhci)
283 struct usb_hcd *hcd = xhci_to_hcd(xhci);
284 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
287 * calculate number of msi-x vectors supported.
288 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
289 * with max number of interrupters based on the xhci HCSPARAMS1.
290 * - num_online_cpus: maximum msi-x vectors per CPUs core.
291 * Add additional 1 vector to ensure always available interrupt.
293 xhci->msix_count = min(num_online_cpus() + 1,
294 HCS_MAX_INTRS(xhci->hcs_params1));
297 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
299 if (!xhci->msix_entries)
302 for (i = 0; i < xhci->msix_count; i++) {
303 xhci->msix_entries[i].entry = i;
304 xhci->msix_entries[i].vector = 0;
307 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
309 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
310 "Failed to enable MSI-X");
314 for (i = 0; i < xhci->msix_count; i++) {
315 ret = request_irq(xhci->msix_entries[i].vector,
317 0, "xhci_hcd", xhci_to_hcd(xhci));
322 hcd->msix_enabled = 1;
326 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
328 pci_disable_msix(pdev);
330 kfree(xhci->msix_entries);
331 xhci->msix_entries = NULL;
335 /* Free any IRQs and disable MSI-X */
336 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
338 struct usb_hcd *hcd = xhci_to_hcd(xhci);
339 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
341 if (xhci->quirks & XHCI_PLAT)
346 if (xhci->msix_entries) {
347 pci_disable_msix(pdev);
348 kfree(xhci->msix_entries);
349 xhci->msix_entries = NULL;
351 pci_disable_msi(pdev);
354 hcd->msix_enabled = 0;
358 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
362 if (xhci->msix_entries) {
363 for (i = 0; i < xhci->msix_count; i++)
364 synchronize_irq(xhci->msix_entries[i].vector);
368 static int xhci_try_enable_msi(struct usb_hcd *hcd)
370 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
371 struct pci_dev *pdev;
374 /* The xhci platform device has set up IRQs through usb_add_hcd. */
375 if (xhci->quirks & XHCI_PLAT)
378 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
380 * Some Fresco Logic host controllers advertise MSI, but fail to
381 * generate interrupts. Don't even try to enable MSI.
383 if (xhci->quirks & XHCI_BROKEN_MSI)
386 /* unregister the legacy interrupt */
388 free_irq(hcd->irq, hcd);
391 ret = xhci_setup_msix(xhci);
393 /* fall back to msi*/
394 ret = xhci_setup_msi(xhci);
397 /* hcd->irq is 0, we have MSI */
401 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
406 if (!strlen(hcd->irq_descr))
407 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
408 hcd->driver->description, hcd->self.busnum);
410 /* fall back to legacy interrupt*/
411 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
412 hcd->irq_descr, hcd);
414 xhci_err(xhci, "request interrupt %d failed\n",
418 hcd->irq = pdev->irq;
424 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
429 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
433 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
439 static void compliance_mode_recovery(unsigned long arg)
441 struct xhci_hcd *xhci;
446 xhci = (struct xhci_hcd *)arg;
448 for (i = 0; i < xhci->num_usb3_ports; i++) {
449 temp = readl(xhci->usb3_ports[i]);
450 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
452 * Compliance Mode Detected. Letting USB Core
453 * handle the Warm Reset
455 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
456 "Compliance mode detected->port %d",
458 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
459 "Attempting compliance mode recovery");
460 hcd = xhci->shared_hcd;
462 if (hcd->state == HC_STATE_SUSPENDED)
463 usb_hcd_resume_root_hub(hcd);
465 usb_hcd_poll_rh_status(hcd);
469 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
470 mod_timer(&xhci->comp_mode_recovery_timer,
471 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
475 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
476 * that causes ports behind that hardware to enter compliance mode sometimes.
477 * The quirk creates a timer that polls every 2 seconds the link state of
478 * each host controller's port and recovers it by issuing a Warm reset
479 * if Compliance mode is detected, otherwise the port will become "dead" (no
480 * device connections or disconnections will be detected anymore). Becasue no
481 * status event is generated when entering compliance mode (per xhci spec),
482 * this quirk is needed on systems that have the failing hardware installed.
484 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
486 xhci->port_status_u0 = 0;
487 setup_timer(&xhci->comp_mode_recovery_timer,
488 compliance_mode_recovery, (unsigned long)xhci);
489 xhci->comp_mode_recovery_timer.expires = jiffies +
490 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
492 add_timer(&xhci->comp_mode_recovery_timer);
493 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
494 "Compliance mode recovery timer initialized");
498 * This function identifies the systems that have installed the SN65LVPE502CP
499 * USB3.0 re-driver and that need the Compliance Mode Quirk.
501 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
503 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
505 const char *dmi_product_name, *dmi_sys_vendor;
507 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
508 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
509 if (!dmi_product_name || !dmi_sys_vendor)
512 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
515 if (strstr(dmi_product_name, "Z420") ||
516 strstr(dmi_product_name, "Z620") ||
517 strstr(dmi_product_name, "Z820") ||
518 strstr(dmi_product_name, "Z1 Workstation"))
524 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
526 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
531 * Initialize memory for HCD and xHC (one-time init).
533 * Program the PAGESIZE register, initialize the device context array, create
534 * device contexts (?), set up a command ring segment (or two?), create event
535 * ring (one for now).
537 int xhci_init(struct usb_hcd *hcd)
539 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
542 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
543 spin_lock_init(&xhci->lock);
544 if (xhci->hci_version == 0x95 && link_quirk) {
545 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
546 "QUIRK: Not clearing Link TRB chain bits.");
547 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
549 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
550 "xHCI doesn't need link TRB QUIRK");
552 retval = xhci_mem_init(xhci, GFP_KERNEL);
553 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
555 /* Initializing Compliance Mode Recovery Data If Needed */
556 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
557 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
558 compliance_mode_recovery_timer_init(xhci);
564 /*-------------------------------------------------------------------------*/
567 static int xhci_run_finished(struct xhci_hcd *xhci)
569 if (xhci_start(xhci)) {
573 xhci->shared_hcd->state = HC_STATE_RUNNING;
574 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
576 if (xhci->quirks & XHCI_NEC_HOST)
577 xhci_ring_cmd_db(xhci);
579 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
580 "Finished xhci_run for USB3 roothub");
585 * Start the HC after it was halted.
587 * This function is called by the USB core when the HC driver is added.
588 * Its opposite is xhci_stop().
590 * xhci_init() must be called once before this function can be called.
591 * Reset the HC, enable device slot contexts, program DCBAAP, and
592 * set command ring pointer and event ring pointer.
594 * Setup MSI-X vectors and enable interrupts.
596 int xhci_run(struct usb_hcd *hcd)
601 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
603 /* Start the xHCI host controller running only after the USB 2.0 roothub
607 hcd->uses_new_polling = 1;
608 if (!usb_hcd_is_primary_hcd(hcd))
609 return xhci_run_finished(xhci);
611 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
613 ret = xhci_try_enable_msi(hcd);
617 xhci_dbg(xhci, "Command ring memory map follows:\n");
618 xhci_debug_ring(xhci, xhci->cmd_ring);
619 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
620 xhci_dbg_cmd_ptrs(xhci);
622 xhci_dbg(xhci, "ERST memory map follows:\n");
623 xhci_dbg_erst(xhci, &xhci->erst);
624 xhci_dbg(xhci, "Event ring:\n");
625 xhci_debug_ring(xhci, xhci->event_ring);
626 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
627 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
628 temp_64 &= ~ERST_PTR_MASK;
629 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
630 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
632 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
633 "// Set the interrupt modulation register");
634 temp = readl(&xhci->ir_set->irq_control);
635 temp &= ~ER_IRQ_INTERVAL_MASK;
637 * the increment interval is 8 times as much as that defined
638 * in xHCI spec on MTK's controller
640 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
641 writel(temp, &xhci->ir_set->irq_control);
643 /* Set the HCD state before we enable the irqs */
644 temp = readl(&xhci->op_regs->command);
646 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
647 "// Enable interrupts, cmd = 0x%x.", temp);
648 writel(temp, &xhci->op_regs->command);
650 temp = readl(&xhci->ir_set->irq_pending);
651 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
652 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
653 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
654 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
655 xhci_print_ir_set(xhci, 0);
657 if (xhci->quirks & XHCI_NEC_HOST) {
658 struct xhci_command *command;
659 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
662 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
663 TRB_TYPE(TRB_NEC_GET_FW));
665 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
666 "Finished xhci_run for USB2 roothub");
669 EXPORT_SYMBOL_GPL(xhci_run);
674 * This function is called by the USB core when the HC driver is removed.
675 * Its opposite is xhci_run().
677 * Disable device contexts, disable IRQs, and quiesce the HC.
678 * Reset the HC, finish any completed transactions, and cleanup memory.
680 void xhci_stop(struct usb_hcd *hcd)
683 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
685 mutex_lock(&xhci->mutex);
687 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
688 spin_lock_irq(&xhci->lock);
690 xhci->xhc_state |= XHCI_STATE_HALTED;
691 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
695 spin_unlock_irq(&xhci->lock);
698 if (!usb_hcd_is_primary_hcd(hcd)) {
699 mutex_unlock(&xhci->mutex);
703 xhci_cleanup_msix(xhci);
705 /* Deleting Compliance Mode Recovery Timer */
706 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
707 (!(xhci_all_ports_seen_u0(xhci)))) {
708 del_timer_sync(&xhci->comp_mode_recovery_timer);
709 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
710 "%s: compliance mode recovery timer deleted",
714 if (xhci->quirks & XHCI_AMD_PLL_FIX)
717 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
718 "// Disabling event ring interrupts");
719 temp = readl(&xhci->op_regs->status);
720 writel(temp & ~STS_EINT, &xhci->op_regs->status);
721 temp = readl(&xhci->ir_set->irq_pending);
722 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
723 xhci_print_ir_set(xhci, 0);
725 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
726 xhci_mem_cleanup(xhci);
727 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
728 "xhci_stop completed - status = %x",
729 readl(&xhci->op_regs->status));
730 mutex_unlock(&xhci->mutex);
734 * Shutdown HC (not bus-specific)
736 * This is called when the machine is rebooting or halting. We assume that the
737 * machine will be powered off, and the HC's internal state will be reset.
738 * Don't bother to free memory.
740 * This will only ever be called with the main usb_hcd (the USB3 roothub).
742 void xhci_shutdown(struct usb_hcd *hcd)
744 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
746 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
747 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
749 spin_lock_irq(&xhci->lock);
751 /* Workaround for spurious wakeups at shutdown with HSW */
752 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
754 spin_unlock_irq(&xhci->lock);
756 xhci_cleanup_msix(xhci);
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_shutdown completed - status = %x",
760 readl(&xhci->op_regs->status));
762 EXPORT_SYMBOL_GPL(xhci_shutdown);
765 static void xhci_save_registers(struct xhci_hcd *xhci)
767 xhci->s3.command = readl(&xhci->op_regs->command);
768 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
769 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
770 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
771 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
772 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
773 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
774 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
775 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
778 static void xhci_restore_registers(struct xhci_hcd *xhci)
780 writel(xhci->s3.command, &xhci->op_regs->command);
781 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
782 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
783 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
784 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
785 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
786 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
787 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
788 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
791 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
795 /* step 2: initialize command ring buffer */
796 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
797 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
798 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
799 xhci->cmd_ring->dequeue) &
800 (u64) ~CMD_RING_RSVD_BITS) |
801 xhci->cmd_ring->cycle_state;
802 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
803 "// Setting command ring address to 0x%llx",
804 (long unsigned long) val_64);
805 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
809 * The whole command ring must be cleared to zero when we suspend the host.
811 * The host doesn't save the command ring pointer in the suspend well, so we
812 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
813 * aligned, because of the reserved bits in the command ring dequeue pointer
814 * register. Therefore, we can't just set the dequeue pointer back in the
815 * middle of the ring (TRBs are 16-byte aligned).
817 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
819 struct xhci_ring *ring;
820 struct xhci_segment *seg;
822 ring = xhci->cmd_ring;
826 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
827 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
828 cpu_to_le32(~TRB_CYCLE);
830 } while (seg != ring->deq_seg);
832 /* Reset the software enqueue and dequeue pointers */
833 ring->deq_seg = ring->first_seg;
834 ring->dequeue = ring->first_seg->trbs;
835 ring->enq_seg = ring->deq_seg;
836 ring->enqueue = ring->dequeue;
838 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
840 * Ring is now zeroed, so the HW should look for change of ownership
841 * when the cycle bit is set to 1.
843 ring->cycle_state = 1;
846 * Reset the hardware dequeue pointer.
847 * Yes, this will need to be re-written after resume, but we're paranoid
848 * and want to make sure the hardware doesn't access bogus memory
849 * because, say, the BIOS or an SMI started the host without changing
850 * the command ring pointers.
852 xhci_set_cmd_ring_deq(xhci);
855 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
858 __le32 __iomem **port_array;
862 spin_lock_irqsave(&xhci->lock, flags);
864 /* disble usb3 ports Wake bits*/
865 port_index = xhci->num_usb3_ports;
866 port_array = xhci->usb3_ports;
867 while (port_index--) {
868 t1 = readl(port_array[port_index]);
869 t1 = xhci_port_state_to_neutral(t1);
870 t2 = t1 & ~PORT_WAKE_BITS;
872 writel(t2, port_array[port_index]);
875 /* disble usb2 ports Wake bits*/
876 port_index = xhci->num_usb2_ports;
877 port_array = xhci->usb2_ports;
878 while (port_index--) {
879 t1 = readl(port_array[port_index]);
880 t1 = xhci_port_state_to_neutral(t1);
881 t2 = t1 & ~PORT_WAKE_BITS;
883 writel(t2, port_array[port_index]);
886 spin_unlock_irqrestore(&xhci->lock, flags);
889 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
891 __le32 __iomem **port_array;
896 status = readl(&xhci->op_regs->status);
897 if (status & STS_EINT)
900 * Checking STS_EINT is not enough as there is a lag between a change
901 * bit being set and the Port Status Change Event that it generated
902 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
905 port_index = xhci->num_usb2_ports;
906 port_array = xhci->usb2_ports;
907 while (port_index--) {
908 portsc = readl(port_array[port_index]);
909 if (portsc & PORT_CHANGE_MASK ||
910 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
913 port_index = xhci->num_usb3_ports;
914 port_array = xhci->usb3_ports;
915 while (port_index--) {
916 portsc = readl(port_array[port_index]);
917 if (portsc & PORT_CHANGE_MASK ||
918 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
925 * Stop HC (not bus-specific)
927 * This is called when the machine transition into S3/S4 mode.
930 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
933 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
934 struct usb_hcd *hcd = xhci_to_hcd(xhci);
940 if (hcd->state != HC_STATE_SUSPENDED ||
941 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
944 /* Clear root port wake on bits if wakeup not allowed. */
946 xhci_disable_port_wake_on_bits(xhci);
948 /* Don't poll the roothubs on bus suspend. */
949 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
950 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
951 del_timer_sync(&hcd->rh_timer);
952 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
953 del_timer_sync(&xhci->shared_hcd->rh_timer);
955 spin_lock_irq(&xhci->lock);
956 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
957 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
958 /* step 1: stop endpoint */
959 /* skipped assuming that port suspend has done */
961 /* step 2: clear Run/Stop bit */
962 command = readl(&xhci->op_regs->command);
964 writel(command, &xhci->op_regs->command);
966 /* Some chips from Fresco Logic need an extraordinary delay */
967 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
969 if (xhci_handshake(&xhci->op_regs->status,
970 STS_HALT, STS_HALT, delay)) {
971 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
972 spin_unlock_irq(&xhci->lock);
975 xhci_clear_command_ring(xhci);
977 /* step 3: save registers */
978 xhci_save_registers(xhci);
980 /* step 4: set CSS flag */
981 command = readl(&xhci->op_regs->command);
983 writel(command, &xhci->op_regs->command);
984 if (xhci_handshake(&xhci->op_regs->status,
985 STS_SAVE, 0, 20 * 1000)) {
986 xhci_warn(xhci, "WARN: xHC save state timeout\n");
987 spin_unlock_irq(&xhci->lock);
990 spin_unlock_irq(&xhci->lock);
993 * Deleting Compliance Mode Recovery Timer because the xHCI Host
994 * is about to be suspended.
996 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
997 (!(xhci_all_ports_seen_u0(xhci)))) {
998 del_timer_sync(&xhci->comp_mode_recovery_timer);
999 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1000 "%s: compliance mode recovery timer deleted",
1004 /* step 5: remove core well power */
1005 /* synchronize irq when using MSI-X */
1006 xhci_msix_sync_irqs(xhci);
1010 EXPORT_SYMBOL_GPL(xhci_suspend);
1013 * start xHC (not bus-specific)
1015 * This is called when the machine transition from S3/S4 mode.
1018 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1020 u32 command, temp = 0;
1021 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1022 struct usb_hcd *secondary_hcd;
1024 bool comp_timer_running = false;
1025 bool pending_portevent = false;
1030 /* Wait a bit if either of the roothubs need to settle from the
1031 * transition into bus suspend.
1033 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1034 time_before(jiffies,
1035 xhci->bus_state[1].next_statechange))
1038 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1039 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1041 spin_lock_irq(&xhci->lock);
1042 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1047 * Some controllers might lose power during suspend, so wait
1048 * for controller not ready bit to clear, just as in xHC init.
1050 retval = xhci_handshake(&xhci->op_regs->status,
1051 STS_CNR, 0, 10 * 1000 * 1000);
1053 xhci_warn(xhci, "Controller not ready at resume %d\n",
1055 spin_unlock_irq(&xhci->lock);
1058 /* step 1: restore register */
1059 xhci_restore_registers(xhci);
1060 /* step 2: initialize command ring buffer */
1061 xhci_set_cmd_ring_deq(xhci);
1062 /* step 3: restore state and start state*/
1063 /* step 3: set CRS flag */
1064 command = readl(&xhci->op_regs->command);
1066 writel(command, &xhci->op_regs->command);
1068 * Some controllers take up to 55+ ms to complete the controller
1069 * restore so setting the timeout to 100ms. Xhci specification
1070 * doesn't mention any timeout value.
1072 if (xhci_handshake(&xhci->op_regs->status,
1073 STS_RESTORE, 0, 100 * 1000)) {
1074 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1075 spin_unlock_irq(&xhci->lock);
1078 temp = readl(&xhci->op_regs->status);
1081 /* If restore operation fails, re-initialize the HC during resume */
1082 if ((temp & STS_SRE) || hibernated) {
1084 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1085 !(xhci_all_ports_seen_u0(xhci))) {
1086 del_timer_sync(&xhci->comp_mode_recovery_timer);
1087 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1088 "Compliance Mode Recovery Timer deleted!");
1091 /* Let the USB core know _both_ roothubs lost power. */
1092 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1093 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1095 xhci_dbg(xhci, "Stop HCD\n");
1098 spin_unlock_irq(&xhci->lock);
1099 xhci_cleanup_msix(xhci);
1101 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1102 temp = readl(&xhci->op_regs->status);
1103 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1104 temp = readl(&xhci->ir_set->irq_pending);
1105 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1106 xhci_print_ir_set(xhci, 0);
1108 xhci_dbg(xhci, "cleaning up memory\n");
1109 xhci_mem_cleanup(xhci);
1110 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1111 readl(&xhci->op_regs->status));
1113 /* USB core calls the PCI reinit and start functions twice:
1114 * first with the primary HCD, and then with the secondary HCD.
1115 * If we don't do the same, the host will never be started.
1117 if (!usb_hcd_is_primary_hcd(hcd))
1118 secondary_hcd = hcd;
1120 secondary_hcd = xhci->shared_hcd;
1122 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1123 retval = xhci_init(hcd->primary_hcd);
1126 comp_timer_running = true;
1128 xhci_dbg(xhci, "Start the primary HCD\n");
1129 retval = xhci_run(hcd->primary_hcd);
1131 xhci_dbg(xhci, "Start the secondary HCD\n");
1132 retval = xhci_run(secondary_hcd);
1134 hcd->state = HC_STATE_SUSPENDED;
1135 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1139 /* step 4: set Run/Stop bit */
1140 command = readl(&xhci->op_regs->command);
1142 writel(command, &xhci->op_regs->command);
1143 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1146 /* step 5: walk topology and initialize portsc,
1147 * portpmsc and portli
1149 /* this is done in bus_resume */
1151 /* step 6: restart each of the previously
1152 * Running endpoints by ringing their doorbells
1155 spin_unlock_irq(&xhci->lock);
1160 * Resume roothubs only if there are pending events.
1161 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1162 * the first wake signalling failed, give it that chance.
1164 pending_portevent = xhci_pending_portevent(xhci);
1165 if (!pending_portevent) {
1167 pending_portevent = xhci_pending_portevent(xhci);
1170 if (pending_portevent) {
1171 usb_hcd_resume_root_hub(xhci->shared_hcd);
1172 usb_hcd_resume_root_hub(hcd);
1176 * If system is subject to the Quirk, Compliance Mode Timer needs to
1177 * be re-initialized Always after a system resume. Ports are subject
1178 * to suffer the Compliance Mode issue again. It doesn't matter if
1179 * ports have entered previously to U0 before system's suspension.
1181 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1182 compliance_mode_recovery_timer_init(xhci);
1184 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1185 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1187 /* Re-enable port polling. */
1188 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1189 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1190 usb_hcd_poll_rh_status(xhci->shared_hcd);
1191 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1192 usb_hcd_poll_rh_status(hcd);
1196 EXPORT_SYMBOL_GPL(xhci_resume);
1197 #endif /* CONFIG_PM */
1199 /*-------------------------------------------------------------------------*/
1202 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1203 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1204 * value to right shift 1 for the bitmask.
1206 * Index = (epnum * 2) + direction - 1,
1207 * where direction = 0 for OUT, 1 for IN.
1208 * For control endpoints, the IN index is used (OUT index is unused), so
1209 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1211 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1214 if (usb_endpoint_xfer_control(desc))
1215 index = (unsigned int) (usb_endpoint_num(desc)*2);
1217 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1218 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1222 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1223 * address from the XHCI endpoint index.
1225 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1227 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1228 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1229 return direction | number;
1232 /* Find the flag for this endpoint (for use in the control context). Use the
1233 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1236 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1238 return 1 << (xhci_get_endpoint_index(desc) + 1);
1241 /* Find the flag for this endpoint (for use in the control context). Use the
1242 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1245 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1247 return 1 << (ep_index + 1);
1250 /* Compute the last valid endpoint context index. Basically, this is the
1251 * endpoint index plus one. For slot contexts with more than valid endpoint,
1252 * we find the most significant bit set in the added contexts flags.
1253 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1254 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1256 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1258 return fls(added_ctxs) - 1;
1261 /* Returns 1 if the arguments are OK;
1262 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1264 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1265 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1267 struct xhci_hcd *xhci;
1268 struct xhci_virt_device *virt_dev;
1270 if (!hcd || (check_ep && !ep) || !udev) {
1271 pr_debug("xHCI %s called with invalid args\n", func);
1274 if (!udev->parent) {
1275 pr_debug("xHCI %s called for root hub\n", func);
1279 xhci = hcd_to_xhci(hcd);
1280 if (check_virt_dev) {
1281 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1282 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1287 virt_dev = xhci->devs[udev->slot_id];
1288 if (virt_dev->udev != udev) {
1289 xhci_dbg(xhci, "xHCI %s called with udev and "
1290 "virt_dev does not match\n", func);
1295 if (xhci->xhc_state & XHCI_STATE_HALTED)
1301 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1302 struct usb_device *udev, struct xhci_command *command,
1303 bool ctx_change, bool must_succeed);
1306 * Full speed devices may have a max packet size greater than 8 bytes, but the
1307 * USB core doesn't know that until it reads the first 8 bytes of the
1308 * descriptor. If the usb_device's max packet size changes after that point,
1309 * we need to issue an evaluate context command and wait on it.
1311 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1312 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1314 struct xhci_container_ctx *out_ctx;
1315 struct xhci_input_control_ctx *ctrl_ctx;
1316 struct xhci_ep_ctx *ep_ctx;
1317 struct xhci_command *command;
1318 int max_packet_size;
1319 int hw_max_packet_size;
1322 out_ctx = xhci->devs[slot_id]->out_ctx;
1323 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1324 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1325 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1326 if (hw_max_packet_size != max_packet_size) {
1327 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1328 "Max Packet Size for ep 0 changed.");
1329 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1330 "Max packet size in usb_device = %d",
1332 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1333 "Max packet size in xHCI HW = %d",
1334 hw_max_packet_size);
1335 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1336 "Issuing evaluate context command.");
1338 /* Set up the input context flags for the command */
1339 /* FIXME: This won't work if a non-default control endpoint
1340 * changes max packet sizes.
1343 command = xhci_alloc_command(xhci, false, true, mem_flags);
1347 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1348 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1350 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1353 goto command_cleanup;
1355 /* Set up the modified control endpoint 0 */
1356 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1357 xhci->devs[slot_id]->out_ctx, ep_index);
1359 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1360 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1361 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1362 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1364 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1365 ctrl_ctx->drop_flags = 0;
1367 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1368 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1369 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1370 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1372 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1375 /* Clean up the input context for later use by bandwidth
1378 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1380 kfree(command->completion);
1387 * non-error returns are a promise to giveback() the urb later
1388 * we drop ownership so next owner (or urb unlink) can get it
1390 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1392 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1393 struct xhci_td *buffer;
1394 unsigned long flags;
1396 unsigned int slot_id, ep_index;
1397 struct urb_priv *urb_priv;
1402 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1403 true, true, __func__);
1405 return ret ? ret : -EINVAL;
1407 slot_id = urb->dev->slot_id;
1408 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1410 if (!HCD_HW_ACCESSIBLE(hcd)) {
1411 if (!in_interrupt())
1412 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1417 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1418 size = urb->number_of_packets;
1419 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1420 urb->transfer_buffer_length > 0 &&
1421 urb->transfer_flags & URB_ZERO_PACKET &&
1422 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1427 urb_priv = kzalloc(sizeof(struct urb_priv) +
1428 size * sizeof(struct xhci_td *), mem_flags);
1432 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1438 for (i = 0; i < size; i++) {
1439 urb_priv->td[i] = buffer;
1443 urb_priv->length = size;
1444 urb_priv->td_cnt = 0;
1445 urb->hcpriv = urb_priv;
1447 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1448 /* Check to see if the max packet size for the default control
1449 * endpoint changed during FS device enumeration
1451 if (urb->dev->speed == USB_SPEED_FULL) {
1452 ret = xhci_check_maxpacket(xhci, slot_id,
1453 ep_index, urb, mem_flags);
1455 xhci_urb_free_priv(urb_priv);
1461 /* We have a spinlock and interrupts disabled, so we must pass
1462 * atomic context to this function, which may allocate memory.
1464 spin_lock_irqsave(&xhci->lock, flags);
1465 if (xhci->xhc_state & XHCI_STATE_DYING)
1467 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1471 spin_unlock_irqrestore(&xhci->lock, flags);
1472 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1473 spin_lock_irqsave(&xhci->lock, flags);
1474 if (xhci->xhc_state & XHCI_STATE_DYING)
1476 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1477 EP_GETTING_STREAMS) {
1478 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1479 "is transitioning to using streams.\n");
1481 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1482 EP_GETTING_NO_STREAMS) {
1483 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1484 "is transitioning to "
1485 "not having streams.\n");
1488 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1493 spin_unlock_irqrestore(&xhci->lock, flags);
1494 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1495 spin_lock_irqsave(&xhci->lock, flags);
1496 if (xhci->xhc_state & XHCI_STATE_DYING)
1498 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1502 spin_unlock_irqrestore(&xhci->lock, flags);
1504 spin_lock_irqsave(&xhci->lock, flags);
1505 if (xhci->xhc_state & XHCI_STATE_DYING)
1507 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1511 spin_unlock_irqrestore(&xhci->lock, flags);
1516 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1517 "non-responsive xHCI host.\n",
1518 urb->ep->desc.bEndpointAddress, urb);
1521 xhci_urb_free_priv(urb_priv);
1523 spin_unlock_irqrestore(&xhci->lock, flags);
1528 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1529 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1530 * should pick up where it left off in the TD, unless a Set Transfer Ring
1531 * Dequeue Pointer is issued.
1533 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1534 * the ring. Since the ring is a contiguous structure, they can't be physically
1535 * removed. Instead, there are two options:
1537 * 1) If the HC is in the middle of processing the URB to be canceled, we
1538 * simply move the ring's dequeue pointer past those TRBs using the Set
1539 * Transfer Ring Dequeue Pointer command. This will be the common case,
1540 * when drivers timeout on the last submitted URB and attempt to cancel.
1542 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1543 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1544 * HC will need to invalidate the any TRBs it has cached after the stop
1545 * endpoint command, as noted in the xHCI 0.95 errata.
1547 * 3) The TD may have completed by the time the Stop Endpoint Command
1548 * completes, so software needs to handle that case too.
1550 * This function should protect against the TD enqueueing code ringing the
1551 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1552 * It also needs to account for multiple cancellations on happening at the same
1553 * time for the same endpoint.
1555 * Note that this function can be called in any context, or so says
1556 * usb_hcd_unlink_urb()
1558 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1560 unsigned long flags;
1563 struct xhci_hcd *xhci;
1564 struct urb_priv *urb_priv;
1566 unsigned int ep_index;
1567 struct xhci_ring *ep_ring;
1568 struct xhci_virt_ep *ep;
1569 struct xhci_command *command;
1571 xhci = hcd_to_xhci(hcd);
1572 spin_lock_irqsave(&xhci->lock, flags);
1573 /* Make sure the URB hasn't completed or been unlinked already */
1574 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1575 if (ret || !urb->hcpriv)
1577 temp = readl(&xhci->op_regs->status);
1578 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1579 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1580 "HW died, freeing TD.");
1581 urb_priv = urb->hcpriv;
1582 for (i = urb_priv->td_cnt;
1583 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1585 td = urb_priv->td[i];
1586 if (!list_empty(&td->td_list))
1587 list_del_init(&td->td_list);
1588 if (!list_empty(&td->cancelled_td_list))
1589 list_del_init(&td->cancelled_td_list);
1592 usb_hcd_unlink_urb_from_ep(hcd, urb);
1593 spin_unlock_irqrestore(&xhci->lock, flags);
1594 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1595 xhci_urb_free_priv(urb_priv);
1599 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1600 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1601 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1607 urb_priv = urb->hcpriv;
1608 i = urb_priv->td_cnt;
1609 if (i < urb_priv->length)
1610 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1611 "Cancel URB %p, dev %s, ep 0x%x, "
1612 "starting at offset 0x%llx",
1613 urb, urb->dev->devpath,
1614 urb->ep->desc.bEndpointAddress,
1615 (unsigned long long) xhci_trb_virt_to_dma(
1616 urb_priv->td[i]->start_seg,
1617 urb_priv->td[i]->first_trb));
1619 for (; i < urb_priv->length; i++) {
1620 td = urb_priv->td[i];
1621 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1624 /* Queue a stop endpoint command, but only if this is
1625 * the first cancellation to be handled.
1627 if (!(ep->ep_state & EP_HALT_PENDING)) {
1628 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1633 ep->ep_state |= EP_HALT_PENDING;
1634 ep->stop_cmds_pending++;
1635 ep->stop_cmd_timer.expires = jiffies +
1636 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1637 add_timer(&ep->stop_cmd_timer);
1638 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1640 xhci_ring_cmd_db(xhci);
1643 spin_unlock_irqrestore(&xhci->lock, flags);
1647 /* Drop an endpoint from a new bandwidth configuration for this device.
1648 * Only one call to this function is allowed per endpoint before
1649 * check_bandwidth() or reset_bandwidth() must be called.
1650 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1651 * add the endpoint to the schedule with possibly new parameters denoted by a
1652 * different endpoint descriptor in usb_host_endpoint.
1653 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1656 * The USB core will not allow URBs to be queued to an endpoint that is being
1657 * disabled, so there's no need for mutual exclusion to protect
1658 * the xhci->devs[slot_id] structure.
1660 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1661 struct usb_host_endpoint *ep)
1663 struct xhci_hcd *xhci;
1664 struct xhci_container_ctx *in_ctx, *out_ctx;
1665 struct xhci_input_control_ctx *ctrl_ctx;
1666 unsigned int ep_index;
1667 struct xhci_ep_ctx *ep_ctx;
1669 u32 new_add_flags, new_drop_flags;
1672 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1675 xhci = hcd_to_xhci(hcd);
1676 if (xhci->xhc_state & XHCI_STATE_DYING)
1679 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1680 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1681 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1682 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1683 __func__, drop_flag);
1687 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1688 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1689 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1691 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1696 ep_index = xhci_get_endpoint_index(&ep->desc);
1697 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1698 /* If the HC already knows the endpoint is disabled,
1699 * or the HCD has noted it is disabled, ignore this request
1701 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1702 cpu_to_le32(EP_STATE_DISABLED)) ||
1703 le32_to_cpu(ctrl_ctx->drop_flags) &
1704 xhci_get_endpoint_flag(&ep->desc)) {
1705 /* Do not warn when called after a usb_device_reset */
1706 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1707 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1712 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1713 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1715 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1716 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1718 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1720 if (xhci->quirks & XHCI_MTK_HOST)
1721 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1723 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1724 (unsigned int) ep->desc.bEndpointAddress,
1726 (unsigned int) new_drop_flags,
1727 (unsigned int) new_add_flags);
1731 /* Add an endpoint to a new possible bandwidth configuration for this device.
1732 * Only one call to this function is allowed per endpoint before
1733 * check_bandwidth() or reset_bandwidth() must be called.
1734 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1735 * add the endpoint to the schedule with possibly new parameters denoted by a
1736 * different endpoint descriptor in usb_host_endpoint.
1737 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1740 * The USB core will not allow URBs to be queued to an endpoint until the
1741 * configuration or alt setting is installed in the device, so there's no need
1742 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1744 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1745 struct usb_host_endpoint *ep)
1747 struct xhci_hcd *xhci;
1748 struct xhci_container_ctx *in_ctx;
1749 unsigned int ep_index;
1750 struct xhci_input_control_ctx *ctrl_ctx;
1752 u32 new_add_flags, new_drop_flags;
1753 struct xhci_virt_device *virt_dev;
1756 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1758 /* So we won't queue a reset ep command for a root hub */
1762 xhci = hcd_to_xhci(hcd);
1763 if (xhci->xhc_state & XHCI_STATE_DYING)
1766 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1767 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1768 /* FIXME when we have to issue an evaluate endpoint command to
1769 * deal with ep0 max packet size changing once we get the
1772 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1773 __func__, added_ctxs);
1777 virt_dev = xhci->devs[udev->slot_id];
1778 in_ctx = virt_dev->in_ctx;
1779 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1781 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1786 ep_index = xhci_get_endpoint_index(&ep->desc);
1787 /* If this endpoint is already in use, and the upper layers are trying
1788 * to add it again without dropping it, reject the addition.
1790 if (virt_dev->eps[ep_index].ring &&
1791 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1792 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1793 "without dropping it.\n",
1794 (unsigned int) ep->desc.bEndpointAddress);
1798 /* If the HCD has already noted the endpoint is enabled,
1799 * ignore this request.
1801 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1802 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1808 * Configuration and alternate setting changes must be done in
1809 * process context, not interrupt context (or so documenation
1810 * for usb_set_interface() and usb_set_configuration() claim).
1812 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1813 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1814 __func__, ep->desc.bEndpointAddress);
1818 if (xhci->quirks & XHCI_MTK_HOST) {
1819 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1821 xhci_free_or_cache_endpoint_ring(xhci,
1822 virt_dev, ep_index);
1827 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1828 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1830 /* If xhci_endpoint_disable() was called for this endpoint, but the
1831 * xHC hasn't been notified yet through the check_bandwidth() call,
1832 * this re-adds a new state for the endpoint from the new endpoint
1833 * descriptors. We must drop and re-add this endpoint, so we leave the
1836 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1838 /* Store the usb_device pointer for later use */
1841 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1842 (unsigned int) ep->desc.bEndpointAddress,
1844 (unsigned int) new_drop_flags,
1845 (unsigned int) new_add_flags);
1849 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1851 struct xhci_input_control_ctx *ctrl_ctx;
1852 struct xhci_ep_ctx *ep_ctx;
1853 struct xhci_slot_ctx *slot_ctx;
1856 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1858 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1863 /* When a device's add flag and drop flag are zero, any subsequent
1864 * configure endpoint command will leave that endpoint's state
1865 * untouched. Make sure we don't leave any old state in the input
1866 * endpoint contexts.
1868 ctrl_ctx->drop_flags = 0;
1869 ctrl_ctx->add_flags = 0;
1870 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1871 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1872 /* Endpoint 0 is always valid */
1873 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1874 for (i = 1; i < 31; ++i) {
1875 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1876 ep_ctx->ep_info = 0;
1877 ep_ctx->ep_info2 = 0;
1879 ep_ctx->tx_info = 0;
1883 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1884 struct usb_device *udev, u32 *cmd_status)
1888 switch (*cmd_status) {
1889 case COMP_CMD_ABORT:
1891 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1895 dev_warn(&udev->dev,
1896 "Not enough host controller resources for new device state.\n");
1898 /* FIXME: can we allocate more resources for the HC? */
1901 case COMP_2ND_BW_ERR:
1902 dev_warn(&udev->dev,
1903 "Not enough bandwidth for new device state.\n");
1905 /* FIXME: can we go back to the old state? */
1908 /* the HCD set up something wrong */
1909 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1911 "and endpoint is not disabled.\n");
1915 dev_warn(&udev->dev,
1916 "ERROR: Incompatible device for endpoint configure command.\n");
1920 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1921 "Successful Endpoint Configure command");
1925 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1933 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1934 struct usb_device *udev, u32 *cmd_status)
1937 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1939 switch (*cmd_status) {
1940 case COMP_CMD_ABORT:
1942 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1946 dev_warn(&udev->dev,
1947 "WARN: xHCI driver setup invalid evaluate context command.\n");
1951 dev_warn(&udev->dev,
1952 "WARN: slot not enabled for evaluate context command.\n");
1955 case COMP_CTX_STATE:
1956 dev_warn(&udev->dev,
1957 "WARN: invalid context state for evaluate context command.\n");
1958 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1962 dev_warn(&udev->dev,
1963 "ERROR: Incompatible device for evaluate context command.\n");
1967 /* Max Exit Latency too large error */
1968 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1972 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1973 "Successful evaluate context command");
1977 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1985 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1986 struct xhci_input_control_ctx *ctrl_ctx)
1988 u32 valid_add_flags;
1989 u32 valid_drop_flags;
1991 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1992 * (bit 1). The default control endpoint is added during the Address
1993 * Device command and is never removed until the slot is disabled.
1995 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1996 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1998 /* Use hweight32 to count the number of ones in the add flags, or
1999 * number of endpoints added. Don't count endpoints that are changed
2000 * (both added and dropped).
2002 return hweight32(valid_add_flags) -
2003 hweight32(valid_add_flags & valid_drop_flags);
2006 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2007 struct xhci_input_control_ctx *ctrl_ctx)
2009 u32 valid_add_flags;
2010 u32 valid_drop_flags;
2012 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2013 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2015 return hweight32(valid_drop_flags) -
2016 hweight32(valid_add_flags & valid_drop_flags);
2020 * We need to reserve the new number of endpoints before the configure endpoint
2021 * command completes. We can't subtract the dropped endpoints from the number
2022 * of active endpoints until the command completes because we can oversubscribe
2023 * the host in this case:
2025 * - the first configure endpoint command drops more endpoints than it adds
2026 * - a second configure endpoint command that adds more endpoints is queued
2027 * - the first configure endpoint command fails, so the config is unchanged
2028 * - the second command may succeed, even though there isn't enough resources
2030 * Must be called with xhci->lock held.
2032 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2033 struct xhci_input_control_ctx *ctrl_ctx)
2037 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2038 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2039 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2040 "Not enough ep ctxs: "
2041 "%u active, need to add %u, limit is %u.",
2042 xhci->num_active_eps, added_eps,
2043 xhci->limit_active_eps);
2046 xhci->num_active_eps += added_eps;
2047 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2048 "Adding %u ep ctxs, %u now active.", added_eps,
2049 xhci->num_active_eps);
2054 * The configure endpoint was failed by the xHC for some other reason, so we
2055 * need to revert the resources that failed configuration would have used.
2057 * Must be called with xhci->lock held.
2059 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2060 struct xhci_input_control_ctx *ctrl_ctx)
2064 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2065 xhci->num_active_eps -= num_failed_eps;
2066 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2067 "Removing %u failed ep ctxs, %u now active.",
2069 xhci->num_active_eps);
2073 * Now that the command has completed, clean up the active endpoint count by
2074 * subtracting out the endpoints that were dropped (but not changed).
2076 * Must be called with xhci->lock held.
2078 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2079 struct xhci_input_control_ctx *ctrl_ctx)
2081 u32 num_dropped_eps;
2083 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2084 xhci->num_active_eps -= num_dropped_eps;
2085 if (num_dropped_eps)
2086 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2087 "Removing %u dropped ep ctxs, %u now active.",
2089 xhci->num_active_eps);
2092 static unsigned int xhci_get_block_size(struct usb_device *udev)
2094 switch (udev->speed) {
2096 case USB_SPEED_FULL:
2098 case USB_SPEED_HIGH:
2100 case USB_SPEED_SUPER:
2101 case USB_SPEED_SUPER_PLUS:
2103 case USB_SPEED_UNKNOWN:
2104 case USB_SPEED_WIRELESS:
2106 /* Should never happen */
2112 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2114 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2116 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2121 /* If we are changing a LS/FS device under a HS hub,
2122 * make sure (if we are activating a new TT) that the HS bus has enough
2123 * bandwidth for this new TT.
2125 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2126 struct xhci_virt_device *virt_dev,
2129 struct xhci_interval_bw_table *bw_table;
2130 struct xhci_tt_bw_info *tt_info;
2132 /* Find the bandwidth table for the root port this TT is attached to. */
2133 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2134 tt_info = virt_dev->tt_info;
2135 /* If this TT already had active endpoints, the bandwidth for this TT
2136 * has already been added. Removing all periodic endpoints (and thus
2137 * making the TT enactive) will only decrease the bandwidth used.
2141 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2142 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2146 /* Not sure why we would have no new active endpoints...
2148 * Maybe because of an Evaluate Context change for a hub update or a
2149 * control endpoint 0 max packet size change?
2150 * FIXME: skip the bandwidth calculation in that case.
2155 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2156 struct xhci_virt_device *virt_dev)
2158 unsigned int bw_reserved;
2160 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2161 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2164 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2165 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2172 * This algorithm is a very conservative estimate of the worst-case scheduling
2173 * scenario for any one interval. The hardware dynamically schedules the
2174 * packets, so we can't tell which microframe could be the limiting factor in
2175 * the bandwidth scheduling. This only takes into account periodic endpoints.
2177 * Obviously, we can't solve an NP complete problem to find the minimum worst
2178 * case scenario. Instead, we come up with an estimate that is no less than
2179 * the worst case bandwidth used for any one microframe, but may be an
2182 * We walk the requirements for each endpoint by interval, starting with the
2183 * smallest interval, and place packets in the schedule where there is only one
2184 * possible way to schedule packets for that interval. In order to simplify
2185 * this algorithm, we record the largest max packet size for each interval, and
2186 * assume all packets will be that size.
2188 * For interval 0, we obviously must schedule all packets for each interval.
2189 * The bandwidth for interval 0 is just the amount of data to be transmitted
2190 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2191 * the number of packets).
2193 * For interval 1, we have two possible microframes to schedule those packets
2194 * in. For this algorithm, if we can schedule the same number of packets for
2195 * each possible scheduling opportunity (each microframe), we will do so. The
2196 * remaining number of packets will be saved to be transmitted in the gaps in
2197 * the next interval's scheduling sequence.
2199 * As we move those remaining packets to be scheduled with interval 2 packets,
2200 * we have to double the number of remaining packets to transmit. This is
2201 * because the intervals are actually powers of 2, and we would be transmitting
2202 * the previous interval's packets twice in this interval. We also have to be
2203 * sure that when we look at the largest max packet size for this interval, we
2204 * also look at the largest max packet size for the remaining packets and take
2205 * the greater of the two.
2207 * The algorithm continues to evenly distribute packets in each scheduling
2208 * opportunity, and push the remaining packets out, until we get to the last
2209 * interval. Then those packets and their associated overhead are just added
2210 * to the bandwidth used.
2212 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2213 struct xhci_virt_device *virt_dev,
2216 unsigned int bw_reserved;
2217 unsigned int max_bandwidth;
2218 unsigned int bw_used;
2219 unsigned int block_size;
2220 struct xhci_interval_bw_table *bw_table;
2221 unsigned int packet_size = 0;
2222 unsigned int overhead = 0;
2223 unsigned int packets_transmitted = 0;
2224 unsigned int packets_remaining = 0;
2227 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2228 return xhci_check_ss_bw(xhci, virt_dev);
2230 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2231 max_bandwidth = HS_BW_LIMIT;
2232 /* Convert percent of bus BW reserved to blocks reserved */
2233 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2235 max_bandwidth = FS_BW_LIMIT;
2236 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2239 bw_table = virt_dev->bw_table;
2240 /* We need to translate the max packet size and max ESIT payloads into
2241 * the units the hardware uses.
2243 block_size = xhci_get_block_size(virt_dev->udev);
2245 /* If we are manipulating a LS/FS device under a HS hub, double check
2246 * that the HS bus has enough bandwidth if we are activing a new TT.
2248 if (virt_dev->tt_info) {
2249 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2250 "Recalculating BW for rootport %u",
2251 virt_dev->real_port);
2252 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2253 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2254 "newly activated TT.\n");
2257 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2258 "Recalculating BW for TT slot %u port %u",
2259 virt_dev->tt_info->slot_id,
2260 virt_dev->tt_info->ttport);
2262 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2263 "Recalculating BW for rootport %u",
2264 virt_dev->real_port);
2267 /* Add in how much bandwidth will be used for interval zero, or the
2268 * rounded max ESIT payload + number of packets * largest overhead.
2270 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2271 bw_table->interval_bw[0].num_packets *
2272 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2274 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2275 unsigned int bw_added;
2276 unsigned int largest_mps;
2277 unsigned int interval_overhead;
2280 * How many packets could we transmit in this interval?
2281 * If packets didn't fit in the previous interval, we will need
2282 * to transmit that many packets twice within this interval.
2284 packets_remaining = 2 * packets_remaining +
2285 bw_table->interval_bw[i].num_packets;
2287 /* Find the largest max packet size of this or the previous
2290 if (list_empty(&bw_table->interval_bw[i].endpoints))
2293 struct xhci_virt_ep *virt_ep;
2294 struct list_head *ep_entry;
2296 ep_entry = bw_table->interval_bw[i].endpoints.next;
2297 virt_ep = list_entry(ep_entry,
2298 struct xhci_virt_ep, bw_endpoint_list);
2299 /* Convert to blocks, rounding up */
2300 largest_mps = DIV_ROUND_UP(
2301 virt_ep->bw_info.max_packet_size,
2304 if (largest_mps > packet_size)
2305 packet_size = largest_mps;
2307 /* Use the larger overhead of this or the previous interval. */
2308 interval_overhead = xhci_get_largest_overhead(
2309 &bw_table->interval_bw[i]);
2310 if (interval_overhead > overhead)
2311 overhead = interval_overhead;
2313 /* How many packets can we evenly distribute across
2314 * (1 << (i + 1)) possible scheduling opportunities?
2316 packets_transmitted = packets_remaining >> (i + 1);
2318 /* Add in the bandwidth used for those scheduled packets */
2319 bw_added = packets_transmitted * (overhead + packet_size);
2321 /* How many packets do we have remaining to transmit? */
2322 packets_remaining = packets_remaining % (1 << (i + 1));
2324 /* What largest max packet size should those packets have? */
2325 /* If we've transmitted all packets, don't carry over the
2326 * largest packet size.
2328 if (packets_remaining == 0) {
2331 } else if (packets_transmitted > 0) {
2332 /* Otherwise if we do have remaining packets, and we've
2333 * scheduled some packets in this interval, take the
2334 * largest max packet size from endpoints with this
2337 packet_size = largest_mps;
2338 overhead = interval_overhead;
2340 /* Otherwise carry over packet_size and overhead from the last
2341 * time we had a remainder.
2343 bw_used += bw_added;
2344 if (bw_used > max_bandwidth) {
2345 xhci_warn(xhci, "Not enough bandwidth. "
2346 "Proposed: %u, Max: %u\n",
2347 bw_used, max_bandwidth);
2352 * Ok, we know we have some packets left over after even-handedly
2353 * scheduling interval 15. We don't know which microframes they will
2354 * fit into, so we over-schedule and say they will be scheduled every
2357 if (packets_remaining > 0)
2358 bw_used += overhead + packet_size;
2360 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2361 unsigned int port_index = virt_dev->real_port - 1;
2363 /* OK, we're manipulating a HS device attached to a
2364 * root port bandwidth domain. Include the number of active TTs
2365 * in the bandwidth used.
2367 bw_used += TT_HS_OVERHEAD *
2368 xhci->rh_bw[port_index].num_active_tts;
2371 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2372 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2373 "Available: %u " "percent",
2374 bw_used, max_bandwidth, bw_reserved,
2375 (max_bandwidth - bw_used - bw_reserved) * 100 /
2378 bw_used += bw_reserved;
2379 if (bw_used > max_bandwidth) {
2380 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2381 bw_used, max_bandwidth);
2385 bw_table->bw_used = bw_used;
2389 static bool xhci_is_async_ep(unsigned int ep_type)
2391 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2392 ep_type != ISOC_IN_EP &&
2393 ep_type != INT_IN_EP);
2396 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2398 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2401 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2403 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2405 if (ep_bw->ep_interval == 0)
2406 return SS_OVERHEAD_BURST +
2407 (ep_bw->mult * ep_bw->num_packets *
2408 (SS_OVERHEAD + mps));
2409 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2410 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2411 1 << ep_bw->ep_interval);
2415 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2416 struct xhci_bw_info *ep_bw,
2417 struct xhci_interval_bw_table *bw_table,
2418 struct usb_device *udev,
2419 struct xhci_virt_ep *virt_ep,
2420 struct xhci_tt_bw_info *tt_info)
2422 struct xhci_interval_bw *interval_bw;
2423 int normalized_interval;
2425 if (xhci_is_async_ep(ep_bw->type))
2428 if (udev->speed >= USB_SPEED_SUPER) {
2429 if (xhci_is_sync_in_ep(ep_bw->type))
2430 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2431 xhci_get_ss_bw_consumed(ep_bw);
2433 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2434 xhci_get_ss_bw_consumed(ep_bw);
2438 /* SuperSpeed endpoints never get added to intervals in the table, so
2439 * this check is only valid for HS/FS/LS devices.
2441 if (list_empty(&virt_ep->bw_endpoint_list))
2443 /* For LS/FS devices, we need to translate the interval expressed in
2444 * microframes to frames.
2446 if (udev->speed == USB_SPEED_HIGH)
2447 normalized_interval = ep_bw->ep_interval;
2449 normalized_interval = ep_bw->ep_interval - 3;
2451 if (normalized_interval == 0)
2452 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2453 interval_bw = &bw_table->interval_bw[normalized_interval];
2454 interval_bw->num_packets -= ep_bw->num_packets;
2455 switch (udev->speed) {
2457 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2459 case USB_SPEED_FULL:
2460 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2462 case USB_SPEED_HIGH:
2463 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2465 case USB_SPEED_SUPER:
2466 case USB_SPEED_SUPER_PLUS:
2467 case USB_SPEED_UNKNOWN:
2468 case USB_SPEED_WIRELESS:
2469 /* Should never happen because only LS/FS/HS endpoints will get
2470 * added to the endpoint list.
2475 tt_info->active_eps -= 1;
2476 list_del_init(&virt_ep->bw_endpoint_list);
2479 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2480 struct xhci_bw_info *ep_bw,
2481 struct xhci_interval_bw_table *bw_table,
2482 struct usb_device *udev,
2483 struct xhci_virt_ep *virt_ep,
2484 struct xhci_tt_bw_info *tt_info)
2486 struct xhci_interval_bw *interval_bw;
2487 struct xhci_virt_ep *smaller_ep;
2488 int normalized_interval;
2490 if (xhci_is_async_ep(ep_bw->type))
2493 if (udev->speed == USB_SPEED_SUPER) {
2494 if (xhci_is_sync_in_ep(ep_bw->type))
2495 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2496 xhci_get_ss_bw_consumed(ep_bw);
2498 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2499 xhci_get_ss_bw_consumed(ep_bw);
2503 /* For LS/FS devices, we need to translate the interval expressed in
2504 * microframes to frames.
2506 if (udev->speed == USB_SPEED_HIGH)
2507 normalized_interval = ep_bw->ep_interval;
2509 normalized_interval = ep_bw->ep_interval - 3;
2511 if (normalized_interval == 0)
2512 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2513 interval_bw = &bw_table->interval_bw[normalized_interval];
2514 interval_bw->num_packets += ep_bw->num_packets;
2515 switch (udev->speed) {
2517 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2519 case USB_SPEED_FULL:
2520 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2522 case USB_SPEED_HIGH:
2523 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2525 case USB_SPEED_SUPER:
2526 case USB_SPEED_SUPER_PLUS:
2527 case USB_SPEED_UNKNOWN:
2528 case USB_SPEED_WIRELESS:
2529 /* Should never happen because only LS/FS/HS endpoints will get
2530 * added to the endpoint list.
2536 tt_info->active_eps += 1;
2537 /* Insert the endpoint into the list, largest max packet size first. */
2538 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2540 if (ep_bw->max_packet_size >=
2541 smaller_ep->bw_info.max_packet_size) {
2542 /* Add the new ep before the smaller endpoint */
2543 list_add_tail(&virt_ep->bw_endpoint_list,
2544 &smaller_ep->bw_endpoint_list);
2548 /* Add the new endpoint at the end of the list. */
2549 list_add_tail(&virt_ep->bw_endpoint_list,
2550 &interval_bw->endpoints);
2553 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2554 struct xhci_virt_device *virt_dev,
2557 struct xhci_root_port_bw_info *rh_bw_info;
2558 if (!virt_dev->tt_info)
2561 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2562 if (old_active_eps == 0 &&
2563 virt_dev->tt_info->active_eps != 0) {
2564 rh_bw_info->num_active_tts += 1;
2565 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2566 } else if (old_active_eps != 0 &&
2567 virt_dev->tt_info->active_eps == 0) {
2568 rh_bw_info->num_active_tts -= 1;
2569 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2573 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2574 struct xhci_virt_device *virt_dev,
2575 struct xhci_container_ctx *in_ctx)
2577 struct xhci_bw_info ep_bw_info[31];
2579 struct xhci_input_control_ctx *ctrl_ctx;
2580 int old_active_eps = 0;
2582 if (virt_dev->tt_info)
2583 old_active_eps = virt_dev->tt_info->active_eps;
2585 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2587 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2592 for (i = 0; i < 31; i++) {
2593 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2596 /* Make a copy of the BW info in case we need to revert this */
2597 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2598 sizeof(ep_bw_info[i]));
2599 /* Drop the endpoint from the interval table if the endpoint is
2600 * being dropped or changed.
2602 if (EP_IS_DROPPED(ctrl_ctx, i))
2603 xhci_drop_ep_from_interval_table(xhci,
2604 &virt_dev->eps[i].bw_info,
2610 /* Overwrite the information stored in the endpoints' bw_info */
2611 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2612 for (i = 0; i < 31; i++) {
2613 /* Add any changed or added endpoints to the interval table */
2614 if (EP_IS_ADDED(ctrl_ctx, i))
2615 xhci_add_ep_to_interval_table(xhci,
2616 &virt_dev->eps[i].bw_info,
2623 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2624 /* Ok, this fits in the bandwidth we have.
2625 * Update the number of active TTs.
2627 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2631 /* We don't have enough bandwidth for this, revert the stored info. */
2632 for (i = 0; i < 31; i++) {
2633 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2636 /* Drop the new copies of any added or changed endpoints from
2637 * the interval table.
2639 if (EP_IS_ADDED(ctrl_ctx, i)) {
2640 xhci_drop_ep_from_interval_table(xhci,
2641 &virt_dev->eps[i].bw_info,
2647 /* Revert the endpoint back to its old information */
2648 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2649 sizeof(ep_bw_info[i]));
2650 /* Add any changed or dropped endpoints back into the table */
2651 if (EP_IS_DROPPED(ctrl_ctx, i))
2652 xhci_add_ep_to_interval_table(xhci,
2653 &virt_dev->eps[i].bw_info,
2663 /* Issue a configure endpoint command or evaluate context command
2664 * and wait for it to finish.
2666 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2667 struct usb_device *udev,
2668 struct xhci_command *command,
2669 bool ctx_change, bool must_succeed)
2672 unsigned long flags;
2673 struct xhci_input_control_ctx *ctrl_ctx;
2674 struct xhci_virt_device *virt_dev;
2679 spin_lock_irqsave(&xhci->lock, flags);
2680 virt_dev = xhci->devs[udev->slot_id];
2682 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2684 spin_unlock_irqrestore(&xhci->lock, flags);
2685 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2690 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2691 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2692 spin_unlock_irqrestore(&xhci->lock, flags);
2693 xhci_warn(xhci, "Not enough host resources, "
2694 "active endpoint contexts = %u\n",
2695 xhci->num_active_eps);
2698 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2699 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2700 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2701 xhci_free_host_resources(xhci, ctrl_ctx);
2702 spin_unlock_irqrestore(&xhci->lock, flags);
2703 xhci_warn(xhci, "Not enough bandwidth\n");
2708 ret = xhci_queue_configure_endpoint(xhci, command,
2709 command->in_ctx->dma,
2710 udev->slot_id, must_succeed);
2712 ret = xhci_queue_evaluate_context(xhci, command,
2713 command->in_ctx->dma,
2714 udev->slot_id, must_succeed);
2716 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2717 xhci_free_host_resources(xhci, ctrl_ctx);
2718 spin_unlock_irqrestore(&xhci->lock, flags);
2719 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2720 "FIXME allocate a new ring segment");
2723 xhci_ring_cmd_db(xhci);
2724 spin_unlock_irqrestore(&xhci->lock, flags);
2726 /* Wait for the configure endpoint command to complete */
2727 wait_for_completion(command->completion);
2730 ret = xhci_configure_endpoint_result(xhci, udev,
2733 ret = xhci_evaluate_context_result(xhci, udev,
2736 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2737 spin_lock_irqsave(&xhci->lock, flags);
2738 /* If the command failed, remove the reserved resources.
2739 * Otherwise, clean up the estimate to include dropped eps.
2742 xhci_free_host_resources(xhci, ctrl_ctx);
2744 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2745 spin_unlock_irqrestore(&xhci->lock, flags);
2750 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2751 struct xhci_virt_device *vdev, int i)
2753 struct xhci_virt_ep *ep = &vdev->eps[i];
2755 if (ep->ep_state & EP_HAS_STREAMS) {
2756 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2757 xhci_get_endpoint_address(i));
2758 xhci_free_stream_info(xhci, ep->stream_info);
2759 ep->stream_info = NULL;
2760 ep->ep_state &= ~EP_HAS_STREAMS;
2764 /* Called after one or more calls to xhci_add_endpoint() or
2765 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2766 * to call xhci_reset_bandwidth().
2768 * Since we are in the middle of changing either configuration or
2769 * installing a new alt setting, the USB core won't allow URBs to be
2770 * enqueued for any endpoint on the old config or interface. Nothing
2771 * else should be touching the xhci->devs[slot_id] structure, so we
2772 * don't need to take the xhci->lock for manipulating that.
2774 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2778 struct xhci_hcd *xhci;
2779 struct xhci_virt_device *virt_dev;
2780 struct xhci_input_control_ctx *ctrl_ctx;
2781 struct xhci_slot_ctx *slot_ctx;
2782 struct xhci_command *command;
2784 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2787 xhci = hcd_to_xhci(hcd);
2788 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2789 (xhci->xhc_state & XHCI_STATE_REMOVING))
2792 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2793 virt_dev = xhci->devs[udev->slot_id];
2795 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2799 command->in_ctx = virt_dev->in_ctx;
2801 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2802 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2804 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2807 goto command_cleanup;
2809 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2810 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2811 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2813 /* Don't issue the command if there's no endpoints to update. */
2814 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2815 ctrl_ctx->drop_flags == 0) {
2817 goto command_cleanup;
2819 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2820 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2821 for (i = 31; i >= 1; i--) {
2822 __le32 le32 = cpu_to_le32(BIT(i));
2824 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2825 || (ctrl_ctx->add_flags & le32) || i == 1) {
2826 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2827 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2831 xhci_dbg(xhci, "New Input Control Context:\n");
2832 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2833 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2835 ret = xhci_configure_endpoint(xhci, udev, command,
2838 /* Callee should call reset_bandwidth() */
2839 goto command_cleanup;
2841 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2842 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2843 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2845 /* Free any rings that were dropped, but not changed. */
2846 for (i = 1; i < 31; ++i) {
2847 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2848 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2849 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2850 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2853 xhci_zero_in_ctx(xhci, virt_dev);
2855 * Install any rings for completely new endpoints or changed endpoints,
2856 * and free or cache any old rings from changed endpoints.
2858 for (i = 1; i < 31; ++i) {
2859 if (!virt_dev->eps[i].new_ring)
2861 /* Only cache or free the old ring if it exists.
2862 * It may not if this is the first add of an endpoint.
2864 if (virt_dev->eps[i].ring) {
2865 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2867 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2868 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2869 virt_dev->eps[i].new_ring = NULL;
2872 kfree(command->completion);
2878 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2880 struct xhci_hcd *xhci;
2881 struct xhci_virt_device *virt_dev;
2884 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2887 xhci = hcd_to_xhci(hcd);
2889 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2890 virt_dev = xhci->devs[udev->slot_id];
2891 /* Free any rings allocated for added endpoints */
2892 for (i = 0; i < 31; ++i) {
2893 if (virt_dev->eps[i].new_ring) {
2894 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2895 virt_dev->eps[i].new_ring = NULL;
2898 xhci_zero_in_ctx(xhci, virt_dev);
2901 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2902 struct xhci_container_ctx *in_ctx,
2903 struct xhci_container_ctx *out_ctx,
2904 struct xhci_input_control_ctx *ctrl_ctx,
2905 u32 add_flags, u32 drop_flags)
2907 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2908 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2909 xhci_slot_copy(xhci, in_ctx, out_ctx);
2910 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2912 xhci_dbg(xhci, "Input Context:\n");
2913 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2916 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2917 unsigned int slot_id, unsigned int ep_index,
2918 struct xhci_dequeue_state *deq_state)
2920 struct xhci_input_control_ctx *ctrl_ctx;
2921 struct xhci_container_ctx *in_ctx;
2922 struct xhci_ep_ctx *ep_ctx;
2926 in_ctx = xhci->devs[slot_id]->in_ctx;
2927 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2929 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2934 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2935 xhci->devs[slot_id]->out_ctx, ep_index);
2936 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2937 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2938 deq_state->new_deq_ptr);
2940 xhci_warn(xhci, "WARN Cannot submit config ep after "
2941 "reset ep command\n");
2942 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2943 deq_state->new_deq_seg,
2944 deq_state->new_deq_ptr);
2947 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2949 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2950 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2951 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2952 added_ctxs, added_ctxs);
2955 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2956 unsigned int ep_index, struct xhci_td *td)
2958 struct xhci_dequeue_state deq_state;
2959 struct xhci_virt_ep *ep;
2960 struct usb_device *udev = td->urb->dev;
2962 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2963 "Cleaning up stalled endpoint ring");
2964 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2965 /* We need to move the HW's dequeue pointer past this TD,
2966 * or it will attempt to resend it on the next doorbell ring.
2968 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2969 ep_index, ep->stopped_stream, td, &deq_state);
2971 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2974 /* HW with the reset endpoint quirk will use the saved dequeue state to
2975 * issue a configure endpoint command later.
2977 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2978 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2979 "Queueing new dequeue state");
2980 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2981 ep_index, ep->stopped_stream, &deq_state);
2983 /* Better hope no one uses the input context between now and the
2984 * reset endpoint completion!
2985 * XXX: No idea how this hardware will react when stream rings
2988 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2989 "Setting up input context for "
2990 "configure endpoint command");
2991 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2992 ep_index, &deq_state);
2996 /* Called when clearing halted device. The core should have sent the control
2997 * message to clear the device halt condition. The host side of the halt should
2998 * already be cleared with a reset endpoint command issued when the STALL tx
2999 * event was received.
3001 * Context: in_interrupt
3004 void xhci_endpoint_reset(struct usb_hcd *hcd,
3005 struct usb_host_endpoint *ep)
3007 struct xhci_hcd *xhci;
3009 xhci = hcd_to_xhci(hcd);
3012 * We might need to implement the config ep cmd in xhci 4.8.1 note:
3013 * The Reset Endpoint Command may only be issued to endpoints in the
3014 * Halted state. If software wishes reset the Data Toggle or Sequence
3015 * Number of an endpoint that isn't in the Halted state, then software
3016 * may issue a Configure Endpoint Command with the Drop and Add bits set
3017 * for the target endpoint. that is in the Stopped state.
3020 /* For now just print debug to follow the situation */
3021 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
3022 ep->desc.bEndpointAddress);
3025 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3026 struct usb_device *udev, struct usb_host_endpoint *ep,
3027 unsigned int slot_id)
3030 unsigned int ep_index;
3031 unsigned int ep_state;
3035 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3037 return ret ? ret : -EINVAL;
3038 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3039 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3040 " descriptor for ep 0x%x does not support streams\n",
3041 ep->desc.bEndpointAddress);
3045 ep_index = xhci_get_endpoint_index(&ep->desc);
3046 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3047 if (ep_state & EP_HAS_STREAMS ||
3048 ep_state & EP_GETTING_STREAMS) {
3049 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3050 "already has streams set up.\n",
3051 ep->desc.bEndpointAddress);
3052 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3053 "dynamic stream context array reallocation.\n");
3056 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3057 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3058 "endpoint 0x%x; URBs are pending.\n",
3059 ep->desc.bEndpointAddress);
3065 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3066 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3068 unsigned int max_streams;
3070 /* The stream context array size must be a power of two */
3071 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3073 * Find out how many primary stream array entries the host controller
3074 * supports. Later we may use secondary stream arrays (similar to 2nd
3075 * level page entries), but that's an optional feature for xHCI host
3076 * controllers. xHCs must support at least 4 stream IDs.
3078 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3079 if (*num_stream_ctxs > max_streams) {
3080 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3082 *num_stream_ctxs = max_streams;
3083 *num_streams = max_streams;
3087 /* Returns an error code if one of the endpoint already has streams.
3088 * This does not change any data structures, it only checks and gathers
3091 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3092 struct usb_device *udev,
3093 struct usb_host_endpoint **eps, unsigned int num_eps,
3094 unsigned int *num_streams, u32 *changed_ep_bitmask)
3096 unsigned int max_streams;
3097 unsigned int endpoint_flag;
3101 for (i = 0; i < num_eps; i++) {
3102 ret = xhci_check_streams_endpoint(xhci, udev,
3103 eps[i], udev->slot_id);
3107 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3108 if (max_streams < (*num_streams - 1)) {
3109 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3110 eps[i]->desc.bEndpointAddress,
3112 *num_streams = max_streams+1;
3115 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3116 if (*changed_ep_bitmask & endpoint_flag)
3118 *changed_ep_bitmask |= endpoint_flag;
3123 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3124 struct usb_device *udev,
3125 struct usb_host_endpoint **eps, unsigned int num_eps)
3127 u32 changed_ep_bitmask = 0;
3128 unsigned int slot_id;
3129 unsigned int ep_index;
3130 unsigned int ep_state;
3133 slot_id = udev->slot_id;
3134 if (!xhci->devs[slot_id])
3137 for (i = 0; i < num_eps; i++) {
3138 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3139 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3140 /* Are streams already being freed for the endpoint? */
3141 if (ep_state & EP_GETTING_NO_STREAMS) {
3142 xhci_warn(xhci, "WARN Can't disable streams for "
3144 "streams are being disabled already\n",
3145 eps[i]->desc.bEndpointAddress);
3148 /* Are there actually any streams to free? */
3149 if (!(ep_state & EP_HAS_STREAMS) &&
3150 !(ep_state & EP_GETTING_STREAMS)) {
3151 xhci_warn(xhci, "WARN Can't disable streams for "
3153 "streams are already disabled!\n",
3154 eps[i]->desc.bEndpointAddress);
3155 xhci_warn(xhci, "WARN xhci_free_streams() called "
3156 "with non-streams endpoint\n");
3159 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3161 return changed_ep_bitmask;
3165 * The USB device drivers use this function (through the HCD interface in USB
3166 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3167 * coordinate mass storage command queueing across multiple endpoints (basically
3168 * a stream ID == a task ID).
3170 * Setting up streams involves allocating the same size stream context array
3171 * for each endpoint and issuing a configure endpoint command for all endpoints.
3173 * Don't allow the call to succeed if one endpoint only supports one stream
3174 * (which means it doesn't support streams at all).
3176 * Drivers may get less stream IDs than they asked for, if the host controller
3177 * hardware or endpoints claim they can't support the number of requested
3180 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3181 struct usb_host_endpoint **eps, unsigned int num_eps,
3182 unsigned int num_streams, gfp_t mem_flags)
3185 struct xhci_hcd *xhci;
3186 struct xhci_virt_device *vdev;
3187 struct xhci_command *config_cmd;
3188 struct xhci_input_control_ctx *ctrl_ctx;
3189 unsigned int ep_index;
3190 unsigned int num_stream_ctxs;
3191 unsigned int max_packet;
3192 unsigned long flags;
3193 u32 changed_ep_bitmask = 0;
3198 /* Add one to the number of streams requested to account for
3199 * stream 0 that is reserved for xHCI usage.
3202 xhci = hcd_to_xhci(hcd);
3203 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3206 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3207 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3208 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3209 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3213 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3215 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3218 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3220 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3222 xhci_free_command(xhci, config_cmd);
3226 /* Check to make sure all endpoints are not already configured for
3227 * streams. While we're at it, find the maximum number of streams that
3228 * all the endpoints will support and check for duplicate endpoints.
3230 spin_lock_irqsave(&xhci->lock, flags);
3231 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3232 num_eps, &num_streams, &changed_ep_bitmask);
3234 xhci_free_command(xhci, config_cmd);
3235 spin_unlock_irqrestore(&xhci->lock, flags);
3238 if (num_streams <= 1) {
3239 xhci_warn(xhci, "WARN: endpoints can't handle "
3240 "more than one stream.\n");
3241 xhci_free_command(xhci, config_cmd);
3242 spin_unlock_irqrestore(&xhci->lock, flags);
3245 vdev = xhci->devs[udev->slot_id];
3246 /* Mark each endpoint as being in transition, so
3247 * xhci_urb_enqueue() will reject all URBs.
3249 for (i = 0; i < num_eps; i++) {
3250 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3251 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3253 spin_unlock_irqrestore(&xhci->lock, flags);
3255 /* Setup internal data structures and allocate HW data structures for
3256 * streams (but don't install the HW structures in the input context
3257 * until we're sure all memory allocation succeeded).
3259 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3260 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3261 num_stream_ctxs, num_streams);
3263 for (i = 0; i < num_eps; i++) {
3264 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3265 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&eps[i]->desc));
3266 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3269 max_packet, mem_flags);
3270 if (!vdev->eps[ep_index].stream_info)
3272 /* Set maxPstreams in endpoint context and update deq ptr to
3273 * point to stream context array. FIXME
3277 /* Set up the input context for a configure endpoint command. */
3278 for (i = 0; i < num_eps; i++) {
3279 struct xhci_ep_ctx *ep_ctx;
3281 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3282 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3284 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3285 vdev->out_ctx, ep_index);
3286 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3287 vdev->eps[ep_index].stream_info);
3289 /* Tell the HW to drop its old copy of the endpoint context info
3290 * and add the updated copy from the input context.
3292 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3293 vdev->out_ctx, ctrl_ctx,
3294 changed_ep_bitmask, changed_ep_bitmask);
3296 /* Issue and wait for the configure endpoint command */
3297 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3300 /* xHC rejected the configure endpoint command for some reason, so we
3301 * leave the old ring intact and free our internal streams data
3307 spin_lock_irqsave(&xhci->lock, flags);
3308 for (i = 0; i < num_eps; i++) {
3309 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3310 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3311 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3312 udev->slot_id, ep_index);
3313 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3315 xhci_free_command(xhci, config_cmd);
3316 spin_unlock_irqrestore(&xhci->lock, flags);
3318 /* Subtract 1 for stream 0, which drivers can't use */
3319 return num_streams - 1;
3322 /* If it didn't work, free the streams! */
3323 for (i = 0; i < num_eps; i++) {
3324 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3325 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3326 vdev->eps[ep_index].stream_info = NULL;
3327 /* FIXME Unset maxPstreams in endpoint context and
3328 * update deq ptr to point to normal string ring.
3330 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3331 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3332 xhci_endpoint_zero(xhci, vdev, eps[i]);
3334 xhci_free_command(xhci, config_cmd);
3338 /* Transition the endpoint from using streams to being a "normal" endpoint
3341 * Modify the endpoint context state, submit a configure endpoint command,
3342 * and free all endpoint rings for streams if that completes successfully.
3344 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3345 struct usb_host_endpoint **eps, unsigned int num_eps,
3349 struct xhci_hcd *xhci;
3350 struct xhci_virt_device *vdev;
3351 struct xhci_command *command;
3352 struct xhci_input_control_ctx *ctrl_ctx;
3353 unsigned int ep_index;
3354 unsigned long flags;
3355 u32 changed_ep_bitmask;
3357 xhci = hcd_to_xhci(hcd);
3358 vdev = xhci->devs[udev->slot_id];
3360 /* Set up a configure endpoint command to remove the streams rings */
3361 spin_lock_irqsave(&xhci->lock, flags);
3362 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3363 udev, eps, num_eps);
3364 if (changed_ep_bitmask == 0) {
3365 spin_unlock_irqrestore(&xhci->lock, flags);
3369 /* Use the xhci_command structure from the first endpoint. We may have
3370 * allocated too many, but the driver may call xhci_free_streams() for
3371 * each endpoint it grouped into one call to xhci_alloc_streams().
3373 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3374 command = vdev->eps[ep_index].stream_info->free_streams_command;
3375 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3377 spin_unlock_irqrestore(&xhci->lock, flags);
3378 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3383 for (i = 0; i < num_eps; i++) {
3384 struct xhci_ep_ctx *ep_ctx;
3386 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3387 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3388 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3389 EP_GETTING_NO_STREAMS;
3391 xhci_endpoint_copy(xhci, command->in_ctx,
3392 vdev->out_ctx, ep_index);
3393 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3394 &vdev->eps[ep_index]);
3396 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3397 vdev->out_ctx, ctrl_ctx,
3398 changed_ep_bitmask, changed_ep_bitmask);
3399 spin_unlock_irqrestore(&xhci->lock, flags);
3401 /* Issue and wait for the configure endpoint command,
3402 * which must succeed.
3404 ret = xhci_configure_endpoint(xhci, udev, command,
3407 /* xHC rejected the configure endpoint command for some reason, so we
3408 * leave the streams rings intact.
3413 spin_lock_irqsave(&xhci->lock, flags);
3414 for (i = 0; i < num_eps; i++) {
3415 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3416 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3417 vdev->eps[ep_index].stream_info = NULL;
3418 /* FIXME Unset maxPstreams in endpoint context and
3419 * update deq ptr to point to normal string ring.
3421 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3422 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3424 spin_unlock_irqrestore(&xhci->lock, flags);
3430 * Deletes endpoint resources for endpoints that were active before a Reset
3431 * Device command, or a Disable Slot command. The Reset Device command leaves
3432 * the control endpoint intact, whereas the Disable Slot command deletes it.
3434 * Must be called with xhci->lock held.
3436 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3437 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3440 unsigned int num_dropped_eps = 0;
3441 unsigned int drop_flags = 0;
3443 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3444 if (virt_dev->eps[i].ring) {
3445 drop_flags |= 1 << i;
3449 xhci->num_active_eps -= num_dropped_eps;
3450 if (num_dropped_eps)
3451 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3452 "Dropped %u ep ctxs, flags = 0x%x, "
3454 num_dropped_eps, drop_flags,
3455 xhci->num_active_eps);
3459 * This submits a Reset Device Command, which will set the device state to 0,
3460 * set the device address to 0, and disable all the endpoints except the default
3461 * control endpoint. The USB core should come back and call
3462 * xhci_address_device(), and then re-set up the configuration. If this is
3463 * called because of a usb_reset_and_verify_device(), then the old alternate
3464 * settings will be re-installed through the normal bandwidth allocation
3467 * Wait for the Reset Device command to finish. Remove all structures
3468 * associated with the endpoints that were disabled. Clear the input device
3469 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3471 * If the virt_dev to be reset does not exist or does not match the udev,
3472 * it means the device is lost, possibly due to the xHC restore error and
3473 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3474 * re-allocate the device.
3476 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3479 unsigned long flags;
3480 struct xhci_hcd *xhci;
3481 unsigned int slot_id;
3482 struct xhci_virt_device *virt_dev;
3483 struct xhci_command *reset_device_cmd;
3484 int last_freed_endpoint;
3485 struct xhci_slot_ctx *slot_ctx;
3486 int old_active_eps = 0;
3488 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3491 xhci = hcd_to_xhci(hcd);
3492 slot_id = udev->slot_id;
3493 virt_dev = xhci->devs[slot_id];
3495 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3496 "not exist. Re-allocate the device\n", slot_id);
3497 ret = xhci_alloc_dev(hcd, udev);
3504 if (virt_dev->tt_info)
3505 old_active_eps = virt_dev->tt_info->active_eps;
3507 if (virt_dev->udev != udev) {
3508 /* If the virt_dev and the udev does not match, this virt_dev
3509 * may belong to another udev.
3510 * Re-allocate the device.
3512 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3513 "not match the udev. Re-allocate the device\n",
3515 ret = xhci_alloc_dev(hcd, udev);
3522 /* If device is not setup, there is no point in resetting it */
3523 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3524 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3525 SLOT_STATE_DISABLED)
3528 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3529 /* Allocate the command structure that holds the struct completion.
3530 * Assume we're in process context, since the normal device reset
3531 * process has to wait for the device anyway. Storage devices are
3532 * reset as part of error handling, so use GFP_NOIO instead of
3535 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3536 if (!reset_device_cmd) {
3537 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3541 /* Attempt to submit the Reset Device command to the command ring */
3542 spin_lock_irqsave(&xhci->lock, flags);
3544 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3546 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3547 spin_unlock_irqrestore(&xhci->lock, flags);
3548 goto command_cleanup;
3550 xhci_ring_cmd_db(xhci);
3551 spin_unlock_irqrestore(&xhci->lock, flags);
3553 /* Wait for the Reset Device command to finish */
3554 wait_for_completion(reset_device_cmd->completion);
3556 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3557 * unless we tried to reset a slot ID that wasn't enabled,
3558 * or the device wasn't in the addressed or configured state.
3560 ret = reset_device_cmd->status;
3562 case COMP_CMD_ABORT:
3564 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3566 goto command_cleanup;
3567 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3568 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3569 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3571 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3572 xhci_dbg(xhci, "Not freeing device rings.\n");
3573 /* Don't treat this as an error. May change my mind later. */
3575 goto command_cleanup;
3577 xhci_dbg(xhci, "Successful reset device command.\n");
3580 if (xhci_is_vendor_info_code(xhci, ret))
3582 xhci_warn(xhci, "Unknown completion code %u for "
3583 "reset device command.\n", ret);
3585 goto command_cleanup;
3588 /* Free up host controller endpoint resources */
3589 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3590 spin_lock_irqsave(&xhci->lock, flags);
3591 /* Don't delete the default control endpoint resources */
3592 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3593 spin_unlock_irqrestore(&xhci->lock, flags);
3596 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3597 last_freed_endpoint = 1;
3598 for (i = 1; i < 31; ++i) {
3599 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3601 if (ep->ep_state & EP_HAS_STREAMS) {
3602 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3603 xhci_get_endpoint_address(i));
3604 xhci_free_stream_info(xhci, ep->stream_info);
3605 ep->stream_info = NULL;
3606 ep->ep_state &= ~EP_HAS_STREAMS;
3610 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3611 last_freed_endpoint = i;
3613 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3614 xhci_drop_ep_from_interval_table(xhci,
3615 &virt_dev->eps[i].bw_info,
3620 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3622 /* If necessary, update the number of active TTs on this root port */
3623 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3625 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3626 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3630 xhci_free_command(xhci, reset_device_cmd);
3635 * At this point, the struct usb_device is about to go away, the device has
3636 * disconnected, and all traffic has been stopped and the endpoints have been
3637 * disabled. Free any HC data structures associated with that device.
3639 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3641 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3642 struct xhci_virt_device *virt_dev;
3643 unsigned long flags;
3646 struct xhci_command *command;
3648 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3652 #ifndef CONFIG_USB_DEFAULT_PERSIST
3654 * We called pm_runtime_get_noresume when the device was attached.
3655 * Decrement the counter here to allow controller to runtime suspend
3656 * if no devices remain.
3658 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3659 pm_runtime_put_noidle(hcd->self.controller);
3662 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3663 /* If the host is halted due to driver unload, we still need to free the
3666 if (ret <= 0 && ret != -ENODEV) {
3671 virt_dev = xhci->devs[udev->slot_id];
3673 /* Stop any wayward timer functions (which may grab the lock) */
3674 for (i = 0; i < 31; ++i) {
3675 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3676 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3679 spin_lock_irqsave(&xhci->lock, flags);
3681 virt_dev->udev = NULL;
3683 /* Don't disable the slot if the host controller is dead. */
3684 state = readl(&xhci->op_regs->status);
3685 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3686 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3687 xhci_free_virt_device(xhci, udev->slot_id);
3688 spin_unlock_irqrestore(&xhci->lock, flags);
3693 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3695 spin_unlock_irqrestore(&xhci->lock, flags);
3696 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3699 xhci_ring_cmd_db(xhci);
3700 spin_unlock_irqrestore(&xhci->lock, flags);
3703 * Event command completion handler will free any data structures
3704 * associated with the slot. XXX Can free sleep?
3709 * Checks if we have enough host controller resources for the default control
3712 * Must be called with xhci->lock held.
3714 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3716 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3717 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3718 "Not enough ep ctxs: "
3719 "%u active, need to add 1, limit is %u.",
3720 xhci->num_active_eps, xhci->limit_active_eps);
3723 xhci->num_active_eps += 1;
3724 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3725 "Adding 1 ep ctx, %u now active.",
3726 xhci->num_active_eps);
3732 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3733 * timed out, or allocating memory failed. Returns 1 on success.
3735 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3737 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3738 unsigned long flags;
3740 struct xhci_command *command;
3742 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3746 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3747 mutex_lock(&xhci->mutex);
3748 spin_lock_irqsave(&xhci->lock, flags);
3749 command->completion = &xhci->addr_dev;
3750 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3752 spin_unlock_irqrestore(&xhci->lock, flags);
3753 mutex_unlock(&xhci->mutex);
3754 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3758 xhci_ring_cmd_db(xhci);
3759 spin_unlock_irqrestore(&xhci->lock, flags);
3761 wait_for_completion(command->completion);
3762 slot_id = xhci->slot_id;
3763 mutex_unlock(&xhci->mutex);
3765 if (!slot_id || command->status != COMP_SUCCESS) {
3766 xhci_err(xhci, "Error while assigning device slot ID\n");
3767 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3769 readl(&xhci->cap_regs->hcs_params1)));
3774 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3775 spin_lock_irqsave(&xhci->lock, flags);
3776 ret = xhci_reserve_host_control_ep_resources(xhci);
3778 spin_unlock_irqrestore(&xhci->lock, flags);
3779 xhci_warn(xhci, "Not enough host resources, "
3780 "active endpoint contexts = %u\n",
3781 xhci->num_active_eps);
3784 spin_unlock_irqrestore(&xhci->lock, flags);
3786 /* Use GFP_NOIO, since this function can be called from
3787 * xhci_discover_or_reset_device(), which may be called as part of
3788 * mass storage driver error handling.
3790 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3791 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3794 udev->slot_id = slot_id;
3796 #ifndef CONFIG_USB_DEFAULT_PERSIST
3798 * If resetting upon resume, we can't put the controller into runtime
3799 * suspend if there is a device attached.
3801 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3802 pm_runtime_get_noresume(hcd->self.controller);
3807 /* Is this a LS or FS device under a HS hub? */
3808 /* Hub or peripherial? */
3812 /* Disable slot, if we can do it without mem alloc */
3813 spin_lock_irqsave(&xhci->lock, flags);
3814 command->completion = NULL;
3815 command->status = 0;
3816 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3818 xhci_ring_cmd_db(xhci);
3819 spin_unlock_irqrestore(&xhci->lock, flags);
3824 * Issue an Address Device command and optionally send a corresponding
3825 * SetAddress request to the device.
3827 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3828 enum xhci_setup_dev setup)
3830 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3831 unsigned long flags;
3832 struct xhci_virt_device *virt_dev;
3834 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3835 struct xhci_slot_ctx *slot_ctx;
3836 struct xhci_input_control_ctx *ctrl_ctx;
3838 struct xhci_command *command = NULL;
3840 mutex_lock(&xhci->mutex);
3842 if (xhci->xhc_state) { /* dying, removing or halted */
3847 if (!udev->slot_id) {
3848 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3849 "Bad Slot ID %d", udev->slot_id);
3854 virt_dev = xhci->devs[udev->slot_id];
3856 if (WARN_ON(!virt_dev)) {
3858 * In plug/unplug torture test with an NEC controller,
3859 * a zero-dereference was observed once due to virt_dev = 0.
3860 * Print useful debug rather than crash if it is observed again!
3862 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3868 if (setup == SETUP_CONTEXT_ONLY) {
3869 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3870 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3871 SLOT_STATE_DEFAULT) {
3872 xhci_dbg(xhci, "Slot already in default state\n");
3877 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3883 command->in_ctx = virt_dev->in_ctx;
3884 command->completion = &xhci->addr_dev;
3886 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3887 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3889 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3895 * If this is the first Set Address since device plug-in or
3896 * virt_device realloaction after a resume with an xHCI power loss,
3897 * then set up the slot context.
3899 if (!slot_ctx->dev_info)
3900 xhci_setup_addressable_virt_dev(xhci, udev);
3901 /* Otherwise, update the control endpoint ring enqueue pointer. */
3903 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3904 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3905 ctrl_ctx->drop_flags = 0;
3907 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3908 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3909 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3910 le32_to_cpu(slot_ctx->dev_info) >> 27);
3912 spin_lock_irqsave(&xhci->lock, flags);
3913 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3914 udev->slot_id, setup);
3916 spin_unlock_irqrestore(&xhci->lock, flags);
3917 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3918 "FIXME: allocate a command ring segment");
3921 xhci_ring_cmd_db(xhci);
3922 spin_unlock_irqrestore(&xhci->lock, flags);
3924 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3925 wait_for_completion(command->completion);
3927 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3928 * the SetAddress() "recovery interval" required by USB and aborting the
3929 * command on a timeout.
3931 switch (command->status) {
3932 case COMP_CMD_ABORT:
3934 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3937 case COMP_CTX_STATE:
3939 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3940 act, udev->slot_id);
3944 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3948 dev_warn(&udev->dev,
3949 "ERROR: Incompatible device for setup %s command\n", act);
3953 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3954 "Successful setup %s command", act);
3958 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3959 act, command->status);
3960 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3961 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3962 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3968 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3969 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3970 "Op regs DCBAA ptr = %#016llx", temp_64);
3971 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3972 "Slot ID %d dcbaa entry @%p = %#016llx",
3974 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3975 (unsigned long long)
3976 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3977 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3978 "Output Context DMA address = %#08llx",
3979 (unsigned long long)virt_dev->out_ctx->dma);
3980 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3981 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3982 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3983 le32_to_cpu(slot_ctx->dev_info) >> 27);
3984 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3985 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3987 * USB core uses address 1 for the roothubs, so we add one to the
3988 * address given back to us by the HC.
3990 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3991 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3992 le32_to_cpu(slot_ctx->dev_info) >> 27);
3993 /* Zero the input context control for later use */
3994 ctrl_ctx->add_flags = 0;
3995 ctrl_ctx->drop_flags = 0;
3997 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3998 "Internal device address = %d",
3999 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4001 mutex_unlock(&xhci->mutex);
4006 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4008 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4011 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4013 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4017 * Transfer the port index into real index in the HW port status
4018 * registers. Caculate offset between the port's PORTSC register
4019 * and port status base. Divide the number of per port register
4020 * to get the real index. The raw port number bases 1.
4022 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4024 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4025 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
4026 __le32 __iomem *addr;
4029 if (hcd->speed < HCD_USB3)
4030 addr = xhci->usb2_ports[port1 - 1];
4032 addr = xhci->usb3_ports[port1 - 1];
4034 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4039 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4040 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4042 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4043 struct usb_device *udev, u16 max_exit_latency)
4045 struct xhci_virt_device *virt_dev;
4046 struct xhci_command *command;
4047 struct xhci_input_control_ctx *ctrl_ctx;
4048 struct xhci_slot_ctx *slot_ctx;
4049 unsigned long flags;
4052 spin_lock_irqsave(&xhci->lock, flags);
4054 virt_dev = xhci->devs[udev->slot_id];
4057 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4058 * xHC was re-initialized. Exit latency will be set later after
4059 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4062 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4063 spin_unlock_irqrestore(&xhci->lock, flags);
4067 /* Attempt to issue an Evaluate Context command to change the MEL. */
4068 command = xhci->lpm_command;
4069 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4071 spin_unlock_irqrestore(&xhci->lock, flags);
4072 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4077 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4078 spin_unlock_irqrestore(&xhci->lock, flags);
4080 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4081 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4082 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4083 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4084 slot_ctx->dev_state = 0;
4086 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4087 "Set up evaluate context for LPM MEL change.");
4088 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4089 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4091 /* Issue and wait for the evaluate context command. */
4092 ret = xhci_configure_endpoint(xhci, udev, command,
4094 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4095 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4098 spin_lock_irqsave(&xhci->lock, flags);
4099 virt_dev->current_mel = max_exit_latency;
4100 spin_unlock_irqrestore(&xhci->lock, flags);
4107 /* BESL to HIRD Encoding array for USB2 LPM */
4108 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4109 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4111 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4112 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4113 struct usb_device *udev)
4115 int u2del, besl, besl_host;
4116 int besl_device = 0;
4119 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4120 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4122 if (field & USB_BESL_SUPPORT) {
4123 for (besl_host = 0; besl_host < 16; besl_host++) {
4124 if (xhci_besl_encoding[besl_host] >= u2del)
4127 /* Use baseline BESL value as default */
4128 if (field & USB_BESL_BASELINE_VALID)
4129 besl_device = USB_GET_BESL_BASELINE(field);
4130 else if (field & USB_BESL_DEEP_VALID)
4131 besl_device = USB_GET_BESL_DEEP(field);
4136 besl_host = (u2del - 51) / 75 + 1;
4139 besl = besl_host + besl_device;
4146 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4147 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4154 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4156 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4157 l1 = udev->l1_params.timeout / 256;
4159 /* device has preferred BESLD */
4160 if (field & USB_BESL_DEEP_VALID) {
4161 besld = USB_GET_BESL_DEEP(field);
4165 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4168 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4169 struct usb_device *udev, int enable)
4171 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4172 __le32 __iomem **port_array;
4173 __le32 __iomem *pm_addr, *hlpm_addr;
4174 u32 pm_val, hlpm_val, field;
4175 unsigned int port_num;
4176 unsigned long flags;
4177 int hird, exit_latency;
4180 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4184 if (!udev->parent || udev->parent->parent ||
4185 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4188 if (udev->usb2_hw_lpm_capable != 1)
4191 spin_lock_irqsave(&xhci->lock, flags);
4193 port_array = xhci->usb2_ports;
4194 port_num = udev->portnum - 1;
4195 pm_addr = port_array[port_num] + PORTPMSC;
4196 pm_val = readl(pm_addr);
4197 hlpm_addr = port_array[port_num] + PORTHLPMC;
4199 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4200 enable ? "enable" : "disable", port_num + 1);
4203 /* Host supports BESL timeout instead of HIRD */
4204 if (udev->usb2_hw_lpm_besl_capable) {
4205 /* if device doesn't have a preferred BESL value use a
4206 * default one which works with mixed HIRD and BESL
4207 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4209 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4210 if ((field & USB_BESL_SUPPORT) &&
4211 (field & USB_BESL_BASELINE_VALID))
4212 hird = USB_GET_BESL_BASELINE(field);
4214 hird = udev->l1_params.besl;
4216 exit_latency = xhci_besl_encoding[hird];
4217 spin_unlock_irqrestore(&xhci->lock, flags);
4219 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4220 * input context for link powermanagement evaluate
4221 * context commands. It is protected by hcd->bandwidth
4222 * mutex and is shared by all devices. We need to set
4223 * the max ext latency in USB 2 BESL LPM as well, so
4224 * use the same mutex and xhci_change_max_exit_latency()
4226 mutex_lock(hcd->bandwidth_mutex);
4227 ret = xhci_change_max_exit_latency(xhci, udev,
4229 mutex_unlock(hcd->bandwidth_mutex);
4233 spin_lock_irqsave(&xhci->lock, flags);
4235 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4236 writel(hlpm_val, hlpm_addr);
4240 hird = xhci_calculate_hird_besl(xhci, udev);
4243 pm_val &= ~PORT_HIRD_MASK;
4244 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4245 writel(pm_val, pm_addr);
4246 pm_val = readl(pm_addr);
4248 writel(pm_val, pm_addr);
4252 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4253 writel(pm_val, pm_addr);
4256 if (udev->usb2_hw_lpm_besl_capable) {
4257 spin_unlock_irqrestore(&xhci->lock, flags);
4258 mutex_lock(hcd->bandwidth_mutex);
4259 xhci_change_max_exit_latency(xhci, udev, 0);
4260 mutex_unlock(hcd->bandwidth_mutex);
4261 readl_poll_timeout(port_array[port_num], pm_val,
4262 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4268 spin_unlock_irqrestore(&xhci->lock, flags);
4272 /* check if a usb2 port supports a given extened capability protocol
4273 * only USB2 ports extended protocol capability values are cached.
4274 * Return 1 if capability is supported
4276 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4277 unsigned capability)
4279 u32 port_offset, port_count;
4282 for (i = 0; i < xhci->num_ext_caps; i++) {
4283 if (xhci->ext_caps[i] & capability) {
4284 /* port offsets starts at 1 */
4285 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4286 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4287 if (port >= port_offset &&
4288 port < port_offset + port_count)
4295 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4297 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4298 int portnum = udev->portnum - 1;
4300 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4304 /* we only support lpm for non-hub device connected to root hub yet */
4305 if (!udev->parent || udev->parent->parent ||
4306 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4309 if (xhci->hw_lpm_support == 1 &&
4310 xhci_check_usb2_port_capability(
4311 xhci, portnum, XHCI_HLC)) {
4312 udev->usb2_hw_lpm_capable = 1;
4313 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4314 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4315 if (xhci_check_usb2_port_capability(xhci, portnum,
4317 udev->usb2_hw_lpm_besl_capable = 1;
4323 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4325 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4326 static unsigned long long xhci_service_interval_to_ns(
4327 struct usb_endpoint_descriptor *desc)
4329 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4332 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4333 enum usb3_link_state state)
4335 unsigned long long sel;
4336 unsigned long long pel;
4337 unsigned int max_sel_pel;
4342 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4343 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4344 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4345 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4349 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4350 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4351 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4355 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4357 return USB3_LPM_DISABLED;
4360 if (sel <= max_sel_pel && pel <= max_sel_pel)
4361 return USB3_LPM_DEVICE_INITIATED;
4363 if (sel > max_sel_pel)
4364 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4365 "due to long SEL %llu ms\n",
4368 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4369 "due to long PEL %llu ms\n",
4371 return USB3_LPM_DISABLED;
4374 /* The U1 timeout should be the maximum of the following values:
4375 * - For control endpoints, U1 system exit latency (SEL) * 3
4376 * - For bulk endpoints, U1 SEL * 5
4377 * - For interrupt endpoints:
4378 * - Notification EPs, U1 SEL * 3
4379 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4380 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4382 static unsigned long long xhci_calculate_intel_u1_timeout(
4383 struct usb_device *udev,
4384 struct usb_endpoint_descriptor *desc)
4386 unsigned long long timeout_ns;
4390 ep_type = usb_endpoint_type(desc);
4392 case USB_ENDPOINT_XFER_CONTROL:
4393 timeout_ns = udev->u1_params.sel * 3;
4395 case USB_ENDPOINT_XFER_BULK:
4396 timeout_ns = udev->u1_params.sel * 5;
4398 case USB_ENDPOINT_XFER_INT:
4399 intr_type = usb_endpoint_interrupt_type(desc);
4400 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4401 timeout_ns = udev->u1_params.sel * 3;
4404 /* Otherwise the calculation is the same as isoc eps */
4405 case USB_ENDPOINT_XFER_ISOC:
4406 timeout_ns = xhci_service_interval_to_ns(desc);
4407 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4408 if (timeout_ns < udev->u1_params.sel * 2)
4409 timeout_ns = udev->u1_params.sel * 2;
4418 /* Returns the hub-encoded U1 timeout value. */
4419 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4420 struct usb_device *udev,
4421 struct usb_endpoint_descriptor *desc)
4423 unsigned long long timeout_ns;
4425 /* Prevent U1 if service interval is shorter than U1 exit latency */
4426 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4427 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4428 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4429 return USB3_LPM_DISABLED;
4433 if (xhci->quirks & XHCI_INTEL_HOST)
4434 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4436 timeout_ns = udev->u1_params.sel;
4438 /* The U1 timeout is encoded in 1us intervals.
4439 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4441 if (timeout_ns == USB3_LPM_DISABLED)
4444 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4446 /* If the necessary timeout value is bigger than what we can set in the
4447 * USB 3.0 hub, we have to disable hub-initiated U1.
4449 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4451 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4452 "due to long timeout %llu ms\n", timeout_ns);
4453 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4456 /* The U2 timeout should be the maximum of:
4457 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4458 * - largest bInterval of any active periodic endpoint (to avoid going
4459 * into lower power link states between intervals).
4460 * - the U2 Exit Latency of the device
4462 static unsigned long long xhci_calculate_intel_u2_timeout(
4463 struct usb_device *udev,
4464 struct usb_endpoint_descriptor *desc)
4466 unsigned long long timeout_ns;
4467 unsigned long long u2_del_ns;
4469 timeout_ns = 10 * 1000 * 1000;
4471 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4472 (xhci_service_interval_to_ns(desc) > timeout_ns))
4473 timeout_ns = xhci_service_interval_to_ns(desc);
4475 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4476 if (u2_del_ns > timeout_ns)
4477 timeout_ns = u2_del_ns;
4482 /* Returns the hub-encoded U2 timeout value. */
4483 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4484 struct usb_device *udev,
4485 struct usb_endpoint_descriptor *desc)
4487 unsigned long long timeout_ns;
4489 /* Prevent U2 if service interval is shorter than U2 exit latency */
4490 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4491 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4492 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4493 return USB3_LPM_DISABLED;
4497 if (xhci->quirks & XHCI_INTEL_HOST)
4498 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4500 timeout_ns = udev->u2_params.sel;
4502 /* The U2 timeout is encoded in 256us intervals */
4503 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4504 /* If the necessary timeout value is bigger than what we can set in the
4505 * USB 3.0 hub, we have to disable hub-initiated U2.
4507 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4509 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4510 "due to long timeout %llu ms\n", timeout_ns);
4511 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4514 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4515 struct usb_device *udev,
4516 struct usb_endpoint_descriptor *desc,
4517 enum usb3_link_state state,
4520 if (state == USB3_LPM_U1)
4521 return xhci_calculate_u1_timeout(xhci, udev, desc);
4522 else if (state == USB3_LPM_U2)
4523 return xhci_calculate_u2_timeout(xhci, udev, desc);
4525 return USB3_LPM_DISABLED;
4528 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4529 struct usb_device *udev,
4530 struct usb_endpoint_descriptor *desc,
4531 enum usb3_link_state state,
4536 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4537 desc, state, timeout);
4539 /* If we found we can't enable hub-initiated LPM, and
4540 * the U1 or U2 exit latency was too high to allow
4541 * device-initiated LPM as well, then we will disable LPM
4542 * for this device, so stop searching any further.
4544 if (alt_timeout == USB3_LPM_DISABLED) {
4545 *timeout = alt_timeout;
4548 if (alt_timeout > *timeout)
4549 *timeout = alt_timeout;
4553 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4554 struct usb_device *udev,
4555 struct usb_host_interface *alt,
4556 enum usb3_link_state state,
4561 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4562 if (xhci_update_timeout_for_endpoint(xhci, udev,
4563 &alt->endpoint[j].desc, state, timeout))
4570 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4571 enum usb3_link_state state)
4573 struct usb_device *parent;
4574 unsigned int num_hubs;
4576 if (state == USB3_LPM_U2)
4579 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4580 for (parent = udev->parent, num_hubs = 0; parent->parent;
4581 parent = parent->parent)
4587 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4588 " below second-tier hub.\n");
4589 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4590 "to decrease power consumption.\n");
4594 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4595 struct usb_device *udev,
4596 enum usb3_link_state state)
4598 if (xhci->quirks & XHCI_INTEL_HOST)
4599 return xhci_check_intel_tier_policy(udev, state);
4604 /* Returns the U1 or U2 timeout that should be enabled.
4605 * If the tier check or timeout setting functions return with a non-zero exit
4606 * code, that means the timeout value has been finalized and we shouldn't look
4607 * at any more endpoints.
4609 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4610 struct usb_device *udev, enum usb3_link_state state)
4612 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4613 struct usb_host_config *config;
4616 u16 timeout = USB3_LPM_DISABLED;
4618 if (state == USB3_LPM_U1)
4620 else if (state == USB3_LPM_U2)
4623 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4628 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4631 /* Gather some information about the currently installed configuration
4632 * and alternate interface settings.
4634 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4638 config = udev->actconfig;
4642 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4643 struct usb_driver *driver;
4644 struct usb_interface *intf = config->interface[i];
4649 /* Check if any currently bound drivers want hub-initiated LPM
4652 if (intf->dev.driver) {
4653 driver = to_usb_driver(intf->dev.driver);
4654 if (driver && driver->disable_hub_initiated_lpm) {
4655 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4656 state_name, driver->name);
4657 timeout = xhci_get_timeout_no_hub_lpm(udev,
4659 if (timeout == USB3_LPM_DISABLED)
4664 /* Not sure how this could happen... */
4665 if (!intf->cur_altsetting)
4668 if (xhci_update_timeout_for_interface(xhci, udev,
4669 intf->cur_altsetting,
4676 static int calculate_max_exit_latency(struct usb_device *udev,
4677 enum usb3_link_state state_changed,
4678 u16 hub_encoded_timeout)
4680 unsigned long long u1_mel_us = 0;
4681 unsigned long long u2_mel_us = 0;
4682 unsigned long long mel_us = 0;
4688 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4689 hub_encoded_timeout == USB3_LPM_DISABLED);
4690 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4691 hub_encoded_timeout == USB3_LPM_DISABLED);
4693 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4694 hub_encoded_timeout != USB3_LPM_DISABLED);
4695 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4696 hub_encoded_timeout != USB3_LPM_DISABLED);
4698 /* If U1 was already enabled and we're not disabling it,
4699 * or we're going to enable U1, account for the U1 max exit latency.
4701 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4703 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4704 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4706 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4708 if (u1_mel_us > u2_mel_us)
4712 /* xHCI host controller max exit latency field is only 16 bits wide. */
4713 if (mel_us > MAX_EXIT) {
4714 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4715 "is too big.\n", mel_us);
4721 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4722 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4723 struct usb_device *udev, enum usb3_link_state state)
4725 struct xhci_hcd *xhci;
4726 u16 hub_encoded_timeout;
4730 xhci = hcd_to_xhci(hcd);
4731 /* The LPM timeout values are pretty host-controller specific, so don't
4732 * enable hub-initiated timeouts unless the vendor has provided
4733 * information about their timeout algorithm.
4735 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4736 !xhci->devs[udev->slot_id])
4737 return USB3_LPM_DISABLED;
4739 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4740 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4742 /* Max Exit Latency is too big, disable LPM. */
4743 hub_encoded_timeout = USB3_LPM_DISABLED;
4747 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4750 return hub_encoded_timeout;
4753 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4754 struct usb_device *udev, enum usb3_link_state state)
4756 struct xhci_hcd *xhci;
4759 xhci = hcd_to_xhci(hcd);
4760 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4761 !xhci->devs[udev->slot_id])
4764 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4765 return xhci_change_max_exit_latency(xhci, udev, mel);
4767 #else /* CONFIG_PM */
4769 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4770 struct usb_device *udev, int enable)
4775 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4780 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4781 struct usb_device *udev, enum usb3_link_state state)
4783 return USB3_LPM_DISABLED;
4786 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4787 struct usb_device *udev, enum usb3_link_state state)
4791 #endif /* CONFIG_PM */
4793 /*-------------------------------------------------------------------------*/
4795 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4796 * internal data structures for the device.
4798 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4799 struct usb_tt *tt, gfp_t mem_flags)
4801 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4802 struct xhci_virt_device *vdev;
4803 struct xhci_command *config_cmd;
4804 struct xhci_input_control_ctx *ctrl_ctx;
4805 struct xhci_slot_ctx *slot_ctx;
4806 unsigned long flags;
4807 unsigned think_time;
4810 /* Ignore root hubs */
4814 vdev = xhci->devs[hdev->slot_id];
4816 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4819 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4821 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4824 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4826 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4828 xhci_free_command(xhci, config_cmd);
4832 spin_lock_irqsave(&xhci->lock, flags);
4833 if (hdev->speed == USB_SPEED_HIGH &&
4834 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4835 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4836 xhci_free_command(xhci, config_cmd);
4837 spin_unlock_irqrestore(&xhci->lock, flags);
4841 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4842 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4843 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4844 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4846 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4847 * but it may be already set to 1 when setup an xHCI virtual
4848 * device, so clear it anyway.
4851 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4852 else if (hdev->speed == USB_SPEED_FULL)
4853 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4855 if (xhci->hci_version > 0x95) {
4856 xhci_dbg(xhci, "xHCI version %x needs hub "
4857 "TT think time and number of ports\n",
4858 (unsigned int) xhci->hci_version);
4859 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4860 /* Set TT think time - convert from ns to FS bit times.
4861 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4862 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4864 * xHCI 1.0: this field shall be 0 if the device is not a
4867 think_time = tt->think_time;
4868 if (think_time != 0)
4869 think_time = (think_time / 666) - 1;
4870 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4871 slot_ctx->tt_info |=
4872 cpu_to_le32(TT_THINK_TIME(think_time));
4874 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4875 "TT think time or number of ports\n",
4876 (unsigned int) xhci->hci_version);
4878 slot_ctx->dev_state = 0;
4879 spin_unlock_irqrestore(&xhci->lock, flags);
4881 xhci_dbg(xhci, "Set up %s for hub device.\n",
4882 (xhci->hci_version > 0x95) ?
4883 "configure endpoint" : "evaluate context");
4884 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4885 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4887 /* Issue and wait for the configure endpoint or
4888 * evaluate context command.
4890 if (xhci->hci_version > 0x95)
4891 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4894 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4897 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4898 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4900 xhci_free_command(xhci, config_cmd);
4904 int xhci_get_frame(struct usb_hcd *hcd)
4906 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4907 /* EHCI mods by the periodic size. Why? */
4908 return readl(&xhci->run_regs->microframe_index) >> 3;
4911 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4913 struct xhci_hcd *xhci;
4914 struct device *dev = hcd->self.controller;
4917 /* Accept arbitrarily long scatter-gather lists */
4918 hcd->self.sg_tablesize = ~0;
4920 /* support to build packet from discontinuous buffers */
4921 hcd->self.no_sg_constraint = 1;
4923 /* XHCI controllers don't stop the ep queue on short packets :| */
4924 hcd->self.no_stop_on_short = 1;
4926 xhci = hcd_to_xhci(hcd);
4928 if (usb_hcd_is_primary_hcd(hcd)) {
4929 xhci->main_hcd = hcd;
4930 /* Mark the first roothub as being USB 2.0.
4931 * The xHCI driver will register the USB 3.0 roothub.
4933 hcd->speed = HCD_USB2;
4934 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4936 * USB 2.0 roothub under xHCI has an integrated TT,
4937 * (rate matching hub) as opposed to having an OHCI/UHCI
4938 * companion controller.
4942 /* Some 3.1 hosts return sbrn 0x30, can't rely on sbrn alone */
4943 if (xhci->sbrn == 0x31 || xhci->usb3_rhub.min_rev >= 1) {
4944 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4945 hcd->speed = HCD_USB31;
4946 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4948 /* xHCI private pointer was set in xhci_pci_probe for the second
4949 * registered roothub.
4954 mutex_init(&xhci->mutex);
4955 xhci->cap_regs = hcd->regs;
4956 xhci->op_regs = hcd->regs +
4957 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4958 xhci->run_regs = hcd->regs +
4959 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4960 /* Cache read-only capability registers */
4961 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4962 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4963 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4964 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4965 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4966 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4967 if (xhci->hci_version > 0x100)
4968 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4969 xhci_print_registers(xhci);
4971 xhci->quirks |= quirks;
4973 get_quirks(dev, xhci);
4975 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4976 * success event after a short transfer. This quirk will ignore such
4979 if (xhci->hci_version > 0x96)
4980 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4982 /* Make sure the HC is halted. */
4983 retval = xhci_halt(xhci);
4987 xhci_dbg(xhci, "Resetting HCD\n");
4988 /* Reset the internal HC memory state and registers. */
4989 retval = xhci_reset(xhci);
4992 xhci_dbg(xhci, "Reset complete\n");
4995 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4996 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4997 * address memory pointers actually. So, this driver clears the AC64
4998 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4999 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5001 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5002 xhci->hcc_params &= ~BIT(0);
5004 /* Set dma_mask and coherent_dma_mask to 64-bits,
5005 * if xHC supports 64-bit addressing */
5006 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5007 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5008 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5009 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5012 * This is to avoid error in cases where a 32-bit USB
5013 * controller is used on a 64-bit capable system.
5015 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5018 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5019 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5022 xhci_dbg(xhci, "Calling HCD init\n");
5023 /* Initialize HCD and host controller data structures. */
5024 retval = xhci_init(hcd);
5027 xhci_dbg(xhci, "Called HCD init\n");
5029 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
5030 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5034 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5036 static const struct hc_driver xhci_hc_driver = {
5037 .description = "xhci-hcd",
5038 .product_desc = "xHCI Host Controller",
5039 .hcd_priv_size = sizeof(struct xhci_hcd),
5042 * generic hardware linkage
5045 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5048 * basic lifecycle operations
5050 .reset = NULL, /* set in xhci_init_driver() */
5053 .shutdown = xhci_shutdown,
5056 * managing i/o requests and associated device resources
5058 .urb_enqueue = xhci_urb_enqueue,
5059 .urb_dequeue = xhci_urb_dequeue,
5060 .alloc_dev = xhci_alloc_dev,
5061 .free_dev = xhci_free_dev,
5062 .alloc_streams = xhci_alloc_streams,
5063 .free_streams = xhci_free_streams,
5064 .add_endpoint = xhci_add_endpoint,
5065 .drop_endpoint = xhci_drop_endpoint,
5066 .endpoint_reset = xhci_endpoint_reset,
5067 .check_bandwidth = xhci_check_bandwidth,
5068 .reset_bandwidth = xhci_reset_bandwidth,
5069 .address_device = xhci_address_device,
5070 .enable_device = xhci_enable_device,
5071 .update_hub_device = xhci_update_hub_device,
5072 .reset_device = xhci_discover_or_reset_device,
5075 * scheduling support
5077 .get_frame_number = xhci_get_frame,
5082 .hub_control = xhci_hub_control,
5083 .hub_status_data = xhci_hub_status_data,
5084 .bus_suspend = xhci_bus_suspend,
5085 .bus_resume = xhci_bus_resume,
5088 * call back when device connected and addressed
5090 .update_device = xhci_update_device,
5091 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5092 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5093 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5094 .find_raw_port_number = xhci_find_raw_port_number,
5097 void xhci_init_driver(struct hc_driver *drv,
5098 const struct xhci_driver_overrides *over)
5102 /* Copy the generic table to drv then apply the overrides */
5103 *drv = xhci_hc_driver;
5106 drv->hcd_priv_size += over->extra_priv_size;
5108 drv->reset = over->reset;
5110 drv->start = over->start;
5113 EXPORT_SYMBOL_GPL(xhci_init_driver);
5115 MODULE_DESCRIPTION(DRIVER_DESC);
5116 MODULE_AUTHOR(DRIVER_AUTHOR);
5117 MODULE_LICENSE("GPL");
5119 static int __init xhci_hcd_init(void)
5122 * Check the compiler generated sizes of structures that must be laid
5123 * out in specific ways for hardware access.
5125 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5126 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5127 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5128 /* xhci_device_control has eight fields, and also
5129 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5131 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5132 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5133 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5134 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5135 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5136 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5137 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5146 * If an init function is provided, an exit function must also be provided
5147 * to allow module unload.
5149 static void __exit xhci_hcd_fini(void) { }
5151 module_init(xhci_hcd_init);
5152 module_exit(xhci_hcd_fini);