1 // SPDX-License-Identifier: GPL-2.0
4 * xHCI host controller driver
6 * Copyright (C) 2008 Intel Corp.
9 * Some code borrowed from the Linux EHCI driver.
12 #ifndef __LINUX_XHCI_HCD_H
13 #define __LINUX_XHCI_HCD_H
15 #include <linux/usb.h>
16 #include <linux/timer.h>
17 #include <linux/kernel.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
21 /* Code sharing between pci-quirks and xhci hcd */
22 #include "xhci-ext-caps.h"
23 #include "pci-quirks.h"
25 /* xHCI PCI Configuration Registers */
26 #define XHCI_SBRN_OFFSET (0x60)
28 /* Max number of USB devices for any host controller - limit in section 6.1 */
29 #define MAX_HC_SLOTS 256
30 /* Section 5.3.3 - MaxPorts */
31 #define MAX_HC_PORTS 127
34 * xHCI register interface.
35 * This corresponds to the eXtensible Host Controller Interface (xHCI)
36 * Revision 0.95 specification
40 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
41 * @hc_capbase: length of the capabilities register and HC version number
42 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
43 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
44 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
45 * @hcc_params: HCCPARAMS - Capability Parameters
46 * @db_off: DBOFF - Doorbell array offset
47 * @run_regs_off: RTSOFF - Runtime register space offset
48 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
50 struct xhci_cap_regs {
58 __le32 hcc_params2; /* xhci 1.1 */
59 /* Reserved up to (CAPLENGTH - 0x1C) */
62 /* hc_capbase bitmasks */
63 /* bits 7:0 - how long is the Capabilities register */
64 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
66 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
68 /* HCSPARAMS1 - hcs_params1 - bitmasks */
69 /* bits 0:7, Max Device Slots */
70 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
71 #define HCS_SLOTS_MASK 0xff
72 /* bits 8:18, Max Interrupters */
73 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
74 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
75 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
77 /* HCSPARAMS2 - hcs_params2 - bitmasks */
78 /* bits 0:3, frames or uframes that SW needs to queue transactions
79 * ahead of the HW to meet periodic deadlines */
80 #define HCS_IST(p) (((p) >> 0) & 0xf)
81 /* bits 4:7, max number of Event Ring segments */
82 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
83 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
84 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
85 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
86 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
88 /* HCSPARAMS3 - hcs_params3 - bitmasks */
89 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
90 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
91 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
92 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
94 /* HCCPARAMS - hcc_params - bitmasks */
95 /* true: HC can use 64-bit address pointers */
96 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
97 /* true: HC can do bandwidth negotiation */
98 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
99 /* true: HC uses 64-byte Device Context structures
100 * FIXME 64-byte context structures aren't supported yet.
102 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
103 /* true: HC has port power switches */
104 #define HCC_PPC(p) ((p) & (1 << 3))
105 /* true: HC has port indicators */
106 #define HCS_INDICATOR(p) ((p) & (1 << 4))
107 /* true: HC has Light HC Reset Capability */
108 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
109 /* true: HC supports latency tolerance messaging */
110 #define HCC_LTC(p) ((p) & (1 << 6))
111 /* true: no secondary Stream ID Support */
112 #define HCC_NSS(p) ((p) & (1 << 7))
113 /* true: HC supports Stopped - Short Packet */
114 #define HCC_SPC(p) ((p) & (1 << 9))
115 /* true: HC has Contiguous Frame ID Capability */
116 #define HCC_CFC(p) ((p) & (1 << 11))
117 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
118 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
119 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
120 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
122 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
124 /* db_off bitmask - bits 0:1 reserved */
125 #define DBOFF_MASK (~0x3)
127 /* run_regs_off bitmask - bits 0:4 reserved */
128 #define RTSOFF_MASK (~0x1f)
130 /* HCCPARAMS2 - hcc_params2 - bitmasks */
131 /* true: HC supports U3 entry Capability */
132 #define HCC2_U3C(p) ((p) & (1 << 0))
133 /* true: HC supports Configure endpoint command Max exit latency too large */
134 #define HCC2_CMC(p) ((p) & (1 << 1))
135 /* true: HC supports Force Save context Capability */
136 #define HCC2_FSC(p) ((p) & (1 << 2))
137 /* true: HC supports Compliance Transition Capability */
138 #define HCC2_CTC(p) ((p) & (1 << 3))
139 /* true: HC support Large ESIT payload Capability > 48k */
140 #define HCC2_LEC(p) ((p) & (1 << 4))
141 /* true: HC support Configuration Information Capability */
142 #define HCC2_CIC(p) ((p) & (1 << 5))
143 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
144 #define HCC2_ETC(p) ((p) & (1 << 6))
146 /* Number of registers per port */
147 #define NUM_PORT_REGS 4
155 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
156 * @command: USBCMD - xHC command register
157 * @status: USBSTS - xHC status register
158 * @page_size: This indicates the page size that the host controller
159 * supports. If bit n is set, the HC supports a page size
160 * of 2^(n+12), up to a 128MB page size.
161 * 4K is the minimum page size.
162 * @cmd_ring: CRP - 64-bit Command Ring Pointer
163 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
164 * @config_reg: CONFIG - Configure Register
165 * @port_status_base: PORTSCn - base address for Port Status and Control
166 * Each port has a Port Status and Control register,
167 * followed by a Port Power Management Status and Control
168 * register, a Port Link Info register, and a reserved
170 * @port_power_base: PORTPMSCn - base address for
171 * Port Power Management Status and Control
172 * @port_link_base: PORTLIn - base address for Port Link Info (current
173 * Link PM state and control) for USB 2.1 and USB 3.0
176 struct xhci_op_regs {
182 __le32 dev_notification;
184 /* rsvd: offset 0x20-2F */
188 /* rsvd: offset 0x3C-3FF */
189 __le32 reserved4[241];
190 /* port 1 registers, which serve as a base address for other ports */
191 __le32 port_status_base;
192 __le32 port_power_base;
193 __le32 port_link_base;
195 /* registers for ports 2-255 */
196 __le32 reserved6[NUM_PORT_REGS*254];
199 /* USBCMD - USB command - command bitmasks */
200 /* start/stop HC execution - do not write unless HC is halted*/
201 #define CMD_RUN XHCI_CMD_RUN
202 /* Reset HC - resets internal HC state machine and all registers (except
203 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
204 * The xHCI driver must reinitialize the xHC after setting this bit.
206 #define CMD_RESET (1 << 1)
207 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
208 #define CMD_EIE XHCI_CMD_EIE
209 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
210 #define CMD_HSEIE XHCI_CMD_HSEIE
211 /* bits 4:6 are reserved (and should be preserved on writes). */
212 /* light reset (port status stays unchanged) - reset completed when this is 0 */
213 #define CMD_LRESET (1 << 7)
214 /* host controller save/restore state. */
215 #define CMD_CSS (1 << 8)
216 #define CMD_CRS (1 << 9)
217 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
218 #define CMD_EWE XHCI_CMD_EWE
219 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
220 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
221 * '0' means the xHC can power it off if all ports are in the disconnect,
222 * disabled, or powered-off state.
224 #define CMD_PM_INDEX (1 << 11)
225 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
226 #define CMD_ETE (1 << 14)
227 /* bits 15:31 are reserved (and should be preserved on writes). */
229 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
230 #define XHCI_RESET_SHORT_USEC (250 * 1000)
232 /* IMAN - Interrupt Management Register */
233 #define IMAN_IE (1 << 1)
234 #define IMAN_IP (1 << 0)
236 /* USBSTS - USB status - status bitmasks */
237 /* HC not running - set to 1 when run/stop bit is cleared. */
238 #define STS_HALT XHCI_STS_HALT
239 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
240 #define STS_FATAL (1 << 2)
241 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
242 #define STS_EINT (1 << 3)
243 /* port change detect */
244 #define STS_PORT (1 << 4)
245 /* bits 5:7 reserved and zeroed */
246 /* save state status - '1' means xHC is saving state */
247 #define STS_SAVE (1 << 8)
248 /* restore state status - '1' means xHC is restoring state */
249 #define STS_RESTORE (1 << 9)
250 /* true: save or restore error */
251 #define STS_SRE (1 << 10)
252 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
253 #define STS_CNR XHCI_STS_CNR
254 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
255 #define STS_HCE (1 << 12)
256 /* bits 13:31 reserved and should be preserved */
259 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
260 * Generate a device notification event when the HC sees a transaction with a
261 * notification type that matches a bit set in this bit field.
263 #define DEV_NOTE_MASK (0xffff)
264 #define ENABLE_DEV_NOTE(x) (1 << (x))
265 /* Most of the device notification types should only be used for debug.
266 * SW does need to pay attention to function wake notifications.
268 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
270 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
271 /* bit 0 is the command ring cycle state */
272 /* stop ring operation after completion of the currently executing command */
273 #define CMD_RING_PAUSE (1 << 1)
274 /* stop ring immediately - abort the currently executing command */
275 #define CMD_RING_ABORT (1 << 2)
276 /* true: command ring is running */
277 #define CMD_RING_RUNNING (1 << 3)
278 /* bits 4:5 reserved and should be preserved */
279 /* Command Ring pointer - bit mask for the lower 32 bits. */
280 #define CMD_RING_RSVD_BITS (0x3f)
282 /* CONFIG - Configure Register - config_reg bitmasks */
283 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
284 #define MAX_DEVS(p) ((p) & 0xff)
285 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
286 #define CONFIG_U3E (1 << 8)
287 /* bit 9: Configuration Information Enable, xhci 1.1 */
288 #define CONFIG_CIE (1 << 9)
289 /* bits 10:31 - reserved and should be preserved */
291 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
292 /* true: device connected */
293 #define PORT_CONNECT (1 << 0)
294 /* true: port enabled */
295 #define PORT_PE (1 << 1)
296 /* bit 2 reserved and zeroed */
297 /* true: port has an over-current condition */
298 #define PORT_OC (1 << 3)
299 /* true: port reset signaling asserted */
300 #define PORT_RESET (1 << 4)
301 /* Port Link State - bits 5:8
302 * A read gives the current link PM state of the port,
303 * a write with Link State Write Strobe set sets the link state.
305 #define PORT_PLS_MASK (0xf << 5)
306 #define XDEV_U0 (0x0 << 5)
307 #define XDEV_U1 (0x1 << 5)
308 #define XDEV_U2 (0x2 << 5)
309 #define XDEV_U3 (0x3 << 5)
310 #define XDEV_DISABLED (0x4 << 5)
311 #define XDEV_RXDETECT (0x5 << 5)
312 #define XDEV_INACTIVE (0x6 << 5)
313 #define XDEV_POLLING (0x7 << 5)
314 #define XDEV_RECOVERY (0x8 << 5)
315 #define XDEV_HOT_RESET (0x9 << 5)
316 #define XDEV_COMP_MODE (0xa << 5)
317 #define XDEV_TEST_MODE (0xb << 5)
318 #define XDEV_RESUME (0xf << 5)
320 /* true: port has power (see HCC_PPC) */
321 #define PORT_POWER (1 << 9)
322 /* bits 10:13 indicate device speed:
323 * 0 - undefined speed - port hasn't be initialized by a reset yet
330 #define DEV_SPEED_MASK (0xf << 10)
331 #define XDEV_FS (0x1 << 10)
332 #define XDEV_LS (0x2 << 10)
333 #define XDEV_HS (0x3 << 10)
334 #define XDEV_SS (0x4 << 10)
335 #define XDEV_SSP (0x5 << 10)
336 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
337 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
338 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
339 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
340 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
341 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
342 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
343 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
345 /* Bits 20:23 in the Slot Context are the speed for the device */
346 #define SLOT_SPEED_FS (XDEV_FS << 10)
347 #define SLOT_SPEED_LS (XDEV_LS << 10)
348 #define SLOT_SPEED_HS (XDEV_HS << 10)
349 #define SLOT_SPEED_SS (XDEV_SS << 10)
350 #define SLOT_SPEED_SSP (XDEV_SSP << 10)
351 /* Port Indicator Control */
352 #define PORT_LED_OFF (0 << 14)
353 #define PORT_LED_AMBER (1 << 14)
354 #define PORT_LED_GREEN (2 << 14)
355 #define PORT_LED_MASK (3 << 14)
356 /* Port Link State Write Strobe - set this when changing link state */
357 #define PORT_LINK_STROBE (1 << 16)
358 /* true: connect status change */
359 #define PORT_CSC (1 << 17)
360 /* true: port enable change */
361 #define PORT_PEC (1 << 18)
362 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
363 * into an enabled state, and the device into the default state. A "warm" reset
364 * also resets the link, forcing the device through the link training sequence.
365 * SW can also look at the Port Reset register to see when warm reset is done.
367 #define PORT_WRC (1 << 19)
368 /* true: over-current change */
369 #define PORT_OCC (1 << 20)
370 /* true: reset change - 1 to 0 transition of PORT_RESET */
371 #define PORT_RC (1 << 21)
372 /* port link status change - set on some port link state transitions:
374 * ------------------------------------------------------------------------------
375 * - U3 to Resume Wakeup signaling from a device
376 * - Resume to Recovery to U0 USB 3.0 device resume
377 * - Resume to U0 USB 2.0 device resume
378 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
379 * - U3 to U0 Software resume of USB 2.0 device complete
380 * - U2 to U0 L1 resume of USB 2.1 device complete
381 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
382 * - U0 to disabled L1 entry error with USB 2.1 device
383 * - Any state to inactive Error on USB 3.0 port
385 #define PORT_PLC (1 << 22)
386 /* port configure error change - port failed to configure its link partner */
387 #define PORT_CEC (1 << 23)
388 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
389 PORT_RC | PORT_PLC | PORT_CEC)
392 /* Cold Attach Status - xHC can set this bit to report device attached during
393 * Sx state. Warm port reset should be perfomed to clear this bit and move port
394 * to connected state.
396 #define PORT_CAS (1 << 24)
397 /* wake on connect (enable) */
398 #define PORT_WKCONN_E (1 << 25)
399 /* wake on disconnect (enable) */
400 #define PORT_WKDISC_E (1 << 26)
401 /* wake on over-current (enable) */
402 #define PORT_WKOC_E (1 << 27)
403 /* bits 28:29 reserved */
404 /* true: device is non-removable - for USB 3.0 roothub emulation */
405 #define PORT_DEV_REMOVE (1 << 30)
406 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
407 #define PORT_WR (1 << 31)
409 /* We mark duplicate entries with -1 */
410 #define DUPLICATE_ENTRY ((u8)(-1))
412 /* Port Power Management Status and Control - port_power_base bitmasks */
413 /* Inactivity timer value for transitions into U1, in microseconds.
414 * Timeout can be up to 127us. 0xFF means an infinite timeout.
416 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
417 #define PORT_U1_TIMEOUT_MASK 0xff
418 /* Inactivity timer value for transitions into U2 */
419 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
420 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
421 /* Bits 24:31 for port testing */
423 /* USB2 Protocol PORTSPMSC */
424 #define PORT_L1S_MASK 7
425 #define PORT_L1S_SUCCESS 1
426 #define PORT_RWE (1 << 3)
427 #define PORT_HIRD(p) (((p) & 0xf) << 4)
428 #define PORT_HIRD_MASK (0xf << 4)
429 #define PORT_L1DS_MASK (0xff << 8)
430 #define PORT_L1DS(p) (((p) & 0xff) << 8)
431 #define PORT_HLE (1 << 16)
432 #define PORT_TEST_MODE_SHIFT 28
434 /* USB3 Protocol PORTLI Port Link Information */
435 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
436 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
438 /* USB2 Protocol PORTHLPMC */
439 #define PORT_HIRDM(p)((p) & 3)
440 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
441 #define PORT_BESLD(p)(((p) & 0xf) << 10)
443 /* use 512 microseconds as USB2 LPM L1 default timeout. */
444 #define XHCI_L1_TIMEOUT 512
446 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
447 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
448 * by other operating systems.
450 * XHCI 1.0 errata 8/14/12 Table 13 notes:
451 * "Software should choose xHC BESL/BESLD field values that do not violate a
452 * device's resume latency requirements,
453 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
454 * or not program values < '4' if BLC = '0' and a BESL device is attached.
456 #define XHCI_DEFAULT_BESL 4
459 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
460 * to complete link training. usually link trainig completes much faster
461 * so check status 10 times with 36ms sleep in places we need to wait for
462 * polling to complete.
464 #define XHCI_PORT_POLLING_LFPS_TIME 36
467 * struct xhci_intr_reg - Interrupt Register Set
468 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
469 * interrupts and check for pending interrupts.
470 * @irq_control: IMOD - Interrupt Moderation Register.
471 * Used to throttle interrupts.
472 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
473 * @erst_base: ERST base address.
474 * @erst_dequeue: Event ring dequeue pointer.
476 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
477 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
478 * multiple segments of the same size. The HC places events on the ring and
479 * "updates the Cycle bit in the TRBs to indicate to software the current
480 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
481 * updates the dequeue pointer.
483 struct xhci_intr_reg {
492 /* irq_pending bitmasks */
493 #define ER_IRQ_PENDING(p) ((p) & 0x1)
494 /* bits 2:31 need to be preserved */
495 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
496 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
497 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
498 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
500 /* irq_control bitmasks */
501 /* Minimum interval between interrupts (in 250ns intervals). The interval
502 * between interrupts will be longer if there are no events on the event ring.
503 * Default is 4000 (1 ms).
505 #define ER_IRQ_INTERVAL_MASK (0xffff)
506 /* Counter used to count down the time to the next interrupt - HW use only */
507 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
509 /* erst_size bitmasks */
510 /* Preserve bits 16:31 of erst_size */
511 #define ERST_SIZE_MASK (0xffff << 16)
513 /* erst_dequeue bitmasks */
514 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
515 * where the current dequeue pointer lies. This is an optional HW hint.
517 #define ERST_DESI_MASK (0x7)
518 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
519 * a work queue (or delayed service routine)?
521 #define ERST_EHB (1 << 3)
522 #define ERST_PTR_MASK (0xf)
525 * struct xhci_run_regs
527 * MFINDEX - current microframe number
529 * Section 5.5 Host Controller Runtime Registers:
530 * "Software should read and write these registers using only Dword (32 bit)
531 * or larger accesses"
533 struct xhci_run_regs {
534 __le32 microframe_index;
536 struct xhci_intr_reg ir_set[128];
540 * struct doorbell_array
542 * Bits 0 - 7: Endpoint target
544 * Bits 16 - 31: Stream ID
548 struct xhci_doorbell_array {
549 __le32 doorbell[256];
552 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
553 #define DB_VALUE_HOST 0x00000000
556 * struct xhci_protocol_caps
557 * @revision: major revision, minor revision, capability ID,
558 * and next capability pointer.
559 * @name_string: Four ASCII characters to say which spec this xHC
560 * follows, typically "USB ".
561 * @port_info: Port offset, count, and protocol-defined information.
563 struct xhci_protocol_caps {
569 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
570 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
571 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
572 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
573 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
575 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
576 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
577 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
578 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
579 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
580 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
582 #define PLT_MASK (0x03 << 6)
583 #define PLT_SYM (0x00 << 6)
584 #define PLT_ASYM_RX (0x02 << 6)
585 #define PLT_ASYM_TX (0x03 << 6)
588 * struct xhci_container_ctx
589 * @type: Type of context. Used to calculated offsets to contained contexts.
590 * @size: Size of the context data
591 * @bytes: The raw context data given to HW
592 * @dma: dma address of the bytes
594 * Represents either a Device or Input context. Holds a pointer to the raw
595 * memory used for the context (bytes) and dma address of it (dma).
597 struct xhci_container_ctx {
599 #define XHCI_CTX_TYPE_DEVICE 0x1
600 #define XHCI_CTX_TYPE_INPUT 0x2
609 * struct xhci_slot_ctx
610 * @dev_info: Route string, device speed, hub info, and last valid endpoint
611 * @dev_info2: Max exit latency for device number, root hub port number
612 * @tt_info: tt_info is used to construct split transaction tokens
613 * @dev_state: slot state and device address
615 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
616 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
617 * reserved at the end of the slot context for HC internal use.
619 struct xhci_slot_ctx {
624 /* offset 0x10 to 0x1f reserved for HC internal use */
628 /* dev_info bitmasks */
629 /* Route String - 0:19 */
630 #define ROUTE_STRING_MASK (0xfffff)
631 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
632 #define DEV_SPEED (0xf << 20)
633 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
634 /* bit 24 reserved */
635 /* Is this LS/FS device connected through a HS hub? - bit 25 */
636 #define DEV_MTT (0x1 << 25)
637 /* Set if the device is a hub - bit 26 */
638 #define DEV_HUB (0x1 << 26)
639 /* Index of the last valid endpoint context in this device context - 27:31 */
640 #define LAST_CTX_MASK (0x1f << 27)
641 #define LAST_CTX(p) ((p) << 27)
642 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
643 #define SLOT_FLAG (1 << 0)
644 #define EP0_FLAG (1 << 1)
646 /* dev_info2 bitmasks */
647 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
648 #define MAX_EXIT (0xffff)
649 /* Root hub port number that is needed to access the USB device */
650 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
651 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
652 /* Maximum number of ports under a hub device */
653 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
654 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
656 /* tt_info bitmasks */
658 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
659 * The Slot ID of the hub that isolates the high speed signaling from
660 * this low or full-speed device. '0' if attached to root hub port.
662 #define TT_SLOT (0xff)
664 * The number of the downstream facing port of the high-speed hub
665 * '0' if the device is not low or full speed.
667 #define TT_PORT (0xff << 8)
668 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
669 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
671 /* dev_state bitmasks */
672 /* USB device address - assigned by the HC */
673 #define DEV_ADDR_MASK (0xff)
674 /* bits 8:26 reserved */
676 #define SLOT_STATE (0x1f << 27)
677 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
679 #define SLOT_STATE_DISABLED 0
680 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
681 #define SLOT_STATE_DEFAULT 1
682 #define SLOT_STATE_ADDRESSED 2
683 #define SLOT_STATE_CONFIGURED 3
687 * @ep_info: endpoint state, streams, mult, and interval information.
688 * @ep_info2: information on endpoint type, max packet size, max burst size,
689 * error count, and whether the HC will force an event for all
691 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
692 * defines one stream, this points to the endpoint transfer ring.
693 * Otherwise, it points to a stream context array, which has a
694 * ring pointer for each flow.
696 * Average TRB lengths for the endpoint ring and
697 * max payload within an Endpoint Service Interval Time (ESIT).
699 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
700 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
701 * reserved at the end of the endpoint context for HC internal use.
708 /* offset 0x14 - 0x1f reserved for HC internal use */
712 /* ep_info bitmasks */
714 * Endpoint State - bits 0:2
717 * 2 - halted due to halt condition - ok to manipulate endpoint ring
722 #define EP_STATE_MASK (0x7)
723 #define EP_STATE_DISABLED 0
724 #define EP_STATE_RUNNING 1
725 #define EP_STATE_HALTED 2
726 #define EP_STATE_STOPPED 3
727 #define EP_STATE_ERROR 4
728 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
730 /* Mult - Max number of burtst within an interval, in EP companion desc. */
731 #define EP_MULT(p) (((p) & 0x3) << 8)
732 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
733 /* bits 10:14 are Max Primary Streams */
734 /* bit 15 is Linear Stream Array */
735 /* Interval - period between requests to an endpoint - 125u increments. */
736 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
737 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
738 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
739 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
740 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
741 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
742 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
743 #define EP_HAS_LSA (1 << 15)
744 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
745 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
747 /* ep_info2 bitmasks */
749 * Force Event - generate transfer events for all TRBs for this endpoint
750 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
752 #define FORCE_EVENT (0x1)
753 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
754 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
755 #define EP_TYPE(p) ((p) << 3)
756 #define ISOC_OUT_EP 1
757 #define BULK_OUT_EP 2
764 /* bit 7 is Host Initiate Disable - for disabling stream selection */
765 #define MAX_BURST(p) (((p)&0xff) << 8)
766 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
767 #define MAX_PACKET(p) (((p)&0xffff) << 16)
768 #define MAX_PACKET_MASK (0xffff << 16)
769 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
771 /* tx_info bitmasks */
772 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
773 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
774 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
775 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
778 #define EP_CTX_CYCLE_MASK (1 << 0)
779 #define SCTX_DEQ_MASK (~0xfL)
783 * struct xhci_input_control_context
784 * Input control context; see section 6.2.5.
786 * @drop_context: set the bit of the endpoint context you want to disable
787 * @add_context: set the bit of the endpoint context you want to enable
789 struct xhci_input_control_ctx {
795 #define EP_IS_ADDED(ctrl_ctx, i) \
796 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
797 #define EP_IS_DROPPED(ctrl_ctx, i) \
798 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
800 /* Represents everything that is needed to issue a command on the command ring.
801 * It's useful to pre-allocate these for commands that cannot fail due to
802 * out-of-memory errors, like freeing streams.
804 struct xhci_command {
805 /* Input context for changing device state */
806 struct xhci_container_ctx *in_ctx;
809 /* If completion is null, no one is waiting on this command
810 * and the structure can be freed after the command completes.
812 struct completion *completion;
813 union xhci_trb *command_trb;
814 struct list_head cmd_list;
817 /* drop context bitmasks */
818 #define DROP_EP(x) (0x1 << x)
819 /* add context bitmasks */
820 #define ADD_EP(x) (0x1 << x)
822 struct xhci_stream_ctx {
823 /* 64-bit stream ring address, cycle state, and stream type */
825 /* offset 0x14 - 0x1f reserved for HC internal use */
829 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
830 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
831 /* Secondary stream array type, dequeue pointer is to a transfer ring */
833 /* Primary stream array type, dequeue pointer is to a transfer ring */
835 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
840 #define SCT_SSA_128 6
841 #define SCT_SSA_256 7
843 /* Assume no secondary streams for now */
844 struct xhci_stream_info {
845 struct xhci_ring **stream_rings;
846 /* Number of streams, including stream 0 (which drivers can't use) */
847 unsigned int num_streams;
848 /* The stream context array may be bigger than
849 * the number of streams the driver asked for
851 struct xhci_stream_ctx *stream_ctx_array;
852 unsigned int num_stream_ctxs;
853 dma_addr_t ctx_array_dma;
854 /* For mapping physical TRB addresses to segments in stream rings */
855 struct radix_tree_root trb_address_map;
856 struct xhci_command *free_streams_command;
859 #define SMALL_STREAM_ARRAY_SIZE 256
860 #define MEDIUM_STREAM_ARRAY_SIZE 1024
862 /* Some Intel xHCI host controllers need software to keep track of the bus
863 * bandwidth. Keep track of endpoint info here. Each root port is allocated
864 * the full bus bandwidth. We must also treat TTs (including each port under a
865 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
866 * (DMI) also limits the total bandwidth (across all domains) that can be used.
868 struct xhci_bw_info {
869 /* ep_interval is zero-based */
870 unsigned int ep_interval;
871 /* mult and num_packets are one-based */
873 unsigned int num_packets;
874 unsigned int max_packet_size;
875 unsigned int max_esit_payload;
879 /* "Block" sizes in bytes the hardware uses for different device speeds.
880 * The logic in this part of the hardware limits the number of bits the hardware
881 * can use, so must represent bandwidth in a less precise manner to mimic what
882 * the scheduler hardware computes.
889 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
890 * with each byte transferred. SuperSpeed devices have an initial overhead to
891 * set up bursts. These are in blocks, see above. LS overhead has already been
892 * translated into FS blocks.
894 #define DMI_OVERHEAD 8
895 #define DMI_OVERHEAD_BURST 4
896 #define SS_OVERHEAD 8
897 #define SS_OVERHEAD_BURST 32
898 #define HS_OVERHEAD 26
899 #define FS_OVERHEAD 20
900 #define LS_OVERHEAD 128
901 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
902 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
903 * of overhead associated with split transfers crossing microframe boundaries.
904 * 31 blocks is pure protocol overhead.
906 #define TT_HS_OVERHEAD (31 + 94)
907 #define TT_DMI_OVERHEAD (25 + 12)
909 /* Bandwidth limits in blocks */
910 #define FS_BW_LIMIT 1285
911 #define TT_BW_LIMIT 1320
912 #define HS_BW_LIMIT 1607
913 #define SS_BW_LIMIT_IN 3906
914 #define DMI_BW_LIMIT_IN 3906
915 #define SS_BW_LIMIT_OUT 3906
916 #define DMI_BW_LIMIT_OUT 3906
918 /* Percentage of bus bandwidth reserved for non-periodic transfers */
919 #define FS_BW_RESERVED 10
920 #define HS_BW_RESERVED 20
921 #define SS_BW_RESERVED 10
923 struct xhci_virt_ep {
924 struct xhci_ring *ring;
925 /* Related to endpoints that are configured to use stream IDs only */
926 struct xhci_stream_info *stream_info;
927 /* Temporary storage in case the configure endpoint command fails and we
928 * have to restore the device state to the previous state
930 struct xhci_ring *new_ring;
931 unsigned int ep_state;
932 #define SET_DEQ_PENDING (1 << 0)
933 #define EP_HALTED (1 << 1) /* For stall handling */
934 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
935 /* Transitioning the endpoint to using streams, don't enqueue URBs */
936 #define EP_GETTING_STREAMS (1 << 3)
937 #define EP_HAS_STREAMS (1 << 4)
938 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
939 #define EP_GETTING_NO_STREAMS (1 << 5)
940 #define EP_HARD_CLEAR_TOGGLE (1 << 6)
941 #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
942 /* ---- Related to URB cancellation ---- */
943 struct list_head cancelled_td_list;
944 /* Watchdog timer for stop endpoint command to cancel URBs */
945 struct timer_list stop_cmd_timer;
946 struct xhci_hcd *xhci;
947 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
948 * command. We'll need to update the ring's dequeue segment and dequeue
949 * pointer after the command completes.
951 struct xhci_segment *queued_deq_seg;
952 union xhci_trb *queued_deq_ptr;
954 * Sometimes the xHC can not process isochronous endpoint ring quickly
955 * enough, and it will miss some isoc tds on the ring and generate
956 * a Missed Service Error Event.
957 * Set skip flag when receive a Missed Service Error Event and
958 * process the missed tds on the endpoint ring.
961 /* Bandwidth checking storage */
962 struct xhci_bw_info bw_info;
963 struct list_head bw_endpoint_list;
964 /* Isoch Frame ID checking storage */
966 /* Use new Isoch TRB layout needed for extended TBC support */
967 bool use_extended_tbc;
970 enum xhci_overhead_type {
971 LS_OVERHEAD_TYPE = 0,
976 struct xhci_interval_bw {
977 unsigned int num_packets;
978 /* Sorted by max packet size.
979 * Head of the list is the greatest max packet size.
981 struct list_head endpoints;
982 /* How many endpoints of each speed are present. */
983 unsigned int overhead[3];
986 #define XHCI_MAX_INTERVAL 16
988 struct xhci_interval_bw_table {
989 unsigned int interval0_esit_payload;
990 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
991 /* Includes reserved bandwidth for async endpoints */
992 unsigned int bw_used;
993 unsigned int ss_bw_in;
994 unsigned int ss_bw_out;
997 #define EP_CTX_PER_DEV 31
999 struct xhci_virt_device {
1000 struct usb_device *udev;
1002 * Commands to the hardware are passed an "input context" that
1003 * tells the hardware what to change in its data structures.
1004 * The hardware will return changes in an "output context" that
1005 * software must allocate for the hardware. We need to keep
1006 * track of input and output contexts separately because
1007 * these commands might fail and we don't trust the hardware.
1009 struct xhci_container_ctx *out_ctx;
1010 /* Used for addressing devices and configuration changes */
1011 struct xhci_container_ctx *in_ctx;
1012 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1015 struct xhci_interval_bw_table *bw_table;
1016 struct xhci_tt_bw_info *tt_info;
1018 * flags for state tracking based on events and issued commands.
1019 * Software can not rely on states from output contexts because of
1020 * latency between events and xHC updating output context values.
1021 * See xhci 1.1 section 4.8.3 for more details
1023 unsigned long flags;
1024 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1026 /* The current max exit latency for the enabled USB3 link states. */
1028 /* Used for the debugfs interfaces. */
1029 void *debugfs_private;
1033 * For each roothub, keep track of the bandwidth information for each periodic
1036 * If a high speed hub is attached to the roothub, each TT associated with that
1037 * hub is a separate bandwidth domain. The interval information for the
1038 * endpoints on the devices under that TT will appear in the TT structure.
1040 struct xhci_root_port_bw_info {
1041 struct list_head tts;
1042 unsigned int num_active_tts;
1043 struct xhci_interval_bw_table bw_table;
1046 struct xhci_tt_bw_info {
1047 struct list_head tt_list;
1050 struct xhci_interval_bw_table bw_table;
1056 * struct xhci_device_context_array
1057 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1059 struct xhci_device_context_array {
1060 /* 64-bit device addresses; we only write 32-bit addresses */
1061 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1062 /* private xHCD pointers */
1065 /* TODO: write function to set the 64-bit device DMA address */
1067 * TODO: change this to be dynamically sized at HC mem init time since the HC
1068 * might not be able to handle the maximum number of devices possible.
1072 struct xhci_transfer_event {
1073 /* 64-bit buffer address, or immediate data */
1075 __le32 transfer_len;
1076 /* This field is interpreted differently based on the type of TRB */
1080 /* Transfer event TRB length bit mask */
1082 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1084 /** Transfer Event bit fields **/
1085 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1087 /* Completion Code - only applicable for some types of TRBs */
1088 #define COMP_CODE_MASK (0xff << 24)
1089 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1090 #define COMP_INVALID 0
1091 #define COMP_SUCCESS 1
1092 #define COMP_DATA_BUFFER_ERROR 2
1093 #define COMP_BABBLE_DETECTED_ERROR 3
1094 #define COMP_USB_TRANSACTION_ERROR 4
1095 #define COMP_TRB_ERROR 5
1096 #define COMP_STALL_ERROR 6
1097 #define COMP_RESOURCE_ERROR 7
1098 #define COMP_BANDWIDTH_ERROR 8
1099 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1100 #define COMP_INVALID_STREAM_TYPE_ERROR 10
1101 #define COMP_SLOT_NOT_ENABLED_ERROR 11
1102 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1103 #define COMP_SHORT_PACKET 13
1104 #define COMP_RING_UNDERRUN 14
1105 #define COMP_RING_OVERRUN 15
1106 #define COMP_VF_EVENT_RING_FULL_ERROR 16
1107 #define COMP_PARAMETER_ERROR 17
1108 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
1109 #define COMP_CONTEXT_STATE_ERROR 19
1110 #define COMP_NO_PING_RESPONSE_ERROR 20
1111 #define COMP_EVENT_RING_FULL_ERROR 21
1112 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1113 #define COMP_MISSED_SERVICE_ERROR 23
1114 #define COMP_COMMAND_RING_STOPPED 24
1115 #define COMP_COMMAND_ABORTED 25
1116 #define COMP_STOPPED 26
1117 #define COMP_STOPPED_LENGTH_INVALID 27
1118 #define COMP_STOPPED_SHORT_PACKET 28
1119 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1120 #define COMP_ISOCH_BUFFER_OVERRUN 31
1121 #define COMP_EVENT_LOST_ERROR 32
1122 #define COMP_UNDEFINED_ERROR 33
1123 #define COMP_INVALID_STREAM_ID_ERROR 34
1124 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
1125 #define COMP_SPLIT_TRANSACTION_ERROR 36
1127 static inline const char *xhci_trb_comp_code_string(u8 status)
1134 case COMP_DATA_BUFFER_ERROR:
1135 return "Data Buffer Error";
1136 case COMP_BABBLE_DETECTED_ERROR:
1137 return "Babble Detected";
1138 case COMP_USB_TRANSACTION_ERROR:
1139 return "USB Transaction Error";
1140 case COMP_TRB_ERROR:
1142 case COMP_STALL_ERROR:
1143 return "Stall Error";
1144 case COMP_RESOURCE_ERROR:
1145 return "Resource Error";
1146 case COMP_BANDWIDTH_ERROR:
1147 return "Bandwidth Error";
1148 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1149 return "No Slots Available Error";
1150 case COMP_INVALID_STREAM_TYPE_ERROR:
1151 return "Invalid Stream Type Error";
1152 case COMP_SLOT_NOT_ENABLED_ERROR:
1153 return "Slot Not Enabled Error";
1154 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1155 return "Endpoint Not Enabled Error";
1156 case COMP_SHORT_PACKET:
1157 return "Short Packet";
1158 case COMP_RING_UNDERRUN:
1159 return "Ring Underrun";
1160 case COMP_RING_OVERRUN:
1161 return "Ring Overrun";
1162 case COMP_VF_EVENT_RING_FULL_ERROR:
1163 return "VF Event Ring Full Error";
1164 case COMP_PARAMETER_ERROR:
1165 return "Parameter Error";
1166 case COMP_BANDWIDTH_OVERRUN_ERROR:
1167 return "Bandwidth Overrun Error";
1168 case COMP_CONTEXT_STATE_ERROR:
1169 return "Context State Error";
1170 case COMP_NO_PING_RESPONSE_ERROR:
1171 return "No Ping Response Error";
1172 case COMP_EVENT_RING_FULL_ERROR:
1173 return "Event Ring Full Error";
1174 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1175 return "Incompatible Device Error";
1176 case COMP_MISSED_SERVICE_ERROR:
1177 return "Missed Service Error";
1178 case COMP_COMMAND_RING_STOPPED:
1179 return "Command Ring Stopped";
1180 case COMP_COMMAND_ABORTED:
1181 return "Command Aborted";
1184 case COMP_STOPPED_LENGTH_INVALID:
1185 return "Stopped - Length Invalid";
1186 case COMP_STOPPED_SHORT_PACKET:
1187 return "Stopped - Short Packet";
1188 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1189 return "Max Exit Latency Too Large Error";
1190 case COMP_ISOCH_BUFFER_OVERRUN:
1191 return "Isoch Buffer Overrun";
1192 case COMP_EVENT_LOST_ERROR:
1193 return "Event Lost Error";
1194 case COMP_UNDEFINED_ERROR:
1195 return "Undefined Error";
1196 case COMP_INVALID_STREAM_ID_ERROR:
1197 return "Invalid Stream ID Error";
1198 case COMP_SECONDARY_BANDWIDTH_ERROR:
1199 return "Secondary Bandwidth Error";
1200 case COMP_SPLIT_TRANSACTION_ERROR:
1201 return "Split Transaction Error";
1207 struct xhci_link_trb {
1208 /* 64-bit segment pointer*/
1214 /* control bitfields */
1215 #define LINK_TOGGLE (0x1<<1)
1217 /* Command completion event TRB */
1218 struct xhci_event_cmd {
1219 /* Pointer to command TRB, or the value passed by the event data trb */
1225 /* flags bitmasks */
1227 /* Address device - disable SetAddress */
1228 #define TRB_BSR (1<<9)
1230 /* Configure Endpoint - Deconfigure */
1231 #define TRB_DC (1<<9)
1233 /* Stop Ring - Transfer State Preserve */
1234 #define TRB_TSP (1<<9)
1236 enum xhci_ep_reset_type {
1242 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1243 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1245 /* Set Latency Tolerance Value */
1246 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1248 /* Get Port Bandwidth */
1249 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1252 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1253 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1255 enum xhci_setup_dev {
1257 SETUP_CONTEXT_ADDRESS,
1260 /* bits 16:23 are the virtual function ID */
1261 /* bits 24:31 are the slot ID */
1262 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1263 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1265 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1266 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1267 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1269 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1270 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1271 #define LAST_EP_INDEX 30
1273 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1274 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1275 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1276 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1278 /* Link TRB specific fields */
1279 #define TRB_TC (1<<1)
1281 /* Port Status Change Event TRB fields */
1282 /* Port ID - bits 31:24 */
1283 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1285 #define EVENT_DATA (1 << 2)
1287 /* Normal TRB fields */
1288 /* transfer_len bitmasks - bits 0:16 */
1289 #define TRB_LEN(p) ((p) & 0x1ffff)
1290 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1291 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1292 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1293 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1294 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1295 /* Interrupter Target - which MSI-X vector to target the completion event at */
1296 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1297 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1298 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1299 #define TRB_TBC(p) (((p) & 0x3) << 7)
1300 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1302 /* Cycle bit - indicates TRB ownership by HC or HCD */
1303 #define TRB_CYCLE (1<<0)
1305 * Force next event data TRB to be evaluated before task switch.
1306 * Used to pass OS data back after a TD completes.
1308 #define TRB_ENT (1<<1)
1309 /* Interrupt on short packet */
1310 #define TRB_ISP (1<<2)
1311 /* Set PCIe no snoop attribute */
1312 #define TRB_NO_SNOOP (1<<3)
1313 /* Chain multiple TRBs into a TD */
1314 #define TRB_CHAIN (1<<4)
1315 /* Interrupt on completion */
1316 #define TRB_IOC (1<<5)
1317 /* The buffer pointer contains immediate data */
1318 #define TRB_IDT (1<<6)
1320 /* Block Event Interrupt */
1321 #define TRB_BEI (1<<9)
1323 /* Control transfer TRB specific fields */
1324 #define TRB_DIR_IN (1<<16)
1325 #define TRB_TX_TYPE(p) ((p) << 16)
1326 #define TRB_DATA_OUT 2
1327 #define TRB_DATA_IN 3
1329 /* Isochronous TRB specific fields */
1330 #define TRB_SIA (1<<31)
1331 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1333 struct xhci_generic_trb {
1338 struct xhci_link_trb link;
1339 struct xhci_transfer_event trans_event;
1340 struct xhci_event_cmd event_cmd;
1341 struct xhci_generic_trb generic;
1345 #define TRB_TYPE_BITMASK (0xfc00)
1346 #define TRB_TYPE(p) ((p) << 10)
1347 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1349 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1350 #define TRB_NORMAL 1
1351 /* setup stage for control transfers */
1353 /* data stage for control transfers */
1355 /* status stage for control transfers */
1356 #define TRB_STATUS 4
1357 /* isoc transfers */
1359 /* TRB for linking ring segments */
1361 #define TRB_EVENT_DATA 7
1362 /* Transfer Ring No-op (not for the command ring) */
1363 #define TRB_TR_NOOP 8
1365 /* Enable Slot Command */
1366 #define TRB_ENABLE_SLOT 9
1367 /* Disable Slot Command */
1368 #define TRB_DISABLE_SLOT 10
1369 /* Address Device Command */
1370 #define TRB_ADDR_DEV 11
1371 /* Configure Endpoint Command */
1372 #define TRB_CONFIG_EP 12
1373 /* Evaluate Context Command */
1374 #define TRB_EVAL_CONTEXT 13
1375 /* Reset Endpoint Command */
1376 #define TRB_RESET_EP 14
1377 /* Stop Transfer Ring Command */
1378 #define TRB_STOP_RING 15
1379 /* Set Transfer Ring Dequeue Pointer Command */
1380 #define TRB_SET_DEQ 16
1381 /* Reset Device Command */
1382 #define TRB_RESET_DEV 17
1383 /* Force Event Command (opt) */
1384 #define TRB_FORCE_EVENT 18
1385 /* Negotiate Bandwidth Command (opt) */
1386 #define TRB_NEG_BANDWIDTH 19
1387 /* Set Latency Tolerance Value Command (opt) */
1388 #define TRB_SET_LT 20
1389 /* Get port bandwidth Command */
1390 #define TRB_GET_BW 21
1391 /* Force Header Command - generate a transaction or link management packet */
1392 #define TRB_FORCE_HEADER 22
1393 /* No-op Command - not for transfer rings */
1394 #define TRB_CMD_NOOP 23
1395 /* TRB IDs 24-31 reserved */
1397 /* Transfer Event */
1398 #define TRB_TRANSFER 32
1399 /* Command Completion Event */
1400 #define TRB_COMPLETION 33
1401 /* Port Status Change Event */
1402 #define TRB_PORT_STATUS 34
1403 /* Bandwidth Request Event (opt) */
1404 #define TRB_BANDWIDTH_EVENT 35
1405 /* Doorbell Event (opt) */
1406 #define TRB_DOORBELL 36
1407 /* Host Controller Event */
1408 #define TRB_HC_EVENT 37
1409 /* Device Notification Event - device sent function wake notification */
1410 #define TRB_DEV_NOTE 38
1411 /* MFINDEX Wrap Event - microframe counter wrapped */
1412 #define TRB_MFINDEX_WRAP 39
1413 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1415 /* Nec vendor-specific command completion event. */
1416 #define TRB_NEC_CMD_COMP 48
1417 /* Get NEC firmware revision. */
1418 #define TRB_NEC_GET_FW 49
1420 static inline const char *xhci_trb_type_string(u8 type)
1426 return "Setup Stage";
1428 return "Data Stage";
1430 return "Status Stage";
1435 case TRB_EVENT_DATA:
1436 return "Event Data";
1439 case TRB_ENABLE_SLOT:
1440 return "Enable Slot Command";
1441 case TRB_DISABLE_SLOT:
1442 return "Disable Slot Command";
1444 return "Address Device Command";
1446 return "Configure Endpoint Command";
1447 case TRB_EVAL_CONTEXT:
1448 return "Evaluate Context Command";
1450 return "Reset Endpoint Command";
1452 return "Stop Ring Command";
1454 return "Set TR Dequeue Pointer Command";
1456 return "Reset Device Command";
1457 case TRB_FORCE_EVENT:
1458 return "Force Event Command";
1459 case TRB_NEG_BANDWIDTH:
1460 return "Negotiate Bandwidth Command";
1462 return "Set Latency Tolerance Value Command";
1464 return "Get Port Bandwidth Command";
1465 case TRB_FORCE_HEADER:
1466 return "Force Header Command";
1468 return "No-Op Command";
1470 return "Transfer Event";
1471 case TRB_COMPLETION:
1472 return "Command Completion Event";
1473 case TRB_PORT_STATUS:
1474 return "Port Status Change Event";
1475 case TRB_BANDWIDTH_EVENT:
1476 return "Bandwidth Request Event";
1478 return "Doorbell Event";
1480 return "Host Controller Event";
1482 return "Device Notification Event";
1483 case TRB_MFINDEX_WRAP:
1484 return "MFINDEX Wrap Event";
1485 case TRB_NEC_CMD_COMP:
1486 return "NEC Command Completion Event";
1487 case TRB_NEC_GET_FW:
1488 return "NET Get Firmware Revision Command";
1494 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1495 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1496 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1497 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1498 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1499 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1501 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1502 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1505 * TRBS_PER_SEGMENT must be a multiple of 4,
1506 * since the command ring is 64-byte aligned.
1507 * It must also be greater than 16.
1509 #define TRBS_PER_SEGMENT 256
1510 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1511 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1512 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1513 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1514 /* TRB buffer pointers can't cross 64KB boundaries */
1515 #define TRB_MAX_BUFF_SHIFT 16
1516 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1517 /* How much data is left before the 64KB boundary? */
1518 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1519 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1521 struct xhci_segment {
1522 union xhci_trb *trbs;
1523 /* private to HCD */
1524 struct xhci_segment *next;
1526 /* Max packet sized bounce buffer for td-fragmant alignment */
1527 dma_addr_t bounce_dma;
1529 unsigned int bounce_offs;
1530 unsigned int bounce_len;
1534 struct list_head td_list;
1535 struct list_head cancelled_td_list;
1537 struct xhci_segment *start_seg;
1538 union xhci_trb *first_trb;
1539 union xhci_trb *last_trb;
1540 struct xhci_segment *bounce_seg;
1541 /* actual_length of the URB has already been set */
1542 bool urb_length_set;
1545 /* xHCI command default timeout value */
1546 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1548 /* command descriptor */
1550 struct xhci_command *command;
1551 union xhci_trb *cmd_trb;
1554 struct xhci_dequeue_state {
1555 struct xhci_segment *new_deq_seg;
1556 union xhci_trb *new_deq_ptr;
1557 int new_cycle_state;
1558 unsigned int stream_id;
1561 enum xhci_ring_type {
1571 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1594 struct xhci_segment *first_seg;
1595 struct xhci_segment *last_seg;
1596 union xhci_trb *enqueue;
1597 struct xhci_segment *enq_seg;
1598 union xhci_trb *dequeue;
1599 struct xhci_segment *deq_seg;
1600 struct list_head td_list;
1602 * Write the cycle state into the TRB cycle field to give ownership of
1603 * the TRB to the host controller (if we are the producer), or to check
1604 * if we own the TRB (if we are the consumer). See section 4.9.1.
1607 unsigned int stream_id;
1608 unsigned int num_segs;
1609 unsigned int num_trbs_free;
1610 unsigned int num_trbs_free_temp;
1611 unsigned int bounce_buf_len;
1612 enum xhci_ring_type type;
1613 bool last_td_was_short;
1614 struct radix_tree_root *trb_address_map;
1617 struct xhci_erst_entry {
1618 /* 64-bit event ring segment address */
1626 struct xhci_erst_entry *entries;
1627 unsigned int num_entries;
1628 /* xhci->event_ring keeps track of segment dma addresses */
1629 dma_addr_t erst_dma_addr;
1630 /* Num entries the ERST can contain */
1631 unsigned int erst_size;
1634 struct xhci_scratchpad {
1643 struct xhci_td td[0];
1647 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1648 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1649 * meaning 64 ring segments.
1650 * Initial allocated size of the ERST, in number of entries */
1651 #define ERST_NUM_SEGS 1
1652 /* Initial allocated size of the ERST, in number of entries */
1653 #define ERST_SIZE 64
1654 /* Initial number of event segment rings allocated */
1655 #define ERST_ENTRIES 1
1656 /* Poll every 60 seconds */
1657 #define POLL_TIMEOUT 60
1658 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1659 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1660 /* XXX: Make these module parameters */
1677 struct list_head list;
1680 struct xhci_bus_state {
1681 unsigned long bus_suspended;
1682 unsigned long next_statechange;
1684 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1685 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1687 u32 suspended_ports;
1688 u32 port_remote_wakeup;
1689 unsigned long resume_done[USB_MAXCHILDREN];
1690 /* which ports have started to resume */
1691 unsigned long resuming_ports;
1692 /* Which ports are waiting on RExit to U0 transition. */
1693 unsigned long rexit_ports;
1694 struct completion rexit_done[USB_MAXCHILDREN];
1699 * It can take up to 20 ms to transition from RExit to U0 on the
1700 * Intel Lynx Point LP xHCI host.
1702 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1704 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1706 if (hcd->speed >= HCD_USB3)
1712 struct xhci_port_cap {
1713 u32 *psi; /* array of protocol speed ID entries */
1721 __le32 __iomem *addr;
1724 struct xhci_hub *rhub;
1725 struct xhci_port_cap *port_cap;
1729 struct xhci_port **ports;
1730 unsigned int num_ports;
1731 struct usb_hcd *hcd;
1732 /* supported prococol extended capabiliy values */
1737 /* There is one xhci_hcd structure per controller */
1739 struct usb_hcd *main_hcd;
1740 struct usb_hcd *shared_hcd;
1741 /* glue to PCI and HCD framework */
1742 struct xhci_cap_regs __iomem *cap_regs;
1743 struct xhci_op_regs __iomem *op_regs;
1744 struct xhci_run_regs __iomem *run_regs;
1745 struct xhci_doorbell_array __iomem *dba;
1746 /* Our HCD's current interrupter register set */
1747 struct xhci_intr_reg __iomem *ir_set;
1749 /* Cached register copies of read-only HC data */
1758 /* packed release number */
1762 u8 max_interrupters;
1765 /* imod_interval in ns (I * 250ns) */
1768 /* 4KB min, 128MB max */
1770 /* Valid values are 12 to 20, inclusive */
1774 /* optional clocks */
1776 struct clk *reg_clk;
1777 /* data structures */
1778 struct xhci_device_context_array *dcbaa;
1779 struct xhci_ring *cmd_ring;
1780 unsigned int cmd_ring_state;
1781 #define CMD_RING_STATE_RUNNING (1 << 0)
1782 #define CMD_RING_STATE_ABORTED (1 << 1)
1783 #define CMD_RING_STATE_STOPPED (1 << 2)
1784 struct list_head cmd_list;
1785 unsigned int cmd_ring_reserved_trbs;
1786 struct delayed_work cmd_timer;
1787 struct completion cmd_ring_stop_completion;
1788 struct xhci_command *current_cmd;
1789 struct xhci_ring *event_ring;
1790 struct xhci_erst erst;
1792 struct xhci_scratchpad *scratchpad;
1793 /* Store LPM test failed devices' information */
1794 struct list_head lpm_failed_devs;
1796 /* slot enabling and address device helpers */
1797 /* these are not thread safe so use mutex */
1799 /* For USB 3.0 LPM enable/disable. */
1800 struct xhci_command *lpm_command;
1801 /* Internal mirror of the HW's dcbaa */
1802 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1803 /* For keeping track of bandwidth domains per roothub. */
1804 struct xhci_root_port_bw_info *rh_bw;
1807 struct dma_pool *device_pool;
1808 struct dma_pool *segment_pool;
1809 struct dma_pool *small_streams_pool;
1810 struct dma_pool *medium_streams_pool;
1812 /* Host controller watchdog timer structures */
1813 unsigned int xhc_state;
1814 unsigned long run_graceperiod;
1817 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1819 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1820 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1821 * that sees this status (other than the timer that set it) should stop touching
1822 * hardware immediately. Interrupt handlers should return immediately when
1823 * they see this status (any time they drop and re-acquire xhci->lock).
1824 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1825 * putting the TD on the canceled list, etc.
1827 * There are no reports of xHCI host controllers that display this issue.
1829 #define XHCI_STATE_DYING (1 << 0)
1830 #define XHCI_STATE_HALTED (1 << 1)
1831 #define XHCI_STATE_REMOVING (1 << 2)
1832 unsigned long long quirks;
1833 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1834 #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1835 #define XHCI_NEC_HOST BIT_ULL(2)
1836 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1837 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1839 * Certain Intel host controllers have a limit to the number of endpoint
1840 * contexts they can handle. Ideally, they would signal that they can't handle
1841 * anymore endpoint contexts by returning a Resource Error for the Configure
1842 * Endpoint command, but they don't. Instead they expect software to keep track
1843 * of the number of active endpoints for them, across configure endpoint
1844 * commands, reset device commands, disable slot commands, and address device
1847 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1848 #define XHCI_BROKEN_MSI BIT_ULL(6)
1849 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1850 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1851 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1852 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1853 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1854 #define XHCI_INTEL_HOST BIT_ULL(12)
1855 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1856 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1857 #define XHCI_AVOID_BEI BIT_ULL(15)
1858 #define XHCI_PLAT BIT_ULL(16)
1859 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1860 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1861 /* For controllers with a broken beyond repair streams implementation */
1862 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1863 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1864 #define XHCI_MTK_HOST BIT_ULL(21)
1865 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1866 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1867 #define XHCI_MISSING_CAS BIT_ULL(24)
1868 /* For controller with a broken Port Disable implementation */
1869 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1870 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1871 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1872 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1873 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1874 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1875 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1876 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
1877 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1878 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1879 #define XHCI_DISABLE_SPARSE BIT_ULL(38)
1881 unsigned int num_active_eps;
1882 unsigned int limit_active_eps;
1883 /* There are two roothubs to keep track of bus suspend info for */
1884 struct xhci_bus_state bus_state[2];
1885 struct xhci_port *hw_ports;
1886 struct xhci_hub usb2_rhub;
1887 struct xhci_hub usb3_rhub;
1888 /* support xHCI 0.96 spec USB2 software LPM */
1889 unsigned sw_lpm_support:1;
1890 /* support xHCI 1.0 spec USB2 hardware LPM */
1891 unsigned hw_lpm_support:1;
1892 /* Broken Suspend flag for SNPS Suspend resume issue */
1893 unsigned broken_suspend:1;
1894 /* cached usb2 extened protocol capabilites */
1896 unsigned int num_ext_caps;
1897 /* cached extended protocol port capabilities */
1898 struct xhci_port_cap *port_caps;
1899 unsigned int num_port_caps;
1900 /* Compliance Mode Recovery Data */
1901 struct timer_list comp_mode_recovery_timer;
1904 /* Compliance Mode Timer Triggered every 2 seconds */
1905 #define COMP_MODE_RCVRY_MSECS 2000
1907 struct dentry *debugfs_root;
1908 struct dentry *debugfs_slots;
1909 struct list_head regset_list;
1912 /* platform-specific data -- must come last */
1913 unsigned long priv[0] __aligned(sizeof(s64));
1916 /* Platform specific overrides to generic XHCI hc_driver ops */
1917 struct xhci_driver_overrides {
1918 size_t extra_priv_size;
1919 int (*reset)(struct usb_hcd *hcd);
1920 int (*start)(struct usb_hcd *hcd);
1923 #define XHCI_CFC_DELAY 10
1925 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1926 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1928 struct usb_hcd *primary_hcd;
1930 if (usb_hcd_is_primary_hcd(hcd))
1933 primary_hcd = hcd->primary_hcd;
1935 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1938 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1940 return xhci->main_hcd;
1943 #define xhci_dbg(xhci, fmt, args...) \
1944 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1945 #define xhci_err(xhci, fmt, args...) \
1946 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1947 #define xhci_warn(xhci, fmt, args...) \
1948 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1949 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1950 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1951 #define xhci_info(xhci, fmt, args...) \
1952 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1955 * Registers should always be accessed with double word or quad word accesses.
1957 * Some xHCI implementations may support 64-bit address pointers. Registers
1958 * with 64-bit address pointers should be written to with dword accesses by
1959 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1960 * xHCI implementations that do not support 64-bit address pointers will ignore
1961 * the high dword, and write order is irrelevant.
1963 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1964 __le64 __iomem *regs)
1966 return lo_hi_readq(regs);
1968 static inline void xhci_write_64(struct xhci_hcd *xhci,
1969 const u64 val, __le64 __iomem *regs)
1971 lo_hi_writeq(val, regs);
1974 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1976 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1979 /* xHCI debugging */
1980 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1981 struct xhci_container_ctx *ctx);
1982 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1983 const char *fmt, ...);
1985 /* xHCI memory management */
1986 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1987 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1988 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1989 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1990 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1991 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1992 struct usb_device *udev);
1993 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1994 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1995 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1996 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1997 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1998 struct xhci_virt_device *virt_dev,
1999 int old_active_eps);
2000 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2001 void xhci_update_bw_info(struct xhci_hcd *xhci,
2002 struct xhci_container_ctx *in_ctx,
2003 struct xhci_input_control_ctx *ctrl_ctx,
2004 struct xhci_virt_device *virt_dev);
2005 void xhci_endpoint_copy(struct xhci_hcd *xhci,
2006 struct xhci_container_ctx *in_ctx,
2007 struct xhci_container_ctx *out_ctx,
2008 unsigned int ep_index);
2009 void xhci_slot_copy(struct xhci_hcd *xhci,
2010 struct xhci_container_ctx *in_ctx,
2011 struct xhci_container_ctx *out_ctx);
2012 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2013 struct usb_device *udev, struct usb_host_endpoint *ep,
2015 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2016 unsigned int num_segs, unsigned int cycle_state,
2017 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2018 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2019 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2020 unsigned int num_trbs, gfp_t flags);
2021 int xhci_alloc_erst(struct xhci_hcd *xhci,
2022 struct xhci_ring *evt_ring,
2023 struct xhci_erst *erst,
2025 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2026 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2027 struct xhci_virt_device *virt_dev,
2028 unsigned int ep_index);
2029 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2030 unsigned int num_stream_ctxs,
2031 unsigned int num_streams,
2032 unsigned int max_packet, gfp_t flags);
2033 void xhci_free_stream_info(struct xhci_hcd *xhci,
2034 struct xhci_stream_info *stream_info);
2035 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2036 struct xhci_ep_ctx *ep_ctx,
2037 struct xhci_stream_info *stream_info);
2038 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2039 struct xhci_virt_ep *ep);
2040 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2041 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2042 struct xhci_ring *xhci_dma_to_transfer_ring(
2043 struct xhci_virt_ep *ep,
2045 struct xhci_ring *xhci_stream_id_to_ring(
2046 struct xhci_virt_device *dev,
2047 unsigned int ep_index,
2048 unsigned int stream_id);
2049 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2050 bool allocate_completion, gfp_t mem_flags);
2051 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2052 bool allocate_completion, gfp_t mem_flags);
2053 void xhci_urb_free_priv(struct urb_priv *urb_priv);
2054 void xhci_free_command(struct xhci_hcd *xhci,
2055 struct xhci_command *command);
2056 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2057 int type, gfp_t flags);
2058 void xhci_free_container_ctx(struct xhci_hcd *xhci,
2059 struct xhci_container_ctx *ctx);
2061 /* xHCI host controller glue */
2062 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2063 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
2064 void xhci_quiesce(struct xhci_hcd *xhci);
2065 int xhci_halt(struct xhci_hcd *xhci);
2066 int xhci_start(struct xhci_hcd *xhci);
2067 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
2068 int xhci_run(struct usb_hcd *hcd);
2069 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2070 void xhci_shutdown(struct usb_hcd *hcd);
2071 void xhci_init_driver(struct hc_driver *drv,
2072 const struct xhci_driver_overrides *over);
2073 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2074 int xhci_ext_cap_init(struct xhci_hcd *xhci);
2076 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2077 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2079 irqreturn_t xhci_irq(struct usb_hcd *hcd);
2080 irqreturn_t xhci_msi_irq(int irq, void *hcd);
2081 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2082 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2083 struct xhci_virt_device *virt_dev,
2084 struct usb_device *hdev,
2085 struct usb_tt *tt, gfp_t mem_flags);
2087 /* xHCI ring, segment, TRB, and TD functions */
2088 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2089 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2090 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2091 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2092 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2093 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2094 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2095 u32 trb_type, u32 slot_id);
2096 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2097 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2098 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2099 u32 field1, u32 field2, u32 field3, u32 field4);
2100 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2101 int slot_id, unsigned int ep_index, int suspend);
2102 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2103 int slot_id, unsigned int ep_index);
2104 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2105 int slot_id, unsigned int ep_index);
2106 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2107 int slot_id, unsigned int ep_index);
2108 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2109 struct urb *urb, int slot_id, unsigned int ep_index);
2110 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2111 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2112 bool command_must_succeed);
2113 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2114 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2115 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2116 int slot_id, unsigned int ep_index,
2117 enum xhci_ep_reset_type reset_type);
2118 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2120 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
2121 unsigned int slot_id, unsigned int ep_index,
2122 unsigned int stream_id, struct xhci_td *cur_td,
2123 struct xhci_dequeue_state *state);
2124 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
2125 unsigned int slot_id, unsigned int ep_index,
2126 struct xhci_dequeue_state *deq_state);
2127 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2128 unsigned int stream_id, struct xhci_td *td);
2129 void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2130 void xhci_handle_command_timeout(struct work_struct *work);
2132 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2133 unsigned int ep_index, unsigned int stream_id);
2134 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2135 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2136 unsigned int count_trbs(u64 addr, u64 len);
2138 /* xHCI roothub code */
2139 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2141 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2143 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2144 char *buf, u16 wLength);
2145 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2146 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2147 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2149 void xhci_hc_died(struct xhci_hcd *xhci);
2152 int xhci_bus_suspend(struct usb_hcd *hcd);
2153 int xhci_bus_resume(struct usb_hcd *hcd);
2154 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2156 #define xhci_bus_suspend NULL
2157 #define xhci_bus_resume NULL
2158 #define xhci_get_resuming_ports NULL
2159 #endif /* CONFIG_PM */
2161 u32 xhci_port_state_to_neutral(u32 state);
2162 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2164 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2167 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2168 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2169 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2171 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2172 unsigned int slot_id, unsigned int ep_index,
2173 unsigned int stream_id);
2175 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2178 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2179 xhci_get_endpoint_index(&urb->ep->desc),
2183 static inline char *xhci_slot_state_string(u32 state)
2186 case SLOT_STATE_ENABLED:
2187 return "enabled/disabled";
2188 case SLOT_STATE_DEFAULT:
2190 case SLOT_STATE_ADDRESSED:
2192 case SLOT_STATE_CONFIGURED:
2193 return "configured";
2199 static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2202 static char str[256];
2203 int type = TRB_FIELD_TO_TYPE(field3);
2208 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2209 field1, field0, GET_INTR_TARGET(field2),
2210 xhci_trb_type_string(type),
2211 field3 & TRB_IOC ? 'I' : 'i',
2212 field3 & TRB_CHAIN ? 'C' : 'c',
2213 field3 & TRB_TC ? 'T' : 't',
2214 field3 & TRB_CYCLE ? 'C' : 'c');
2217 case TRB_COMPLETION:
2218 case TRB_PORT_STATUS:
2219 case TRB_BANDWIDTH_EVENT:
2223 case TRB_MFINDEX_WRAP:
2225 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2227 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2228 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2229 /* Macro decrements 1, maybe it shouldn't?!? */
2230 TRB_TO_EP_INDEX(field3) + 1,
2231 xhci_trb_type_string(type),
2232 field3 & EVENT_DATA ? 'E' : 'e',
2233 field3 & TRB_CYCLE ? 'C' : 'c');
2237 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2239 (field0 & 0xff00) >> 8,
2240 (field0 & 0xff000000) >> 24,
2241 (field0 & 0xff0000) >> 16,
2242 (field1 & 0xff00) >> 8,
2244 (field1 & 0xff000000) >> 16 |
2245 (field1 & 0xff0000) >> 16,
2246 TRB_LEN(field2), GET_TD_SIZE(field2),
2247 GET_INTR_TARGET(field2),
2248 xhci_trb_type_string(type),
2249 field3 & TRB_IDT ? 'I' : 'i',
2250 field3 & TRB_IOC ? 'I' : 'i',
2251 field3 & TRB_CYCLE ? 'C' : 'c');
2254 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2255 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2256 GET_INTR_TARGET(field2),
2257 xhci_trb_type_string(type),
2258 field3 & TRB_IDT ? 'I' : 'i',
2259 field3 & TRB_IOC ? 'I' : 'i',
2260 field3 & TRB_CHAIN ? 'C' : 'c',
2261 field3 & TRB_NO_SNOOP ? 'S' : 's',
2262 field3 & TRB_ISP ? 'I' : 'i',
2263 field3 & TRB_ENT ? 'E' : 'e',
2264 field3 & TRB_CYCLE ? 'C' : 'c');
2267 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2268 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2269 GET_INTR_TARGET(field2),
2270 xhci_trb_type_string(type),
2271 field3 & TRB_IOC ? 'I' : 'i',
2272 field3 & TRB_CHAIN ? 'C' : 'c',
2273 field3 & TRB_ENT ? 'E' : 'e',
2274 field3 & TRB_CYCLE ? 'C' : 'c');
2278 case TRB_EVENT_DATA:
2281 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2282 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2283 GET_INTR_TARGET(field2),
2284 xhci_trb_type_string(type),
2285 field3 & TRB_BEI ? 'B' : 'b',
2286 field3 & TRB_IDT ? 'I' : 'i',
2287 field3 & TRB_IOC ? 'I' : 'i',
2288 field3 & TRB_CHAIN ? 'C' : 'c',
2289 field3 & TRB_NO_SNOOP ? 'S' : 's',
2290 field3 & TRB_ISP ? 'I' : 'i',
2291 field3 & TRB_ENT ? 'E' : 'e',
2292 field3 & TRB_CYCLE ? 'C' : 'c');
2296 case TRB_ENABLE_SLOT:
2299 xhci_trb_type_string(type),
2300 field3 & TRB_CYCLE ? 'C' : 'c');
2302 case TRB_DISABLE_SLOT:
2303 case TRB_NEG_BANDWIDTH:
2305 "%s: slot %d flags %c",
2306 xhci_trb_type_string(type),
2307 TRB_TO_SLOT_ID(field3),
2308 field3 & TRB_CYCLE ? 'C' : 'c');
2312 "%s: ctx %08x%08x slot %d flags %c:%c",
2313 xhci_trb_type_string(type),
2315 TRB_TO_SLOT_ID(field3),
2316 field3 & TRB_BSR ? 'B' : 'b',
2317 field3 & TRB_CYCLE ? 'C' : 'c');
2321 "%s: ctx %08x%08x slot %d flags %c:%c",
2322 xhci_trb_type_string(type),
2324 TRB_TO_SLOT_ID(field3),
2325 field3 & TRB_DC ? 'D' : 'd',
2326 field3 & TRB_CYCLE ? 'C' : 'c');
2328 case TRB_EVAL_CONTEXT:
2330 "%s: ctx %08x%08x slot %d flags %c",
2331 xhci_trb_type_string(type),
2333 TRB_TO_SLOT_ID(field3),
2334 field3 & TRB_CYCLE ? 'C' : 'c');
2338 "%s: ctx %08x%08x slot %d ep %d flags %c",
2339 xhci_trb_type_string(type),
2341 TRB_TO_SLOT_ID(field3),
2342 /* Macro decrements 1, maybe it shouldn't?!? */
2343 TRB_TO_EP_INDEX(field3) + 1,
2344 field3 & TRB_CYCLE ? 'C' : 'c');
2348 "%s: slot %d sp %d ep %d flags %c",
2349 xhci_trb_type_string(type),
2350 TRB_TO_SLOT_ID(field3),
2351 TRB_TO_SUSPEND_PORT(field3),
2352 /* Macro decrements 1, maybe it shouldn't?!? */
2353 TRB_TO_EP_INDEX(field3) + 1,
2354 field3 & TRB_CYCLE ? 'C' : 'c');
2358 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2359 xhci_trb_type_string(type),
2361 TRB_TO_STREAM_ID(field2),
2362 TRB_TO_SLOT_ID(field3),
2363 /* Macro decrements 1, maybe it shouldn't?!? */
2364 TRB_TO_EP_INDEX(field3) + 1,
2365 field3 & TRB_CYCLE ? 'C' : 'c');
2369 "%s: slot %d flags %c",
2370 xhci_trb_type_string(type),
2371 TRB_TO_SLOT_ID(field3),
2372 field3 & TRB_CYCLE ? 'C' : 'c');
2374 case TRB_FORCE_EVENT:
2376 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2377 xhci_trb_type_string(type),
2379 TRB_TO_VF_INTR_TARGET(field2),
2380 TRB_TO_VF_ID(field3),
2381 field3 & TRB_CYCLE ? 'C' : 'c');
2385 "%s: belt %d flags %c",
2386 xhci_trb_type_string(type),
2387 TRB_TO_BELT(field3),
2388 field3 & TRB_CYCLE ? 'C' : 'c');
2392 "%s: ctx %08x%08x slot %d speed %d flags %c",
2393 xhci_trb_type_string(type),
2395 TRB_TO_SLOT_ID(field3),
2396 TRB_TO_DEV_SPEED(field3),
2397 field3 & TRB_CYCLE ? 'C' : 'c');
2399 case TRB_FORCE_HEADER:
2401 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2402 xhci_trb_type_string(type),
2403 field2, field1, field0 & 0xffffffe0,
2404 TRB_TO_PACKET_TYPE(field0),
2405 TRB_TO_ROOTHUB_PORT(field3),
2406 field3 & TRB_CYCLE ? 'C' : 'c');
2410 "type '%s' -> raw %08x %08x %08x %08x",
2411 xhci_trb_type_string(type),
2412 field0, field1, field2, field3);
2418 static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2419 u32 tt_info, u32 state)
2421 static char str[1024];
2427 speed = info & DEV_SPEED;
2428 hub = info & DEV_HUB;
2429 mtt = info & DEV_MTT;
2431 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2432 info & ROUTE_STRING_MASK,
2447 case SLOT_SPEED_SSP:
2448 s = "super-speed plus";
2451 s = "UNKNOWN speed";
2453 mtt ? " multi-TT" : "",
2455 (info & LAST_CTX_MASK) >> 27,
2457 DEVINFO_TO_ROOT_HUB_PORT(info2),
2458 DEVINFO_TO_MAX_PORTS(info2));
2460 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2461 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2462 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2463 state & DEV_ADDR_MASK,
2464 xhci_slot_state_string(GET_SLOT_STATE(state)));
2470 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2472 switch (portsc & PORT_PLS_MASK) {
2491 case XDEV_HOT_RESET:
2493 case XDEV_COMP_MODE:
2494 return "Compliance mode";
2495 case XDEV_TEST_MODE:
2505 static inline const char *xhci_decode_portsc(u32 portsc)
2507 static char str[256];
2510 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2511 portsc & PORT_POWER ? "Powered" : "Powered-off",
2512 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2513 portsc & PORT_PE ? "Enabled" : "Disabled",
2514 xhci_portsc_link_state_string(portsc),
2515 DEV_PORT_SPEED(portsc));
2517 if (portsc & PORT_OC)
2518 ret += sprintf(str + ret, "OverCurrent ");
2519 if (portsc & PORT_RESET)
2520 ret += sprintf(str + ret, "In-Reset ");
2522 ret += sprintf(str + ret, "Change: ");
2523 if (portsc & PORT_CSC)
2524 ret += sprintf(str + ret, "CSC ");
2525 if (portsc & PORT_PEC)
2526 ret += sprintf(str + ret, "PEC ");
2527 if (portsc & PORT_WRC)
2528 ret += sprintf(str + ret, "WRC ");
2529 if (portsc & PORT_OCC)
2530 ret += sprintf(str + ret, "OCC ");
2531 if (portsc & PORT_RC)
2532 ret += sprintf(str + ret, "PRC ");
2533 if (portsc & PORT_PLC)
2534 ret += sprintf(str + ret, "PLC ");
2535 if (portsc & PORT_CEC)
2536 ret += sprintf(str + ret, "CEC ");
2537 if (portsc & PORT_CAS)
2538 ret += sprintf(str + ret, "CAS ");
2540 ret += sprintf(str + ret, "Wake: ");
2541 if (portsc & PORT_WKCONN_E)
2542 ret += sprintf(str + ret, "WCE ");
2543 if (portsc & PORT_WKDISC_E)
2544 ret += sprintf(str + ret, "WDE ");
2545 if (portsc & PORT_WKOC_E)
2546 ret += sprintf(str + ret, "WOE ");
2551 static inline const char *xhci_ep_state_string(u8 state)
2554 case EP_STATE_DISABLED:
2556 case EP_STATE_RUNNING:
2558 case EP_STATE_HALTED:
2560 case EP_STATE_STOPPED:
2562 case EP_STATE_ERROR:
2569 static inline const char *xhci_ep_type_string(u8 type)
2591 static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2594 static char str[1024];
2612 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2613 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2615 ep_state = info & EP_STATE_MASK;
2616 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2617 interval = CTX_TO_EP_INTERVAL(info);
2618 mult = CTX_TO_EP_MULT(info) + 1;
2619 lsa = !!(info & EP_HAS_LSA);
2621 cerr = (info2 & (3 << 1)) >> 1;
2622 ep_type = CTX_TO_EP_TYPE(info2);
2623 hid = !!(info2 & (1 << 7));
2624 burst = CTX_TO_MAX_BURST(info2);
2625 maxp = MAX_PACKET_DECODED(info2);
2627 avg = EP_AVG_TRB_LENGTH(tx_info);
2629 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2630 xhci_ep_state_string(ep_state), mult,
2631 max_pstr, lsa ? "LSA " : "");
2633 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2634 (1 << interval) * 125, esit, cerr);
2636 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2637 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2640 ret += sprintf(str + ret, "avg trb len %d", avg);
2645 #endif /* __LINUX_XHCI_HCD_H */