2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
46 #include "musb_core.h"
47 #include "musb_trace.h"
50 /* ----------------------------------------------------------------------- */
52 #define is_buffer_mapped(req) (is_dma_capable() && \
53 (req->map_state != UN_MAPPED))
55 /* Maps the buffer to dma */
57 static inline void map_dma_buffer(struct musb_request *request,
58 struct musb *musb, struct musb_ep *musb_ep)
60 int compatible = true;
61 struct dma_controller *dma = musb->dma_controller;
63 request->map_state = UN_MAPPED;
65 if (!is_dma_capable() || !musb_ep->dma)
68 /* Check if DMA engine can handle this request.
69 * DMA code must reject the USB request explicitly.
70 * Default behaviour is to map the request.
72 if (dma->is_compatible)
73 compatible = dma->is_compatible(musb_ep->dma,
74 musb_ep->packet_sz, request->request.buf,
75 request->request.length);
79 if (request->request.dma == DMA_ADDR_INVALID) {
83 dma_addr = dma_map_single(
86 request->request.length,
90 ret = dma_mapping_error(musb->controller, dma_addr);
94 request->request.dma = dma_addr;
95 request->map_state = MUSB_MAPPED;
97 dma_sync_single_for_device(musb->controller,
99 request->request.length,
103 request->map_state = PRE_MAPPED;
107 /* Unmap the buffer from dma and maps it back to cpu */
108 static inline void unmap_dma_buffer(struct musb_request *request,
111 struct musb_ep *musb_ep = request->ep;
113 if (!is_buffer_mapped(request) || !musb_ep->dma)
116 if (request->request.dma == DMA_ADDR_INVALID) {
117 dev_vdbg(musb->controller,
118 "not unmapping a never mapped buffer\n");
121 if (request->map_state == MUSB_MAPPED) {
122 dma_unmap_single(musb->controller,
123 request->request.dma,
124 request->request.length,
128 request->request.dma = DMA_ADDR_INVALID;
129 } else { /* PRE_MAPPED */
130 dma_sync_single_for_cpu(musb->controller,
131 request->request.dma,
132 request->request.length,
137 request->map_state = UN_MAPPED;
141 * Immediately complete a request.
143 * @param request the request to complete
144 * @param status the status to complete the request with
145 * Context: controller locked, IRQs blocked.
147 void musb_g_giveback(
149 struct usb_request *request,
151 __releases(ep->musb->lock)
152 __acquires(ep->musb->lock)
154 struct musb_request *req;
158 req = to_musb_request(request);
160 list_del(&req->list);
161 if (req->request.status == -EINPROGRESS)
162 req->request.status = status;
166 spin_unlock(&musb->lock);
168 if (!dma_mapping_error(&musb->g.dev, request->dma))
169 unmap_dma_buffer(req, musb);
171 trace_musb_req_gb(req);
172 usb_gadget_giveback_request(&req->ep->end_point, &req->request);
173 spin_lock(&musb->lock);
177 /* ----------------------------------------------------------------------- */
180 * Abort requests queued to an endpoint using the status. Synchronous.
181 * caller locked controller and blocked irqs, and selected this ep.
183 static void nuke(struct musb_ep *ep, const int status)
185 struct musb *musb = ep->musb;
186 struct musb_request *req = NULL;
187 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
191 if (is_dma_capable() && ep->dma) {
192 struct dma_controller *c = ep->musb->dma_controller;
197 * The programming guide says that we must not clear
198 * the DMAMODE bit before DMAENAB, so we only
199 * clear it in the second write...
201 musb_writew(epio, MUSB_TXCSR,
202 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
203 musb_writew(epio, MUSB_TXCSR,
204 0 | MUSB_TXCSR_FLUSHFIFO);
206 musb_writew(epio, MUSB_RXCSR,
207 0 | MUSB_RXCSR_FLUSHFIFO);
208 musb_writew(epio, MUSB_RXCSR,
209 0 | MUSB_RXCSR_FLUSHFIFO);
212 value = c->channel_abort(ep->dma);
213 musb_dbg(musb, "%s: abort DMA --> %d", ep->name, value);
214 c->channel_release(ep->dma);
218 while (!list_empty(&ep->req_list)) {
219 req = list_first_entry(&ep->req_list, struct musb_request, list);
220 musb_g_giveback(ep, &req->request, status);
224 /* ----------------------------------------------------------------------- */
226 /* Data transfers - pure PIO, pure DMA, or mixed mode */
229 * This assumes the separate CPPI engine is responding to DMA requests
230 * from the usb core ... sequenced a bit differently from mentor dma.
233 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
235 if (can_bulk_split(musb, ep->type))
236 return ep->hw_ep->max_packet_sz_tx;
238 return ep->packet_sz;
242 * An endpoint is transmitting data. This can be called either from
243 * the IRQ routine or from ep.queue() to kickstart a request on an
246 * Context: controller locked, IRQs blocked, endpoint selected
248 static void txstate(struct musb *musb, struct musb_request *req)
250 u8 epnum = req->epnum;
251 struct musb_ep *musb_ep;
252 void __iomem *epio = musb->endpoints[epnum].regs;
253 struct usb_request *request;
254 u16 fifo_count = 0, csr;
259 /* Check if EP is disabled */
260 if (!musb_ep->desc) {
261 musb_dbg(musb, "ep:%s disabled - ignore request",
262 musb_ep->end_point.name);
266 /* we shouldn't get here while DMA is active ... but we do ... */
267 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
268 musb_dbg(musb, "dma pending...");
272 /* read TXCSR before */
273 csr = musb_readw(epio, MUSB_TXCSR);
275 request = &req->request;
276 fifo_count = min(max_ep_writesize(musb, musb_ep),
277 (int)(request->length - request->actual));
279 if (csr & MUSB_TXCSR_TXPKTRDY) {
280 musb_dbg(musb, "%s old packet still ready , txcsr %03x",
281 musb_ep->end_point.name, csr);
285 if (csr & MUSB_TXCSR_P_SENDSTALL) {
286 musb_dbg(musb, "%s stalling, txcsr %03x",
287 musb_ep->end_point.name, csr);
291 musb_dbg(musb, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x",
292 epnum, musb_ep->packet_sz, fifo_count,
295 #ifndef CONFIG_MUSB_PIO_ONLY
296 if (is_buffer_mapped(req)) {
297 struct dma_controller *c = musb->dma_controller;
300 /* setup DMA, then program endpoint CSR */
301 request_size = min_t(size_t, request->length - request->actual,
302 musb_ep->dma->max_len);
304 use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
306 /* MUSB_TXCSR_P_ISO is still set correctly */
308 if (musb_dma_inventra(musb) || musb_dma_ux500(musb)) {
309 if (request_size < musb_ep->packet_sz)
310 musb_ep->dma->desired_mode = 0;
312 musb_ep->dma->desired_mode = 1;
314 use_dma = use_dma && c->channel_program(
315 musb_ep->dma, musb_ep->packet_sz,
316 musb_ep->dma->desired_mode,
317 request->dma + request->actual, request_size);
319 if (musb_ep->dma->desired_mode == 0) {
321 * We must not clear the DMAMODE bit
322 * before the DMAENAB bit -- and the
323 * latter doesn't always get cleared
324 * before we get here...
326 csr &= ~(MUSB_TXCSR_AUTOSET
327 | MUSB_TXCSR_DMAENAB);
328 musb_writew(epio, MUSB_TXCSR, csr
329 | MUSB_TXCSR_P_WZC_BITS);
330 csr &= ~MUSB_TXCSR_DMAMODE;
331 csr |= (MUSB_TXCSR_DMAENAB |
333 /* against programming guide */
335 csr |= (MUSB_TXCSR_DMAENAB
339 * Enable Autoset according to table
341 * bulk_split hb_mult Autoset_Enable
343 * 0 >0 No(High BW ISO)
347 if (!musb_ep->hb_mult ||
350 csr |= MUSB_TXCSR_AUTOSET;
352 csr &= ~MUSB_TXCSR_P_UNDERRUN;
354 musb_writew(epio, MUSB_TXCSR, csr);
358 if (is_cppi_enabled(musb)) {
359 /* program endpoint CSR first, then setup DMA */
360 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
361 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
363 musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS &
364 ~MUSB_TXCSR_P_UNDERRUN) | csr);
366 /* ensure writebuffer is empty */
367 csr = musb_readw(epio, MUSB_TXCSR);
370 * NOTE host side sets DMAENAB later than this; both are
371 * OK since the transfer dma glue (between CPPI and
372 * Mentor fifos) just tells CPPI it could start. Data
373 * only moves to the USB TX fifo when both fifos are
377 * "mode" is irrelevant here; handle terminating ZLPs
378 * like PIO does, since the hardware RNDIS mode seems
379 * unreliable except for the
380 * last-packet-is-already-short case.
382 use_dma = use_dma && c->channel_program(
383 musb_ep->dma, musb_ep->packet_sz,
385 request->dma + request->actual,
388 c->channel_release(musb_ep->dma);
390 csr &= ~MUSB_TXCSR_DMAENAB;
391 musb_writew(epio, MUSB_TXCSR, csr);
392 /* invariant: prequest->buf is non-null */
394 } else if (tusb_dma_omap(musb))
395 use_dma = use_dma && c->channel_program(
396 musb_ep->dma, musb_ep->packet_sz,
398 request->dma + request->actual,
405 * Unmap the dma buffer back to cpu if dma channel
408 unmap_dma_buffer(req, musb);
410 musb_write_fifo(musb_ep->hw_ep, fifo_count,
411 (u8 *) (request->buf + request->actual));
412 request->actual += fifo_count;
413 csr |= MUSB_TXCSR_TXPKTRDY;
414 csr &= ~MUSB_TXCSR_P_UNDERRUN;
415 musb_writew(epio, MUSB_TXCSR, csr);
418 /* host may already have the data when this message shows... */
419 musb_dbg(musb, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d",
420 musb_ep->end_point.name, use_dma ? "dma" : "pio",
421 request->actual, request->length,
422 musb_readw(epio, MUSB_TXCSR),
424 musb_readw(epio, MUSB_TXMAXP));
428 * FIFO state update (e.g. data ready).
429 * Called from IRQ, with controller locked.
431 void musb_g_tx(struct musb *musb, u8 epnum)
434 struct musb_request *req;
435 struct usb_request *request;
436 u8 __iomem *mbase = musb->mregs;
437 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
438 void __iomem *epio = musb->endpoints[epnum].regs;
439 struct dma_channel *dma;
441 musb_ep_select(mbase, epnum);
442 req = next_request(musb_ep);
443 request = &req->request;
445 csr = musb_readw(epio, MUSB_TXCSR);
446 musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);
448 dma = is_dma_capable() ? musb_ep->dma : NULL;
451 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
452 * probably rates reporting as a host error.
454 if (csr & MUSB_TXCSR_P_SENTSTALL) {
455 csr |= MUSB_TXCSR_P_WZC_BITS;
456 csr &= ~MUSB_TXCSR_P_SENTSTALL;
457 musb_writew(epio, MUSB_TXCSR, csr);
461 if (csr & MUSB_TXCSR_P_UNDERRUN) {
462 /* We NAKed, no big deal... little reason to care. */
463 csr |= MUSB_TXCSR_P_WZC_BITS;
464 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
465 musb_writew(epio, MUSB_TXCSR, csr);
466 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
470 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
472 * SHOULD NOT HAPPEN... has with CPPI though, after
473 * changing SENDSTALL (and other cases); harmless?
475 musb_dbg(musb, "%s dma still busy?", musb_ep->end_point.name);
481 trace_musb_req_tx(req);
483 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
484 csr |= MUSB_TXCSR_P_WZC_BITS;
485 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
486 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
487 musb_writew(epio, MUSB_TXCSR, csr);
488 /* Ensure writebuffer is empty. */
489 csr = musb_readw(epio, MUSB_TXCSR);
490 request->actual += musb_ep->dma->actual_len;
491 musb_dbg(musb, "TXCSR%d %04x, DMA off, len %zu, req %p",
492 epnum, csr, musb_ep->dma->actual_len, request);
496 * First, maybe a terminating short packet. Some DMA
497 * engines might handle this by themselves.
499 if ((request->zero && request->length)
500 && (request->length % musb_ep->packet_sz == 0)
501 && (request->actual == request->length)) {
504 * On DMA completion, FIFO may not be
507 if (csr & MUSB_TXCSR_TXPKTRDY)
510 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
511 | MUSB_TXCSR_TXPKTRDY);
515 if (request->actual == request->length) {
516 musb_g_giveback(musb_ep, request, 0);
518 * In the giveback function the MUSB lock is
519 * released and acquired after sometime. During
520 * this time period the INDEX register could get
521 * changed by the gadget_queue function especially
522 * on SMP systems. Reselect the INDEX to be sure
523 * we are reading/modifying the right registers
525 musb_ep_select(mbase, epnum);
526 req = musb_ep->desc ? next_request(musb_ep) : NULL;
528 musb_dbg(musb, "%s idle now",
529 musb_ep->end_point.name);
538 /* ------------------------------------------------------------ */
541 * Context: controller locked, IRQs blocked, endpoint selected
543 static void rxstate(struct musb *musb, struct musb_request *req)
545 const u8 epnum = req->epnum;
546 struct usb_request *request = &req->request;
547 struct musb_ep *musb_ep;
548 void __iomem *epio = musb->endpoints[epnum].regs;
551 u16 csr = musb_readw(epio, MUSB_RXCSR);
552 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
555 if (hw_ep->is_shared_fifo)
556 musb_ep = &hw_ep->ep_in;
558 musb_ep = &hw_ep->ep_out;
560 fifo_count = musb_ep->packet_sz;
562 /* Check if EP is disabled */
563 if (!musb_ep->desc) {
564 musb_dbg(musb, "ep:%s disabled - ignore request",
565 musb_ep->end_point.name);
569 /* We shouldn't get here while DMA is active, but we do... */
570 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
571 musb_dbg(musb, "DMA pending...");
575 if (csr & MUSB_RXCSR_P_SENDSTALL) {
576 musb_dbg(musb, "%s stalling, RXCSR %04x",
577 musb_ep->end_point.name, csr);
581 if (is_cppi_enabled(musb) && is_buffer_mapped(req)) {
582 struct dma_controller *c = musb->dma_controller;
583 struct dma_channel *channel = musb_ep->dma;
585 /* NOTE: CPPI won't actually stop advancing the DMA
586 * queue after short packet transfers, so this is almost
587 * always going to run as IRQ-per-packet DMA so that
588 * faults will be handled correctly.
590 if (c->channel_program(channel,
592 !request->short_not_ok,
593 request->dma + request->actual,
594 request->length - request->actual)) {
596 /* make sure that if an rxpkt arrived after the irq,
597 * the cppi engine will be ready to take it as soon
600 csr &= ~(MUSB_RXCSR_AUTOCLEAR
601 | MUSB_RXCSR_DMAMODE);
602 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
603 musb_writew(epio, MUSB_RXCSR, csr);
608 if (csr & MUSB_RXCSR_RXPKTRDY) {
609 fifo_count = musb_readw(epio, MUSB_RXCOUNT);
612 * Enable Mode 1 on RX transfers only when short_not_ok flag
613 * is set. Currently short_not_ok flag is set only from
614 * file_storage and f_mass_storage drivers
617 if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
622 if (request->actual < request->length) {
623 if (!is_buffer_mapped(req))
624 goto buffer_aint_mapped;
626 if (musb_dma_inventra(musb)) {
627 struct dma_controller *c;
628 struct dma_channel *channel;
630 unsigned int transfer_size;
632 c = musb->dma_controller;
633 channel = musb_ep->dma;
635 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
636 * mode 0 only. So we do not get endpoint interrupts due to DMA
637 * completion. We only get interrupts from DMA controller.
639 * We could operate in DMA mode 1 if we knew the size of the tranfer
640 * in advance. For mass storage class, request->length = what the host
641 * sends, so that'd work. But for pretty much everything else,
642 * request->length is routinely more than what the host sends. For
643 * most these gadgets, end of is signified either by a short packet,
644 * or filling the last byte of the buffer. (Sending extra data in
645 * that last pckate should trigger an overflow fault.) But in mode 1,
646 * we don't get DMA completion interrupt for short packets.
648 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
649 * to get endpoint interrupt on every DMA req, but that didn't seem
652 * REVISIT an updated g_file_storage can set req->short_not_ok, which
653 * then becomes usable as a runtime "use mode 1" hint...
656 /* Experimental: Mode1 works with mass storage use cases */
658 csr |= MUSB_RXCSR_AUTOCLEAR;
659 musb_writew(epio, MUSB_RXCSR, csr);
660 csr |= MUSB_RXCSR_DMAENAB;
661 musb_writew(epio, MUSB_RXCSR, csr);
664 * this special sequence (enabling and then
665 * disabling MUSB_RXCSR_DMAMODE) is required
666 * to get DMAReq to activate
668 musb_writew(epio, MUSB_RXCSR,
669 csr | MUSB_RXCSR_DMAMODE);
670 musb_writew(epio, MUSB_RXCSR, csr);
672 transfer_size = min_t(unsigned int,
676 musb_ep->dma->desired_mode = 1;
678 if (!musb_ep->hb_mult &&
679 musb_ep->hw_ep->rx_double_buffered)
680 csr |= MUSB_RXCSR_AUTOCLEAR;
681 csr |= MUSB_RXCSR_DMAENAB;
682 musb_writew(epio, MUSB_RXCSR, csr);
684 transfer_size = min(request->length - request->actual,
685 (unsigned)fifo_count);
686 musb_ep->dma->desired_mode = 0;
689 use_dma = c->channel_program(
692 channel->desired_mode,
701 if ((musb_dma_ux500(musb)) &&
702 (request->actual < request->length)) {
704 struct dma_controller *c;
705 struct dma_channel *channel;
706 unsigned int transfer_size = 0;
708 c = musb->dma_controller;
709 channel = musb_ep->dma;
711 /* In case first packet is short */
712 if (fifo_count < musb_ep->packet_sz)
713 transfer_size = fifo_count;
714 else if (request->short_not_ok)
715 transfer_size = min_t(unsigned int,
720 transfer_size = min_t(unsigned int,
723 (unsigned)fifo_count);
725 csr &= ~MUSB_RXCSR_DMAMODE;
726 csr |= (MUSB_RXCSR_DMAENAB |
727 MUSB_RXCSR_AUTOCLEAR);
729 musb_writew(epio, MUSB_RXCSR, csr);
731 if (transfer_size <= musb_ep->packet_sz) {
732 musb_ep->dma->desired_mode = 0;
734 musb_ep->dma->desired_mode = 1;
735 /* Mode must be set after DMAENAB */
736 csr |= MUSB_RXCSR_DMAMODE;
737 musb_writew(epio, MUSB_RXCSR, csr);
740 if (c->channel_program(channel,
742 channel->desired_mode,
750 len = request->length - request->actual;
751 musb_dbg(musb, "%s OUT/RX pio fifo %d/%d, maxpacket %d",
752 musb_ep->end_point.name,
756 fifo_count = min_t(unsigned, len, fifo_count);
758 if (tusb_dma_omap(musb)) {
759 struct dma_controller *c = musb->dma_controller;
760 struct dma_channel *channel = musb_ep->dma;
761 u32 dma_addr = request->dma + request->actual;
764 ret = c->channel_program(channel,
766 channel->desired_mode,
774 * Unmap the dma buffer back to cpu if dma channel
775 * programming fails. This buffer is mapped if the
776 * channel allocation is successful
778 unmap_dma_buffer(req, musb);
781 * Clear DMAENAB and AUTOCLEAR for the
784 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
785 musb_writew(epio, MUSB_RXCSR, csr);
788 fifo_count = min_t(unsigned int,
789 request->length - request->actual,
790 (unsigned int)fifo_count);
791 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
792 (request->buf + request->actual));
793 request->actual += fifo_count;
795 /* REVISIT if we left anything in the fifo, flush
796 * it and report -EOVERFLOW
800 csr |= MUSB_RXCSR_P_WZC_BITS;
801 csr &= ~MUSB_RXCSR_RXPKTRDY;
802 musb_writew(epio, MUSB_RXCSR, csr);
806 /* reach the end or short packet detected */
807 if (request->actual == request->length ||
808 fifo_count < musb_ep->packet_sz)
809 musb_g_giveback(musb_ep, request, 0);
813 * Data ready for a request; called from IRQ
815 void musb_g_rx(struct musb *musb, u8 epnum)
818 struct musb_request *req;
819 struct usb_request *request;
820 void __iomem *mbase = musb->mregs;
821 struct musb_ep *musb_ep;
822 void __iomem *epio = musb->endpoints[epnum].regs;
823 struct dma_channel *dma;
824 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
826 if (hw_ep->is_shared_fifo)
827 musb_ep = &hw_ep->ep_in;
829 musb_ep = &hw_ep->ep_out;
831 musb_ep_select(mbase, epnum);
833 req = next_request(musb_ep);
837 trace_musb_req_rx(req);
838 request = &req->request;
840 csr = musb_readw(epio, MUSB_RXCSR);
841 dma = is_dma_capable() ? musb_ep->dma : NULL;
843 musb_dbg(musb, "<== %s, rxcsr %04x%s %p", musb_ep->end_point.name,
844 csr, dma ? " (dma)" : "", request);
846 if (csr & MUSB_RXCSR_P_SENTSTALL) {
847 csr |= MUSB_RXCSR_P_WZC_BITS;
848 csr &= ~MUSB_RXCSR_P_SENTSTALL;
849 musb_writew(epio, MUSB_RXCSR, csr);
853 if (csr & MUSB_RXCSR_P_OVERRUN) {
854 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
855 csr &= ~MUSB_RXCSR_P_OVERRUN;
856 musb_writew(epio, MUSB_RXCSR, csr);
858 musb_dbg(musb, "%s iso overrun on %p", musb_ep->name, request);
859 if (request->status == -EINPROGRESS)
860 request->status = -EOVERFLOW;
862 if (csr & MUSB_RXCSR_INCOMPRX) {
863 /* REVISIT not necessarily an error */
864 musb_dbg(musb, "%s, incomprx", musb_ep->end_point.name);
867 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
868 /* "should not happen"; likely RXPKTRDY pending for DMA */
869 musb_dbg(musb, "%s busy, csr %04x",
870 musb_ep->end_point.name, csr);
874 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
875 csr &= ~(MUSB_RXCSR_AUTOCLEAR
877 | MUSB_RXCSR_DMAMODE);
878 musb_writew(epio, MUSB_RXCSR,
879 MUSB_RXCSR_P_WZC_BITS | csr);
881 request->actual += musb_ep->dma->actual_len;
883 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
884 defined(CONFIG_USB_UX500_DMA)
885 /* Autoclear doesn't clear RxPktRdy for short packets */
886 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
888 & (musb_ep->packet_sz - 1))) {
890 csr &= ~MUSB_RXCSR_RXPKTRDY;
891 musb_writew(epio, MUSB_RXCSR, csr);
894 /* incomplete, and not short? wait for next IN packet */
895 if ((request->actual < request->length)
896 && (musb_ep->dma->actual_len
897 == musb_ep->packet_sz)) {
898 /* In double buffer case, continue to unload fifo if
899 * there is Rx packet in FIFO.
901 csr = musb_readw(epio, MUSB_RXCSR);
902 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
903 hw_ep->rx_double_buffered)
908 musb_g_giveback(musb_ep, request, 0);
910 * In the giveback function the MUSB lock is
911 * released and acquired after sometime. During
912 * this time period the INDEX register could get
913 * changed by the gadget_queue function especially
914 * on SMP systems. Reselect the INDEX to be sure
915 * we are reading/modifying the right registers
917 musb_ep_select(mbase, epnum);
919 req = next_request(musb_ep);
923 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
924 defined(CONFIG_USB_UX500_DMA)
927 /* Analyze request */
931 /* ------------------------------------------------------------ */
933 static int musb_gadget_enable(struct usb_ep *ep,
934 const struct usb_endpoint_descriptor *desc)
937 struct musb_ep *musb_ep;
938 struct musb_hw_ep *hw_ep;
945 int status = -EINVAL;
950 musb_ep = to_musb_ep(ep);
951 hw_ep = musb_ep->hw_ep;
953 musb = musb_ep->musb;
955 epnum = musb_ep->current_epnum;
957 spin_lock_irqsave(&musb->lock, flags);
963 musb_ep->type = usb_endpoint_type(desc);
965 /* check direction and (later) maxpacket size against endpoint */
966 if (usb_endpoint_num(desc) != epnum)
969 /* REVISIT this rules out high bandwidth periodic transfers */
970 tmp = usb_endpoint_maxp(desc);
974 if (usb_endpoint_dir_in(desc))
975 ok = musb->hb_iso_tx;
977 ok = musb->hb_iso_rx;
980 musb_dbg(musb, "no support for high bandwidth ISO");
983 musb_ep->hb_mult = (tmp >> 11) & 3;
985 musb_ep->hb_mult = 0;
988 musb_ep->packet_sz = tmp & 0x7ff;
989 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
991 /* enable the interrupts for the endpoint, set the endpoint
992 * packet size (or fail), set the mode, clear the fifo
994 musb_ep_select(mbase, epnum);
995 if (usb_endpoint_dir_in(desc)) {
997 if (hw_ep->is_shared_fifo)
1002 if (tmp > hw_ep->max_packet_sz_tx) {
1003 musb_dbg(musb, "packet size beyond hardware FIFO size");
1007 musb->intrtxe |= (1 << epnum);
1008 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1010 /* REVISIT if can_bulk_split(), use by updating "tmp";
1011 * likewise high bandwidth periodic tx
1013 /* Set TXMAXP with the FIFO size of the endpoint
1014 * to disable double buffering mode.
1016 if (musb->double_buffer_not_ok) {
1017 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1019 if (can_bulk_split(musb, musb_ep->type))
1020 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
1021 musb_ep->packet_sz) - 1;
1022 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1023 | (musb_ep->hb_mult << 11));
1026 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1027 if (musb_readw(regs, MUSB_TXCSR)
1028 & MUSB_TXCSR_FIFONOTEMPTY)
1029 csr |= MUSB_TXCSR_FLUSHFIFO;
1030 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1031 csr |= MUSB_TXCSR_P_ISO;
1033 /* set twice in case of double buffering */
1034 musb_writew(regs, MUSB_TXCSR, csr);
1035 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1036 musb_writew(regs, MUSB_TXCSR, csr);
1040 if (hw_ep->is_shared_fifo)
1045 if (tmp > hw_ep->max_packet_sz_rx) {
1046 musb_dbg(musb, "packet size beyond hardware FIFO size");
1050 musb->intrrxe |= (1 << epnum);
1051 musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
1053 /* REVISIT if can_bulk_combine() use by updating "tmp"
1054 * likewise high bandwidth periodic rx
1056 /* Set RXMAXP with the FIFO size of the endpoint
1057 * to disable double buffering mode.
1059 if (musb->double_buffer_not_ok)
1060 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1062 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1063 | (musb_ep->hb_mult << 11));
1065 /* force shared fifo to OUT-only mode */
1066 if (hw_ep->is_shared_fifo) {
1067 csr = musb_readw(regs, MUSB_TXCSR);
1068 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1069 musb_writew(regs, MUSB_TXCSR, csr);
1072 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1073 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1074 csr |= MUSB_RXCSR_P_ISO;
1075 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1076 csr |= MUSB_RXCSR_DISNYET;
1078 /* set twice in case of double buffering */
1079 musb_writew(regs, MUSB_RXCSR, csr);
1080 musb_writew(regs, MUSB_RXCSR, csr);
1083 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1084 * for some reason you run out of channels here.
1086 if (is_dma_capable() && musb->dma_controller) {
1087 struct dma_controller *c = musb->dma_controller;
1089 musb_ep->dma = c->channel_alloc(c, hw_ep,
1090 (desc->bEndpointAddress & USB_DIR_IN));
1092 musb_ep->dma = NULL;
1094 musb_ep->desc = desc;
1096 musb_ep->wedged = 0;
1099 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1100 musb_driver_name, musb_ep->end_point.name,
1101 ({ char *s; switch (musb_ep->type) {
1102 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1103 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1104 default: s = "iso"; break;
1106 musb_ep->is_in ? "IN" : "OUT",
1107 musb_ep->dma ? "dma, " : "",
1108 musb_ep->packet_sz);
1110 schedule_delayed_work(&musb->irq_work, 0);
1113 spin_unlock_irqrestore(&musb->lock, flags);
1118 * Disable an endpoint flushing all requests queued.
1120 static int musb_gadget_disable(struct usb_ep *ep)
1122 unsigned long flags;
1125 struct musb_ep *musb_ep;
1129 musb_ep = to_musb_ep(ep);
1130 musb = musb_ep->musb;
1131 epnum = musb_ep->current_epnum;
1132 epio = musb->endpoints[epnum].regs;
1134 spin_lock_irqsave(&musb->lock, flags);
1135 musb_ep_select(musb->mregs, epnum);
1137 /* zero the endpoint sizes */
1138 if (musb_ep->is_in) {
1139 musb->intrtxe &= ~(1 << epnum);
1140 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
1141 musb_writew(epio, MUSB_TXMAXP, 0);
1143 musb->intrrxe &= ~(1 << epnum);
1144 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
1145 musb_writew(epio, MUSB_RXMAXP, 0);
1148 /* abort all pending DMA and requests */
1149 nuke(musb_ep, -ESHUTDOWN);
1151 musb_ep->desc = NULL;
1152 musb_ep->end_point.desc = NULL;
1154 schedule_delayed_work(&musb->irq_work, 0);
1156 spin_unlock_irqrestore(&(musb->lock), flags);
1158 musb_dbg(musb, "%s", musb_ep->end_point.name);
1164 * Allocate a request for an endpoint.
1165 * Reused by ep0 code.
1167 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1169 struct musb_ep *musb_ep = to_musb_ep(ep);
1170 struct musb_request *request = NULL;
1172 request = kzalloc(sizeof *request, gfp_flags);
1176 request->request.dma = DMA_ADDR_INVALID;
1177 request->epnum = musb_ep->current_epnum;
1178 request->ep = musb_ep;
1180 trace_musb_req_alloc(request);
1181 return &request->request;
1186 * Reused by ep0 code.
1188 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1190 struct musb_request *request = to_musb_request(req);
1192 trace_musb_req_free(request);
1196 static LIST_HEAD(buffers);
1198 struct free_record {
1199 struct list_head list;
1206 * Context: controller locked, IRQs blocked.
1208 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1210 trace_musb_req_start(req);
1211 musb_ep_select(musb->mregs, req->epnum);
1218 static int musb_ep_restart_resume_work(struct musb *musb, void *data)
1220 struct musb_request *req = data;
1222 musb_ep_restart(musb, req);
1227 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1230 struct musb_ep *musb_ep;
1231 struct musb_request *request;
1234 unsigned long lockflags;
1241 musb_ep = to_musb_ep(ep);
1242 musb = musb_ep->musb;
1244 request = to_musb_request(req);
1245 request->musb = musb;
1247 if (request->ep != musb_ep)
1250 status = pm_runtime_get(musb->controller);
1251 if ((status != -EINPROGRESS) && status < 0) {
1252 dev_err(musb->controller,
1253 "pm runtime get failed in %s\n",
1255 pm_runtime_put_noidle(musb->controller);
1261 trace_musb_req_enq(request);
1263 /* request is mine now... */
1264 request->request.actual = 0;
1265 request->request.status = -EINPROGRESS;
1266 request->epnum = musb_ep->current_epnum;
1267 request->tx = musb_ep->is_in;
1269 map_dma_buffer(request, musb, musb_ep);
1271 spin_lock_irqsave(&musb->lock, lockflags);
1273 /* don't queue if the ep is down */
1274 if (!musb_ep->desc) {
1275 musb_dbg(musb, "req %p queued to %s while ep %s",
1276 req, ep->name, "disabled");
1277 status = -ESHUTDOWN;
1278 unmap_dma_buffer(request, musb);
1282 /* add request to the list */
1283 list_add_tail(&request->list, &musb_ep->req_list);
1285 /* it this is the head of the queue, start i/o ... */
1286 if (!musb_ep->busy && &request->list == musb_ep->req_list.next) {
1287 status = musb_queue_resume_work(musb,
1288 musb_ep_restart_resume_work,
1291 dev_err(musb->controller, "%s resume work: %i\n",
1293 list_del(&request->list);
1298 spin_unlock_irqrestore(&musb->lock, lockflags);
1299 pm_runtime_mark_last_busy(musb->controller);
1300 pm_runtime_put_autosuspend(musb->controller);
1305 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1307 struct musb_ep *musb_ep = to_musb_ep(ep);
1308 struct musb_request *req = to_musb_request(request);
1309 struct musb_request *r;
1310 unsigned long flags;
1312 struct musb *musb = musb_ep->musb;
1314 if (!ep || !request || req->ep != musb_ep)
1317 trace_musb_req_deq(req);
1319 spin_lock_irqsave(&musb->lock, flags);
1321 list_for_each_entry(r, &musb_ep->req_list, list) {
1326 dev_err(musb->controller, "request %p not queued to %s\n",
1332 /* if the hardware doesn't have the request, easy ... */
1333 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1334 musb_g_giveback(musb_ep, request, -ECONNRESET);
1336 /* ... else abort the dma transfer ... */
1337 else if (is_dma_capable() && musb_ep->dma) {
1338 struct dma_controller *c = musb->dma_controller;
1340 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1341 if (c->channel_abort)
1342 status = c->channel_abort(musb_ep->dma);
1346 musb_g_giveback(musb_ep, request, -ECONNRESET);
1348 /* NOTE: by sticking to easily tested hardware/driver states,
1349 * we leave counting of in-flight packets imprecise.
1351 musb_g_giveback(musb_ep, request, -ECONNRESET);
1355 spin_unlock_irqrestore(&musb->lock, flags);
1360 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1361 * data but will queue requests.
1363 * exported to ep0 code
1365 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1367 struct musb_ep *musb_ep = to_musb_ep(ep);
1368 u8 epnum = musb_ep->current_epnum;
1369 struct musb *musb = musb_ep->musb;
1370 void __iomem *epio = musb->endpoints[epnum].regs;
1371 void __iomem *mbase;
1372 unsigned long flags;
1374 struct musb_request *request;
1379 mbase = musb->mregs;
1381 spin_lock_irqsave(&musb->lock, flags);
1383 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1388 musb_ep_select(mbase, epnum);
1390 request = next_request(musb_ep);
1393 musb_dbg(musb, "request in progress, cannot halt %s",
1398 /* Cannot portably stall with non-empty FIFO */
1399 if (musb_ep->is_in) {
1400 csr = musb_readw(epio, MUSB_TXCSR);
1401 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1402 musb_dbg(musb, "FIFO busy, cannot halt %s",
1409 musb_ep->wedged = 0;
1411 /* set/clear the stall and toggle bits */
1412 musb_dbg(musb, "%s: %s stall", ep->name, value ? "set" : "clear");
1413 if (musb_ep->is_in) {
1414 csr = musb_readw(epio, MUSB_TXCSR);
1415 csr |= MUSB_TXCSR_P_WZC_BITS
1416 | MUSB_TXCSR_CLRDATATOG;
1418 csr |= MUSB_TXCSR_P_SENDSTALL;
1420 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1421 | MUSB_TXCSR_P_SENTSTALL);
1422 csr &= ~MUSB_TXCSR_TXPKTRDY;
1423 musb_writew(epio, MUSB_TXCSR, csr);
1425 csr = musb_readw(epio, MUSB_RXCSR);
1426 csr |= MUSB_RXCSR_P_WZC_BITS
1427 | MUSB_RXCSR_FLUSHFIFO
1428 | MUSB_RXCSR_CLRDATATOG;
1430 csr |= MUSB_RXCSR_P_SENDSTALL;
1432 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1433 | MUSB_RXCSR_P_SENTSTALL);
1434 musb_writew(epio, MUSB_RXCSR, csr);
1437 /* maybe start the first request in the queue */
1438 if (!musb_ep->busy && !value && request) {
1439 musb_dbg(musb, "restarting the request");
1440 musb_ep_restart(musb, request);
1444 spin_unlock_irqrestore(&musb->lock, flags);
1449 * Sets the halt feature with the clear requests ignored
1451 static int musb_gadget_set_wedge(struct usb_ep *ep)
1453 struct musb_ep *musb_ep = to_musb_ep(ep);
1458 musb_ep->wedged = 1;
1460 return usb_ep_set_halt(ep);
1463 static int musb_gadget_fifo_status(struct usb_ep *ep)
1465 struct musb_ep *musb_ep = to_musb_ep(ep);
1466 void __iomem *epio = musb_ep->hw_ep->regs;
1467 int retval = -EINVAL;
1469 if (musb_ep->desc && !musb_ep->is_in) {
1470 struct musb *musb = musb_ep->musb;
1471 int epnum = musb_ep->current_epnum;
1472 void __iomem *mbase = musb->mregs;
1473 unsigned long flags;
1475 spin_lock_irqsave(&musb->lock, flags);
1477 musb_ep_select(mbase, epnum);
1478 /* FIXME return zero unless RXPKTRDY is set */
1479 retval = musb_readw(epio, MUSB_RXCOUNT);
1481 spin_unlock_irqrestore(&musb->lock, flags);
1486 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1488 struct musb_ep *musb_ep = to_musb_ep(ep);
1489 struct musb *musb = musb_ep->musb;
1490 u8 epnum = musb_ep->current_epnum;
1491 void __iomem *epio = musb->endpoints[epnum].regs;
1492 void __iomem *mbase;
1493 unsigned long flags;
1496 mbase = musb->mregs;
1498 spin_lock_irqsave(&musb->lock, flags);
1499 musb_ep_select(mbase, (u8) epnum);
1501 /* disable interrupts */
1502 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
1504 if (musb_ep->is_in) {
1505 csr = musb_readw(epio, MUSB_TXCSR);
1506 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1507 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1509 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1510 * to interrupt current FIFO loading, but not flushing
1511 * the already loaded ones.
1513 csr &= ~MUSB_TXCSR_TXPKTRDY;
1514 musb_writew(epio, MUSB_TXCSR, csr);
1515 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1516 musb_writew(epio, MUSB_TXCSR, csr);
1519 csr = musb_readw(epio, MUSB_RXCSR);
1520 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1521 musb_writew(epio, MUSB_RXCSR, csr);
1522 musb_writew(epio, MUSB_RXCSR, csr);
1525 /* re-enable interrupt */
1526 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1527 spin_unlock_irqrestore(&musb->lock, flags);
1530 static const struct usb_ep_ops musb_ep_ops = {
1531 .enable = musb_gadget_enable,
1532 .disable = musb_gadget_disable,
1533 .alloc_request = musb_alloc_request,
1534 .free_request = musb_free_request,
1535 .queue = musb_gadget_queue,
1536 .dequeue = musb_gadget_dequeue,
1537 .set_halt = musb_gadget_set_halt,
1538 .set_wedge = musb_gadget_set_wedge,
1539 .fifo_status = musb_gadget_fifo_status,
1540 .fifo_flush = musb_gadget_fifo_flush
1543 /* ----------------------------------------------------------------------- */
1545 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1547 struct musb *musb = gadget_to_musb(gadget);
1549 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1552 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1554 struct musb *musb = gadget_to_musb(gadget);
1555 void __iomem *mregs = musb->mregs;
1556 unsigned long flags;
1557 int status = -EINVAL;
1561 spin_lock_irqsave(&musb->lock, flags);
1563 switch (musb->xceiv->otg->state) {
1564 case OTG_STATE_B_PERIPHERAL:
1565 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1566 * that's part of the standard usb 1.1 state machine, and
1567 * doesn't affect OTG transitions.
1569 if (musb->may_wakeup && musb->is_suspended)
1572 case OTG_STATE_B_IDLE:
1573 /* Start SRP ... OTG not required. */
1574 devctl = musb_readb(mregs, MUSB_DEVCTL);
1575 musb_dbg(musb, "Sending SRP: devctl: %02x", devctl);
1576 devctl |= MUSB_DEVCTL_SESSION;
1577 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1578 devctl = musb_readb(mregs, MUSB_DEVCTL);
1580 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1581 devctl = musb_readb(mregs, MUSB_DEVCTL);
1586 while (devctl & MUSB_DEVCTL_SESSION) {
1587 devctl = musb_readb(mregs, MUSB_DEVCTL);
1592 spin_unlock_irqrestore(&musb->lock, flags);
1593 otg_start_srp(musb->xceiv->otg);
1594 spin_lock_irqsave(&musb->lock, flags);
1596 /* Block idling for at least 1s */
1597 musb_platform_try_idle(musb,
1598 jiffies + msecs_to_jiffies(1 * HZ));
1603 musb_dbg(musb, "Unhandled wake: %s",
1604 usb_otg_state_string(musb->xceiv->otg->state));
1610 power = musb_readb(mregs, MUSB_POWER);
1611 power |= MUSB_POWER_RESUME;
1612 musb_writeb(mregs, MUSB_POWER, power);
1613 musb_dbg(musb, "issue wakeup");
1615 /* FIXME do this next chunk in a timer callback, no udelay */
1618 power = musb_readb(mregs, MUSB_POWER);
1619 power &= ~MUSB_POWER_RESUME;
1620 musb_writeb(mregs, MUSB_POWER, power);
1622 spin_unlock_irqrestore(&musb->lock, flags);
1627 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1629 gadget->is_selfpowered = !!is_selfpowered;
1633 static void musb_pullup(struct musb *musb, int is_on)
1637 power = musb_readb(musb->mregs, MUSB_POWER);
1639 power |= MUSB_POWER_SOFTCONN;
1641 power &= ~MUSB_POWER_SOFTCONN;
1643 /* FIXME if on, HdrcStart; if off, HdrcStop */
1645 musb_dbg(musb, "gadget D+ pullup %s",
1646 is_on ? "on" : "off");
1647 musb_writeb(musb->mregs, MUSB_POWER, power);
1651 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1653 musb_dbg(musb, "<= %s =>\n", __func__);
1656 * FIXME iff driver's softconnect flag is set (as it is during probe,
1657 * though that can clear it), just musb_pullup().
1664 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1666 struct musb *musb = gadget_to_musb(gadget);
1668 if (!musb->xceiv->set_power)
1670 return usb_phy_set_power(musb->xceiv, mA);
1673 static void musb_gadget_work(struct work_struct *work)
1676 unsigned long flags;
1678 musb = container_of(work, struct musb, gadget_work.work);
1679 pm_runtime_get_sync(musb->controller);
1680 spin_lock_irqsave(&musb->lock, flags);
1681 musb_pullup(musb, musb->softconnect);
1682 spin_unlock_irqrestore(&musb->lock, flags);
1683 pm_runtime_mark_last_busy(musb->controller);
1684 pm_runtime_put_autosuspend(musb->controller);
1687 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1689 struct musb *musb = gadget_to_musb(gadget);
1690 unsigned long flags;
1694 /* NOTE: this assumes we are sensing vbus; we'd rather
1695 * not pullup unless the B-session is active.
1697 spin_lock_irqsave(&musb->lock, flags);
1698 if (is_on != musb->softconnect) {
1699 musb->softconnect = is_on;
1700 schedule_delayed_work(&musb->gadget_work, 0);
1702 spin_unlock_irqrestore(&musb->lock, flags);
1707 #ifdef CONFIG_BLACKFIN
1708 static struct usb_ep *musb_match_ep(struct usb_gadget *g,
1709 struct usb_endpoint_descriptor *desc,
1710 struct usb_ss_ep_comp_descriptor *ep_comp)
1712 struct usb_ep *ep = NULL;
1714 switch (usb_endpoint_type(desc)) {
1715 case USB_ENDPOINT_XFER_ISOC:
1716 case USB_ENDPOINT_XFER_BULK:
1717 if (usb_endpoint_dir_in(desc))
1718 ep = gadget_find_ep_by_name(g, "ep5in");
1720 ep = gadget_find_ep_by_name(g, "ep6out");
1722 case USB_ENDPOINT_XFER_INT:
1723 if (usb_endpoint_dir_in(desc))
1724 ep = gadget_find_ep_by_name(g, "ep1in");
1726 ep = gadget_find_ep_by_name(g, "ep2out");
1732 if (ep && usb_gadget_ep_match_desc(g, ep, desc, ep_comp))
1738 #define musb_match_ep NULL
1741 static int musb_gadget_start(struct usb_gadget *g,
1742 struct usb_gadget_driver *driver);
1743 static int musb_gadget_stop(struct usb_gadget *g);
1745 static const struct usb_gadget_ops musb_gadget_operations = {
1746 .get_frame = musb_gadget_get_frame,
1747 .wakeup = musb_gadget_wakeup,
1748 .set_selfpowered = musb_gadget_set_self_powered,
1749 /* .vbus_session = musb_gadget_vbus_session, */
1750 .vbus_draw = musb_gadget_vbus_draw,
1751 .pullup = musb_gadget_pullup,
1752 .udc_start = musb_gadget_start,
1753 .udc_stop = musb_gadget_stop,
1754 .match_ep = musb_match_ep,
1757 /* ----------------------------------------------------------------------- */
1761 /* Only this registration code "knows" the rule (from USB standards)
1762 * about there being only one external upstream port. It assumes
1763 * all peripheral ports are external...
1767 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1769 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1771 memset(ep, 0, sizeof *ep);
1773 ep->current_epnum = epnum;
1778 INIT_LIST_HEAD(&ep->req_list);
1780 sprintf(ep->name, "ep%d%s", epnum,
1781 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1782 is_in ? "in" : "out"));
1783 ep->end_point.name = ep->name;
1784 INIT_LIST_HEAD(&ep->end_point.ep_list);
1786 usb_ep_set_maxpacket_limit(&ep->end_point, 64);
1787 ep->end_point.caps.type_control = true;
1788 ep->end_point.ops = &musb_g_ep0_ops;
1789 musb->g.ep0 = &ep->end_point;
1792 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx);
1794 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx);
1795 ep->end_point.caps.type_iso = true;
1796 ep->end_point.caps.type_bulk = true;
1797 ep->end_point.caps.type_int = true;
1798 ep->end_point.ops = &musb_ep_ops;
1799 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1802 if (!epnum || hw_ep->is_shared_fifo) {
1803 ep->end_point.caps.dir_in = true;
1804 ep->end_point.caps.dir_out = true;
1806 ep->end_point.caps.dir_in = true;
1808 ep->end_point.caps.dir_out = true;
1812 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1813 * to the rest of the driver state.
1815 static inline void musb_g_init_endpoints(struct musb *musb)
1818 struct musb_hw_ep *hw_ep;
1821 /* initialize endpoint list just once */
1822 INIT_LIST_HEAD(&(musb->g.ep_list));
1824 for (epnum = 0, hw_ep = musb->endpoints;
1825 epnum < musb->nr_endpoints;
1827 if (hw_ep->is_shared_fifo /* || !epnum */) {
1828 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1831 if (hw_ep->max_packet_sz_tx) {
1832 init_peripheral_ep(musb, &hw_ep->ep_in,
1836 if (hw_ep->max_packet_sz_rx) {
1837 init_peripheral_ep(musb, &hw_ep->ep_out,
1845 /* called once during driver setup to initialize and link into
1846 * the driver model; memory is zeroed.
1848 int musb_gadget_setup(struct musb *musb)
1852 /* REVISIT minor race: if (erroneously) setting up two
1853 * musb peripherals at the same time, only the bus lock
1857 musb->g.ops = &musb_gadget_operations;
1858 musb->g.max_speed = USB_SPEED_HIGH;
1859 musb->g.speed = USB_SPEED_UNKNOWN;
1861 MUSB_DEV_MODE(musb);
1862 musb->xceiv->otg->default_a = 0;
1863 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1865 /* this "gadget" abstracts/virtualizes the controller */
1866 musb->g.name = musb_driver_name;
1867 #if IS_ENABLED(CONFIG_USB_MUSB_DUAL_ROLE)
1869 #elif IS_ENABLED(CONFIG_USB_MUSB_GADGET)
1872 INIT_DELAYED_WORK(&musb->gadget_work, musb_gadget_work);
1873 musb_g_init_endpoints(musb);
1875 musb->is_active = 0;
1876 musb_platform_try_idle(musb, 0);
1878 status = usb_add_gadget_udc(musb->controller, &musb->g);
1884 musb->g.dev.parent = NULL;
1885 device_unregister(&musb->g.dev);
1889 void musb_gadget_cleanup(struct musb *musb)
1891 if (musb->port_mode == MUSB_PORT_MODE_HOST)
1894 cancel_delayed_work_sync(&musb->gadget_work);
1895 usb_del_gadget_udc(&musb->g);
1899 * Register the gadget driver. Used by gadget drivers when
1900 * registering themselves with the controller.
1902 * -EINVAL something went wrong (not driver)
1903 * -EBUSY another gadget is already using the controller
1904 * -ENOMEM no memory to perform the operation
1906 * @param driver the gadget driver
1907 * @return <0 if error, 0 if everything is fine
1909 static int musb_gadget_start(struct usb_gadget *g,
1910 struct usb_gadget_driver *driver)
1912 struct musb *musb = gadget_to_musb(g);
1913 struct usb_otg *otg = musb->xceiv->otg;
1914 unsigned long flags;
1917 if (driver->max_speed < USB_SPEED_HIGH) {
1922 pm_runtime_get_sync(musb->controller);
1924 musb->softconnect = 0;
1925 musb->gadget_driver = driver;
1927 spin_lock_irqsave(&musb->lock, flags);
1928 musb->is_active = 1;
1930 otg_set_peripheral(otg, &musb->g);
1931 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1932 spin_unlock_irqrestore(&musb->lock, flags);
1936 /* REVISIT: funcall to other code, which also
1937 * handles power budgeting ... this way also
1938 * ensures HdrcStart is indirectly called.
1940 if (musb->xceiv->last_event == USB_EVENT_ID)
1941 musb_platform_set_vbus(musb, 1);
1943 pm_runtime_mark_last_busy(musb->controller);
1944 pm_runtime_put_autosuspend(musb->controller);
1953 * Unregister the gadget driver. Used by gadget drivers when
1954 * unregistering themselves from the controller.
1956 * @param driver the gadget driver to unregister
1958 static int musb_gadget_stop(struct usb_gadget *g)
1960 struct musb *musb = gadget_to_musb(g);
1961 unsigned long flags;
1963 pm_runtime_get_sync(musb->controller);
1966 * REVISIT always use otg_set_peripheral() here too;
1967 * this needs to shut down the OTG engine.
1970 spin_lock_irqsave(&musb->lock, flags);
1972 musb_hnp_stop(musb);
1974 (void) musb_gadget_vbus_draw(&musb->g, 0);
1976 musb->xceiv->otg->state = OTG_STATE_UNDEFINED;
1978 otg_set_peripheral(musb->xceiv->otg, NULL);
1980 musb->is_active = 0;
1981 musb->gadget_driver = NULL;
1982 musb_platform_try_idle(musb, 0);
1983 spin_unlock_irqrestore(&musb->lock, flags);
1986 * FIXME we need to be able to register another
1987 * gadget driver here and have everything work;
1988 * that currently misbehaves.
1991 /* Force check of devctl register for PM runtime */
1992 schedule_delayed_work(&musb->irq_work, 0);
1994 pm_runtime_mark_last_busy(musb->controller);
1995 pm_runtime_put_autosuspend(musb->controller);
2000 /* ----------------------------------------------------------------------- */
2002 /* lifecycle operations called through plat_uds.c */
2004 void musb_g_resume(struct musb *musb)
2006 musb->is_suspended = 0;
2007 switch (musb->xceiv->otg->state) {
2008 case OTG_STATE_B_IDLE:
2010 case OTG_STATE_B_WAIT_ACON:
2011 case OTG_STATE_B_PERIPHERAL:
2012 musb->is_active = 1;
2013 if (musb->gadget_driver && musb->gadget_driver->resume) {
2014 spin_unlock(&musb->lock);
2015 musb->gadget_driver->resume(&musb->g);
2016 spin_lock(&musb->lock);
2020 WARNING("unhandled RESUME transition (%s)\n",
2021 usb_otg_state_string(musb->xceiv->otg->state));
2025 /* called when SOF packets stop for 3+ msec */
2026 void musb_g_suspend(struct musb *musb)
2030 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2031 musb_dbg(musb, "musb_g_suspend: devctl %02x", devctl);
2033 switch (musb->xceiv->otg->state) {
2034 case OTG_STATE_B_IDLE:
2035 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2036 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2038 case OTG_STATE_B_PERIPHERAL:
2039 musb->is_suspended = 1;
2040 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2041 spin_unlock(&musb->lock);
2042 musb->gadget_driver->suspend(&musb->g);
2043 spin_lock(&musb->lock);
2047 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2048 * A_PERIPHERAL may need care too
2050 WARNING("unhandled SUSPEND transition (%s)",
2051 usb_otg_state_string(musb->xceiv->otg->state));
2055 /* Called during SRP */
2056 void musb_g_wakeup(struct musb *musb)
2058 musb_gadget_wakeup(&musb->g);
2061 /* called when VBUS drops below session threshold, and in other cases */
2062 void musb_g_disconnect(struct musb *musb)
2064 void __iomem *mregs = musb->mregs;
2065 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2067 musb_dbg(musb, "musb_g_disconnect: devctl %02x", devctl);
2070 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2072 /* don't draw vbus until new b-default session */
2073 (void) musb_gadget_vbus_draw(&musb->g, 0);
2075 musb->g.speed = USB_SPEED_UNKNOWN;
2076 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2077 spin_unlock(&musb->lock);
2078 musb->gadget_driver->disconnect(&musb->g);
2079 spin_lock(&musb->lock);
2082 switch (musb->xceiv->otg->state) {
2084 musb_dbg(musb, "Unhandled disconnect %s, setting a_idle",
2085 usb_otg_state_string(musb->xceiv->otg->state));
2086 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2087 MUSB_HST_MODE(musb);
2089 case OTG_STATE_A_PERIPHERAL:
2090 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2091 MUSB_HST_MODE(musb);
2093 case OTG_STATE_B_WAIT_ACON:
2094 case OTG_STATE_B_HOST:
2095 case OTG_STATE_B_PERIPHERAL:
2096 case OTG_STATE_B_IDLE:
2097 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2099 case OTG_STATE_B_SRP_INIT:
2103 musb->is_active = 0;
2106 void musb_g_reset(struct musb *musb)
2107 __releases(musb->lock)
2108 __acquires(musb->lock)
2110 void __iomem *mbase = musb->mregs;
2111 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2114 musb_dbg(musb, "<== %s driver '%s'",
2115 (devctl & MUSB_DEVCTL_BDEVICE)
2116 ? "B-Device" : "A-Device",
2118 ? musb->gadget_driver->driver.name
2122 /* report reset, if we didn't already (flushing EP state) */
2123 if (musb->gadget_driver && musb->g.speed != USB_SPEED_UNKNOWN) {
2124 spin_unlock(&musb->lock);
2125 usb_gadget_udc_reset(&musb->g, musb->gadget_driver);
2126 spin_lock(&musb->lock);
2130 else if (devctl & MUSB_DEVCTL_HR)
2131 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2134 /* what speed did we negotiate? */
2135 power = musb_readb(mbase, MUSB_POWER);
2136 musb->g.speed = (power & MUSB_POWER_HSMODE)
2137 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2139 /* start in USB_STATE_DEFAULT */
2140 musb->is_active = 1;
2141 musb->is_suspended = 0;
2142 MUSB_DEV_MODE(musb);
2144 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2146 musb->may_wakeup = 0;
2147 musb->g.b_hnp_enable = 0;
2148 musb->g.a_alt_hnp_support = 0;
2149 musb->g.a_hnp_support = 0;
2150 musb->g.quirk_zlp_not_supp = 1;
2152 /* Normal reset, as B-Device;
2153 * or else after HNP, as A-Device
2155 if (!musb->g.is_otg) {
2156 /* USB device controllers that are not OTG compatible
2157 * may not have DEVCTL register in silicon.
2158 * In that case, do not rely on devctl for setting
2161 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2162 musb->g.is_a_peripheral = 0;
2163 } else if (devctl & MUSB_DEVCTL_BDEVICE) {
2164 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2165 musb->g.is_a_peripheral = 0;
2167 musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL;
2168 musb->g.is_a_peripheral = 1;
2171 /* start with default limits on VBUS power draw */
2172 (void) musb_gadget_vbus_draw(&musb->g, 8);