drivers/usb/musb/tusb6010.c

   1 /*
   2  * TUSB6010 USB 2.0 OTG Dual Role controller
   3  *
   4  * Copyright (C) 2006 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Notes:
  12  * - Driver assumes that interface to external host (main CPU) is
  13  *   configured for NOR FLASH interface instead of VLYNQ serial
  14  *   interface.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/err.h>
  21 #include <linux/prefetch.h>
  22 #include <linux/usb.h>
  23 #include <linux/irq.h>
  24 #include <linux/io.h>
  25 #include <linux/device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/usb/usb_phy_generic.h>
  29
  30 #include "musb_core.h"
  31
  32 struct tusb6010_glue {
  33         struct device           *dev;
  34         struct platform_device  *musb;
  35         struct platform_device  *phy;
  36 };
  37
  38 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
  39
  40 #define TUSB_REV_MAJOR(reg_val)         ((reg_val >> 4) & 0xf)
  41 #define TUSB_REV_MINOR(reg_val)         (reg_val & 0xf)
  42
  43 /*
  44  * Checks the revision. We need to use the DMA register as 3.0 does not
  45  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
  46  */
  47 static u8 tusb_get_revision(struct musb *musb)
  48 {
  49         void __iomem    *tbase = musb->ctrl_base;
  50         u32             die_id;
  51         u8              rev;
  52
  53         rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
  54         if (TUSB_REV_MAJOR(rev) == 3) {
  55                 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
  56                                 TUSB_DIDR1_HI));
  57                 if (die_id >= TUSB_DIDR1_HI_REV_31)
  58                         rev |= 1;
  59         }
  60
  61         return rev;
  62 }
  63
  64 static void tusb_print_revision(struct musb *musb)
  65 {
  66         void __iomem    *tbase = musb->ctrl_base;
  67         u8              rev;
  68
  69         rev = musb->tusb_revision;
  70
  71         pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
  72                 "prcm",
  73                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
  74                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
  75                 "int",
  76                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  77                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  78                 "gpio",
  79                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
  80                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
  81                 "dma",
  82                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  83                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  84                 "dieid",
  85                 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
  86                 "rev",
  87                 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
  88 }
  89
  90 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
  91                                 | TUSB_PHY_OTG_CTRL_TESTM0)
  92
  93 /*
  94  * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
  95  * Disables power detection in PHY for the duration of idle.
  96  */
  97 static void tusb_wbus_quirk(struct musb *musb, int enabled)
  98 {
  99         void __iomem    *tbase = musb->ctrl_base;
 100         static u32      phy_otg_ctrl, phy_otg_ena;
 101         u32             tmp;
 102
 103         if (enabled) {
 104                 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
 105                 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
 106                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
 107                                 | phy_otg_ena | WBUS_QUIRK_MASK;
 108                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
 109                 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
 110                 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
 111                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
 112                 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
 113                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
 114                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
 115         } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
 116                                         & TUSB_PHY_OTG_CTRL_TESTM2) {
 117                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
 118                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
 119                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
 120                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
 121                 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
 122                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
 123                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
 124                 phy_otg_ctrl = 0;
 125                 phy_otg_ena = 0;
 126         }
 127 }
 128
 129 static u32 tusb_fifo_offset(u8 epnum)
 130 {
 131         return 0x200 + (epnum * 0x20);
 132 }
 133
 134 static u32 tusb_ep_offset(u8 epnum, u16 offset)
 135 {
 136         return 0x10 + offset;
 137 }
 138
 139 /* TUSB mapping: "flat" plus ep0 special cases */
 140 static void tusb_ep_select(void __iomem *mbase, u8 epnum)
 141 {
 142         musb_writeb(mbase, MUSB_INDEX, epnum);
 143 }
 144
 145 /*
 146  * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
 147  */
 148 static u8 tusb_readb(const void __iomem *addr, unsigned offset)
 149 {
 150         u16 tmp;
 151         u8 val;
 152
 153         tmp = __raw_readw(addr + (offset & ~1));
 154         if (offset & 1)
 155                 val = (tmp >> 8);
 156         else
 157                 val = tmp & 0xff;
 158
 159         return val;
 160 }
 161
 162 static void tusb_writeb(void __iomem *addr, unsigned offset, u8 data)
 163 {
 164         u16 tmp;
 165
 166         tmp = __raw_readw(addr + (offset & ~1));
 167         if (offset & 1)
 168                 tmp = (data << 8) | (tmp & 0xff);
 169         else
 170                 tmp = (tmp & 0xff00) | data;
 171
 172         __raw_writew(tmp, addr + (offset & ~1));
 173 }
 174
 175 /*
 176  * TUSB 6010 may use a parallel bus that doesn't support byte ops;
 177  * so both loading and unloading FIFOs need explicit byte counts.
 178  */
 179
 180 static inline void
 181 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
 182 {
 183         u32             val;
 184         int             i;
 185
 186         if (len > 4) {
 187                 for (i = 0; i < (len >> 2); i++) {
 188                         memcpy(&val, buf, 4);
 189                         musb_writel(fifo, 0, val);
 190                         buf += 4;
 191                 }
 192                 len %= 4;
 193         }
 194         if (len > 0) {
 195                 /* Write the rest 1 - 3 bytes to FIFO */
 196                 val = 0;
 197                 memcpy(&val, buf, len);
 198                 musb_writel(fifo, 0, val);
 199         }
 200 }
 201
 202 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
 203                                                 void *buf, u16 len)
 204 {
 205         u32             val;
 206         int             i;
 207
 208         if (len > 4) {
 209                 for (i = 0; i < (len >> 2); i++) {
 210                         val = musb_readl(fifo, 0);
 211                         memcpy(buf, &val, 4);
 212                         buf += 4;
 213                 }
 214                 len %= 4;
 215         }
 216         if (len > 0) {
 217                 /* Read the rest 1 - 3 bytes from FIFO */
 218                 val = musb_readl(fifo, 0);
 219                 memcpy(buf, &val, len);
 220         }
 221 }
 222
 223 static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
 224 {
 225         struct musb *musb = hw_ep->musb;
 226         void __iomem    *ep_conf = hw_ep->conf;
 227         void __iomem    *fifo = hw_ep->fifo;
 228         u8              epnum = hw_ep->epnum;
 229
 230         prefetch(buf);
 231
 232         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 233                         'T', epnum, fifo, len, buf);
 234
 235         if (epnum)
 236                 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
 237                         TUSB_EP_CONFIG_XFR_SIZE(len));
 238         else
 239                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
 240                         TUSB_EP0_CONFIG_XFR_SIZE(len));
 241
 242         if (likely((0x01 & (unsigned long) buf) == 0)) {
 243
 244                 /* Best case is 32bit-aligned destination address */
 245                 if ((0x02 & (unsigned long) buf) == 0) {
 246                         if (len >= 4) {
 247                                 iowrite32_rep(fifo, buf, len >> 2);
 248                                 buf += (len & ~0x03);
 249                                 len &= 0x03;
 250                         }
 251                 } else {
 252                         if (len >= 2) {
 253                                 u32 val;
 254                                 int i;
 255
 256                                 /* Cannot use writesw, fifo is 32-bit */
 257                                 for (i = 0; i < (len >> 2); i++) {
 258                                         val = (u32)(*(u16 *)buf);
 259                                         buf += 2;
 260                                         val |= (*(u16 *)buf) << 16;
 261                                         buf += 2;
 262                                         musb_writel(fifo, 0, val);
 263                                 }
 264                                 len &= 0x03;
 265                         }
 266                 }
 267         }
 268
 269         if (len > 0)
 270                 tusb_fifo_write_unaligned(fifo, buf, len);
 271 }
 272
 273 static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
 274 {
 275         struct musb *musb = hw_ep->musb;
 276         void __iomem    *ep_conf = hw_ep->conf;
 277         void __iomem    *fifo = hw_ep->fifo;
 278         u8              epnum = hw_ep->epnum;
 279
 280         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 281                         'R', epnum, fifo, len, buf);
 282
 283         if (epnum)
 284                 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
 285                         TUSB_EP_CONFIG_XFR_SIZE(len));
 286         else
 287                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
 288
 289         if (likely((0x01 & (unsigned long) buf) == 0)) {
 290
 291                 /* Best case is 32bit-aligned destination address */
 292                 if ((0x02 & (unsigned long) buf) == 0) {
 293                         if (len >= 4) {
 294                                 ioread32_rep(fifo, buf, len >> 2);
 295                                 buf += (len & ~0x03);
 296                                 len &= 0x03;
 297                         }
 298                 } else {
 299                         if (len >= 2) {
 300                                 u32 val;
 301                                 int i;
 302
 303                                 /* Cannot use readsw, fifo is 32-bit */
 304                                 for (i = 0; i < (len >> 2); i++) {
 305                                         val = musb_readl(fifo, 0);
 306                                         *(u16 *)buf = (u16)(val & 0xffff);
 307                                         buf += 2;
 308                                         *(u16 *)buf = (u16)(val >> 16);
 309                                         buf += 2;
 310                                 }
 311                                 len &= 0x03;
 312                         }
 313                 }
 314         }
 315
 316         if (len > 0)
 317                 tusb_fifo_read_unaligned(fifo, buf, len);
 318 }
 319
 320 static struct musb *the_musb;
 321
 322 /* This is used by gadget drivers, and OTG transceiver logic, allowing
 323  * at most mA current to be drawn from VBUS during a Default-B session
 324  * (that is, while VBUS exceeds 4.4V).  In Default-A (including pure host
 325  * mode), or low power Default-B sessions, something else supplies power.
 326  * Caller must take care of locking.
 327  */
 328 static int tusb_draw_power(struct usb_phy *x, unsigned mA)
 329 {
 330         struct musb     *musb = the_musb;
 331         void __iomem    *tbase = musb->ctrl_base;
 332         u32             reg;
 333
 334         /* tps65030 seems to consume max 100mA, with maybe 60mA available
 335          * (measured on one board) for things other than tps and tusb.
 336          *
 337          * Boards sharing the CPU clock with CLKIN will need to prevent
 338          * certain idle sleep states while the USB link is active.
 339          *
 340          * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
 341          * The actual current usage would be very board-specific.  For now,
 342          * it's simpler to just use an aggregate (also board-specific).
 343          */
 344         if (x->otg->default_a || mA < (musb->min_power << 1))
 345                 mA = 0;
 346
 347         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
 348         if (mA) {
 349                 musb->is_bus_powered = 1;
 350                 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
 351         } else {
 352                 musb->is_bus_powered = 0;
 353                 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
 354         }
 355         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
 356
 357         dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
 358         return 0;
 359 }
 360
 361 /* workaround for issue 13:  change clock during chip idle
 362  * (to be fixed in rev3 silicon) ... symptoms include disconnect
 363  * or looping suspend/resume cycles
 364  */
 365 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
 366 {
 367         void __iomem    *tbase = musb->ctrl_base;
 368         u32             reg;
 369
 370         reg = musb_readl(tbase, TUSB_PRCM_CONF);
 371         reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
 372
 373         /* 0 = refclk (clkin, XI)
 374          * 1 = PHY 60 MHz (internal PLL)
 375          * 2 = not supported
 376          * 3 = what?
 377          */
 378         if (mode > 0)
 379                 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
 380
 381         musb_writel(tbase, TUSB_PRCM_CONF, reg);
 382
 383         /* FIXME tusb6010_platform_retime(mode == 0); */
 384 }
 385
 386 /*
 387  * Idle TUSB6010 until next wake-up event; NOR access always wakes.
 388  * Other code ensures that we idle unless we're connected _and_ the
 389  * USB link is not suspended ... and tells us the relevant wakeup
 390  * events.  SW_EN for voltage is handled separately.
 391  */
 392 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
 393 {
 394         void __iomem    *tbase = musb->ctrl_base;
 395         u32             reg;
 396
 397         if ((wakeup_enables & TUSB_PRCM_WBUS)
 398                         && (musb->tusb_revision == TUSB_REV_30))
 399                 tusb_wbus_quirk(musb, 1);
 400
 401         tusb_set_clock_source(musb, 0);
 402
 403         wakeup_enables |= TUSB_PRCM_WNORCS;
 404         musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
 405
 406         /* REVISIT writeup of WID implies that if WID set and ID is grounded,
 407          * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
 408          * Presumably that's mostly to save power, hence WID is immaterial ...
 409          */
 410
 411         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
 412         /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
 413         if (is_host_active(musb)) {
 414                 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 415                 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
 416         } else {
 417                 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
 418                 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 419         }
 420         reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
 421         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
 422
 423         dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
 424 }
 425
 426 /*
 427  * Updates cable VBUS status. Caller must take care of locking.
 428  */
 429 static int tusb_musb_vbus_status(struct musb *musb)
 430 {
 431         void __iomem    *tbase = musb->ctrl_base;
 432         u32             otg_stat, prcm_mngmt;
 433         int             ret = 0;
 434
 435         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 436         prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
 437
 438         /* Temporarily enable VBUS detection if it was disabled for
 439          * suspend mode. Unless it's enabled otg_stat and devctl will
 440          * not show correct VBUS state.
 441          */
 442         if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
 443                 u32 tmp = prcm_mngmt;
 444                 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 445                 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
 446                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 447                 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
 448         }
 449
 450         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
 451                 ret = 1;
 452
 453         return ret;
 454 }
 455
 456 static struct timer_list musb_idle_timer;
 457
 458 static void musb_do_idle(unsigned long _musb)
 459 {
 460         struct musb     *musb = (void *)_musb;
 461         unsigned long   flags;
 462
 463         spin_lock_irqsave(&musb->lock, flags);
 464
 465         switch (musb->xceiv->otg->state) {
 466         case OTG_STATE_A_WAIT_BCON:
 467                 if ((musb->a_wait_bcon != 0)
 468                         && (musb->idle_timeout == 0
 469                                 || time_after(jiffies, musb->idle_timeout))) {
 470                         dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
 471                                         usb_otg_state_string(musb->xceiv->otg->state));
 472                 }
 473                 /* FALLTHROUGH */
 474         case OTG_STATE_A_IDLE:
 475                 tusb_musb_set_vbus(musb, 0);
 476         default:
 477                 break;
 478         }
 479
 480         if (!musb->is_active) {
 481                 u32     wakeups;
 482
 483                 /* wait until hub_wq handles port change status */
 484                 if (is_host_active(musb) && (musb->port1_status >> 16))
 485                         goto done;
 486
 487                 if (!musb->gadget_driver) {
 488                         wakeups = 0;
 489                 } else {
 490                         wakeups = TUSB_PRCM_WHOSTDISCON
 491                                 | TUSB_PRCM_WBUS
 492                                         | TUSB_PRCM_WVBUS;
 493                         wakeups |= TUSB_PRCM_WID;
 494                 }
 495                 tusb_allow_idle(musb, wakeups);
 496         }
 497 done:
 498         spin_unlock_irqrestore(&musb->lock, flags);
 499 }
 500
 501 /*
 502  * Maybe put TUSB6010 into idle mode mode depending on USB link status,
 503  * like "disconnected" or "suspended".  We'll be woken out of it by
 504  * connect, resume, or disconnect.
 505  *
 506  * Needs to be called as the last function everywhere where there is
 507  * register access to TUSB6010 because of NOR flash wake-up.
 508  * Caller should own controller spinlock.
 509  *
 510  * Delay because peripheral enables D+ pullup 3msec after SE0, and
 511  * we don't want to treat that full speed J as a wakeup event.
 512  * ... peripherals must draw only suspend current after 10 msec.
 513  */
 514 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
 515 {
 516         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
 517         static unsigned long    last_timer;
 518
 519         if (timeout == 0)
 520                 timeout = default_timeout;
 521
 522         /* Never idle if active, or when VBUS timeout is not set as host */
 523         if (musb->is_active || ((musb->a_wait_bcon == 0)
 524                         && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
 525                 dev_dbg(musb->controller, "%s active, deleting timer\n",
 526                         usb_otg_state_string(musb->xceiv->otg->state));
 527                 del_timer(&musb_idle_timer);
 528                 last_timer = jiffies;
 529                 return;
 530         }
 531
 532         if (time_after(last_timer, timeout)) {
 533                 if (!timer_pending(&musb_idle_timer))
 534                         last_timer = timeout;
 535                 else {
 536                         dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
 537                         return;
 538                 }
 539         }
 540         last_timer = timeout;
 541
 542         dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
 543                 usb_otg_state_string(musb->xceiv->otg->state),
 544                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
 545         mod_timer(&musb_idle_timer, timeout);
 546 }
 547
 548 /* ticks of 60 MHz clock */
 549 #define DEVCLOCK                60000000
 550 #define OTG_TIMER_MS(msecs)     ((msecs) \
 551                 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
 552                                 | TUSB_DEV_OTG_TIMER_ENABLE) \
 553                 : 0)
 554
 555 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
 556 {
 557         void __iomem    *tbase = musb->ctrl_base;
 558         u32             conf, prcm, timer;
 559         u8              devctl;
 560         struct usb_otg  *otg = musb->xceiv->otg;
 561
 562         /* HDRC controls CPEN, but beware current surges during device
 563          * connect.  They can trigger transient overcurrent conditions
 564          * that must be ignored.
 565          */
 566
 567         prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
 568         conf = musb_readl(tbase, TUSB_DEV_CONF);
 569         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 570
 571         if (is_on) {
 572                 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
 573                 otg->default_a = 1;
 574                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
 575                 devctl |= MUSB_DEVCTL_SESSION;
 576
 577                 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
 578                 MUSB_HST_MODE(musb);
 579         } else {
 580                 u32     otg_stat;
 581
 582                 timer = 0;
 583
 584                 /* If ID pin is grounded, we want to be a_idle */
 585                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 586                 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
 587                         switch (musb->xceiv->otg->state) {
 588                         case OTG_STATE_A_WAIT_VRISE:
 589                         case OTG_STATE_A_WAIT_BCON:
 590                                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
 591                                 break;
 592                         case OTG_STATE_A_WAIT_VFALL:
 593                                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
 594                                 break;
 595                         default:
 596                                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
 597                         }
 598                         musb->is_active = 0;
 599                         otg->default_a = 1;
 600                         MUSB_HST_MODE(musb);
 601                 } else {
 602                         musb->is_active = 0;
 603                         otg->default_a = 0;
 604                         musb->xceiv->otg->state = OTG_STATE_B_IDLE;
 605                         MUSB_DEV_MODE(musb);
 606                 }
 607
 608                 devctl &= ~MUSB_DEVCTL_SESSION;
 609                 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
 610         }
 611         prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
 612
 613         musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
 614         musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
 615         musb_writel(tbase, TUSB_DEV_CONF, conf);
 616         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 617
 618         dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
 619                 usb_otg_state_string(musb->xceiv->otg->state),
 620                 musb_readb(musb->mregs, MUSB_DEVCTL),
 621                 musb_readl(tbase, TUSB_DEV_OTG_STAT),
 622                 conf, prcm);
 623 }
 624
 625 /*
 626  * Sets the mode to OTG, peripheral or host by changing the ID detection.
 627  * Caller must take care of locking.
 628  *
 629  * Note that if a mini-A cable is plugged in the ID line will stay down as
 630  * the weak ID pull-up is not able to pull the ID up.
 631  */
 632 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
 633 {
 634         void __iomem    *tbase = musb->ctrl_base;
 635         u32             otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
 636
 637         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 638         phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
 639         phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
 640         dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
 641
 642         switch (musb_mode) {
 643
 644         case MUSB_HOST:         /* Disable PHY ID detect, ground ID */
 645                 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 646                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 647                 dev_conf |= TUSB_DEV_CONF_ID_SEL;
 648                 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
 649                 break;
 650         case MUSB_PERIPHERAL:   /* Disable PHY ID detect, keep ID pull-up on */
 651                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 652                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 653                 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
 654                 break;
 655         case MUSB_OTG:          /* Use PHY ID detection */
 656                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 657                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 658                 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
 659                 break;
 660
 661         default:
 662                 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
 663                 return -EINVAL;
 664         }
 665
 666         musb_writel(tbase, TUSB_PHY_OTG_CTRL,
 667                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
 668         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
 669                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
 670         musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
 671
 672         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 673         if ((musb_mode == MUSB_PERIPHERAL) &&
 674                 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
 675                         INFO("Cannot be peripheral with mini-A cable "
 676                         "otg_stat: %08x\n", otg_stat);
 677
 678         return 0;
 679 }
 680
 681 static inline unsigned long
 682 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
 683 {
 684         u32             otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 685         unsigned long   idle_timeout = 0;
 686         struct usb_otg  *otg = musb->xceiv->otg;
 687
 688         /* ID pin */
 689         if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
 690                 int     default_a;
 691
 692                 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
 693                 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
 694                 otg->default_a = default_a;
 695                 tusb_musb_set_vbus(musb, default_a);
 696
 697                 /* Don't allow idling immediately */
 698                 if (default_a)
 699                         idle_timeout = jiffies + (HZ * 3);
 700         }
 701
 702         /* VBUS state change */
 703         if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
 704
 705                 /* B-dev state machine:  no vbus ~= disconnect */
 706                 if (!otg->default_a) {
 707                         /* ? musb_root_disconnect(musb); */
 708                         musb->port1_status &=
 709                                 ~(USB_PORT_STAT_CONNECTION
 710                                 | USB_PORT_STAT_ENABLE
 711                                 | USB_PORT_STAT_LOW_SPEED
 712                                 | USB_PORT_STAT_HIGH_SPEED
 713                                 | USB_PORT_STAT_TEST
 714                                 );
 715
 716                         if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
 717                                 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
 718                                 if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) {
 719                                         /* INTR_DISCONNECT can hide... */
 720                                         musb->xceiv->otg->state = OTG_STATE_B_IDLE;
 721                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
 722                                 }
 723                                 musb->is_active = 0;
 724                         }
 725                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
 726                                 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
 727                         idle_timeout = jiffies + (1 * HZ);
 728                         schedule_delayed_work(&musb->irq_work, 0);
 729
 730                 } else /* A-dev state machine */ {
 731                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
 732                                 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
 733
 734                         switch (musb->xceiv->otg->state) {
 735                         case OTG_STATE_A_IDLE:
 736                                 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
 737                                 musb_platform_set_vbus(musb, 1);
 738
 739                                 /* CONNECT can wake if a_wait_bcon is set */
 740                                 if (musb->a_wait_bcon != 0)
 741                                         musb->is_active = 0;
 742                                 else
 743                                         musb->is_active = 1;
 744
 745                                 /*
 746                                  * OPT FS A TD.4.6 needs few seconds for
 747                                  * A_WAIT_VRISE
 748                                  */
 749                                 idle_timeout = jiffies + (2 * HZ);
 750
 751                                 break;
 752                         case OTG_STATE_A_WAIT_VRISE:
 753                                 /* ignore; A-session-valid < VBUS_VALID/2,
 754                                  * we monitor this with the timer
 755                                  */
 756                                 break;
 757                         case OTG_STATE_A_WAIT_VFALL:
 758                                 /* REVISIT this irq triggers during short
 759                                  * spikes caused by enumeration ...
 760                                  */
 761                                 if (musb->vbuserr_retry) {
 762                                         musb->vbuserr_retry--;
 763                                         tusb_musb_set_vbus(musb, 1);
 764                                 } else {
 765                                         musb->vbuserr_retry
 766                                                 = VBUSERR_RETRY_COUNT;
 767                                         tusb_musb_set_vbus(musb, 0);
 768                                 }
 769                                 break;
 770                         default:
 771                                 break;
 772                         }
 773                 }
 774         }
 775
 776         /* OTG timer expiration */
 777         if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
 778                 u8      devctl;
 779
 780                 dev_dbg(musb->controller, "%s timer, %03x\n",
 781                         usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
 782
 783                 switch (musb->xceiv->otg->state) {
 784                 case OTG_STATE_A_WAIT_VRISE:
 785                         /* VBUS has probably been valid for a while now,
 786                          * but may well have bounced out of range a bit
 787                          */
 788                         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 789                         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
 790                                 if ((devctl & MUSB_DEVCTL_VBUS)
 791                                                 != MUSB_DEVCTL_VBUS) {
 792                                         dev_dbg(musb->controller, "devctl %02x\n", devctl);
 793                                         break;
 794                                 }
 795                                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
 796                                 musb->is_active = 0;
 797                                 idle_timeout = jiffies
 798                                         + msecs_to_jiffies(musb->a_wait_bcon);
 799                         } else {
 800                                 /* REVISIT report overcurrent to hub? */
 801                                 ERR("vbus too slow, devctl %02x\n", devctl);
 802                                 tusb_musb_set_vbus(musb, 0);
 803                         }
 804                         break;
 805                 case OTG_STATE_A_WAIT_BCON:
 806                         if (musb->a_wait_bcon != 0)
 807                                 idle_timeout = jiffies
 808                                         + msecs_to_jiffies(musb->a_wait_bcon);
 809                         break;
 810                 case OTG_STATE_A_SUSPEND:
 811                         break;
 812                 case OTG_STATE_B_WAIT_ACON:
 813                         break;
 814                 default:
 815                         break;
 816                 }
 817         }
 818         schedule_delayed_work(&musb->irq_work, 0);
 819
 820         return idle_timeout;
 821 }
 822
 823 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
 824 {
 825         struct musb     *musb = __hci;
 826         void __iomem    *tbase = musb->ctrl_base;
 827         unsigned long   flags, idle_timeout = 0;
 828         u32             int_mask, int_src;
 829
 830         spin_lock_irqsave(&musb->lock, flags);
 831
 832         /* Mask all interrupts to allow using both edge and level GPIO irq */
 833         int_mask = musb_readl(tbase, TUSB_INT_MASK);
 834         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
 835
 836         int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
 837         dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
 838
 839         musb->int_usb = (u8) int_src;
 840
 841         /* Acknowledge wake-up source interrupts */
 842         if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
 843                 u32     reg;
 844                 u32     i;
 845
 846                 if (musb->tusb_revision == TUSB_REV_30)
 847                         tusb_wbus_quirk(musb, 0);
 848
 849                 /* there are issues re-locking the PLL on wakeup ... */
 850
 851                 /* work around issue 8 */
 852                 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
 853                         musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
 854                         musb_writel(tbase, TUSB_SCRATCH_PAD, i);
 855                         reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
 856                         if (reg == i)
 857                                 break;
 858                         dev_dbg(musb->controller, "TUSB NOR not ready\n");
 859                 }
 860
 861                 /* work around issue 13 (2nd half) */
 862                 tusb_set_clock_source(musb, 1);
 863
 864                 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
 865                 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
 866                 if (reg & ~TUSB_PRCM_WNORCS) {
 867                         musb->is_active = 1;
 868                         schedule_delayed_work(&musb->irq_work, 0);
 869                 }
 870                 dev_dbg(musb->controller, "wake %sactive %02x\n",
 871                                 musb->is_active ? "" : "in", reg);
 872
 873                 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
 874         }
 875
 876         if (int_src & TUSB_INT_SRC_USB_IP_CONN)
 877                 del_timer(&musb_idle_timer);
 878
 879         /* OTG state change reports (annoyingly) not issued by Mentor core */
 880         if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
 881                                 | TUSB_INT_SRC_OTG_TIMEOUT
 882                                 | TUSB_INT_SRC_ID_STATUS_CHNG))
 883                 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
 884
 885         /* TX dma callback must be handled here, RX dma callback is
 886          * handled in tusb_omap_dma_cb.
 887          */
 888         if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
 889                 u32     dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
 890                 u32     real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
 891
 892                 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
 893                 real_dma_src = ~real_dma_src & dma_src;
 894                 if (tusb_dma_omap(musb) && real_dma_src) {
 895                         int     tx_source = (real_dma_src & 0xffff);
 896                         int     i;
 897
 898                         for (i = 1; i <= 15; i++) {
 899                                 if (tx_source & (1 << i)) {
 900                                         dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
 901                                         musb_dma_completion(musb, i, 1);
 902                                 }
 903                         }
 904                 }
 905                 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
 906         }
 907
 908         /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
 909         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
 910                 u32     musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
 911
 912                 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
 913                 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
 914                 musb->int_tx = (musb_src & 0xffff);
 915         } else {
 916                 musb->int_rx = 0;
 917                 musb->int_tx = 0;
 918         }
 919
 920         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
 921                 musb_interrupt(musb);
 922
 923         /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
 924         musb_writel(tbase, TUSB_INT_SRC_CLEAR,
 925                 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
 926
 927         tusb_musb_try_idle(musb, idle_timeout);
 928
 929         musb_writel(tbase, TUSB_INT_MASK, int_mask);
 930         spin_unlock_irqrestore(&musb->lock, flags);
 931
 932         return IRQ_HANDLED;
 933 }
 934
 935 static int dma_off;
 936
 937 /*
 938  * Enables TUSB6010. Caller must take care of locking.
 939  * REVISIT:
 940  * - Check what is unnecessary in MGC_HdrcStart()
 941  */
 942 static void tusb_musb_enable(struct musb *musb)
 943 {
 944         void __iomem    *tbase = musb->ctrl_base;
 945
 946         /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
 947          * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
 948         musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
 949
 950         /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
 951         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
 952         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
 953         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
 954
 955         /* Clear all subsystem interrups */
 956         musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
 957         musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
 958         musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
 959
 960         /* Acknowledge pending interrupt(s) */
 961         musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
 962
 963         /* Only 0 clock cycles for minimum interrupt de-assertion time and
 964          * interrupt polarity active low seems to work reliably here */
 965         musb_writel(tbase, TUSB_INT_CTRL_CONF,
 966                         TUSB_INT_CTRL_CONF_INT_RELCYC(0));
 967
 968         irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
 969
 970         /* maybe force into the Default-A OTG state machine */
 971         if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
 972                         & TUSB_DEV_OTG_STAT_ID_STATUS))
 973                 musb_writel(tbase, TUSB_INT_SRC_SET,
 974                                 TUSB_INT_SRC_ID_STATUS_CHNG);
 975
 976         if (is_dma_capable() && dma_off)
 977                 printk(KERN_WARNING "%s %s: dma not reactivated\n",
 978                                 __FILE__, __func__);
 979         else
 980                 dma_off = 1;
 981 }
 982
 983 /*
 984  * Disables TUSB6010. Caller must take care of locking.
 985  */
 986 static void tusb_musb_disable(struct musb *musb)
 987 {
 988         void __iomem    *tbase = musb->ctrl_base;
 989
 990         /* FIXME stop DMA, IRQs, timers, ... */
 991
 992         /* disable all IRQs */
 993         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
 994         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
 995         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
 996         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
 997
 998         del_timer(&musb_idle_timer);
 999
1000         if (is_dma_capable() && !dma_off) {
1001                 printk(KERN_WARNING "%s %s: dma still active\n",
1002                                 __FILE__, __func__);
1003                 dma_off = 1;
1004         }
1005 }
1006
1007 /*
1008  * Sets up TUSB6010 CPU interface specific signals and registers
1009  * Note: Settings optimized for OMAP24xx
1010  */
1011 static void tusb_setup_cpu_interface(struct musb *musb)
1012 {
1013         void __iomem    *tbase = musb->ctrl_base;
1014
1015         /*
1016          * Disable GPIO[5:0] pullups (used as output DMA requests)
1017          * Don't disable GPIO[7:6] as they are needed for wake-up.
1018          */
1019         musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1020
1021         /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1022         musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1023
1024         /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1025         musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1026
1027         /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1028          * de-assertion time 2 system clocks p 62 */
1029         musb_writel(tbase, TUSB_DMA_REQ_CONF,
1030                 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1031                 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1032                 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1033
1034         /* Set 0 wait count for synchronous burst access */
1035         musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1036 }
1037
1038 static int tusb_musb_start(struct musb *musb)
1039 {
1040         void __iomem    *tbase = musb->ctrl_base;
1041         int             ret = 0;
1042         unsigned long   flags;
1043         u32             reg;
1044
1045         if (musb->board_set_power)
1046                 ret = musb->board_set_power(1);
1047         if (ret != 0) {
1048                 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1049                 return ret;
1050         }
1051
1052         spin_lock_irqsave(&musb->lock, flags);
1053
1054         if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1055                 TUSB_PROD_TEST_RESET_VAL) {
1056                 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1057                 goto err;
1058         }
1059
1060         musb->tusb_revision = tusb_get_revision(musb);
1061         tusb_print_revision(musb);
1062         if (musb->tusb_revision < 2) {
1063                 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1064                                 musb->tusb_revision);
1065                 goto err;
1066         }
1067
1068         /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1069          * NOR FLASH interface is used */
1070         musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1071
1072         /* Select PHY free running 60MHz as a system clock */
1073         tusb_set_clock_source(musb, 1);
1074
1075         /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1076          * power saving, enable VBus detect and session end comparators,
1077          * enable IDpullup, enable VBus charging */
1078         musb_writel(tbase, TUSB_PRCM_MNGMT,
1079                 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1080                 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1081                 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1082                 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1083                 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1084         tusb_setup_cpu_interface(musb);
1085
1086         /* simplify:  always sense/pullup ID pins, as if in OTG mode */
1087         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1088         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1089         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1090
1091         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1092         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1093         musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1094
1095         spin_unlock_irqrestore(&musb->lock, flags);
1096
1097         return 0;
1098
1099 err:
1100         spin_unlock_irqrestore(&musb->lock, flags);
1101
1102         if (musb->board_set_power)
1103                 musb->board_set_power(0);
1104
1105         return -ENODEV;
1106 }
1107
1108 static int tusb_musb_init(struct musb *musb)
1109 {
1110         struct platform_device  *pdev;
1111         struct resource         *mem;
1112         void __iomem            *sync = NULL;
1113         int                     ret;
1114
1115         musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1116         if (IS_ERR_OR_NULL(musb->xceiv))
1117                 return -EPROBE_DEFER;
1118
1119         pdev = to_platform_device(musb->controller);
1120
1121         /* dma address for async dma */
1122         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1123         if (!mem) {
1124                 pr_debug("no async dma resource?\n");
1125                 ret = -ENODEV;
1126                 goto done;
1127         }
1128         musb->async = mem->start;
1129
1130         /* dma address for sync dma */
1131         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1132         if (!mem) {
1133                 pr_debug("no sync dma resource?\n");
1134                 ret = -ENODEV;
1135                 goto done;
1136         }
1137         musb->sync = mem->start;
1138
1139         sync = ioremap(mem->start, resource_size(mem));
1140         if (!sync) {
1141                 pr_debug("ioremap for sync failed\n");
1142                 ret = -ENOMEM;
1143                 goto done;
1144         }
1145         musb->sync_va = sync;
1146
1147         /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1148          * FIFOs at 0x600, TUSB at 0x800
1149          */
1150         musb->mregs += TUSB_BASE_OFFSET;
1151
1152         ret = tusb_musb_start(musb);
1153         if (ret) {
1154                 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1155                                 ret);
1156                 goto done;
1157         }
1158         musb->isr = tusb_musb_interrupt;
1159
1160         musb->xceiv->set_power = tusb_draw_power;
1161         the_musb = musb;
1162
1163         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1164
1165 done:
1166         if (ret < 0) {
1167                 if (sync)
1168                         iounmap(sync);
1169
1170                 usb_put_phy(musb->xceiv);
1171         }
1172         return ret;
1173 }
1174
1175 static int tusb_musb_exit(struct musb *musb)
1176 {
1177         del_timer_sync(&musb_idle_timer);
1178         the_musb = NULL;
1179
1180         if (musb->board_set_power)
1181                 musb->board_set_power(0);
1182
1183         iounmap(musb->sync_va);
1184
1185         usb_put_phy(musb->xceiv);
1186         return 0;
1187 }
1188
1189 static const struct musb_platform_ops tusb_ops = {
1190         .quirks         = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB,
1191         .init           = tusb_musb_init,
1192         .exit           = tusb_musb_exit,
1193
1194         .ep_offset      = tusb_ep_offset,
1195         .ep_select      = tusb_ep_select,
1196         .fifo_offset    = tusb_fifo_offset,
1197         .readb          = tusb_readb,
1198         .writeb         = tusb_writeb,
1199         .read_fifo      = tusb_read_fifo,
1200         .write_fifo     = tusb_write_fifo,
1201 #ifdef CONFIG_USB_TUSB_OMAP_DMA
1202         .dma_init       = tusb_dma_controller_create,
1203         .dma_exit       = tusb_dma_controller_destroy,
1204 #endif
1205         .enable         = tusb_musb_enable,
1206         .disable        = tusb_musb_disable,
1207
1208         .set_mode       = tusb_musb_set_mode,
1209         .try_idle       = tusb_musb_try_idle,
1210
1211         .vbus_status    = tusb_musb_vbus_status,
1212         .set_vbus       = tusb_musb_set_vbus,
1213 };
1214
1215 static const struct platform_device_info tusb_dev_info = {
1216         .name           = "musb-hdrc",
1217         .id             = PLATFORM_DEVID_AUTO,
1218         .dma_mask       = DMA_BIT_MASK(32),
1219 };
1220
1221 static int tusb_probe(struct platform_device *pdev)
1222 {
1223         struct resource musb_resources[3];
1224         struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
1225         struct platform_device          *musb;
1226         struct tusb6010_glue            *glue;
1227         struct platform_device_info     pinfo;
1228         int                             ret;
1229
1230         glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
1231         if (!glue)
1232                 return -ENOMEM;
1233
1234         glue->dev                       = &pdev->dev;
1235
1236         pdata->platform_ops             = &tusb_ops;
1237
1238         usb_phy_generic_register();
1239         platform_set_drvdata(pdev, glue);
1240
1241         memset(musb_resources, 0x00, sizeof(*musb_resources) *
1242                         ARRAY_SIZE(musb_resources));
1243
1244         musb_resources[0].name = pdev->resource[0].name;
1245         musb_resources[0].start = pdev->resource[0].start;
1246         musb_resources[0].end = pdev->resource[0].end;
1247         musb_resources[0].flags = pdev->resource[0].flags;
1248
1249         musb_resources[1].name = pdev->resource[1].name;
1250         musb_resources[1].start = pdev->resource[1].start;
1251         musb_resources[1].end = pdev->resource[1].end;
1252         musb_resources[1].flags = pdev->resource[1].flags;
1253
1254         musb_resources[2].name = pdev->resource[2].name;
1255         musb_resources[2].start = pdev->resource[2].start;
1256         musb_resources[2].end = pdev->resource[2].end;
1257         musb_resources[2].flags = pdev->resource[2].flags;
1258
1259         pinfo = tusb_dev_info;
1260         pinfo.parent = &pdev->dev;
1261         pinfo.res = musb_resources;
1262         pinfo.num_res = ARRAY_SIZE(musb_resources);
1263         pinfo.data = pdata;
1264         pinfo.size_data = sizeof(*pdata);
1265
1266         glue->musb = musb = platform_device_register_full(&pinfo);
1267         if (IS_ERR(musb)) {
1268                 ret = PTR_ERR(musb);
1269                 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
1270                 return ret;
1271         }
1272
1273         return 0;
1274 }
1275
1276 static int tusb_remove(struct platform_device *pdev)
1277 {
1278         struct tusb6010_glue            *glue = platform_get_drvdata(pdev);
1279
1280         platform_device_unregister(glue->musb);
1281         usb_phy_generic_unregister(glue->phy);
1282
1283         return 0;
1284 }
1285
1286 static struct platform_driver tusb_driver = {
1287         .probe          = tusb_probe,
1288         .remove         = tusb_remove,
1289         .driver         = {
1290                 .name   = "musb-tusb",
1291         },
1292 };
1293
1294 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1295 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1296 MODULE_LICENSE("GPL v2");
1297 module_platform_driver(tusb_driver);