drivers/usb/typec/tcpci.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015-2017 Google, Inc
   4  *
   5  * USB Type-C Port Controller Interface.
   6  */
   7
   8 #ifndef __LINUX_USB_TCPCI_H
   9 #define __LINUX_USB_TCPCI_H
  10
  11 #define TCPC_VENDOR_ID                  0x0
  12 #define TCPC_PRODUCT_ID                 0x2
  13 #define TCPC_BCD_DEV                    0x4
  14 #define TCPC_TC_REV                     0x6
  15 #define TCPC_PD_REV                     0x8
  16 #define TCPC_PD_INT_REV                 0xa
  17
  18 #define TCPC_ALERT                      0x10
  19 #define TCPC_ALERT_VBUS_DISCNCT         BIT(11)
  20 #define TCPC_ALERT_RX_BUF_OVF           BIT(10)
  21 #define TCPC_ALERT_FAULT                BIT(9)
  22 #define TCPC_ALERT_V_ALARM_LO           BIT(8)
  23 #define TCPC_ALERT_V_ALARM_HI           BIT(7)
  24 #define TCPC_ALERT_TX_SUCCESS           BIT(6)
  25 #define TCPC_ALERT_TX_DISCARDED         BIT(5)
  26 #define TCPC_ALERT_TX_FAILED            BIT(4)
  27 #define TCPC_ALERT_RX_HARD_RST          BIT(3)
  28 #define TCPC_ALERT_RX_STATUS            BIT(2)
  29 #define TCPC_ALERT_POWER_STATUS         BIT(1)
  30 #define TCPC_ALERT_CC_STATUS            BIT(0)
  31
  32 #define TCPC_ALERT_MASK                 0x12
  33 #define TCPC_POWER_STATUS_MASK          0x14
  34 #define TCPC_FAULT_STATUS_MASK          0x15
  35 #define TCPC_CONFIG_STD_OUTPUT          0x18
  36
  37 #define TCPC_TCPC_CTRL                  0x19
  38 #define TCPC_TCPC_CTRL_ORIENTATION      BIT(0)
  39
  40 #define TCPC_ROLE_CTRL                  0x1a
  41 #define TCPC_ROLE_CTRL_DRP              BIT(6)
  42 #define TCPC_ROLE_CTRL_RP_VAL_SHIFT     4
  43 #define TCPC_ROLE_CTRL_RP_VAL_MASK      0x3
  44 #define TCPC_ROLE_CTRL_RP_VAL_DEF       0x0
  45 #define TCPC_ROLE_CTRL_RP_VAL_1_5       0x1
  46 #define TCPC_ROLE_CTRL_RP_VAL_3_0       0x2
  47 #define TCPC_ROLE_CTRL_CC2_SHIFT        2
  48 #define TCPC_ROLE_CTRL_CC2_MASK         0x3
  49 #define TCPC_ROLE_CTRL_CC1_SHIFT        0
  50 #define TCPC_ROLE_CTRL_CC1_MASK         0x3
  51 #define TCPC_ROLE_CTRL_CC_RA            0x0
  52 #define TCPC_ROLE_CTRL_CC_RP            0x1
  53 #define TCPC_ROLE_CTRL_CC_RD            0x2
  54 #define TCPC_ROLE_CTRL_CC_OPEN          0x3
  55
  56 #define TCPC_FAULT_CTRL                 0x1b
  57
  58 #define TCPC_POWER_CTRL                 0x1c
  59 #define TCPC_POWER_CTRL_VCONN_ENABLE    BIT(0)
  60
  61 #define TCPC_CC_STATUS                  0x1d
  62 #define TCPC_CC_STATUS_TOGGLING         BIT(5)
  63 #define TCPC_CC_STATUS_TERM             BIT(4)
  64 #define TCPC_CC_STATUS_CC2_SHIFT        2
  65 #define TCPC_CC_STATUS_CC2_MASK         0x3
  66 #define TCPC_CC_STATUS_CC1_SHIFT        0
  67 #define TCPC_CC_STATUS_CC1_MASK         0x3
  68
  69 #define TCPC_POWER_STATUS               0x1e
  70 #define TCPC_POWER_STATUS_UNINIT        BIT(6)
  71 #define TCPC_POWER_STATUS_VBUS_DET      BIT(3)
  72 #define TCPC_POWER_STATUS_VBUS_PRES     BIT(2)
  73
  74 #define TCPC_FAULT_STATUS               0x1f
  75
  76 #define TCPC_COMMAND                    0x23
  77 #define TCPC_CMD_WAKE_I2C               0x11
  78 #define TCPC_CMD_DISABLE_VBUS_DETECT    0x22
  79 #define TCPC_CMD_ENABLE_VBUS_DETECT     0x33
  80 #define TCPC_CMD_DISABLE_SINK_VBUS      0x44
  81 #define TCPC_CMD_SINK_VBUS              0x55
  82 #define TCPC_CMD_DISABLE_SRC_VBUS       0x66
  83 #define TCPC_CMD_SRC_VBUS_DEFAULT       0x77
  84 #define TCPC_CMD_SRC_VBUS_HIGH          0x88
  85 #define TCPC_CMD_LOOK4CONNECTION        0x99
  86 #define TCPC_CMD_RXONEMORE              0xAA
  87 #define TCPC_CMD_I2C_IDLE               0xFF
  88
  89 #define TCPC_DEV_CAP_1                  0x24
  90 #define TCPC_DEV_CAP_2                  0x26
  91 #define TCPC_STD_INPUT_CAP              0x28
  92 #define TCPC_STD_OUTPUT_CAP             0x29
  93
  94 #define TCPC_MSG_HDR_INFO               0x2e
  95 #define TCPC_MSG_HDR_INFO_DATA_ROLE     BIT(3)
  96 #define TCPC_MSG_HDR_INFO_PWR_ROLE      BIT(0)
  97 #define TCPC_MSG_HDR_INFO_REV_SHIFT     1
  98 #define TCPC_MSG_HDR_INFO_REV_MASK      0x3
  99
 100 #define TCPC_RX_DETECT                  0x2f
 101 #define TCPC_RX_DETECT_HARD_RESET       BIT(5)
 102 #define TCPC_RX_DETECT_SOP              BIT(0)
 103
 104 #define TCPC_RX_BYTE_CNT                0x30
 105 #define TCPC_RX_BUF_FRAME_TYPE          0x31
 106 #define TCPC_RX_HDR                     0x32
 107 #define TCPC_RX_DATA                    0x34 /* through 0x4f */
 108
 109 #define TCPC_TRANSMIT                   0x50
 110 #define TCPC_TRANSMIT_RETRY_SHIFT       4
 111 #define TCPC_TRANSMIT_RETRY_MASK        0x3
 112 #define TCPC_TRANSMIT_TYPE_SHIFT        0
 113 #define TCPC_TRANSMIT_TYPE_MASK         0x7
 114
 115 #define TCPC_TX_BYTE_CNT                0x51
 116 #define TCPC_TX_HDR                     0x52
 117 #define TCPC_TX_DATA                    0x54 /* through 0x6f */
 118
 119 #define TCPC_VBUS_VOLTAGE                       0x70
 120 #define TCPC_VBUS_SINK_DISCONNECT_THRESH        0x72
 121 #define TCPC_VBUS_STOP_DISCHARGE_THRESH         0x74
 122 #define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG          0x76
 123 #define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG          0x78
 124
 125 struct tcpci;
 126 struct tcpci_data {
 127         struct regmap *regmap;
 128         int (*init)(struct tcpci *tcpci, struct tcpci_data *data);
 129         int (*set_vconn)(struct tcpci *tcpci, struct tcpci_data *data,
 130                          bool enable);
 131         int (*start_drp_toggling)(struct tcpci *tcpci, struct tcpci_data *data,
 132                                   enum typec_cc_status cc);
 133 };
 134
 135 struct tcpci *tcpci_register_port(struct device *dev, struct tcpci_data *data);
 136 void tcpci_unregister_port(struct tcpci *tcpci);
 137 irqreturn_t tcpci_irq(struct tcpci *tcpci);
 138
 139 #endif /* __LINUX_USB_TCPCI_H */