drivers/video/fbdev/omap2/omapfb/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/sizes.h>
  39 #include <linux/mfd/syscon.h>
  40 #include <linux/regmap.h>
  41 #include <linux/of.h>
  42 #include <linux/component.h>
  43
  44 #include <video/omapfb_dss.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48 #include "dispc.h"
  49
  50 /* DISPC */
  51 #define DISPC_SZ_REGS                   SZ_4K
  52
  53 enum omap_burst_size {
  54         BURST_SIZE_X2 = 0,
  55         BURST_SIZE_X4 = 1,
  56         BURST_SIZE_X8 = 2,
  57 };
  58
  59 #define REG_GET(idx, start, end) \
  60         FLD_GET(dispc_read_reg(idx), start, end)
  61
  62 #define REG_FLD_MOD(idx, val, start, end)                               \
  63         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  64
  65 struct dispc_features {
  66         u8 sw_start;
  67         u8 fp_start;
  68         u8 bp_start;
  69         u16 sw_max;
  70         u16 vp_max;
  71         u16 hp_max;
  72         u8 mgr_width_start;
  73         u8 mgr_height_start;
  74         u16 mgr_width_max;
  75         u16 mgr_height_max;
  76         unsigned long max_lcd_pclk;
  77         unsigned long max_tv_pclk;
  78         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
  79                 const struct omap_video_timings *mgr_timings,
  80                 u16 width, u16 height, u16 out_width, u16 out_height,
  81                 enum omap_color_mode color_mode, bool *five_taps,
  82                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  83                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  84         unsigned long (*calc_core_clk) (unsigned long pclk,
  85                 u16 width, u16 height, u16 out_width, u16 out_height,
  86                 bool mem_to_mem);
  87         u8 num_fifos;
  88
  89         /* swap GFX & WB fifos */
  90         bool gfx_fifo_workaround:1;
  91
  92         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
  93         bool no_framedone_tv:1;
  94
  95         /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
  96         bool mstandby_workaround:1;
  97
  98         bool set_max_preload:1;
  99
 100         /* PIXEL_INC is not added to the last pixel of a line */
 101         bool last_pixel_inc_missing:1;
 102
 103         /* POL_FREQ has ALIGN bit */
 104         bool supports_sync_align:1;
 105
 106         bool has_writeback:1;
 107 };
 108
 109 #define DISPC_MAX_NR_FIFOS 5
 110
 111 static struct {
 112         struct platform_device *pdev;
 113         void __iomem    *base;
 114
 115         int irq;
 116         irq_handler_t user_handler;
 117         void *user_data;
 118
 119         unsigned long core_clk_rate;
 120         unsigned long tv_pclk_rate;
 121
 122         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 123         /* maps which plane is using a fifo. fifo-id -> plane-id */
 124         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 125
 126         bool            ctx_valid;
 127         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 128
 129         const struct dispc_features *feat;
 130
 131         bool is_enabled;
 132
 133         struct regmap *syscon_pol;
 134         u32 syscon_pol_offset;
 135
 136         /* DISPC_CONTROL & DISPC_CONFIG lock*/
 137         spinlock_t control_lock;
 138 } dispc;
 139
 140 enum omap_color_component {
 141         /* used for all color formats for OMAP3 and earlier
 142          * and for RGB and Y color component on OMAP4
 143          */
 144         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 145         /* used for UV component for
 146          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 147          * color formats on OMAP4
 148          */
 149         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 150 };
 151
 152 enum mgr_reg_fields {
 153         DISPC_MGR_FLD_ENABLE,
 154         DISPC_MGR_FLD_STNTFT,
 155         DISPC_MGR_FLD_GO,
 156         DISPC_MGR_FLD_TFTDATALINES,
 157         DISPC_MGR_FLD_STALLMODE,
 158         DISPC_MGR_FLD_TCKENABLE,
 159         DISPC_MGR_FLD_TCKSELECTION,
 160         DISPC_MGR_FLD_CPR,
 161         DISPC_MGR_FLD_FIFOHANDCHECK,
 162         /* used to maintain a count of the above fields */
 163         DISPC_MGR_FLD_NUM,
 164 };
 165
 166 struct dispc_reg_field {
 167         u16 reg;
 168         u8 high;
 169         u8 low;
 170 };
 171
 172 static const struct {
 173         const char *name;
 174         u32 vsync_irq;
 175         u32 framedone_irq;
 176         u32 sync_lost_irq;
 177         struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
 178 } mgr_desc[] = {
 179         [OMAP_DSS_CHANNEL_LCD] = {
 180                 .name           = "LCD",
 181                 .vsync_irq      = DISPC_IRQ_VSYNC,
 182                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 183                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 184                 .reg_desc       = {
 185                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 186                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 187                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 188                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 189                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 190                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 191                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 192                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 193                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 194                 },
 195         },
 196         [OMAP_DSS_CHANNEL_DIGIT] = {
 197                 .name           = "DIGIT",
 198                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 199                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 200                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 201                 .reg_desc       = {
 202                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 203                         [DISPC_MGR_FLD_STNTFT]          = { },
 204                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 205                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 206                         [DISPC_MGR_FLD_STALLMODE]       = { },
 207                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 208                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 209                         [DISPC_MGR_FLD_CPR]             = { },
 210                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 211                 },
 212         },
 213         [OMAP_DSS_CHANNEL_LCD2] = {
 214                 .name           = "LCD2",
 215                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 216                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 217                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 218                 .reg_desc       = {
 219                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 220                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 221                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 222                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 223                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 224                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 225                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 226                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 227                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 228                 },
 229         },
 230         [OMAP_DSS_CHANNEL_LCD3] = {
 231                 .name           = "LCD3",
 232                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 233                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 234                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 235                 .reg_desc       = {
 236                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 237                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 238                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 239                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 240                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 241                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 242                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 243                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 244                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 245                 },
 246         },
 247 };
 248
 249 struct color_conv_coef {
 250         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
 251         int full_range;
 252 };
 253
 254 static unsigned long dispc_fclk_rate(void);
 255 static unsigned long dispc_core_clk_rate(void);
 256 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 257 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 258
 259 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 260 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 261
 262 static inline void dispc_write_reg(const u16 idx, u32 val)
 263 {
 264         __raw_writel(val, dispc.base + idx);
 265 }
 266
 267 static inline u32 dispc_read_reg(const u16 idx)
 268 {
 269         return __raw_readl(dispc.base + idx);
 270 }
 271
 272 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 273 {
 274         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 275         return REG_GET(rfld.reg, rfld.high, rfld.low);
 276 }
 277
 278 static void mgr_fld_write(enum omap_channel channel,
 279                                         enum mgr_reg_fields regfld, int val) {
 280         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 281         const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
 282         unsigned long flags;
 283
 284         if (need_lock)
 285                 spin_lock_irqsave(&dispc.control_lock, flags);
 286
 287         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 288
 289         if (need_lock)
 290                 spin_unlock_irqrestore(&dispc.control_lock, flags);
 291 }
 292
 293 #define SR(reg) \
 294         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 295 #define RR(reg) \
 296         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 297
 298 static void dispc_save_context(void)
 299 {
 300         int i, j;
 301
 302         DSSDBG("dispc_save_context\n");
 303
 304         SR(IRQENABLE);
 305         SR(CONTROL);
 306         SR(CONFIG);
 307         SR(LINE_NUMBER);
 308         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 309                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 310                 SR(GLOBAL_ALPHA);
 311         if (dss_has_feature(FEAT_MGR_LCD2)) {
 312                 SR(CONTROL2);
 313                 SR(CONFIG2);
 314         }
 315         if (dss_has_feature(FEAT_MGR_LCD3)) {
 316                 SR(CONTROL3);
 317                 SR(CONFIG3);
 318         }
 319
 320         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 321                 SR(DEFAULT_COLOR(i));
 322                 SR(TRANS_COLOR(i));
 323                 SR(SIZE_MGR(i));
 324                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 325                         continue;
 326                 SR(TIMING_H(i));
 327                 SR(TIMING_V(i));
 328                 SR(POL_FREQ(i));
 329                 SR(DIVISORo(i));
 330
 331                 SR(DATA_CYCLE1(i));
 332                 SR(DATA_CYCLE2(i));
 333                 SR(DATA_CYCLE3(i));
 334
 335                 if (dss_has_feature(FEAT_CPR)) {
 336                         SR(CPR_COEF_R(i));
 337                         SR(CPR_COEF_G(i));
 338                         SR(CPR_COEF_B(i));
 339                 }
 340         }
 341
 342         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 343                 SR(OVL_BA0(i));
 344                 SR(OVL_BA1(i));
 345                 SR(OVL_POSITION(i));
 346                 SR(OVL_SIZE(i));
 347                 SR(OVL_ATTRIBUTES(i));
 348                 SR(OVL_FIFO_THRESHOLD(i));
 349                 SR(OVL_ROW_INC(i));
 350                 SR(OVL_PIXEL_INC(i));
 351                 if (dss_has_feature(FEAT_PRELOAD))
 352                         SR(OVL_PRELOAD(i));
 353                 if (i == OMAP_DSS_GFX) {
 354                         SR(OVL_WINDOW_SKIP(i));
 355                         SR(OVL_TABLE_BA(i));
 356                         continue;
 357                 }
 358                 SR(OVL_FIR(i));
 359                 SR(OVL_PICTURE_SIZE(i));
 360                 SR(OVL_ACCU0(i));
 361                 SR(OVL_ACCU1(i));
 362
 363                 for (j = 0; j < 8; j++)
 364                         SR(OVL_FIR_COEF_H(i, j));
 365
 366                 for (j = 0; j < 8; j++)
 367                         SR(OVL_FIR_COEF_HV(i, j));
 368
 369                 for (j = 0; j < 5; j++)
 370                         SR(OVL_CONV_COEF(i, j));
 371
 372                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 373                         for (j = 0; j < 8; j++)
 374                                 SR(OVL_FIR_COEF_V(i, j));
 375                 }
 376
 377                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 378                         SR(OVL_BA0_UV(i));
 379                         SR(OVL_BA1_UV(i));
 380                         SR(OVL_FIR2(i));
 381                         SR(OVL_ACCU2_0(i));
 382                         SR(OVL_ACCU2_1(i));
 383
 384                         for (j = 0; j < 8; j++)
 385                                 SR(OVL_FIR_COEF_H2(i, j));
 386
 387                         for (j = 0; j < 8; j++)
 388                                 SR(OVL_FIR_COEF_HV2(i, j));
 389
 390                         for (j = 0; j < 8; j++)
 391                                 SR(OVL_FIR_COEF_V2(i, j));
 392                 }
 393                 if (dss_has_feature(FEAT_ATTR2))
 394                         SR(OVL_ATTRIBUTES2(i));
 395         }
 396
 397         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 398                 SR(DIVISOR);
 399
 400         dispc.ctx_valid = true;
 401
 402         DSSDBG("context saved\n");
 403 }
 404
 405 static void dispc_restore_context(void)
 406 {
 407         int i, j;
 408
 409         DSSDBG("dispc_restore_context\n");
 410
 411         if (!dispc.ctx_valid)
 412                 return;
 413
 414         /*RR(IRQENABLE);*/
 415         /*RR(CONTROL);*/
 416         RR(CONFIG);
 417         RR(LINE_NUMBER);
 418         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 419                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 420                 RR(GLOBAL_ALPHA);
 421         if (dss_has_feature(FEAT_MGR_LCD2))
 422                 RR(CONFIG2);
 423         if (dss_has_feature(FEAT_MGR_LCD3))
 424                 RR(CONFIG3);
 425
 426         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 427                 RR(DEFAULT_COLOR(i));
 428                 RR(TRANS_COLOR(i));
 429                 RR(SIZE_MGR(i));
 430                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 431                         continue;
 432                 RR(TIMING_H(i));
 433                 RR(TIMING_V(i));
 434                 RR(POL_FREQ(i));
 435                 RR(DIVISORo(i));
 436
 437                 RR(DATA_CYCLE1(i));
 438                 RR(DATA_CYCLE2(i));
 439                 RR(DATA_CYCLE3(i));
 440
 441                 if (dss_has_feature(FEAT_CPR)) {
 442                         RR(CPR_COEF_R(i));
 443                         RR(CPR_COEF_G(i));
 444                         RR(CPR_COEF_B(i));
 445                 }
 446         }
 447
 448         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 449                 RR(OVL_BA0(i));
 450                 RR(OVL_BA1(i));
 451                 RR(OVL_POSITION(i));
 452                 RR(OVL_SIZE(i));
 453                 RR(OVL_ATTRIBUTES(i));
 454                 RR(OVL_FIFO_THRESHOLD(i));
 455                 RR(OVL_ROW_INC(i));
 456                 RR(OVL_PIXEL_INC(i));
 457                 if (dss_has_feature(FEAT_PRELOAD))
 458                         RR(OVL_PRELOAD(i));
 459                 if (i == OMAP_DSS_GFX) {
 460                         RR(OVL_WINDOW_SKIP(i));
 461                         RR(OVL_TABLE_BA(i));
 462                         continue;
 463                 }
 464                 RR(OVL_FIR(i));
 465                 RR(OVL_PICTURE_SIZE(i));
 466                 RR(OVL_ACCU0(i));
 467                 RR(OVL_ACCU1(i));
 468
 469                 for (j = 0; j < 8; j++)
 470                         RR(OVL_FIR_COEF_H(i, j));
 471
 472                 for (j = 0; j < 8; j++)
 473                         RR(OVL_FIR_COEF_HV(i, j));
 474
 475                 for (j = 0; j < 5; j++)
 476                         RR(OVL_CONV_COEF(i, j));
 477
 478                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 479                         for (j = 0; j < 8; j++)
 480                                 RR(OVL_FIR_COEF_V(i, j));
 481                 }
 482
 483                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 484                         RR(OVL_BA0_UV(i));
 485                         RR(OVL_BA1_UV(i));
 486                         RR(OVL_FIR2(i));
 487                         RR(OVL_ACCU2_0(i));
 488                         RR(OVL_ACCU2_1(i));
 489
 490                         for (j = 0; j < 8; j++)
 491                                 RR(OVL_FIR_COEF_H2(i, j));
 492
 493                         for (j = 0; j < 8; j++)
 494                                 RR(OVL_FIR_COEF_HV2(i, j));
 495
 496                         for (j = 0; j < 8; j++)
 497                                 RR(OVL_FIR_COEF_V2(i, j));
 498                 }
 499                 if (dss_has_feature(FEAT_ATTR2))
 500                         RR(OVL_ATTRIBUTES2(i));
 501         }
 502
 503         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 504                 RR(DIVISOR);
 505
 506         /* enable last, because LCD & DIGIT enable are here */
 507         RR(CONTROL);
 508         if (dss_has_feature(FEAT_MGR_LCD2))
 509                 RR(CONTROL2);
 510         if (dss_has_feature(FEAT_MGR_LCD3))
 511                 RR(CONTROL3);
 512         /* clear spurious SYNC_LOST_DIGIT interrupts */
 513         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
 514
 515         /*
 516          * enable last so IRQs won't trigger before
 517          * the context is fully restored
 518          */
 519         RR(IRQENABLE);
 520
 521         DSSDBG("context restored\n");
 522 }
 523
 524 #undef SR
 525 #undef RR
 526
 527 int dispc_runtime_get(void)
 528 {
 529         int r;
 530
 531         DSSDBG("dispc_runtime_get\n");
 532
 533         r = pm_runtime_get_sync(&dispc.pdev->dev);
 534         if (WARN_ON(r < 0)) {
 535                 pm_runtime_put_sync(&dispc.pdev->dev);
 536                 return r;
 537         }
 538         return 0;
 539 }
 540 EXPORT_SYMBOL(dispc_runtime_get);
 541
 542 void dispc_runtime_put(void)
 543 {
 544         int r;
 545
 546         DSSDBG("dispc_runtime_put\n");
 547
 548         r = pm_runtime_put_sync(&dispc.pdev->dev);
 549         WARN_ON(r < 0 && r != -ENOSYS);
 550 }
 551 EXPORT_SYMBOL(dispc_runtime_put);
 552
 553 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 554 {
 555         return mgr_desc[channel].vsync_irq;
 556 }
 557 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
 558
 559 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 560 {
 561         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
 562                 return 0;
 563
 564         return mgr_desc[channel].framedone_irq;
 565 }
 566 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
 567
 568 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
 569 {
 570         return mgr_desc[channel].sync_lost_irq;
 571 }
 572 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
 573
 574 u32 dispc_wb_get_framedone_irq(void)
 575 {
 576         return DISPC_IRQ_FRAMEDONEWB;
 577 }
 578
 579 bool dispc_mgr_go_busy(enum omap_channel channel)
 580 {
 581         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 582 }
 583 EXPORT_SYMBOL(dispc_mgr_go_busy);
 584
 585 void dispc_mgr_go(enum omap_channel channel)
 586 {
 587         WARN_ON(!dispc_mgr_is_enabled(channel));
 588         WARN_ON(dispc_mgr_go_busy(channel));
 589
 590         DSSDBG("GO %s\n", mgr_desc[channel].name);
 591
 592         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 593 }
 594 EXPORT_SYMBOL(dispc_mgr_go);
 595
 596 bool dispc_wb_go_busy(void)
 597 {
 598         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 599 }
 600
 601 void dispc_wb_go(void)
 602 {
 603         enum omap_plane plane = OMAP_DSS_WB;
 604         bool enable, go;
 605
 606         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 607
 608         if (!enable)
 609                 return;
 610
 611         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 612         if (go) {
 613                 DSSERR("GO bit not down for WB\n");
 614                 return;
 615         }
 616
 617         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 618 }
 619
 620 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 621 {
 622         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 623 }
 624
 625 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 626 {
 627         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 628 }
 629
 630 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 631 {
 632         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 633 }
 634
 635 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 636 {
 637         BUG_ON(plane == OMAP_DSS_GFX);
 638
 639         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 640 }
 641
 642 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 643                 u32 value)
 644 {
 645         BUG_ON(plane == OMAP_DSS_GFX);
 646
 647         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 648 }
 649
 650 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 651 {
 652         BUG_ON(plane == OMAP_DSS_GFX);
 653
 654         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 655 }
 656
 657 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 658                                 int fir_vinc, int five_taps,
 659                                 enum omap_color_component color_comp)
 660 {
 661         const struct dispc_coef *h_coef, *v_coef;
 662         int i;
 663
 664         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 665         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 666
 667         for (i = 0; i < 8; i++) {
 668                 u32 h, hv;
 669
 670                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 671                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 672                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 673                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 674                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 675                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 676                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 677                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 678
 679                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 680                         dispc_ovl_write_firh_reg(plane, i, h);
 681                         dispc_ovl_write_firhv_reg(plane, i, hv);
 682                 } else {
 683                         dispc_ovl_write_firh2_reg(plane, i, h);
 684                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 685                 }
 686
 687         }
 688
 689         if (five_taps) {
 690                 for (i = 0; i < 8; i++) {
 691                         u32 v;
 692                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 693                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 694                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 695                                 dispc_ovl_write_firv_reg(plane, i, v);
 696                         else
 697                                 dispc_ovl_write_firv2_reg(plane, i, v);
 698                 }
 699         }
 700 }
 701
 702
 703 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
 704                 const struct color_conv_coef *ct)
 705 {
 706 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 707
 708         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 709         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 710         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 711         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 712         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 713
 714         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 715
 716 #undef CVAL
 717 }
 718
 719 static void dispc_setup_color_conv_coef(void)
 720 {
 721         int i;
 722         int num_ovl = dss_feat_get_num_ovls();
 723         const struct color_conv_coef ctbl_bt601_5_ovl = {
 724                 /* YUV -> RGB */
 725                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
 726         };
 727         const struct color_conv_coef ctbl_bt601_5_wb = {
 728                 /* RGB -> YUV */
 729                 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
 730         };
 731
 732         for (i = 1; i < num_ovl; i++)
 733                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
 734
 735         if (dispc.feat->has_writeback)
 736                 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
 737 }
 738
 739 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 740 {
 741         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 742 }
 743
 744 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 745 {
 746         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 747 }
 748
 749 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 750 {
 751         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 752 }
 753
 754 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 755 {
 756         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 757 }
 758
 759 static void dispc_ovl_set_pos(enum omap_plane plane,
 760                 enum omap_overlay_caps caps, int x, int y)
 761 {
 762         u32 val;
 763
 764         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 765                 return;
 766
 767         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 768
 769         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 770 }
 771
 772 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 773                 int height)
 774 {
 775         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 776
 777         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 778                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 779         else
 780                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 781 }
 782
 783 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 784                 int height)
 785 {
 786         u32 val;
 787
 788         BUG_ON(plane == OMAP_DSS_GFX);
 789
 790         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 791
 792         if (plane == OMAP_DSS_WB)
 793                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 794         else
 795                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 796 }
 797
 798 static void dispc_ovl_set_zorder(enum omap_plane plane,
 799                 enum omap_overlay_caps caps, u8 zorder)
 800 {
 801         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 802                 return;
 803
 804         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 805 }
 806
 807 static void dispc_ovl_enable_zorder_planes(void)
 808 {
 809         int i;
 810
 811         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 812                 return;
 813
 814         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 815                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 816 }
 817
 818 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 819                 enum omap_overlay_caps caps, bool enable)
 820 {
 821         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 822                 return;
 823
 824         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 825 }
 826
 827 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 828                 enum omap_overlay_caps caps, u8 global_alpha)
 829 {
 830         static const unsigned shifts[] = { 0, 8, 16, 24, };
 831         int shift;
 832
 833         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 834                 return;
 835
 836         shift = shifts[plane];
 837         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 838 }
 839
 840 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 841 {
 842         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 843 }
 844
 845 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 846 {
 847         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 848 }
 849
 850 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 851                 enum omap_color_mode color_mode)
 852 {
 853         u32 m = 0;
 854         if (plane != OMAP_DSS_GFX) {
 855                 switch (color_mode) {
 856                 case OMAP_DSS_COLOR_NV12:
 857                         m = 0x0; break;
 858                 case OMAP_DSS_COLOR_RGBX16:
 859                         m = 0x1; break;
 860                 case OMAP_DSS_COLOR_RGBA16:
 861                         m = 0x2; break;
 862                 case OMAP_DSS_COLOR_RGB12U:
 863                         m = 0x4; break;
 864                 case OMAP_DSS_COLOR_ARGB16:
 865                         m = 0x5; break;
 866                 case OMAP_DSS_COLOR_RGB16:
 867                         m = 0x6; break;
 868                 case OMAP_DSS_COLOR_ARGB16_1555:
 869                         m = 0x7; break;
 870                 case OMAP_DSS_COLOR_RGB24U:
 871                         m = 0x8; break;
 872                 case OMAP_DSS_COLOR_RGB24P:
 873                         m = 0x9; break;
 874                 case OMAP_DSS_COLOR_YUV2:
 875                         m = 0xa; break;
 876                 case OMAP_DSS_COLOR_UYVY:
 877                         m = 0xb; break;
 878                 case OMAP_DSS_COLOR_ARGB32:
 879                         m = 0xc; break;
 880                 case OMAP_DSS_COLOR_RGBA32:
 881                         m = 0xd; break;
 882                 case OMAP_DSS_COLOR_RGBX32:
 883                         m = 0xe; break;
 884                 case OMAP_DSS_COLOR_XRGB16_1555:
 885                         m = 0xf; break;
 886                 default:
 887                         BUG(); return;
 888                 }
 889         } else {
 890                 switch (color_mode) {
 891                 case OMAP_DSS_COLOR_CLUT1:
 892                         m = 0x0; break;
 893                 case OMAP_DSS_COLOR_CLUT2:
 894                         m = 0x1; break;
 895                 case OMAP_DSS_COLOR_CLUT4:
 896                         m = 0x2; break;
 897                 case OMAP_DSS_COLOR_CLUT8:
 898                         m = 0x3; break;
 899                 case OMAP_DSS_COLOR_RGB12U:
 900                         m = 0x4; break;
 901                 case OMAP_DSS_COLOR_ARGB16:
 902                         m = 0x5; break;
 903                 case OMAP_DSS_COLOR_RGB16:
 904                         m = 0x6; break;
 905                 case OMAP_DSS_COLOR_ARGB16_1555:
 906                         m = 0x7; break;
 907                 case OMAP_DSS_COLOR_RGB24U:
 908                         m = 0x8; break;
 909                 case OMAP_DSS_COLOR_RGB24P:
 910                         m = 0x9; break;
 911                 case OMAP_DSS_COLOR_RGBX16:
 912                         m = 0xa; break;
 913                 case OMAP_DSS_COLOR_RGBA16:
 914                         m = 0xb; break;
 915                 case OMAP_DSS_COLOR_ARGB32:
 916                         m = 0xc; break;
 917                 case OMAP_DSS_COLOR_RGBA32:
 918                         m = 0xd; break;
 919                 case OMAP_DSS_COLOR_RGBX32:
 920                         m = 0xe; break;
 921                 case OMAP_DSS_COLOR_XRGB16_1555:
 922                         m = 0xf; break;
 923                 default:
 924                         BUG(); return;
 925                 }
 926         }
 927
 928         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 929 }
 930
 931 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 932                 enum omap_dss_rotation_type rotation_type)
 933 {
 934         if (dss_has_feature(FEAT_BURST_2D) == 0)
 935                 return;
 936
 937         if (rotation_type == OMAP_DSS_ROT_TILER)
 938                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 939         else
 940                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 941 }
 942
 943 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 944 {
 945         int shift;
 946         u32 val;
 947         int chan = 0, chan2 = 0;
 948
 949         switch (plane) {
 950         case OMAP_DSS_GFX:
 951                 shift = 8;
 952                 break;
 953         case OMAP_DSS_VIDEO1:
 954         case OMAP_DSS_VIDEO2:
 955         case OMAP_DSS_VIDEO3:
 956                 shift = 16;
 957                 break;
 958         default:
 959                 BUG();
 960                 return;
 961         }
 962
 963         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 964         if (dss_has_feature(FEAT_MGR_LCD2)) {
 965                 switch (channel) {
 966                 case OMAP_DSS_CHANNEL_LCD:
 967                         chan = 0;
 968                         chan2 = 0;
 969                         break;
 970                 case OMAP_DSS_CHANNEL_DIGIT:
 971                         chan = 1;
 972                         chan2 = 0;
 973                         break;
 974                 case OMAP_DSS_CHANNEL_LCD2:
 975                         chan = 0;
 976                         chan2 = 1;
 977                         break;
 978                 case OMAP_DSS_CHANNEL_LCD3:
 979                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 980                                 chan = 0;
 981                                 chan2 = 2;
 982                         } else {
 983                                 BUG();
 984                                 return;
 985                         }
 986                         break;
 987                 case OMAP_DSS_CHANNEL_WB:
 988                         chan = 0;
 989                         chan2 = 3;
 990                         break;
 991                 default:
 992                         BUG();
 993                         return;
 994                 }
 995
 996                 val = FLD_MOD(val, chan, shift, shift);
 997                 val = FLD_MOD(val, chan2, 31, 30);
 998         } else {
 999                 val = FLD_MOD(val, channel, shift, shift);
1000         }
1001         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1002 }
1003 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1004
1005 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1006 {
1007         int shift;
1008         u32 val;
1009
1010         switch (plane) {
1011         case OMAP_DSS_GFX:
1012                 shift = 8;
1013                 break;
1014         case OMAP_DSS_VIDEO1:
1015         case OMAP_DSS_VIDEO2:
1016         case OMAP_DSS_VIDEO3:
1017                 shift = 16;
1018                 break;
1019         default:
1020                 BUG();
1021                 return 0;
1022         }
1023
1024         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1025
1026         if (FLD_GET(val, shift, shift) == 1)
1027                 return OMAP_DSS_CHANNEL_DIGIT;
1028
1029         if (!dss_has_feature(FEAT_MGR_LCD2))
1030                 return OMAP_DSS_CHANNEL_LCD;
1031
1032         switch (FLD_GET(val, 31, 30)) {
1033         case 0:
1034         default:
1035                 return OMAP_DSS_CHANNEL_LCD;
1036         case 1:
1037                 return OMAP_DSS_CHANNEL_LCD2;
1038         case 2:
1039                 return OMAP_DSS_CHANNEL_LCD3;
1040         case 3:
1041                 return OMAP_DSS_CHANNEL_WB;
1042         }
1043 }
1044
1045 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1046 {
1047         enum omap_plane plane = OMAP_DSS_WB;
1048
1049         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1050 }
1051
1052 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1053                 enum omap_burst_size burst_size)
1054 {
1055         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1056         int shift;
1057
1058         shift = shifts[plane];
1059         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1060 }
1061
1062 static void dispc_configure_burst_sizes(void)
1063 {
1064         int i;
1065         const int burst_size = BURST_SIZE_X8;
1066
1067         /* Configure burst size always to maximum size */
1068         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1069                 dispc_ovl_set_burst_size(i, burst_size);
1070         if (dispc.feat->has_writeback)
1071                 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1072 }
1073
1074 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1075 {
1076         unsigned unit = dss_feat_get_burst_size_unit();
1077         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1078         return unit * 8;
1079 }
1080
1081 void dispc_enable_gamma_table(bool enable)
1082 {
1083         /*
1084          * This is partially implemented to support only disabling of
1085          * the gamma table.
1086          */
1087         if (enable) {
1088                 DSSWARN("Gamma table enabling for TV not yet supported");
1089                 return;
1090         }
1091
1092         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1093 }
1094
1095 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1096 {
1097         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1098                 return;
1099
1100         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1101 }
1102
1103 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1104                 const struct omap_dss_cpr_coefs *coefs)
1105 {
1106         u32 coef_r, coef_g, coef_b;
1107
1108         if (!dss_mgr_is_lcd(channel))
1109                 return;
1110
1111         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1112                 FLD_VAL(coefs->rb, 9, 0);
1113         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1114                 FLD_VAL(coefs->gb, 9, 0);
1115         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1116                 FLD_VAL(coefs->bb, 9, 0);
1117
1118         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1119         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1120         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1121 }
1122
1123 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1124 {
1125         u32 val;
1126
1127         BUG_ON(plane == OMAP_DSS_GFX);
1128
1129         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1130         val = FLD_MOD(val, enable, 9, 9);
1131         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1132 }
1133
1134 static void dispc_ovl_enable_replication(enum omap_plane plane,
1135                 enum omap_overlay_caps caps, bool enable)
1136 {
1137         static const unsigned shifts[] = { 5, 10, 10, 10 };
1138         int shift;
1139
1140         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1141                 return;
1142
1143         shift = shifts[plane];
1144         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1145 }
1146
1147 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1148                 u16 height)
1149 {
1150         u32 val;
1151
1152         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1153                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1154
1155         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1156 }
1157
1158 static void dispc_init_fifos(void)
1159 {
1160         u32 size;
1161         int fifo;
1162         u8 start, end;
1163         u32 unit;
1164         int i;
1165
1166         unit = dss_feat_get_buffer_size_unit();
1167
1168         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1169
1170         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1171                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1172                 size *= unit;
1173                 dispc.fifo_size[fifo] = size;
1174
1175                 /*
1176                  * By default fifos are mapped directly to overlays, fifo 0 to
1177                  * ovl 0, fifo 1 to ovl 1, etc.
1178                  */
1179                 dispc.fifo_assignment[fifo] = fifo;
1180         }
1181
1182         /*
1183          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1184          * causes problems with certain use cases, like using the tiler in 2D
1185          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1186          * giving GFX plane a larger fifo. WB but should work fine with a
1187          * smaller fifo.
1188          */
1189         if (dispc.feat->gfx_fifo_workaround) {
1190                 u32 v;
1191
1192                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1193
1194                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1195                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1196                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1197                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1198
1199                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1200
1201                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1202                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1203         }
1204
1205         /*
1206          * Setup default fifo thresholds.
1207          */
1208         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1209                 u32 low, high;
1210                 const bool use_fifomerge = false;
1211                 const bool manual_update = false;
1212
1213                 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1214                         use_fifomerge, manual_update);
1215
1216                 dispc_ovl_set_fifo_threshold(i, low, high);
1217         }
1218
1219         if (dispc.feat->has_writeback) {
1220                 u32 low, high;
1221                 const bool use_fifomerge = false;
1222                 const bool manual_update = false;
1223
1224                 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1225                         use_fifomerge, manual_update);
1226
1227                 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1228         }
1229 }
1230
1231 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1232 {
1233         int fifo;
1234         u32 size = 0;
1235
1236         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1237                 if (dispc.fifo_assignment[fifo] == plane)
1238                         size += dispc.fifo_size[fifo];
1239         }
1240
1241         return size;
1242 }
1243
1244 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1245 {
1246         u8 hi_start, hi_end, lo_start, lo_end;
1247         u32 unit;
1248
1249         unit = dss_feat_get_buffer_size_unit();
1250
1251         WARN_ON(low % unit != 0);
1252         WARN_ON(high % unit != 0);
1253
1254         low /= unit;
1255         high /= unit;
1256
1257         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1258         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1259
1260         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1261                         plane,
1262                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1263                                 lo_start, lo_end) * unit,
1264                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1265                                 hi_start, hi_end) * unit,
1266                         low * unit, high * unit);
1267
1268         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1269                         FLD_VAL(high, hi_start, hi_end) |
1270                         FLD_VAL(low, lo_start, lo_end));
1271
1272         /*
1273          * configure the preload to the pipeline's high threhold, if HT it's too
1274          * large for the preload field, set the threshold to the maximum value
1275          * that can be held by the preload register
1276          */
1277         if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1278                         plane != OMAP_DSS_WB)
1279                 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1280 }
1281
1282 void dispc_enable_fifomerge(bool enable)
1283 {
1284         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1285                 WARN_ON(enable);
1286                 return;
1287         }
1288
1289         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1290         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1291 }
1292
1293 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1294                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1295                 bool manual_update)
1296 {
1297         /*
1298          * All sizes are in bytes. Both the buffer and burst are made of
1299          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1300          */
1301
1302         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1303         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1304         int i;
1305
1306         burst_size = dispc_ovl_get_burst_size(plane);
1307         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1308
1309         if (use_fifomerge) {
1310                 total_fifo_size = 0;
1311                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1312                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1313         } else {
1314                 total_fifo_size = ovl_fifo_size;
1315         }
1316
1317         /*
1318          * We use the same low threshold for both fifomerge and non-fifomerge
1319          * cases, but for fifomerge we calculate the high threshold using the
1320          * combined fifo size
1321          */
1322
1323         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1324                 *fifo_low = ovl_fifo_size - burst_size * 2;
1325                 *fifo_high = total_fifo_size - burst_size;
1326         } else if (plane == OMAP_DSS_WB) {
1327                 /*
1328                  * Most optimal configuration for writeback is to push out data
1329                  * to the interconnect the moment writeback pushes enough pixels
1330                  * in the FIFO to form a burst
1331                  */
1332                 *fifo_low = 0;
1333                 *fifo_high = burst_size;
1334         } else {
1335                 *fifo_low = ovl_fifo_size - burst_size;
1336                 *fifo_high = total_fifo_size - buf_unit;
1337         }
1338 }
1339
1340 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1341 {
1342         int bit;
1343
1344         if (plane == OMAP_DSS_GFX)
1345                 bit = 14;
1346         else
1347                 bit = 23;
1348
1349         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1350 }
1351
1352 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1353         int low, int high)
1354 {
1355         dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1356                 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1357 }
1358
1359 static void dispc_init_mflag(void)
1360 {
1361         int i;
1362
1363         /*
1364          * HACK: NV12 color format and MFLAG seem to have problems working
1365          * together: using two displays, and having an NV12 overlay on one of
1366          * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1367          * Changing MFLAG thresholds and PRELOAD to certain values seem to
1368          * remove the errors, but there doesn't seem to be a clear logic on
1369          * which values work and which not.
1370          *
1371          * As a work-around, set force MFLAG to always on.
1372          */
1373         dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1374                 (1 << 0) |      /* MFLAG_CTRL = force always on */
1375                 (0 << 2));      /* MFLAG_START = disable */
1376
1377         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1378                 u32 size = dispc_ovl_get_fifo_size(i);
1379                 u32 unit = dss_feat_get_buffer_size_unit();
1380                 u32 low, high;
1381
1382                 dispc_ovl_set_mflag(i, true);
1383
1384                 /*
1385                  * Simulation team suggests below thesholds:
1386                  * HT = fifosize * 5 / 8;
1387                  * LT = fifosize * 4 / 8;
1388                  */
1389
1390                 low = size * 4 / 8 / unit;
1391                 high = size * 5 / 8 / unit;
1392
1393                 dispc_ovl_set_mflag_threshold(i, low, high);
1394         }
1395
1396         if (dispc.feat->has_writeback) {
1397                 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1398                 u32 unit = dss_feat_get_buffer_size_unit();
1399                 u32 low, high;
1400
1401                 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1402
1403                 /*
1404                  * Simulation team suggests below thesholds:
1405                  * HT = fifosize * 5 / 8;
1406                  * LT = fifosize * 4 / 8;
1407                  */
1408
1409                 low = size * 4 / 8 / unit;
1410                 high = size * 5 / 8 / unit;
1411
1412                 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1413         }
1414 }
1415
1416 static void dispc_ovl_set_fir(enum omap_plane plane,
1417                                 int hinc, int vinc,
1418                                 enum omap_color_component color_comp)
1419 {
1420         u32 val;
1421
1422         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1423                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1424
1425                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1426                                         &hinc_start, &hinc_end);
1427                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1428                                         &vinc_start, &vinc_end);
1429                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1430                                 FLD_VAL(hinc, hinc_start, hinc_end);
1431
1432                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1433         } else {
1434                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1435                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1436         }
1437 }
1438
1439 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1440 {
1441         u32 val;
1442         u8 hor_start, hor_end, vert_start, vert_end;
1443
1444         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1445         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1446
1447         val = FLD_VAL(vaccu, vert_start, vert_end) |
1448                         FLD_VAL(haccu, hor_start, hor_end);
1449
1450         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1451 }
1452
1453 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1454 {
1455         u32 val;
1456         u8 hor_start, hor_end, vert_start, vert_end;
1457
1458         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1459         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1460
1461         val = FLD_VAL(vaccu, vert_start, vert_end) |
1462                         FLD_VAL(haccu, hor_start, hor_end);
1463
1464         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1465 }
1466
1467 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1468                 int vaccu)
1469 {
1470         u32 val;
1471
1472         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1473         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1474 }
1475
1476 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1477                 int vaccu)
1478 {
1479         u32 val;
1480
1481         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1482         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1483 }
1484
1485 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1486                 u16 orig_width, u16 orig_height,
1487                 u16 out_width, u16 out_height,
1488                 bool five_taps, u8 rotation,
1489                 enum omap_color_component color_comp)
1490 {
1491         int fir_hinc, fir_vinc;
1492
1493         fir_hinc = 1024 * orig_width / out_width;
1494         fir_vinc = 1024 * orig_height / out_height;
1495
1496         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1497                                 color_comp);
1498         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1499 }
1500
1501 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1502                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1503                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1504 {
1505         int h_accu2_0, h_accu2_1;
1506         int v_accu2_0, v_accu2_1;
1507         int chroma_hinc, chroma_vinc;
1508         int idx;
1509
1510         struct accu {
1511                 s8 h0_m, h0_n;
1512                 s8 h1_m, h1_n;
1513                 s8 v0_m, v0_n;
1514                 s8 v1_m, v1_n;
1515         };
1516
1517         const struct accu *accu_table;
1518         const struct accu *accu_val;
1519
1520         static const struct accu accu_nv12[4] = {
1521                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1522                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1523                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1524                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1525         };
1526
1527         static const struct accu accu_nv12_ilace[4] = {
1528                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1529                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1530                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1531                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1532         };
1533
1534         static const struct accu accu_yuv[4] = {
1535                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1536                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1537                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1538                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1539         };
1540
1541         switch (rotation) {
1542         case OMAP_DSS_ROT_0:
1543                 idx = 0;
1544                 break;
1545         case OMAP_DSS_ROT_90:
1546                 idx = 1;
1547                 break;
1548         case OMAP_DSS_ROT_180:
1549                 idx = 2;
1550                 break;
1551         case OMAP_DSS_ROT_270:
1552                 idx = 3;
1553                 break;
1554         default:
1555                 BUG();
1556                 return;
1557         }
1558
1559         switch (color_mode) {
1560         case OMAP_DSS_COLOR_NV12:
1561                 if (ilace)
1562                         accu_table = accu_nv12_ilace;
1563                 else
1564                         accu_table = accu_nv12;
1565                 break;
1566         case OMAP_DSS_COLOR_YUV2:
1567         case OMAP_DSS_COLOR_UYVY:
1568                 accu_table = accu_yuv;
1569                 break;
1570         default:
1571                 BUG();
1572                 return;
1573         }
1574
1575         accu_val = &accu_table[idx];
1576
1577         chroma_hinc = 1024 * orig_width / out_width;
1578         chroma_vinc = 1024 * orig_height / out_height;
1579
1580         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1581         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1582         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1583         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1584
1585         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1586         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1587 }
1588
1589 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1590                 u16 orig_width, u16 orig_height,
1591                 u16 out_width, u16 out_height,
1592                 bool ilace, bool five_taps,
1593                 bool fieldmode, enum omap_color_mode color_mode,
1594                 u8 rotation)
1595 {
1596         int accu0 = 0;
1597         int accu1 = 0;
1598         u32 l;
1599
1600         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1601                                 out_width, out_height, five_taps,
1602                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1603         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1604
1605         /* RESIZEENABLE and VERTICALTAPS */
1606         l &= ~((0x3 << 5) | (0x1 << 21));
1607         l |= (orig_width != out_width) ? (1 << 5) : 0;
1608         l |= (orig_height != out_height) ? (1 << 6) : 0;
1609         l |= five_taps ? (1 << 21) : 0;
1610
1611         /* VRESIZECONF and HRESIZECONF */
1612         if (dss_has_feature(FEAT_RESIZECONF)) {
1613                 l &= ~(0x3 << 7);
1614                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1615                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1616         }
1617
1618         /* LINEBUFFERSPLIT */
1619         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1620                 l &= ~(0x1 << 22);
1621                 l |= five_taps ? (1 << 22) : 0;
1622         }
1623
1624         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1625
1626         /*
1627          * field 0 = even field = bottom field
1628          * field 1 = odd field = top field
1629          */
1630         if (ilace && !fieldmode) {
1631                 accu1 = 0;
1632                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1633                 if (accu0 >= 1024/2) {
1634                         accu1 = 1024/2;
1635                         accu0 -= accu1;
1636                 }
1637         }
1638
1639         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1640         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1641 }
1642
1643 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1644                 u16 orig_width, u16 orig_height,
1645                 u16 out_width, u16 out_height,
1646                 bool ilace, bool five_taps,
1647                 bool fieldmode, enum omap_color_mode color_mode,
1648                 u8 rotation)
1649 {
1650         int scale_x = out_width != orig_width;
1651         int scale_y = out_height != orig_height;
1652         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1653
1654         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1655                 return;
1656         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1657                         color_mode != OMAP_DSS_COLOR_UYVY &&
1658                         color_mode != OMAP_DSS_COLOR_NV12)) {
1659                 /* reset chroma resampling for RGB formats  */
1660                 if (plane != OMAP_DSS_WB)
1661                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1662                 return;
1663         }
1664
1665         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1666                         out_height, ilace, color_mode, rotation);
1667
1668         switch (color_mode) {
1669         case OMAP_DSS_COLOR_NV12:
1670                 if (chroma_upscale) {
1671                         /* UV is subsampled by 2 horizontally and vertically */
1672                         orig_height >>= 1;
1673                         orig_width >>= 1;
1674                 } else {
1675                         /* UV is downsampled by 2 horizontally and vertically */
1676                         orig_height <<= 1;
1677                         orig_width <<= 1;
1678                 }
1679
1680                 break;
1681         case OMAP_DSS_COLOR_YUV2:
1682         case OMAP_DSS_COLOR_UYVY:
1683                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1684                 if (rotation == OMAP_DSS_ROT_0 ||
1685                                 rotation == OMAP_DSS_ROT_180) {
1686                         if (chroma_upscale)
1687                                 /* UV is subsampled by 2 horizontally */
1688                                 orig_width >>= 1;
1689                         else
1690                                 /* UV is downsampled by 2 horizontally */
1691                                 orig_width <<= 1;
1692                 }
1693
1694                 /* must use FIR for YUV422 if rotated */
1695                 if (rotation != OMAP_DSS_ROT_0)
1696                         scale_x = scale_y = true;
1697
1698                 break;
1699         default:
1700                 BUG();
1701                 return;
1702         }
1703
1704         if (out_width != orig_width)
1705                 scale_x = true;
1706         if (out_height != orig_height)
1707                 scale_y = true;
1708
1709         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1710                         out_width, out_height, five_taps,
1711                                 rotation, DISPC_COLOR_COMPONENT_UV);
1712
1713         if (plane != OMAP_DSS_WB)
1714                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1715                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1716
1717         /* set H scaling */
1718         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1719         /* set V scaling */
1720         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1721 }
1722
1723 static void dispc_ovl_set_scaling(enum omap_plane plane,
1724                 u16 orig_width, u16 orig_height,
1725                 u16 out_width, u16 out_height,
1726                 bool ilace, bool five_taps,
1727                 bool fieldmode, enum omap_color_mode color_mode,
1728                 u8 rotation)
1729 {
1730         BUG_ON(plane == OMAP_DSS_GFX);
1731
1732         dispc_ovl_set_scaling_common(plane,
1733                         orig_width, orig_height,
1734                         out_width, out_height,
1735                         ilace, five_taps,
1736                         fieldmode, color_mode,
1737                         rotation);
1738
1739         dispc_ovl_set_scaling_uv(plane,
1740                 orig_width, orig_height,
1741                 out_width, out_height,
1742                 ilace, five_taps,
1743                 fieldmode, color_mode,
1744                 rotation);
1745 }
1746
1747 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1748                 enum omap_dss_rotation_type rotation_type,
1749                 bool mirroring, enum omap_color_mode color_mode)
1750 {
1751         bool row_repeat = false;
1752         int vidrot = 0;
1753
1754         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1755                         color_mode == OMAP_DSS_COLOR_UYVY) {
1756
1757                 if (mirroring) {
1758                         switch (rotation) {
1759                         case OMAP_DSS_ROT_0:
1760                                 vidrot = 2;
1761                                 break;
1762                         case OMAP_DSS_ROT_90:
1763                                 vidrot = 1;
1764                                 break;
1765                         case OMAP_DSS_ROT_180:
1766                                 vidrot = 0;
1767                                 break;
1768                         case OMAP_DSS_ROT_270:
1769                                 vidrot = 3;
1770                                 break;
1771                         }
1772                 } else {
1773                         switch (rotation) {
1774                         case OMAP_DSS_ROT_0:
1775                                 vidrot = 0;
1776                                 break;
1777                         case OMAP_DSS_ROT_90:
1778                                 vidrot = 1;
1779                                 break;
1780                         case OMAP_DSS_ROT_180:
1781                                 vidrot = 2;
1782                                 break;
1783                         case OMAP_DSS_ROT_270:
1784                                 vidrot = 3;
1785                                 break;
1786                         }
1787                 }
1788
1789                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1790                         row_repeat = true;
1791                 else
1792                         row_repeat = false;
1793         }
1794
1795         /*
1796          * OMAP4/5 Errata i631:
1797          * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1798          * rows beyond the framebuffer, which may cause OCP error.
1799          */
1800         if (color_mode == OMAP_DSS_COLOR_NV12 &&
1801                         rotation_type != OMAP_DSS_ROT_TILER)
1802                 vidrot = 1;
1803
1804         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1805         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1806                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1807                         row_repeat ? 1 : 0, 18, 18);
1808
1809         if (color_mode == OMAP_DSS_COLOR_NV12) {
1810                 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1811                                         (rotation == OMAP_DSS_ROT_0 ||
1812                                         rotation == OMAP_DSS_ROT_180);
1813                 /* DOUBLESTRIDE */
1814                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1815         }
1816
1817 }
1818
1819 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1820 {
1821         switch (color_mode) {
1822         case OMAP_DSS_COLOR_CLUT1:
1823                 return 1;
1824         case OMAP_DSS_COLOR_CLUT2:
1825                 return 2;
1826         case OMAP_DSS_COLOR_CLUT4:
1827                 return 4;
1828         case OMAP_DSS_COLOR_CLUT8:
1829         case OMAP_DSS_COLOR_NV12:
1830                 return 8;
1831         case OMAP_DSS_COLOR_RGB12U:
1832         case OMAP_DSS_COLOR_RGB16:
1833         case OMAP_DSS_COLOR_ARGB16:
1834         case OMAP_DSS_COLOR_YUV2:
1835         case OMAP_DSS_COLOR_UYVY:
1836         case OMAP_DSS_COLOR_RGBA16:
1837         case OMAP_DSS_COLOR_RGBX16:
1838         case OMAP_DSS_COLOR_ARGB16_1555:
1839         case OMAP_DSS_COLOR_XRGB16_1555:
1840                 return 16;
1841         case OMAP_DSS_COLOR_RGB24P:
1842                 return 24;
1843         case OMAP_DSS_COLOR_RGB24U:
1844         case OMAP_DSS_COLOR_ARGB32:
1845         case OMAP_DSS_COLOR_RGBA32:
1846         case OMAP_DSS_COLOR_RGBX32:
1847                 return 32;
1848         default:
1849                 BUG();
1850                 return 0;
1851         }
1852 }
1853
1854 static s32 pixinc(int pixels, u8 ps)
1855 {
1856         if (pixels == 1)
1857                 return 1;
1858         else if (pixels > 1)
1859                 return 1 + (pixels - 1) * ps;
1860         else if (pixels < 0)
1861                 return 1 - (-pixels + 1) * ps;
1862         else
1863                 BUG();
1864         return 0;
1865 }
1866
1867 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1868                 u16 screen_width,
1869                 u16 width, u16 height,
1870                 enum omap_color_mode color_mode, bool fieldmode,
1871                 unsigned int field_offset,
1872                 unsigned *offset0, unsigned *offset1,
1873                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1874 {
1875         u8 ps;
1876
1877         /* FIXME CLUT formats */
1878         switch (color_mode) {
1879         case OMAP_DSS_COLOR_CLUT1:
1880         case OMAP_DSS_COLOR_CLUT2:
1881         case OMAP_DSS_COLOR_CLUT4:
1882         case OMAP_DSS_COLOR_CLUT8:
1883                 BUG();
1884                 return;
1885         case OMAP_DSS_COLOR_YUV2:
1886         case OMAP_DSS_COLOR_UYVY:
1887                 ps = 4;
1888                 break;
1889         default:
1890                 ps = color_mode_to_bpp(color_mode) / 8;
1891                 break;
1892         }
1893
1894         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1895                         width, height);
1896
1897         /*
1898          * field 0 = even field = bottom field
1899          * field 1 = odd field = top field
1900          */
1901         switch (rotation + mirror * 4) {
1902         case OMAP_DSS_ROT_0:
1903         case OMAP_DSS_ROT_180:
1904                 /*
1905                  * If the pixel format is YUV or UYVY divide the width
1906                  * of the image by 2 for 0 and 180 degree rotation.
1907                  */
1908                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1909                         color_mode == OMAP_DSS_COLOR_UYVY)
1910                         width = width >> 1;
1911                 /* fall through */
1912         case OMAP_DSS_ROT_90:
1913         case OMAP_DSS_ROT_270:
1914                 *offset1 = 0;
1915                 if (field_offset)
1916                         *offset0 = field_offset * screen_width * ps;
1917                 else
1918                         *offset0 = 0;
1919
1920                 *row_inc = pixinc(1 +
1921                         (y_predecim * screen_width - x_predecim * width) +
1922                         (fieldmode ? screen_width : 0), ps);
1923                 *pix_inc = pixinc(x_predecim, ps);
1924                 break;
1925
1926         case OMAP_DSS_ROT_0 + 4:
1927         case OMAP_DSS_ROT_180 + 4:
1928                 /* If the pixel format is YUV or UYVY divide the width
1929                  * of the image by 2  for 0 degree and 180 degree
1930                  */
1931                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1932                         color_mode == OMAP_DSS_COLOR_UYVY)
1933                         width = width >> 1;
1934                 /* fall through */
1935         case OMAP_DSS_ROT_90 + 4:
1936         case OMAP_DSS_ROT_270 + 4:
1937                 *offset1 = 0;
1938                 if (field_offset)
1939                         *offset0 = field_offset * screen_width * ps;
1940                 else
1941                         *offset0 = 0;
1942                 *row_inc = pixinc(1 -
1943                         (y_predecim * screen_width + x_predecim * width) -
1944                         (fieldmode ? screen_width : 0), ps);
1945                 *pix_inc = pixinc(x_predecim, ps);
1946                 break;
1947
1948         default:
1949                 BUG();
1950                 return;
1951         }
1952 }
1953
1954 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1955                 u16 screen_width,
1956                 u16 width, u16 height,
1957                 enum omap_color_mode color_mode, bool fieldmode,
1958                 unsigned int field_offset,
1959                 unsigned *offset0, unsigned *offset1,
1960                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1961 {
1962         u8 ps;
1963         u16 fbw, fbh;
1964
1965         /* FIXME CLUT formats */
1966         switch (color_mode) {
1967         case OMAP_DSS_COLOR_CLUT1:
1968         case OMAP_DSS_COLOR_CLUT2:
1969         case OMAP_DSS_COLOR_CLUT4:
1970         case OMAP_DSS_COLOR_CLUT8:
1971                 BUG();
1972                 return;
1973         default:
1974                 ps = color_mode_to_bpp(color_mode) / 8;
1975                 break;
1976         }
1977
1978         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1979                         width, height);
1980
1981         /* width & height are overlay sizes, convert to fb sizes */
1982
1983         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1984                 fbw = width;
1985                 fbh = height;
1986         } else {
1987                 fbw = height;
1988                 fbh = width;
1989         }
1990
1991         /*
1992          * field 0 = even field = bottom field
1993          * field 1 = odd field = top field
1994          */
1995         switch (rotation + mirror * 4) {
1996         case OMAP_DSS_ROT_0:
1997                 *offset1 = 0;
1998                 if (field_offset)
1999                         *offset0 = *offset1 + field_offset * screen_width * ps;
2000                 else
2001                         *offset0 = *offset1;
2002                 *row_inc = pixinc(1 +
2003                         (y_predecim * screen_width - fbw * x_predecim) +
2004                         (fieldmode ? screen_width : 0), ps);
2005                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2006                         color_mode == OMAP_DSS_COLOR_UYVY)
2007                         *pix_inc = pixinc(x_predecim, 2 * ps);
2008                 else
2009                         *pix_inc = pixinc(x_predecim, ps);
2010                 break;
2011         case OMAP_DSS_ROT_90:
2012                 *offset1 = screen_width * (fbh - 1) * ps;
2013                 if (field_offset)
2014                         *offset0 = *offset1 + field_offset * ps;
2015                 else
2016                         *offset0 = *offset1;
2017                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2018                                 y_predecim + (fieldmode ? 1 : 0), ps);
2019                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2020                 break;
2021         case OMAP_DSS_ROT_180:
2022                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2023                 if (field_offset)
2024                         *offset0 = *offset1 - field_offset * screen_width * ps;
2025                 else
2026                         *offset0 = *offset1;
2027                 *row_inc = pixinc(-1 -
2028                         (y_predecim * screen_width - fbw * x_predecim) -
2029                         (fieldmode ? screen_width : 0), ps);
2030                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2031                         color_mode == OMAP_DSS_COLOR_UYVY)
2032                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2033                 else
2034                         *pix_inc = pixinc(-x_predecim, ps);
2035                 break;
2036         case OMAP_DSS_ROT_270:
2037                 *offset1 = (fbw - 1) * ps;
2038                 if (field_offset)
2039                         *offset0 = *offset1 - field_offset * ps;
2040                 else
2041                         *offset0 = *offset1;
2042                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2043                                 y_predecim - (fieldmode ? 1 : 0), ps);
2044                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2045                 break;
2046
2047         /* mirroring */
2048         case OMAP_DSS_ROT_0 + 4:
2049                 *offset1 = (fbw - 1) * ps;
2050                 if (field_offset)
2051                         *offset0 = *offset1 + field_offset * screen_width * ps;
2052                 else
2053                         *offset0 = *offset1;
2054                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2055                                 (fieldmode ? screen_width : 0),
2056                                 ps);
2057                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2058                         color_mode == OMAP_DSS_COLOR_UYVY)
2059                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2060                 else
2061                         *pix_inc = pixinc(-x_predecim, ps);
2062                 break;
2063
2064         case OMAP_DSS_ROT_90 + 4:
2065                 *offset1 = 0;
2066                 if (field_offset)
2067                         *offset0 = *offset1 + field_offset * ps;
2068                 else
2069                         *offset0 = *offset1;
2070                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2071                                 y_predecim + (fieldmode ? 1 : 0),
2072                                 ps);
2073                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2074                 break;
2075
2076         case OMAP_DSS_ROT_180 + 4:
2077                 *offset1 = screen_width * (fbh - 1) * ps;
2078                 if (field_offset)
2079                         *offset0 = *offset1 - field_offset * screen_width * ps;
2080                 else
2081                         *offset0 = *offset1;
2082                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2083                                 (fieldmode ? screen_width : 0),
2084                                 ps);
2085                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2086                         color_mode == OMAP_DSS_COLOR_UYVY)
2087                         *pix_inc = pixinc(x_predecim, 2 * ps);
2088                 else
2089                         *pix_inc = pixinc(x_predecim, ps);
2090                 break;
2091
2092         case OMAP_DSS_ROT_270 + 4:
2093                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2094                 if (field_offset)
2095                         *offset0 = *offset1 - field_offset * ps;
2096                 else
2097                         *offset0 = *offset1;
2098                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2099                                 y_predecim - (fieldmode ? 1 : 0),
2100                                 ps);
2101                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2102                 break;
2103
2104         default:
2105                 BUG();
2106                 return;
2107         }
2108 }
2109
2110 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2111                 enum omap_color_mode color_mode, bool fieldmode,
2112                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2113                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2114 {
2115         u8 ps;
2116
2117         switch (color_mode) {
2118         case OMAP_DSS_COLOR_CLUT1:
2119         case OMAP_DSS_COLOR_CLUT2:
2120         case OMAP_DSS_COLOR_CLUT4:
2121         case OMAP_DSS_COLOR_CLUT8:
2122                 BUG();
2123                 return;
2124         default:
2125                 ps = color_mode_to_bpp(color_mode) / 8;
2126                 break;
2127         }
2128
2129         DSSDBG("scrw %d, width %d\n", screen_width, width);
2130
2131         /*
2132          * field 0 = even field = bottom field
2133          * field 1 = odd field = top field
2134          */
2135         *offset1 = 0;
2136         if (field_offset)
2137                 *offset0 = *offset1 + field_offset * screen_width * ps;
2138         else
2139                 *offset0 = *offset1;
2140         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2141                         (fieldmode ? screen_width : 0), ps);
2142         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2143                 color_mode == OMAP_DSS_COLOR_UYVY)
2144                 *pix_inc = pixinc(x_predecim, 2 * ps);
2145         else
2146                 *pix_inc = pixinc(x_predecim, ps);
2147 }
2148
2149 /*
2150  * This function is used to avoid synclosts in OMAP3, because of some
2151  * undocumented horizontal position and timing related limitations.
2152  */
2153 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2154                 const struct omap_video_timings *t, u16 pos_x,
2155                 u16 width, u16 height, u16 out_width, u16 out_height,
2156                 bool five_taps)
2157 {
2158         const int ds = DIV_ROUND_UP(height, out_height);
2159         unsigned long nonactive;
2160         static const u8 limits[3] = { 8, 10, 20 };
2161         u64 val, blank;
2162         int i;
2163
2164         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2165
2166         i = 0;
2167         if (out_height < height)
2168                 i++;
2169         if (out_width < width)
2170                 i++;
2171         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2172         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2173         if (blank <= limits[i])
2174                 return -EINVAL;
2175
2176         /* FIXME add checks for 3-tap filter once the limitations are known */
2177         if (!five_taps)
2178                 return 0;
2179
2180         /*
2181          * Pixel data should be prepared before visible display point starts.
2182          * So, atleast DS-2 lines must have already been fetched by DISPC
2183          * during nonactive - pos_x period.
2184          */
2185         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2186         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2187                 val, max(0, ds - 2) * width);
2188         if (val < max(0, ds - 2) * width)
2189                 return -EINVAL;
2190
2191         /*
2192          * All lines need to be refilled during the nonactive period of which
2193          * only one line can be loaded during the active period. So, atleast
2194          * DS - 1 lines should be loaded during nonactive period.
2195          */
2196         val =  div_u64((u64)nonactive * lclk, pclk);
2197         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2198                 val, max(0, ds - 1) * width);
2199         if (val < max(0, ds - 1) * width)
2200                 return -EINVAL;
2201
2202         return 0;
2203 }
2204
2205 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2206                 const struct omap_video_timings *mgr_timings, u16 width,
2207                 u16 height, u16 out_width, u16 out_height,
2208                 enum omap_color_mode color_mode)
2209 {
2210         u32 core_clk = 0;
2211         u64 tmp;
2212
2213         if (height <= out_height && width <= out_width)
2214                 return (unsigned long) pclk;
2215
2216         if (height > out_height) {
2217                 unsigned int ppl = mgr_timings->x_res;
2218
2219                 tmp = (u64)pclk * height * out_width;
2220                 do_div(tmp, 2 * out_height * ppl);
2221                 core_clk = tmp;
2222
2223                 if (height > 2 * out_height) {
2224                         if (ppl == out_width)
2225                                 return 0;
2226
2227                         tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2228                         do_div(tmp, 2 * out_height * (ppl - out_width));
2229                         core_clk = max_t(u32, core_clk, tmp);
2230                 }
2231         }
2232
2233         if (width > out_width) {
2234                 tmp = (u64)pclk * width;
2235                 do_div(tmp, out_width);
2236                 core_clk = max_t(u32, core_clk, tmp);
2237
2238                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2239                         core_clk <<= 1;
2240         }
2241
2242         return core_clk;
2243 }
2244
2245 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2246                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2247 {
2248         if (height > out_height && width > out_width)
2249                 return pclk * 4;
2250         else
2251                 return pclk * 2;
2252 }
2253
2254 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2255                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2256 {
2257         unsigned int hf, vf;
2258
2259         /*
2260          * FIXME how to determine the 'A' factor
2261          * for the no downscaling case ?
2262          */
2263
2264         if (width > 3 * out_width)
2265                 hf = 4;
2266         else if (width > 2 * out_width)
2267                 hf = 3;
2268         else if (width > out_width)
2269                 hf = 2;
2270         else
2271                 hf = 1;
2272         if (height > out_height)
2273                 vf = 2;
2274         else
2275                 vf = 1;
2276
2277         return pclk * vf * hf;
2278 }
2279
2280 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2281                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2282 {
2283         /*
2284          * If the overlay/writeback is in mem to mem mode, there are no
2285          * downscaling limitations with respect to pixel clock, return 1 as
2286          * required core clock to represent that we have sufficient enough
2287          * core clock to do maximum downscaling
2288          */
2289         if (mem_to_mem)
2290                 return 1;
2291
2292         if (width > out_width)
2293                 return DIV_ROUND_UP(pclk, out_width) * width;
2294         else
2295                 return pclk;
2296 }
2297
2298 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2299                 const struct omap_video_timings *mgr_timings,
2300                 u16 width, u16 height, u16 out_width, u16 out_height,
2301                 enum omap_color_mode color_mode, bool *five_taps,
2302                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2303                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2304 {
2305         int error;
2306         u16 in_width, in_height;
2307         int min_factor = min(*decim_x, *decim_y);
2308         const int maxsinglelinewidth =
2309                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2310
2311         *five_taps = false;
2312
2313         do {
2314                 in_height = height / *decim_y;
2315                 in_width = width / *decim_x;
2316                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2317                                 in_height, out_width, out_height, mem_to_mem);
2318                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2319                         *core_clk > dispc_core_clk_rate());
2320                 if (error) {
2321                         if (*decim_x == *decim_y) {
2322                                 *decim_x = min_factor;
2323                                 ++*decim_y;
2324                         } else {
2325                                 swap(*decim_x, *decim_y);
2326                                 if (*decim_x < *decim_y)
2327                                         ++*decim_x;
2328                         }
2329                 }
2330         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2331
2332         if (error) {
2333                 DSSERR("failed to find scaling settings\n");
2334                 return -EINVAL;
2335         }
2336
2337         if (in_width > maxsinglelinewidth) {
2338                 DSSERR("Cannot scale max input width exceeded");
2339                 return -EINVAL;
2340         }
2341         return 0;
2342 }
2343
2344 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2345                 const struct omap_video_timings *mgr_timings,
2346                 u16 width, u16 height, u16 out_width, u16 out_height,
2347                 enum omap_color_mode color_mode, bool *five_taps,
2348                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2349                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2350 {
2351         int error;
2352         u16 in_width, in_height;
2353         const int maxsinglelinewidth =
2354                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2355
2356         do {
2357                 in_height = height / *decim_y;
2358                 in_width = width / *decim_x;
2359                 *five_taps = in_height > out_height;
2360
2361                 if (in_width > maxsinglelinewidth)
2362                         if (in_height > out_height &&
2363                                                 in_height < out_height * 2)
2364                                 *five_taps = false;
2365 again:
2366                 if (*five_taps)
2367                         *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2368                                                 in_width, in_height, out_width,
2369                                                 out_height, color_mode);
2370                 else
2371                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2372                                         in_height, out_width, out_height,
2373                                         mem_to_mem);
2374
2375                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2376                                 pos_x, in_width, in_height, out_width,
2377                                 out_height, *five_taps);
2378                 if (error && *five_taps) {
2379                         *five_taps = false;
2380                         goto again;
2381                 }
2382
2383                 error = (error || in_width > maxsinglelinewidth * 2 ||
2384                         (in_width > maxsinglelinewidth && *five_taps) ||
2385                         !*core_clk || *core_clk > dispc_core_clk_rate());
2386
2387                 if (!error) {
2388                         /* verify that we're inside the limits of scaler */
2389                         if (in_width / 4 > out_width)
2390                                         error = 1;
2391
2392                         if (*five_taps) {
2393                                 if (in_height / 4 > out_height)
2394                                         error = 1;
2395                         } else {
2396                                 if (in_height / 2 > out_height)
2397                                         error = 1;
2398                         }
2399                 }
2400
2401                 if (error)
2402                         ++*decim_y;
2403         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2404
2405         if (error) {
2406                 DSSERR("failed to find scaling settings\n");
2407                 return -EINVAL;
2408         }
2409
2410         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2411                                 in_height, out_width, out_height, *five_taps)) {
2412                         DSSERR("horizontal timing too tight\n");
2413                         return -EINVAL;
2414         }
2415
2416         if (in_width > (maxsinglelinewidth * 2)) {
2417                 DSSERR("Cannot setup scaling");
2418                 DSSERR("width exceeds maximum width possible");
2419                 return -EINVAL;
2420         }
2421
2422         if (in_width > maxsinglelinewidth && *five_taps) {
2423                 DSSERR("cannot setup scaling with five taps");
2424                 return -EINVAL;
2425         }
2426         return 0;
2427 }
2428
2429 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2430                 const struct omap_video_timings *mgr_timings,
2431                 u16 width, u16 height, u16 out_width, u16 out_height,
2432                 enum omap_color_mode color_mode, bool *five_taps,
2433                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2434                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2435 {
2436         u16 in_width, in_width_max;
2437         int decim_x_min = *decim_x;
2438         u16 in_height = height / *decim_y;
2439         const int maxsinglelinewidth =
2440                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2441         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2442
2443         if (mem_to_mem) {
2444                 in_width_max = out_width * maxdownscale;
2445         } else {
2446                 in_width_max = dispc_core_clk_rate() /
2447                                         DIV_ROUND_UP(pclk, out_width);
2448         }
2449
2450         *decim_x = DIV_ROUND_UP(width, in_width_max);
2451
2452         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2453         if (*decim_x > *x_predecim)
2454                 return -EINVAL;
2455
2456         do {
2457                 in_width = width / *decim_x;
2458         } while (*decim_x <= *x_predecim &&
2459                         in_width > maxsinglelinewidth && ++*decim_x);
2460
2461         if (in_width > maxsinglelinewidth) {
2462                 DSSERR("Cannot scale width exceeds max line width");
2463                 return -EINVAL;
2464         }
2465
2466         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2467                                 out_width, out_height, mem_to_mem);
2468         return 0;
2469 }
2470
2471 #define DIV_FRAC(dividend, divisor) \
2472         ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2473
2474 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2475                 enum omap_overlay_caps caps,
2476                 const struct omap_video_timings *mgr_timings,
2477                 u16 width, u16 height, u16 out_width, u16 out_height,
2478                 enum omap_color_mode color_mode, bool *five_taps,
2479                 int *x_predecim, int *y_predecim, u16 pos_x,
2480                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2481 {
2482         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2483         const int max_decim_limit = 16;
2484         unsigned long core_clk = 0;
2485         int decim_x, decim_y, ret;
2486
2487         if (width == out_width && height == out_height)
2488                 return 0;
2489
2490         if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2491                 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2492                 return -EINVAL;
2493         }
2494
2495         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2496                 return -EINVAL;
2497
2498         if (mem_to_mem) {
2499                 *x_predecim = *y_predecim = 1;
2500         } else {
2501                 *x_predecim = max_decim_limit;
2502                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2503                                 dss_has_feature(FEAT_BURST_2D)) ?
2504                                 2 : max_decim_limit;
2505         }
2506
2507         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2508             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2509             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2510             color_mode == OMAP_DSS_COLOR_CLUT8) {
2511                 *x_predecim = 1;
2512                 *y_predecim = 1;
2513                 *five_taps = false;
2514                 return 0;
2515         }
2516
2517         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2518         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2519
2520         if (decim_x > *x_predecim || out_width > width * 8)
2521                 return -EINVAL;
2522
2523         if (decim_y > *y_predecim || out_height > height * 8)
2524                 return -EINVAL;
2525
2526         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2527                 out_width, out_height, color_mode, five_taps,
2528                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2529                 mem_to_mem);
2530         if (ret)
2531                 return ret;
2532
2533         DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2534                 width, height,
2535                 out_width, out_height,
2536                 out_width / width, DIV_FRAC(out_width, width),
2537                 out_height / height, DIV_FRAC(out_height, height),
2538
2539                 decim_x, decim_y,
2540                 width / decim_x, height / decim_y,
2541                 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2542                 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2543
2544                 *five_taps ? 5 : 3,
2545                 core_clk, dispc_core_clk_rate());
2546
2547         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2548                 DSSERR("failed to set up scaling, "
2549                         "required core clk rate = %lu Hz, "
2550                         "current core clk rate = %lu Hz\n",
2551                         core_clk, dispc_core_clk_rate());
2552                 return -EINVAL;
2553         }
2554
2555         *x_predecim = decim_x;
2556         *y_predecim = decim_y;
2557         return 0;
2558 }
2559
2560 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2561                 const struct omap_overlay_info *oi,
2562                 const struct omap_video_timings *timings,
2563                 int *x_predecim, int *y_predecim)
2564 {
2565         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2566         bool five_taps = true;
2567         bool fieldmode = false;
2568         u16 in_height = oi->height;
2569         u16 in_width = oi->width;
2570         bool ilace = timings->interlace;
2571         u16 out_width, out_height;
2572         int pos_x = oi->pos_x;
2573         unsigned long pclk = dispc_mgr_pclk_rate(channel);
2574         unsigned long lclk = dispc_mgr_lclk_rate(channel);
2575
2576         out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2577         out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2578
2579         if (ilace && oi->height == out_height)
2580                 fieldmode = true;
2581
2582         if (ilace) {
2583                 if (fieldmode)
2584                         in_height /= 2;
2585                 out_height /= 2;
2586
2587                 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2588                                 in_height, out_height);
2589         }
2590
2591         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2592                 return -EINVAL;
2593
2594         return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2595                         in_height, out_width, out_height, oi->color_mode,
2596                         &five_taps, x_predecim, y_predecim, pos_x,
2597                         oi->rotation_type, false);
2598 }
2599 EXPORT_SYMBOL(dispc_ovl_check);
2600
2601 static int dispc_ovl_setup_common(enum omap_plane plane,
2602                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2603                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2604                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2605                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2606                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2607                 bool replication, const struct omap_video_timings *mgr_timings,
2608                 bool mem_to_mem)
2609 {
2610         bool five_taps = true;
2611         bool fieldmode = false;
2612         int r, cconv = 0;
2613         unsigned offset0, offset1;
2614         s32 row_inc;
2615         s32 pix_inc;
2616         u16 frame_width, frame_height;
2617         unsigned int field_offset = 0;
2618         u16 in_height = height;
2619         u16 in_width = width;
2620         int x_predecim = 1, y_predecim = 1;
2621         bool ilace = mgr_timings->interlace;
2622         unsigned long pclk = dispc_plane_pclk_rate(plane);
2623         unsigned long lclk = dispc_plane_lclk_rate(plane);
2624
2625         if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2626                 return -EINVAL;
2627
2628         switch (color_mode) {
2629         case OMAP_DSS_COLOR_YUV2:
2630         case OMAP_DSS_COLOR_UYVY:
2631         case OMAP_DSS_COLOR_NV12:
2632                 if (in_width & 1) {
2633                         DSSERR("input width %d is not even for YUV format\n",
2634                                 in_width);
2635                         return -EINVAL;
2636                 }
2637                 break;
2638
2639         default:
2640                 break;
2641         }
2642
2643         out_width = out_width == 0 ? width : out_width;
2644         out_height = out_height == 0 ? height : out_height;
2645
2646         if (ilace && height == out_height)
2647                 fieldmode = true;
2648
2649         if (ilace) {
2650                 if (fieldmode)
2651                         in_height /= 2;
2652                 pos_y /= 2;
2653                 out_height /= 2;
2654
2655                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2656                         "out_height %d\n", in_height, pos_y,
2657                         out_height);
2658         }
2659
2660         if (!dss_feat_color_mode_supported(plane, color_mode))
2661                 return -EINVAL;
2662
2663         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2664                         in_height, out_width, out_height, color_mode,
2665                         &five_taps, &x_predecim, &y_predecim, pos_x,
2666                         rotation_type, mem_to_mem);
2667         if (r)
2668                 return r;
2669
2670         in_width = in_width / x_predecim;
2671         in_height = in_height / y_predecim;
2672
2673         if (x_predecim > 1 || y_predecim > 1)
2674                 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2675                         x_predecim, y_predecim, in_width, in_height);
2676
2677         switch (color_mode) {
2678         case OMAP_DSS_COLOR_YUV2:
2679         case OMAP_DSS_COLOR_UYVY:
2680         case OMAP_DSS_COLOR_NV12:
2681                 if (in_width & 1) {
2682                         DSSDBG("predecimated input width is not even for YUV format\n");
2683                         DSSDBG("adjusting input width %d -> %d\n",
2684                                 in_width, in_width & ~1);
2685
2686                         in_width &= ~1;
2687                 }
2688                 break;
2689
2690         default:
2691                 break;
2692         }
2693
2694         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2695                         color_mode == OMAP_DSS_COLOR_UYVY ||
2696                         color_mode == OMAP_DSS_COLOR_NV12)
2697                 cconv = 1;
2698
2699         if (ilace && !fieldmode) {
2700                 /*
2701                  * when downscaling the bottom field may have to start several
2702                  * source lines below the top field. Unfortunately ACCUI
2703                  * registers will only hold the fractional part of the offset
2704                  * so the integer part must be added to the base address of the
2705                  * bottom field.
2706                  */
2707                 if (!in_height || in_height == out_height)
2708                         field_offset = 0;
2709                 else
2710                         field_offset = in_height / out_height / 2;
2711         }
2712
2713         /* Fields are independent but interleaved in memory. */
2714         if (fieldmode)
2715                 field_offset = 1;
2716
2717         offset0 = 0;
2718         offset1 = 0;
2719         row_inc = 0;
2720         pix_inc = 0;
2721
2722         if (plane == OMAP_DSS_WB) {
2723                 frame_width = out_width;
2724                 frame_height = out_height;
2725         } else {
2726                 frame_width = in_width;
2727                 frame_height = height;
2728         }
2729
2730         if (rotation_type == OMAP_DSS_ROT_TILER)
2731                 calc_tiler_rotation_offset(screen_width, frame_width,
2732                                 color_mode, fieldmode, field_offset,
2733                                 &offset0, &offset1, &row_inc, &pix_inc,
2734                                 x_predecim, y_predecim);
2735         else if (rotation_type == OMAP_DSS_ROT_DMA)
2736                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2737                                 frame_width, frame_height,
2738                                 color_mode, fieldmode, field_offset,
2739                                 &offset0, &offset1, &row_inc, &pix_inc,
2740                                 x_predecim, y_predecim);
2741         else
2742                 calc_vrfb_rotation_offset(rotation, mirror,
2743                                 screen_width, frame_width, frame_height,
2744                                 color_mode, fieldmode, field_offset,
2745                                 &offset0, &offset1, &row_inc, &pix_inc,
2746                                 x_predecim, y_predecim);
2747
2748         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2749                         offset0, offset1, row_inc, pix_inc);
2750
2751         dispc_ovl_set_color_mode(plane, color_mode);
2752
2753         dispc_ovl_configure_burst_type(plane, rotation_type);
2754
2755         dispc_ovl_set_ba0(plane, paddr + offset0);
2756         dispc_ovl_set_ba1(plane, paddr + offset1);
2757
2758         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2759                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2760                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2761         }
2762
2763         if (dispc.feat->last_pixel_inc_missing)
2764                 row_inc += pix_inc - 1;
2765
2766         dispc_ovl_set_row_inc(plane, row_inc);
2767         dispc_ovl_set_pix_inc(plane, pix_inc);
2768
2769         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2770                         in_height, out_width, out_height);
2771
2772         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2773
2774         dispc_ovl_set_input_size(plane, in_width, in_height);
2775
2776         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2777                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2778                                    out_height, ilace, five_taps, fieldmode,
2779                                    color_mode, rotation);
2780                 dispc_ovl_set_output_size(plane, out_width, out_height);
2781                 dispc_ovl_set_vid_color_conv(plane, cconv);
2782         }
2783
2784         dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2785                         color_mode);
2786
2787         dispc_ovl_set_zorder(plane, caps, zorder);
2788         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2789         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2790
2791         dispc_ovl_enable_replication(plane, caps, replication);
2792
2793         return 0;
2794 }
2795
2796 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2797                 bool replication, const struct omap_video_timings *mgr_timings,
2798                 bool mem_to_mem)
2799 {
2800         int r;
2801         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2802         enum omap_channel channel;
2803
2804         channel = dispc_ovl_get_channel_out(plane);
2805
2806         DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2807                 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2808                 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2809                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2810                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2811
2812         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2813                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2814                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2815                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2816                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2817
2818         return r;
2819 }
2820 EXPORT_SYMBOL(dispc_ovl_setup);
2821
2822 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2823                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2824 {
2825         int r;
2826         u32 l;
2827         enum omap_plane plane = OMAP_DSS_WB;
2828         const int pos_x = 0, pos_y = 0;
2829         const u8 zorder = 0, global_alpha = 0;
2830         const bool replication = false;
2831         bool truncation;
2832         int in_width = mgr_timings->x_res;
2833         int in_height = mgr_timings->y_res;
2834         enum omap_overlay_caps caps =
2835                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2836
2837         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2838                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2839                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2840                 wi->mirror);
2841
2842         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2843                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2844                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2845                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2846                 replication, mgr_timings, mem_to_mem);
2847
2848         switch (wi->color_mode) {
2849         case OMAP_DSS_COLOR_RGB16:
2850         case OMAP_DSS_COLOR_RGB24P:
2851         case OMAP_DSS_COLOR_ARGB16:
2852         case OMAP_DSS_COLOR_RGBA16:
2853         case OMAP_DSS_COLOR_RGB12U:
2854         case OMAP_DSS_COLOR_ARGB16_1555:
2855         case OMAP_DSS_COLOR_XRGB16_1555:
2856         case OMAP_DSS_COLOR_RGBX16:
2857                 truncation = true;
2858                 break;
2859         default:
2860                 truncation = false;
2861                 break;
2862         }
2863
2864         /* setup extra DISPC_WB_ATTRIBUTES */
2865         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2866         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2867         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2868         if (mem_to_mem)
2869                 l = FLD_MOD(l, 1, 26, 24);      /* CAPTUREMODE */
2870         else
2871                 l = FLD_MOD(l, 0, 26, 24);      /* CAPTUREMODE */
2872         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2873
2874         if (mem_to_mem) {
2875                 /* WBDELAYCOUNT */
2876                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2877         } else {
2878                 int wbdelay;
2879
2880                 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2881                         mgr_timings->vbp, 255);
2882
2883                 /* WBDELAYCOUNT */
2884                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2885         }
2886
2887         return r;
2888 }
2889
2890 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2891 {
2892         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2893
2894         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2895
2896         return 0;
2897 }
2898 EXPORT_SYMBOL(dispc_ovl_enable);
2899
2900 bool dispc_ovl_enabled(enum omap_plane plane)
2901 {
2902         return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2903 }
2904 EXPORT_SYMBOL(dispc_ovl_enabled);
2905
2906 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2907 {
2908         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2909         /* flush posted write */
2910         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2911 }
2912 EXPORT_SYMBOL(dispc_mgr_enable);
2913
2914 bool dispc_mgr_is_enabled(enum omap_channel channel)
2915 {
2916         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2917 }
2918 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2919
2920 void dispc_wb_enable(bool enable)
2921 {
2922         dispc_ovl_enable(OMAP_DSS_WB, enable);
2923 }
2924
2925 bool dispc_wb_is_enabled(void)
2926 {
2927         return dispc_ovl_enabled(OMAP_DSS_WB);
2928 }
2929
2930 static void dispc_lcd_enable_signal_polarity(bool act_high)
2931 {
2932         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2933                 return;
2934
2935         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2936 }
2937
2938 void dispc_lcd_enable_signal(bool enable)
2939 {
2940         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2941                 return;
2942
2943         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2944 }
2945
2946 void dispc_pck_free_enable(bool enable)
2947 {
2948         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2949                 return;
2950
2951         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2952 }
2953
2954 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2955 {
2956         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2957 }
2958
2959
2960 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2961 {
2962         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2963 }
2964
2965 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2966 {
2967         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2968 }
2969
2970
2971 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2972 {
2973         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2974 }
2975
2976 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2977                 enum omap_dss_trans_key_type type,
2978                 u32 trans_key)
2979 {
2980         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2981
2982         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2983 }
2984
2985 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2986 {
2987         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2988 }
2989
2990 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2991                 bool enable)
2992 {
2993         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2994                 return;
2995
2996         if (ch == OMAP_DSS_CHANNEL_LCD)
2997                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2998         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2999                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
3000 }
3001
3002 void dispc_mgr_setup(enum omap_channel channel,
3003                 const struct omap_overlay_manager_info *info)
3004 {
3005         dispc_mgr_set_default_color(channel, info->default_color);
3006         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
3007         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
3008         dispc_mgr_enable_alpha_fixed_zorder(channel,
3009                         info->partial_alpha_enabled);
3010         if (dss_has_feature(FEAT_CPR)) {
3011                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3012                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3013         }
3014 }
3015 EXPORT_SYMBOL(dispc_mgr_setup);
3016
3017 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
3018 {
3019         int code;
3020
3021         switch (data_lines) {
3022         case 12:
3023                 code = 0;
3024                 break;
3025         case 16:
3026                 code = 1;
3027                 break;
3028         case 18:
3029                 code = 2;
3030                 break;
3031         case 24:
3032                 code = 3;
3033                 break;
3034         default:
3035                 BUG();
3036                 return;
3037         }
3038
3039         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3040 }
3041
3042 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3043 {
3044         u32 l;
3045         int gpout0, gpout1;
3046
3047         switch (mode) {
3048         case DSS_IO_PAD_MODE_RESET:
3049                 gpout0 = 0;
3050                 gpout1 = 0;
3051                 break;
3052         case DSS_IO_PAD_MODE_RFBI:
3053                 gpout0 = 1;
3054                 gpout1 = 0;
3055                 break;
3056         case DSS_IO_PAD_MODE_BYPASS:
3057                 gpout0 = 1;
3058                 gpout1 = 1;
3059                 break;
3060         default:
3061                 BUG();
3062                 return;
3063         }
3064
3065         l = dispc_read_reg(DISPC_CONTROL);
3066         l = FLD_MOD(l, gpout0, 15, 15);
3067         l = FLD_MOD(l, gpout1, 16, 16);
3068         dispc_write_reg(DISPC_CONTROL, l);
3069 }
3070
3071 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3072 {
3073         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3074 }
3075
3076 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3077                 const struct dss_lcd_mgr_config *config)
3078 {
3079         dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3080
3081         dispc_mgr_enable_stallmode(channel, config->stallmode);
3082         dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3083
3084         dispc_mgr_set_clock_div(channel, &config->clock_info);
3085
3086         dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3087
3088         dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3089
3090         dispc_mgr_set_lcd_type_tft(channel);
3091 }
3092 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3093
3094 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3095 {
3096         return width <= dispc.feat->mgr_width_max &&
3097                 height <= dispc.feat->mgr_height_max;
3098 }
3099
3100 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3101                 int vsw, int vfp, int vbp)
3102 {
3103         if (hsw < 1 || hsw > dispc.feat->sw_max ||
3104                         hfp < 1 || hfp > dispc.feat->hp_max ||
3105                         hbp < 1 || hbp > dispc.feat->hp_max ||
3106                         vsw < 1 || vsw > dispc.feat->sw_max ||
3107                         vfp < 0 || vfp > dispc.feat->vp_max ||
3108                         vbp < 0 || vbp > dispc.feat->vp_max)
3109                 return false;
3110         return true;
3111 }
3112
3113 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3114                 unsigned long pclk)
3115 {
3116         if (dss_mgr_is_lcd(channel))
3117                 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3118         else
3119                 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3120 }
3121
3122 bool dispc_mgr_timings_ok(enum omap_channel channel,
3123                 const struct omap_video_timings *timings)
3124 {
3125         if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3126                 return false;
3127
3128         if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3129                 return false;
3130
3131         if (dss_mgr_is_lcd(channel)) {
3132                 /* TODO: OMAP4+ supports interlace for LCD outputs */
3133                 if (timings->interlace)
3134                         return false;
3135
3136                 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3137                                 timings->hbp, timings->vsw, timings->vfp,
3138                                 timings->vbp))
3139                         return false;
3140         }
3141
3142         return true;
3143 }
3144
3145 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3146                 int hfp, int hbp, int vsw, int vfp, int vbp,
3147                 enum omap_dss_signal_level vsync_level,
3148                 enum omap_dss_signal_level hsync_level,
3149                 enum omap_dss_signal_edge data_pclk_edge,
3150                 enum omap_dss_signal_level de_level,
3151                 enum omap_dss_signal_edge sync_pclk_edge)
3152
3153 {
3154         u32 timing_h, timing_v, l;
3155         bool onoff, rf, ipc, vs, hs, de;
3156
3157         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3158                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3159                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3160         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3161                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3162                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
3163
3164         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3165         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3166
3167         switch (vsync_level) {
3168         case OMAPDSS_SIG_ACTIVE_LOW:
3169                 vs = true;
3170                 break;
3171         case OMAPDSS_SIG_ACTIVE_HIGH:
3172                 vs = false;
3173                 break;
3174         default:
3175                 BUG();
3176         }
3177
3178         switch (hsync_level) {
3179         case OMAPDSS_SIG_ACTIVE_LOW:
3180                 hs = true;
3181                 break;
3182         case OMAPDSS_SIG_ACTIVE_HIGH:
3183                 hs = false;
3184                 break;
3185         default:
3186                 BUG();
3187         }
3188
3189         switch (de_level) {
3190         case OMAPDSS_SIG_ACTIVE_LOW:
3191                 de = true;
3192                 break;
3193         case OMAPDSS_SIG_ACTIVE_HIGH:
3194                 de = false;
3195                 break;
3196         default:
3197                 BUG();
3198         }
3199
3200         switch (data_pclk_edge) {
3201         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3202                 ipc = false;
3203                 break;
3204         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3205                 ipc = true;
3206                 break;
3207         default:
3208                 BUG();
3209         }
3210
3211         /* always use the 'rf' setting */
3212         onoff = true;
3213
3214         switch (sync_pclk_edge) {
3215         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3216                 rf = false;
3217                 break;
3218         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3219                 rf = true;
3220                 break;
3221         default:
3222                 BUG();
3223         }
3224
3225         l = FLD_VAL(onoff, 17, 17) |
3226                 FLD_VAL(rf, 16, 16) |
3227                 FLD_VAL(de, 15, 15) |
3228                 FLD_VAL(ipc, 14, 14) |
3229                 FLD_VAL(hs, 13, 13) |
3230                 FLD_VAL(vs, 12, 12);
3231
3232         /* always set ALIGN bit when available */
3233         if (dispc.feat->supports_sync_align)
3234                 l |= (1 << 18);
3235
3236         dispc_write_reg(DISPC_POL_FREQ(channel), l);
3237
3238         if (dispc.syscon_pol) {
3239                 const int shifts[] = {
3240                         [OMAP_DSS_CHANNEL_LCD] = 0,
3241                         [OMAP_DSS_CHANNEL_LCD2] = 1,
3242                         [OMAP_DSS_CHANNEL_LCD3] = 2,
3243                 };
3244
3245                 u32 mask, val;
3246
3247                 mask = (1 << 0) | (1 << 3) | (1 << 6);
3248                 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3249
3250                 mask <<= 16 + shifts[channel];
3251                 val <<= 16 + shifts[channel];
3252
3253                 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3254                         mask, val);
3255         }
3256 }
3257
3258 /* change name to mode? */
3259 void dispc_mgr_set_timings(enum omap_channel channel,
3260                 const struct omap_video_timings *timings)
3261 {
3262         unsigned xtot, ytot;
3263         unsigned long ht, vt;
3264         struct omap_video_timings t = *timings;
3265
3266         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3267
3268         if (!dispc_mgr_timings_ok(channel, &t)) {
3269                 BUG();
3270                 return;
3271         }
3272
3273         if (dss_mgr_is_lcd(channel)) {
3274                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3275                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3276                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3277
3278                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3279                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3280
3281                 ht = timings->pixelclock / xtot;
3282                 vt = timings->pixelclock / xtot / ytot;
3283
3284                 DSSDBG("pck %u\n", timings->pixelclock);
3285                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3286                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3287                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3288                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
3289                         t.de_level, t.sync_pclk_edge);
3290
3291                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3292         } else {
3293                 if (t.interlace)
3294                         t.y_res /= 2;
3295         }
3296
3297         dispc_mgr_set_size(channel, t.x_res, t.y_res);
3298 }
3299 EXPORT_SYMBOL(dispc_mgr_set_timings);
3300
3301 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3302                 u16 pck_div)
3303 {
3304         BUG_ON(lck_div < 1);
3305         BUG_ON(pck_div < 1);
3306
3307         dispc_write_reg(DISPC_DIVISORo(channel),
3308                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3309
3310         if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3311                         channel == OMAP_DSS_CHANNEL_LCD)
3312                 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3313 }
3314
3315 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3316                 int *pck_div)
3317 {
3318         u32 l;
3319         l = dispc_read_reg(DISPC_DIVISORo(channel));
3320         *lck_div = FLD_GET(l, 23, 16);
3321         *pck_div = FLD_GET(l, 7, 0);
3322 }
3323
3324 static unsigned long dispc_fclk_rate(void)
3325 {
3326         struct dss_pll *pll;
3327         unsigned long r = 0;
3328
3329         switch (dss_get_dispc_clk_source()) {
3330         case OMAP_DSS_CLK_SRC_FCK:
3331                 r = dss_get_dispc_clk_rate();
3332                 break;
3333         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3334                 pll = dss_pll_find("dsi0");
3335                 if (!pll)
3336                         pll = dss_pll_find("video0");
3337
3338                 r = pll->cinfo.clkout[0];
3339                 break;
3340         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3341                 pll = dss_pll_find("dsi1");
3342                 if (!pll)
3343                         pll = dss_pll_find("video1");
3344
3345                 r = pll->cinfo.clkout[0];
3346                 break;
3347         default:
3348                 BUG();
3349                 return 0;
3350         }
3351
3352         return r;
3353 }
3354
3355 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3356 {
3357         struct dss_pll *pll;
3358         int lcd;
3359         unsigned long r;
3360         u32 l;
3361
3362         if (dss_mgr_is_lcd(channel)) {
3363                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3364
3365                 lcd = FLD_GET(l, 23, 16);
3366
3367                 switch (dss_get_lcd_clk_source(channel)) {
3368                 case OMAP_DSS_CLK_SRC_FCK:
3369                         r = dss_get_dispc_clk_rate();
3370                         break;
3371                 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3372                         pll = dss_pll_find("dsi0");
3373                         if (!pll)
3374                                 pll = dss_pll_find("video0");
3375
3376                         r = pll->cinfo.clkout[0];
3377                         break;
3378                 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3379                         pll = dss_pll_find("dsi1");
3380                         if (!pll)
3381                                 pll = dss_pll_find("video1");
3382
3383                         r = pll->cinfo.clkout[0];
3384                         break;
3385                 default:
3386                         BUG();
3387                         return 0;
3388                 }
3389
3390                 return r / lcd;
3391         } else {
3392                 return dispc_fclk_rate();
3393         }
3394 }
3395
3396 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3397 {
3398         unsigned long r;
3399
3400         if (dss_mgr_is_lcd(channel)) {
3401                 int pcd;
3402                 u32 l;
3403
3404                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3405
3406                 pcd = FLD_GET(l, 7, 0);
3407
3408                 r = dispc_mgr_lclk_rate(channel);
3409
3410                 return r / pcd;
3411         } else {
3412                 return dispc.tv_pclk_rate;
3413         }
3414 }
3415
3416 void dispc_set_tv_pclk(unsigned long pclk)
3417 {
3418         dispc.tv_pclk_rate = pclk;
3419 }
3420
3421 static unsigned long dispc_core_clk_rate(void)
3422 {
3423         return dispc.core_clk_rate;
3424 }
3425
3426 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3427 {
3428         enum omap_channel channel;
3429
3430         if (plane == OMAP_DSS_WB)
3431                 return 0;
3432
3433         channel = dispc_ovl_get_channel_out(plane);
3434
3435         return dispc_mgr_pclk_rate(channel);
3436 }
3437
3438 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3439 {
3440         enum omap_channel channel;
3441
3442         if (plane == OMAP_DSS_WB)
3443                 return 0;
3444
3445         channel = dispc_ovl_get_channel_out(plane);
3446
3447         return dispc_mgr_lclk_rate(channel);
3448 }
3449
3450 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3451 {
3452         int lcd, pcd;
3453         enum omap_dss_clk_source lcd_clk_src;
3454
3455         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3456
3457         lcd_clk_src = dss_get_lcd_clk_source(channel);
3458
3459         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3460                 dss_get_generic_clk_source_name(lcd_clk_src),
3461                 dss_feat_get_clk_source_name(lcd_clk_src));
3462
3463         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3464
3465         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3466                 dispc_mgr_lclk_rate(channel), lcd);
3467         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3468                 dispc_mgr_pclk_rate(channel), pcd);
3469 }
3470
3471 void dispc_dump_clocks(struct seq_file *s)
3472 {
3473         int lcd;
3474         u32 l;
3475         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3476
3477         if (dispc_runtime_get())
3478                 return;
3479
3480         seq_printf(s, "- DISPC -\n");
3481
3482         seq_printf(s, "dispc fclk source = %s (%s)\n",
3483                         dss_get_generic_clk_source_name(dispc_clk_src),
3484                         dss_feat_get_clk_source_name(dispc_clk_src));
3485
3486         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3487
3488         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3489                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3490                 l = dispc_read_reg(DISPC_DIVISOR);
3491                 lcd = FLD_GET(l, 23, 16);
3492
3493                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3494                                 (dispc_fclk_rate()/lcd), lcd);
3495         }
3496
3497         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3498
3499         if (dss_has_feature(FEAT_MGR_LCD2))
3500                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3501         if (dss_has_feature(FEAT_MGR_LCD3))
3502                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3503
3504         dispc_runtime_put();
3505 }
3506
3507 static void dispc_dump_regs(struct seq_file *s)
3508 {
3509         int i, j;
3510         const char *mgr_names[] = {
3511                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3512                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3513                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3514                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3515         };
3516         const char *ovl_names[] = {
3517                 [OMAP_DSS_GFX]          = "GFX",
3518                 [OMAP_DSS_VIDEO1]       = "VID1",
3519                 [OMAP_DSS_VIDEO2]       = "VID2",
3520                 [OMAP_DSS_VIDEO3]       = "VID3",
3521                 [OMAP_DSS_WB]           = "WB",
3522         };
3523         const char **p_names;
3524
3525 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3526
3527         if (dispc_runtime_get())
3528                 return;
3529
3530         /* DISPC common registers */
3531         DUMPREG(DISPC_REVISION);
3532         DUMPREG(DISPC_SYSCONFIG);
3533         DUMPREG(DISPC_SYSSTATUS);
3534         DUMPREG(DISPC_IRQSTATUS);
3535         DUMPREG(DISPC_IRQENABLE);
3536         DUMPREG(DISPC_CONTROL);
3537         DUMPREG(DISPC_CONFIG);
3538         DUMPREG(DISPC_CAPABLE);
3539         DUMPREG(DISPC_LINE_STATUS);
3540         DUMPREG(DISPC_LINE_NUMBER);
3541         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3542                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3543                 DUMPREG(DISPC_GLOBAL_ALPHA);
3544         if (dss_has_feature(FEAT_MGR_LCD2)) {
3545                 DUMPREG(DISPC_CONTROL2);
3546                 DUMPREG(DISPC_CONFIG2);
3547         }
3548         if (dss_has_feature(FEAT_MGR_LCD3)) {
3549                 DUMPREG(DISPC_CONTROL3);
3550                 DUMPREG(DISPC_CONFIG3);
3551         }
3552         if (dss_has_feature(FEAT_MFLAG))
3553                 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3554
3555 #undef DUMPREG
3556
3557 #define DISPC_REG(i, name) name(i)
3558 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3559         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3560         dispc_read_reg(DISPC_REG(i, r)))
3561
3562         p_names = mgr_names;
3563
3564         /* DISPC channel specific registers */
3565         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3566                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3567                 DUMPREG(i, DISPC_TRANS_COLOR);
3568                 DUMPREG(i, DISPC_SIZE_MGR);
3569
3570                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3571                         continue;
3572
3573                 DUMPREG(i, DISPC_TIMING_H);
3574                 DUMPREG(i, DISPC_TIMING_V);
3575                 DUMPREG(i, DISPC_POL_FREQ);
3576                 DUMPREG(i, DISPC_DIVISORo);
3577
3578                 DUMPREG(i, DISPC_DATA_CYCLE1);
3579                 DUMPREG(i, DISPC_DATA_CYCLE2);
3580                 DUMPREG(i, DISPC_DATA_CYCLE3);
3581
3582                 if (dss_has_feature(FEAT_CPR)) {
3583                         DUMPREG(i, DISPC_CPR_COEF_R);
3584                         DUMPREG(i, DISPC_CPR_COEF_G);
3585                         DUMPREG(i, DISPC_CPR_COEF_B);
3586                 }
3587         }
3588
3589         p_names = ovl_names;
3590
3591         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3592                 DUMPREG(i, DISPC_OVL_BA0);
3593                 DUMPREG(i, DISPC_OVL_BA1);
3594                 DUMPREG(i, DISPC_OVL_POSITION);
3595                 DUMPREG(i, DISPC_OVL_SIZE);
3596                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3597                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3598                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3599                 DUMPREG(i, DISPC_OVL_ROW_INC);
3600                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3601
3602                 if (dss_has_feature(FEAT_PRELOAD))
3603                         DUMPREG(i, DISPC_OVL_PRELOAD);
3604                 if (dss_has_feature(FEAT_MFLAG))
3605                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3606
3607                 if (i == OMAP_DSS_GFX) {
3608                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3609                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3610                         continue;
3611                 }
3612
3613                 DUMPREG(i, DISPC_OVL_FIR);
3614                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3615                 DUMPREG(i, DISPC_OVL_ACCU0);
3616                 DUMPREG(i, DISPC_OVL_ACCU1);
3617                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3618                         DUMPREG(i, DISPC_OVL_BA0_UV);
3619                         DUMPREG(i, DISPC_OVL_BA1_UV);
3620                         DUMPREG(i, DISPC_OVL_FIR2);
3621                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3622                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3623                 }
3624                 if (dss_has_feature(FEAT_ATTR2))
3625                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3626         }
3627
3628         if (dispc.feat->has_writeback) {
3629                 i = OMAP_DSS_WB;
3630                 DUMPREG(i, DISPC_OVL_BA0);
3631                 DUMPREG(i, DISPC_OVL_BA1);
3632                 DUMPREG(i, DISPC_OVL_SIZE);
3633                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3634                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3635                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3636                 DUMPREG(i, DISPC_OVL_ROW_INC);
3637                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3638
3639                 if (dss_has_feature(FEAT_MFLAG))
3640                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3641
3642                 DUMPREG(i, DISPC_OVL_FIR);
3643                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3644                 DUMPREG(i, DISPC_OVL_ACCU0);
3645                 DUMPREG(i, DISPC_OVL_ACCU1);
3646                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3647                         DUMPREG(i, DISPC_OVL_BA0_UV);
3648                         DUMPREG(i, DISPC_OVL_BA1_UV);
3649                         DUMPREG(i, DISPC_OVL_FIR2);
3650                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3651                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3652                 }
3653                 if (dss_has_feature(FEAT_ATTR2))
3654                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3655         }
3656
3657 #undef DISPC_REG
3658 #undef DUMPREG
3659
3660 #define DISPC_REG(plane, name, i) name(plane, i)
3661 #define DUMPREG(plane, name, i) \
3662         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3663         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3664         dispc_read_reg(DISPC_REG(plane, name, i)))
3665
3666         /* Video pipeline coefficient registers */
3667
3668         /* start from OMAP_DSS_VIDEO1 */
3669         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3670                 for (j = 0; j < 8; j++)
3671                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3672
3673                 for (j = 0; j < 8; j++)
3674                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3675
3676                 for (j = 0; j < 5; j++)
3677                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3678
3679                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3680                         for (j = 0; j < 8; j++)
3681                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3682                 }
3683
3684                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3685                         for (j = 0; j < 8; j++)
3686                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3687
3688                         for (j = 0; j < 8; j++)
3689                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3690
3691                         for (j = 0; j < 8; j++)
3692                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3693                 }
3694         }
3695
3696         dispc_runtime_put();
3697
3698 #undef DISPC_REG
3699 #undef DUMPREG
3700 }
3701
3702 /* calculate clock rates using dividers in cinfo */
3703 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3704                 struct dispc_clock_info *cinfo)
3705 {
3706         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3707                 return -EINVAL;
3708         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3709                 return -EINVAL;
3710
3711         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3712         cinfo->pck = cinfo->lck / cinfo->pck_div;
3713
3714         return 0;
3715 }
3716
3717 bool dispc_div_calc(unsigned long dispc,
3718                 unsigned long pck_min, unsigned long pck_max,
3719                 dispc_div_calc_func func, void *data)
3720 {
3721         int lckd, lckd_start, lckd_stop;
3722         int pckd, pckd_start, pckd_stop;
3723         unsigned long pck, lck;
3724         unsigned long lck_max;
3725         unsigned long pckd_hw_min, pckd_hw_max;
3726         unsigned min_fck_per_pck;
3727         unsigned long fck;
3728
3729 #ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
3730         min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
3731 #else
3732         min_fck_per_pck = 0;
3733 #endif
3734
3735         pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3736         pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3737
3738         lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3739
3740         pck_min = pck_min ? pck_min : 1;
3741         pck_max = pck_max ? pck_max : ULONG_MAX;
3742
3743         lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3744         lckd_stop = min(dispc / pck_min, 255ul);
3745
3746         for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3747                 lck = dispc / lckd;
3748
3749                 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3750                 pckd_stop = min(lck / pck_min, pckd_hw_max);
3751
3752                 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3753                         pck = lck / pckd;
3754
3755                         /*
3756                          * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3757                          * clock, which means we're configuring DISPC fclk here
3758                          * also. Thus we need to use the calculated lck. For
3759                          * OMAP4+ the DISPC fclk is a separate clock.
3760                          */
3761                         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3762                                 fck = dispc_core_clk_rate();
3763                         else
3764                                 fck = lck;
3765
3766                         if (fck < pck * min_fck_per_pck)
3767                                 continue;
3768
3769                         if (func(lckd, pckd, lck, pck, data))
3770                                 return true;
3771                 }
3772         }
3773
3774         return false;
3775 }
3776
3777 void dispc_mgr_set_clock_div(enum omap_channel channel,
3778                 const struct dispc_clock_info *cinfo)
3779 {
3780         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3781         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3782
3783         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3784 }
3785
3786 int dispc_mgr_get_clock_div(enum omap_channel channel,
3787                 struct dispc_clock_info *cinfo)
3788 {
3789         unsigned long fck;
3790
3791         fck = dispc_fclk_rate();
3792
3793         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3794         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3795
3796         cinfo->lck = fck / cinfo->lck_div;
3797         cinfo->pck = cinfo->lck / cinfo->pck_div;
3798
3799         return 0;
3800 }
3801
3802 u32 dispc_read_irqstatus(void)
3803 {
3804         return dispc_read_reg(DISPC_IRQSTATUS);
3805 }
3806 EXPORT_SYMBOL(dispc_read_irqstatus);
3807
3808 void dispc_clear_irqstatus(u32 mask)
3809 {
3810         dispc_write_reg(DISPC_IRQSTATUS, mask);
3811 }
3812 EXPORT_SYMBOL(dispc_clear_irqstatus);
3813
3814 u32 dispc_read_irqenable(void)
3815 {
3816         return dispc_read_reg(DISPC_IRQENABLE);
3817 }
3818 EXPORT_SYMBOL(dispc_read_irqenable);
3819
3820 void dispc_write_irqenable(u32 mask)
3821 {
3822         u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3823
3824         /* clear the irqstatus for newly enabled irqs */
3825         dispc_clear_irqstatus((mask ^ old_mask) & mask);
3826
3827         dispc_write_reg(DISPC_IRQENABLE, mask);
3828 }
3829 EXPORT_SYMBOL(dispc_write_irqenable);
3830
3831 void dispc_enable_sidle(void)
3832 {
3833         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3834 }
3835
3836 void dispc_disable_sidle(void)
3837 {
3838         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3839 }
3840
3841 static void _omap_dispc_initial_config(void)
3842 {
3843         u32 l;
3844
3845         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3846         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3847                 l = dispc_read_reg(DISPC_DIVISOR);
3848                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3849                 l = FLD_MOD(l, 1, 0, 0);
3850                 l = FLD_MOD(l, 1, 23, 16);
3851                 dispc_write_reg(DISPC_DIVISOR, l);
3852
3853                 dispc.core_clk_rate = dispc_fclk_rate();
3854         }
3855
3856         /* FUNCGATED */
3857         if (dss_has_feature(FEAT_FUNCGATED))
3858                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3859
3860         dispc_setup_color_conv_coef();
3861
3862         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3863
3864         dispc_init_fifos();
3865
3866         dispc_configure_burst_sizes();
3867
3868         dispc_ovl_enable_zorder_planes();
3869
3870         if (dispc.feat->mstandby_workaround)
3871                 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3872
3873         if (dss_has_feature(FEAT_MFLAG))
3874                 dispc_init_mflag();
3875 }
3876
3877 static const struct dispc_features omap24xx_dispc_feats = {
3878         .sw_start               =       5,
3879         .fp_start               =       15,
3880         .bp_start               =       27,
3881         .sw_max                 =       64,
3882         .vp_max                 =       255,
3883         .hp_max                 =       256,
3884         .mgr_width_start        =       10,
3885         .mgr_height_start       =       26,
3886         .mgr_width_max          =       2048,
3887         .mgr_height_max         =       2048,
3888         .max_lcd_pclk           =       66500000,
3889         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3890         .calc_core_clk          =       calc_core_clk_24xx,
3891         .num_fifos              =       3,
3892         .no_framedone_tv        =       true,
3893         .set_max_preload        =       false,
3894         .last_pixel_inc_missing =       true,
3895 };
3896
3897 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3898         .sw_start               =       5,
3899         .fp_start               =       15,
3900         .bp_start               =       27,
3901         .sw_max                 =       64,
3902         .vp_max                 =       255,
3903         .hp_max                 =       256,
3904         .mgr_width_start        =       10,
3905         .mgr_height_start       =       26,
3906         .mgr_width_max          =       2048,
3907         .mgr_height_max         =       2048,
3908         .max_lcd_pclk           =       173000000,
3909         .max_tv_pclk            =       59000000,
3910         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3911         .calc_core_clk          =       calc_core_clk_34xx,
3912         .num_fifos              =       3,
3913         .no_framedone_tv        =       true,
3914         .set_max_preload        =       false,
3915         .last_pixel_inc_missing =       true,
3916 };
3917
3918 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3919         .sw_start               =       7,
3920         .fp_start               =       19,
3921         .bp_start               =       31,
3922         .sw_max                 =       256,
3923         .vp_max                 =       4095,
3924         .hp_max                 =       4096,
3925         .mgr_width_start        =       10,
3926         .mgr_height_start       =       26,
3927         .mgr_width_max          =       2048,
3928         .mgr_height_max         =       2048,
3929         .max_lcd_pclk           =       173000000,
3930         .max_tv_pclk            =       59000000,
3931         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3932         .calc_core_clk          =       calc_core_clk_34xx,
3933         .num_fifos              =       3,
3934         .no_framedone_tv        =       true,
3935         .set_max_preload        =       false,
3936         .last_pixel_inc_missing =       true,
3937 };
3938
3939 static const struct dispc_features omap44xx_dispc_feats = {
3940         .sw_start               =       7,
3941         .fp_start               =       19,
3942         .bp_start               =       31,
3943         .sw_max                 =       256,
3944         .vp_max                 =       4095,
3945         .hp_max                 =       4096,
3946         .mgr_width_start        =       10,
3947         .mgr_height_start       =       26,
3948         .mgr_width_max          =       2048,
3949         .mgr_height_max         =       2048,
3950         .max_lcd_pclk           =       170000000,
3951         .max_tv_pclk            =       185625000,
3952         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3953         .calc_core_clk          =       calc_core_clk_44xx,
3954         .num_fifos              =       5,
3955         .gfx_fifo_workaround    =       true,
3956         .set_max_preload        =       true,
3957         .supports_sync_align    =       true,
3958         .has_writeback          =       true,
3959 };
3960
3961 static const struct dispc_features omap54xx_dispc_feats = {
3962         .sw_start               =       7,
3963         .fp_start               =       19,
3964         .bp_start               =       31,
3965         .sw_max                 =       256,
3966         .vp_max                 =       4095,
3967         .hp_max                 =       4096,
3968         .mgr_width_start        =       11,
3969         .mgr_height_start       =       27,
3970         .mgr_width_max          =       4096,
3971         .mgr_height_max         =       4096,
3972         .max_lcd_pclk           =       170000000,
3973         .max_tv_pclk            =       186000000,
3974         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3975         .calc_core_clk          =       calc_core_clk_44xx,
3976         .num_fifos              =       5,
3977         .gfx_fifo_workaround    =       true,
3978         .mstandby_workaround    =       true,
3979         .set_max_preload        =       true,
3980         .supports_sync_align    =       true,
3981         .has_writeback          =       true,
3982 };
3983
3984 static const struct dispc_features *dispc_get_features(void)
3985 {
3986         switch (omapdss_get_version()) {
3987         case OMAPDSS_VER_OMAP24xx:
3988                 return &omap24xx_dispc_feats;
3989
3990         case OMAPDSS_VER_OMAP34xx_ES1:
3991                 return &omap34xx_rev1_0_dispc_feats;
3992
3993         case OMAPDSS_VER_OMAP34xx_ES3:
3994         case OMAPDSS_VER_OMAP3630:
3995         case OMAPDSS_VER_AM35xx:
3996         case OMAPDSS_VER_AM43xx:
3997                 return &omap34xx_rev3_0_dispc_feats;
3998
3999         case OMAPDSS_VER_OMAP4430_ES1:
4000         case OMAPDSS_VER_OMAP4430_ES2:
4001         case OMAPDSS_VER_OMAP4:
4002                 return &omap44xx_dispc_feats;
4003
4004         case OMAPDSS_VER_OMAP5:
4005         case OMAPDSS_VER_DRA7xx:
4006                 return &omap54xx_dispc_feats;
4007
4008         default:
4009                 return NULL;
4010         }
4011 }
4012
4013 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4014 {
4015         if (!dispc.is_enabled)
4016                 return IRQ_NONE;
4017
4018         return dispc.user_handler(irq, dispc.user_data);
4019 }
4020
4021 int dispc_request_irq(irq_handler_t handler, void *dev_id)
4022 {
4023         int r;
4024
4025         if (dispc.user_handler != NULL)
4026                 return -EBUSY;
4027
4028         dispc.user_handler = handler;
4029         dispc.user_data = dev_id;
4030
4031         /* ensure the dispc_irq_handler sees the values above */
4032         smp_wmb();
4033
4034         r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4035                              IRQF_SHARED, "OMAP DISPC", &dispc);
4036         if (r) {
4037                 dispc.user_handler = NULL;
4038                 dispc.user_data = NULL;
4039         }
4040
4041         return r;
4042 }
4043 EXPORT_SYMBOL(dispc_request_irq);
4044
4045 void dispc_free_irq(void *dev_id)
4046 {
4047         devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4048
4049         dispc.user_handler = NULL;
4050         dispc.user_data = NULL;
4051 }
4052 EXPORT_SYMBOL(dispc_free_irq);
4053
4054 /* DISPC HW IP initialisation */
4055 static int dispc_bind(struct device *dev, struct device *master, void *data)
4056 {
4057         struct platform_device *pdev = to_platform_device(dev);
4058         u32 rev;
4059         int r = 0;
4060         struct resource *dispc_mem;
4061         struct device_node *np = pdev->dev.of_node;
4062
4063         dispc.pdev = pdev;
4064
4065         spin_lock_init(&dispc.control_lock);
4066
4067         dispc.feat = dispc_get_features();
4068         if (!dispc.feat)
4069                 return -ENODEV;
4070
4071         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4072         if (!dispc_mem) {
4073                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4074                 return -EINVAL;
4075         }
4076
4077         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4078                                   resource_size(dispc_mem));
4079         if (!dispc.base) {
4080                 DSSERR("can't ioremap DISPC\n");
4081                 return -ENOMEM;
4082         }
4083
4084         dispc.irq = platform_get_irq(dispc.pdev, 0);
4085         if (dispc.irq < 0) {
4086                 DSSERR("platform_get_irq failed\n");
4087                 return -ENODEV;
4088         }
4089
4090         if (np && of_property_read_bool(np, "syscon-pol")) {
4091                 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4092                 if (IS_ERR(dispc.syscon_pol)) {
4093                         dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4094                         return PTR_ERR(dispc.syscon_pol);
4095                 }
4096
4097                 if (of_property_read_u32_index(np, "syscon-pol", 1,
4098                                 &dispc.syscon_pol_offset)) {
4099                         dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4100                         return -EINVAL;
4101                 }
4102         }
4103
4104         pm_runtime_enable(&pdev->dev);
4105
4106         r = dispc_runtime_get();
4107         if (r)
4108                 goto err_runtime_get;
4109
4110         _omap_dispc_initial_config();
4111
4112         rev = dispc_read_reg(DISPC_REVISION);
4113         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4114                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4115
4116         dispc_runtime_put();
4117
4118         dss_init_overlay_managers();
4119
4120         dss_debugfs_create_file("dispc", dispc_dump_regs);
4121
4122         return 0;
4123
4124 err_runtime_get:
4125         pm_runtime_disable(&pdev->dev);
4126         return r;
4127 }
4128
4129 static void dispc_unbind(struct device *dev, struct device *master,
4130                                void *data)
4131 {
4132         pm_runtime_disable(dev);
4133
4134         dss_uninit_overlay_managers();
4135 }
4136
4137 static const struct component_ops dispc_component_ops = {
4138         .bind   = dispc_bind,
4139         .unbind = dispc_unbind,
4140 };
4141
4142 static int dispc_probe(struct platform_device *pdev)
4143 {
4144         return component_add(&pdev->dev, &dispc_component_ops);
4145 }
4146
4147 static int dispc_remove(struct platform_device *pdev)
4148 {
4149         component_del(&pdev->dev, &dispc_component_ops);
4150         return 0;
4151 }
4152
4153 static int dispc_runtime_suspend(struct device *dev)
4154 {
4155         dispc.is_enabled = false;
4156         /* ensure the dispc_irq_handler sees the is_enabled value */
4157         smp_wmb();
4158         /* wait for current handler to finish before turning the DISPC off */
4159         synchronize_irq(dispc.irq);
4160
4161         dispc_save_context();
4162
4163         return 0;
4164 }
4165
4166 static int dispc_runtime_resume(struct device *dev)
4167 {
4168         /*
4169          * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4170          * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4171          * _omap_dispc_initial_config(). We can thus use it to detect if
4172          * we have lost register context.
4173          */
4174         if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4175                 _omap_dispc_initial_config();
4176
4177                 dispc_restore_context();
4178         }
4179
4180         dispc.is_enabled = true;
4181         /* ensure the dispc_irq_handler sees the is_enabled value */
4182         smp_wmb();
4183
4184         return 0;
4185 }
4186
4187 static const struct dev_pm_ops dispc_pm_ops = {
4188         .runtime_suspend = dispc_runtime_suspend,
4189         .runtime_resume = dispc_runtime_resume,
4190 };
4191
4192 static const struct of_device_id dispc_of_match[] = {
4193         { .compatible = "ti,omap2-dispc", },
4194         { .compatible = "ti,omap3-dispc", },
4195         { .compatible = "ti,omap4-dispc", },
4196         { .compatible = "ti,omap5-dispc", },
4197         { .compatible = "ti,dra7-dispc", },
4198         {},
4199 };
4200
4201 static struct platform_driver omap_dispchw_driver = {
4202         .probe          = dispc_probe,
4203         .remove         = dispc_remove,
4204         .driver         = {
4205                 .name   = "omapdss_dispc",
4206                 .pm     = &dispc_pm_ops,
4207                 .of_match_table = dispc_of_match,
4208                 .suppress_bind_attrs = true,
4209         },
4210 };
4211
4212 int __init dispc_init_platform_driver(void)
4213 {
4214         return platform_driver_register(&omap_dispchw_driver);
4215 }
4216
4217 void dispc_uninit_platform_driver(void)
4218 {
4219         platform_driver_unregister(&omap_dispchw_driver);
4220 }