2 * smscufx.c -- Framebuffer driver for SMSC UFX USB controller
4 * Copyright (C) 2011 Steve Glendinning <steve.glendinning@shawell.net>
5 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
6 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
7 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License v2. See the file COPYING in the main directory of this archive for
13 * Based on udlfb, with work from Florian Echtler, Henrik Bjerregaard Pedersen,
16 * Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev
17 * available from http://git.plugable.com
19 * Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven,
20 * usb-skeleton by GregKH.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/usb.h>
29 #include <linux/uaccess.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/delay.h>
37 #define check_warn(status, fmt, args...) \
38 ({ if (status < 0) pr_warn(fmt, ##args); })
40 #define check_warn_return(status, fmt, args...) \
41 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
43 #define check_warn_goto_error(status, fmt, args...) \
44 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
46 #define all_bits_set(x, bits) (((x) & (bits)) == (bits))
48 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
49 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
52 * TODO: Propose standard fb.h ioctl for reporting damage,
53 * using _IOWR() and one of the existing area structs from fb.h
54 * Consider these ioctls deprecated, but they're still used by the
55 * DisplayLink X server as yet - need both to be modified in tandem
56 * when new ioctl(s) are ready.
58 #define UFX_IOCTL_RETURN_EDID (0xAD)
59 #define UFX_IOCTL_REPORT_DAMAGE (0xAA)
61 /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
62 #define BULK_SIZE (512)
63 #define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE)
64 #define WRITES_IN_FLIGHT (4)
66 #define GET_URB_TIMEOUT (HZ)
67 #define FREE_URB_TIMEOUT (HZ*2)
71 #define UFX_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */
72 #define UFX_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */
80 struct list_head entry;
82 struct delayed_work release_urb_work;
87 struct list_head list;
89 struct semaphore limit_sem;
96 struct usb_device *udev;
97 struct device *gdev; /* &udev->dev */
102 bool virtualized; /* true when physical usb device not present */
103 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
104 atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */
105 u8 *edid; /* null until we read edid from hw or get from sysfs */
107 u32 pseudo_palette[256];
110 static struct fb_fix_screeninfo ufx_fix = {
112 .type = FB_TYPE_PACKED_PIXELS,
113 .visual = FB_VISUAL_TRUECOLOR,
117 .accel = FB_ACCEL_NONE,
120 static const u32 smscufx_info_flags = FBINFO_DEFAULT | FBINFO_READS_FAST |
121 FBINFO_VIRTFB | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT |
122 FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR;
124 static struct usb_device_id id_table[] = {
125 {USB_DEVICE(0x0424, 0x9d00),},
126 {USB_DEVICE(0x0424, 0x9d01),},
129 MODULE_DEVICE_TABLE(usb, id_table);
132 static bool console; /* Optionally allow fbcon to consume first framebuffer */
133 static bool fb_defio = true; /* Optionally enable fb_defio mmap support */
135 /* ufx keeps a list of urbs for efficient bulk transfers */
136 static void ufx_urb_completion(struct urb *urb);
137 static struct urb *ufx_get_urb(struct ufx_data *dev);
138 static int ufx_submit_urb(struct ufx_data *dev, struct urb * urb, size_t len);
139 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size);
140 static void ufx_free_urb_list(struct ufx_data *dev);
142 static DEFINE_MUTEX(disconnect_mutex);
144 /* reads a control register */
145 static int ufx_reg_read(struct ufx_data *dev, u32 index, u32 *data)
147 u32 *buf = kmalloc(4, GFP_KERNEL);
155 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
156 USB_VENDOR_REQUEST_READ_REGISTER,
157 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
158 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
164 if (unlikely(ret < 0))
165 pr_warn("Failed to read register index 0x%08x\n", index);
170 /* writes a control register */
171 static int ufx_reg_write(struct ufx_data *dev, u32 index, u32 data)
173 u32 *buf = kmalloc(4, GFP_KERNEL);
184 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
185 USB_VENDOR_REQUEST_WRITE_REGISTER,
186 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
187 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
191 if (unlikely(ret < 0))
192 pr_warn("Failed to write register index 0x%08x with value "
193 "0x%08x\n", index, data);
198 static int ufx_reg_clear_and_set_bits(struct ufx_data *dev, u32 index,
199 u32 bits_to_clear, u32 bits_to_set)
202 int status = ufx_reg_read(dev, index, &data);
203 check_warn_return(status, "ufx_reg_clear_and_set_bits error reading "
206 data &= (~bits_to_clear);
209 status = ufx_reg_write(dev, index, data);
210 check_warn_return(status, "ufx_reg_clear_and_set_bits error writing "
216 static int ufx_reg_set_bits(struct ufx_data *dev, u32 index, u32 bits)
218 return ufx_reg_clear_and_set_bits(dev, index, 0, bits);
221 static int ufx_reg_clear_bits(struct ufx_data *dev, u32 index, u32 bits)
223 return ufx_reg_clear_and_set_bits(dev, index, bits, 0);
226 static int ufx_lite_reset(struct ufx_data *dev)
231 status = ufx_reg_write(dev, 0x3008, 0x00000001);
232 check_warn_return(status, "ufx_lite_reset error writing 0x3008");
234 status = ufx_reg_read(dev, 0x3008, &value);
235 check_warn_return(status, "ufx_lite_reset error reading 0x3008");
237 return (value == 0) ? 0 : -EIO;
240 /* If display is unblanked, then blank it */
241 static int ufx_blank(struct ufx_data *dev, bool wait)
246 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
247 check_warn_return(status, "ufx_blank error reading 0x2004");
249 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
250 check_warn_return(status, "ufx_blank error reading 0x2000");
252 /* return success if display is already blanked */
253 if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100))
256 /* request the DC to blank the display */
257 dc_ctrl |= 0x00000100;
258 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
259 check_warn_return(status, "ufx_blank error writing 0x2000");
261 /* return success immediately if we don't have to wait */
265 for (i = 0; i < 250; i++) {
266 status = ufx_reg_read(dev, 0x2004, &dc_sts);
267 check_warn_return(status, "ufx_blank error reading 0x2004");
269 if (dc_sts & 0x00000100)
273 /* timed out waiting for display to blank */
277 /* If display is blanked, then unblank it */
278 static int ufx_unblank(struct ufx_data *dev, bool wait)
283 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
284 check_warn_return(status, "ufx_unblank error reading 0x2004");
286 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
287 check_warn_return(status, "ufx_unblank error reading 0x2000");
289 /* return success if display is already unblanked */
290 if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0))
293 /* request the DC to unblank the display */
294 dc_ctrl &= ~0x00000100;
295 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
296 check_warn_return(status, "ufx_unblank error writing 0x2000");
298 /* return success immediately if we don't have to wait */
302 for (i = 0; i < 250; i++) {
303 status = ufx_reg_read(dev, 0x2004, &dc_sts);
304 check_warn_return(status, "ufx_unblank error reading 0x2004");
306 if ((dc_sts & 0x00000100) == 0)
310 /* timed out waiting for display to unblank */
314 /* If display is enabled, then disable it */
315 static int ufx_disable(struct ufx_data *dev, bool wait)
320 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
321 check_warn_return(status, "ufx_disable error reading 0x2004");
323 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
324 check_warn_return(status, "ufx_disable error reading 0x2000");
326 /* return success if display is already disabled */
327 if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0))
330 /* request the DC to disable the display */
331 dc_ctrl &= ~(0x00000001);
332 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
333 check_warn_return(status, "ufx_disable error writing 0x2000");
335 /* return success immediately if we don't have to wait */
339 for (i = 0; i < 250; i++) {
340 status = ufx_reg_read(dev, 0x2004, &dc_sts);
341 check_warn_return(status, "ufx_disable error reading 0x2004");
343 if ((dc_sts & 0x00000001) == 0)
347 /* timed out waiting for display to disable */
351 /* If display is disabled, then enable it */
352 static int ufx_enable(struct ufx_data *dev, bool wait)
357 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
358 check_warn_return(status, "ufx_enable error reading 0x2004");
360 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
361 check_warn_return(status, "ufx_enable error reading 0x2000");
363 /* return success if display is already enabled */
364 if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001))
367 /* request the DC to enable the display */
368 dc_ctrl |= 0x00000001;
369 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
370 check_warn_return(status, "ufx_enable error writing 0x2000");
372 /* return success immediately if we don't have to wait */
376 for (i = 0; i < 250; i++) {
377 status = ufx_reg_read(dev, 0x2004, &dc_sts);
378 check_warn_return(status, "ufx_enable error reading 0x2004");
380 if (dc_sts & 0x00000001)
384 /* timed out waiting for display to enable */
388 static int ufx_config_sys_clk(struct ufx_data *dev)
390 int status = ufx_reg_write(dev, 0x700C, 0x8000000F);
391 check_warn_return(status, "error writing 0x700C");
393 status = ufx_reg_write(dev, 0x7014, 0x0010024F);
394 check_warn_return(status, "error writing 0x7014");
396 status = ufx_reg_write(dev, 0x7010, 0x00000000);
397 check_warn_return(status, "error writing 0x7010");
399 status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A);
400 check_warn_return(status, "error clearing PLL1 bypass in 0x700C");
403 status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000);
404 check_warn_return(status, "error clearing output gate in 0x700C");
409 static int ufx_config_ddr2(struct ufx_data *dev)
414 status = ufx_reg_write(dev, 0x0004, 0x001F0F77);
415 check_warn_return(status, "error writing 0x0004");
417 status = ufx_reg_write(dev, 0x0008, 0xFFF00000);
418 check_warn_return(status, "error writing 0x0008");
420 status = ufx_reg_write(dev, 0x000C, 0x0FFF2222);
421 check_warn_return(status, "error writing 0x000C");
423 status = ufx_reg_write(dev, 0x0010, 0x00030814);
424 check_warn_return(status, "error writing 0x0010");
426 status = ufx_reg_write(dev, 0x0014, 0x00500019);
427 check_warn_return(status, "error writing 0x0014");
429 status = ufx_reg_write(dev, 0x0018, 0x020D0F15);
430 check_warn_return(status, "error writing 0x0018");
432 status = ufx_reg_write(dev, 0x001C, 0x02532305);
433 check_warn_return(status, "error writing 0x001C");
435 status = ufx_reg_write(dev, 0x0020, 0x0B030905);
436 check_warn_return(status, "error writing 0x0020");
438 status = ufx_reg_write(dev, 0x0024, 0x00000827);
439 check_warn_return(status, "error writing 0x0024");
441 status = ufx_reg_write(dev, 0x0028, 0x00000000);
442 check_warn_return(status, "error writing 0x0028");
444 status = ufx_reg_write(dev, 0x002C, 0x00000042);
445 check_warn_return(status, "error writing 0x002C");
447 status = ufx_reg_write(dev, 0x0030, 0x09520000);
448 check_warn_return(status, "error writing 0x0030");
450 status = ufx_reg_write(dev, 0x0034, 0x02223314);
451 check_warn_return(status, "error writing 0x0034");
453 status = ufx_reg_write(dev, 0x0038, 0x00430043);
454 check_warn_return(status, "error writing 0x0038");
456 status = ufx_reg_write(dev, 0x003C, 0xF00F000F);
457 check_warn_return(status, "error writing 0x003C");
459 status = ufx_reg_write(dev, 0x0040, 0xF380F00F);
460 check_warn_return(status, "error writing 0x0040");
462 status = ufx_reg_write(dev, 0x0044, 0xF00F0496);
463 check_warn_return(status, "error writing 0x0044");
465 status = ufx_reg_write(dev, 0x0048, 0x03080406);
466 check_warn_return(status, "error writing 0x0048");
468 status = ufx_reg_write(dev, 0x004C, 0x00001000);
469 check_warn_return(status, "error writing 0x004C");
471 status = ufx_reg_write(dev, 0x005C, 0x00000007);
472 check_warn_return(status, "error writing 0x005C");
474 status = ufx_reg_write(dev, 0x0100, 0x54F00012);
475 check_warn_return(status, "error writing 0x0100");
477 status = ufx_reg_write(dev, 0x0104, 0x00004012);
478 check_warn_return(status, "error writing 0x0104");
480 status = ufx_reg_write(dev, 0x0118, 0x40404040);
481 check_warn_return(status, "error writing 0x0118");
483 status = ufx_reg_write(dev, 0x0000, 0x00000001);
484 check_warn_return(status, "error writing 0x0000");
487 status = ufx_reg_read(dev, 0x0000, &tmp);
488 check_warn_return(status, "error reading 0x0000");
490 if (all_bits_set(tmp, 0xC0000000))
494 pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp);
509 static u32 ufx_calc_range(u32 ref_freq)
511 if (ref_freq >= 88000000)
514 if (ref_freq >= 54000000)
517 if (ref_freq >= 34000000)
520 if (ref_freq >= 21000000)
523 if (ref_freq >= 13000000)
526 if (ref_freq >= 8000000)
532 /* calculates PLL divider settings for a desired target frequency */
533 static void ufx_calc_pll_values(const u32 clk_pixel_pll, struct pll_values *asic_pll)
535 const u32 ref_clk = 25000000;
536 u32 div_r0, div_f0, div_q0, div_r1, div_f1, div_q1;
537 u32 min_error = clk_pixel_pll;
539 for (div_r0 = 1; div_r0 <= 32; div_r0++) {
540 u32 ref_freq0 = ref_clk / div_r0;
541 if (ref_freq0 < 5000000)
544 if (ref_freq0 > 200000000)
547 for (div_f0 = 1; div_f0 <= 256; div_f0++) {
548 u32 vco_freq0 = ref_freq0 * div_f0;
550 if (vco_freq0 < 350000000)
553 if (vco_freq0 > 700000000)
556 for (div_q0 = 0; div_q0 < 7; div_q0++) {
557 u32 pllout_freq0 = vco_freq0 / (1 << div_q0);
559 if (pllout_freq0 < 5000000)
562 if (pllout_freq0 > 200000000)
565 for (div_r1 = 1; div_r1 <= 32; div_r1++) {
566 u32 ref_freq1 = pllout_freq0 / div_r1;
568 if (ref_freq1 < 5000000)
571 for (div_f1 = 1; div_f1 <= 256; div_f1++) {
572 u32 vco_freq1 = ref_freq1 * div_f1;
574 if (vco_freq1 < 350000000)
577 if (vco_freq1 > 700000000)
580 for (div_q1 = 0; div_q1 < 7; div_q1++) {
581 u32 pllout_freq1 = vco_freq1 / (1 << div_q1);
582 int error = abs(pllout_freq1 - clk_pixel_pll);
584 if (pllout_freq1 < 5000000)
587 if (pllout_freq1 > 700000000)
590 if (error < min_error) {
593 /* final returned value is equal to calculated value - 1
594 * because a value of 0 = divide by 1 */
595 asic_pll->div_r0 = div_r0 - 1;
596 asic_pll->div_f0 = div_f0 - 1;
597 asic_pll->div_q0 = div_q0;
598 asic_pll->div_r1 = div_r1 - 1;
599 asic_pll->div_f1 = div_f1 - 1;
600 asic_pll->div_q1 = div_q1;
602 asic_pll->range0 = ufx_calc_range(ref_freq0);
603 asic_pll->range1 = ufx_calc_range(ref_freq1);
616 /* sets analog bit PLL configuration values */
617 static int ufx_config_pix_clk(struct ufx_data *dev, u32 pixclock)
619 struct pll_values asic_pll = {0};
620 u32 value, clk_pixel, clk_pixel_pll;
623 /* convert pixclock (in ps) to frequency (in Hz) */
624 clk_pixel = PICOS2KHZ(pixclock) * 1000;
625 pr_debug("pixclock %d ps = clk_pixel %d Hz", pixclock, clk_pixel);
627 /* clk_pixel = 1/2 clk_pixel_pll */
628 clk_pixel_pll = clk_pixel * 2;
630 ufx_calc_pll_values(clk_pixel_pll, &asic_pll);
632 /* Keep BYPASS and RESET signals asserted until configured */
633 status = ufx_reg_write(dev, 0x7000, 0x8000000F);
634 check_warn_return(status, "error writing 0x7000");
636 value = (asic_pll.div_f1 | (asic_pll.div_r1 << 8) |
637 (asic_pll.div_q1 << 16) | (asic_pll.range1 << 20));
638 status = ufx_reg_write(dev, 0x7008, value);
639 check_warn_return(status, "error writing 0x7008");
641 value = (asic_pll.div_f0 | (asic_pll.div_r0 << 8) |
642 (asic_pll.div_q0 << 16) | (asic_pll.range0 << 20));
643 status = ufx_reg_write(dev, 0x7004, value);
644 check_warn_return(status, "error writing 0x7004");
646 status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005);
647 check_warn_return(status,
648 "error clearing PLL0 bypass bits in 0x7000");
651 status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A);
652 check_warn_return(status,
653 "error clearing PLL1 bypass bits in 0x7000");
656 status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000);
657 check_warn_return(status, "error clearing gate bits in 0x7000");
662 static int ufx_set_vid_mode(struct ufx_data *dev, struct fb_var_screeninfo *var)
665 u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end;
666 u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end;
668 int status = ufx_reg_write(dev, 0x8028, 0);
669 check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad");
671 status = ufx_reg_write(dev, 0x8024, 0);
672 check_warn_return(status, "ufx_set_vid_mode error disabling VDAC");
674 /* shut everything down before changing timing */
675 status = ufx_blank(dev, true);
676 check_warn_return(status, "ufx_set_vid_mode error blanking display");
678 status = ufx_disable(dev, true);
679 check_warn_return(status, "ufx_set_vid_mode error disabling display");
681 status = ufx_config_pix_clk(dev, var->pixclock);
682 check_warn_return(status, "ufx_set_vid_mode error configuring pixclock");
684 status = ufx_reg_write(dev, 0x2000, 0x00000104);
685 check_warn_return(status, "ufx_set_vid_mode error writing 0x2000");
687 /* set horizontal timings */
688 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
689 h_active = var->xres;
690 h_blank_start = var->xres + var->right_margin;
691 h_blank_end = var->xres + var->right_margin + var->hsync_len;
692 h_sync_start = var->xres + var->right_margin;
693 h_sync_end = var->xres + var->right_margin + var->hsync_len;
695 temp = ((h_total - 1) << 16) | (h_active - 1);
696 status = ufx_reg_write(dev, 0x2008, temp);
697 check_warn_return(status, "ufx_set_vid_mode error writing 0x2008");
699 temp = ((h_blank_start - 1) << 16) | (h_blank_end - 1);
700 status = ufx_reg_write(dev, 0x200C, temp);
701 check_warn_return(status, "ufx_set_vid_mode error writing 0x200C");
703 temp = ((h_sync_start - 1) << 16) | (h_sync_end - 1);
704 status = ufx_reg_write(dev, 0x2010, temp);
705 check_warn_return(status, "ufx_set_vid_mode error writing 0x2010");
707 /* set vertical timings */
708 v_total = var->upper_margin + var->yres + var->lower_margin + var->vsync_len;
709 v_active = var->yres;
710 v_blank_start = var->yres + var->lower_margin;
711 v_blank_end = var->yres + var->lower_margin + var->vsync_len;
712 v_sync_start = var->yres + var->lower_margin;
713 v_sync_end = var->yres + var->lower_margin + var->vsync_len;
715 temp = ((v_total - 1) << 16) | (v_active - 1);
716 status = ufx_reg_write(dev, 0x2014, temp);
717 check_warn_return(status, "ufx_set_vid_mode error writing 0x2014");
719 temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1);
720 status = ufx_reg_write(dev, 0x2018, temp);
721 check_warn_return(status, "ufx_set_vid_mode error writing 0x2018");
723 temp = ((v_sync_start - 1) << 16) | (v_sync_end - 1);
724 status = ufx_reg_write(dev, 0x201C, temp);
725 check_warn_return(status, "ufx_set_vid_mode error writing 0x201C");
727 status = ufx_reg_write(dev, 0x2020, 0x00000000);
728 check_warn_return(status, "ufx_set_vid_mode error writing 0x2020");
730 status = ufx_reg_write(dev, 0x2024, 0x00000000);
731 check_warn_return(status, "ufx_set_vid_mode error writing 0x2024");
733 /* Set the frame length register (#pix * 2 bytes/pixel) */
734 temp = var->xres * var->yres * 2;
735 temp = (temp + 7) & (~0x7);
736 status = ufx_reg_write(dev, 0x2028, temp);
737 check_warn_return(status, "ufx_set_vid_mode error writing 0x2028");
739 /* enable desired output interface & disable others */
740 status = ufx_reg_write(dev, 0x2040, 0);
741 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
743 status = ufx_reg_write(dev, 0x2044, 0);
744 check_warn_return(status, "ufx_set_vid_mode error writing 0x2044");
746 status = ufx_reg_write(dev, 0x2048, 0);
747 check_warn_return(status, "ufx_set_vid_mode error writing 0x2048");
749 /* set the sync polarities & enable bit */
751 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
754 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
757 status = ufx_reg_write(dev, 0x2040, temp);
758 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
760 /* start everything back up */
761 status = ufx_enable(dev, true);
762 check_warn_return(status, "ufx_set_vid_mode error enabling display");
764 /* Unblank the display */
765 status = ufx_unblank(dev, true);
766 check_warn_return(status, "ufx_set_vid_mode error unblanking display");
769 status = ufx_reg_write(dev, 0x8028, 0x00000003);
770 check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad");
773 status = ufx_reg_write(dev, 0x8024, 0x00000007);
774 check_warn_return(status, "ufx_set_vid_mode error enabling VDAC");
779 static int ufx_ops_mmap(struct fb_info *info, struct vm_area_struct *vma)
781 unsigned long start = vma->vm_start;
782 unsigned long size = vma->vm_end - vma->vm_start;
783 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
784 unsigned long page, pos;
786 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
788 if (size > info->fix.smem_len)
790 if (offset > info->fix.smem_len - size)
793 pos = (unsigned long)info->fix.smem_start + offset;
795 pr_debug("mmap() framebuffer addr:%lu size:%lu\n",
799 page = vmalloc_to_pfn((void *)pos);
800 if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED))
805 if (size > PAGE_SIZE)
814 static void ufx_raw_rect(struct ufx_data *dev, u16 *cmd, int x, int y,
815 int width, int height)
817 size_t packed_line_len = ALIGN((width * 2), 4);
818 size_t packed_rect_len = packed_line_len * height;
825 *((u32 *)&cmd[0]) = cpu_to_le32(0x01);
828 *((u32 *)&cmd[2]) = cpu_to_le32(packed_rect_len + 16);
830 cmd[4] = cpu_to_le16(x);
831 cmd[5] = cpu_to_le16(y);
832 cmd[6] = cpu_to_le16(width);
833 cmd[7] = cpu_to_le16(height);
835 /* frame base address */
836 *((u32 *)&cmd[8]) = cpu_to_le32(0);
838 /* color mode and horizontal resolution */
839 cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres);
841 /* vertical resolution */
842 cmd[11] = cpu_to_le16(dev->info->var.yres);
845 for (line = 0; line < height; line++) {
846 const int line_offset = dev->info->fix.line_length * (y + line);
847 const int byte_offset = line_offset + (x * BPP);
848 memcpy(&cmd[(24 + (packed_line_len * line)) / 2],
849 (char *)dev->info->fix.smem_start + byte_offset, width * BPP);
853 static int ufx_handle_damage(struct ufx_data *dev, int x, int y,
854 int width, int height)
856 size_t packed_line_len = ALIGN((width * 2), 4);
857 int len, status, urb_lines, start_line = 0;
859 if ((width <= 0) || (height <= 0) ||
860 (x + width > dev->info->var.xres) ||
861 (y + height > dev->info->var.yres))
864 if (!atomic_read(&dev->usb_active))
867 while (start_line < height) {
868 struct urb *urb = ufx_get_urb(dev);
870 pr_warn("ufx_handle_damage unable to get urb");
874 /* assume we have enough space to transfer at least one line */
875 BUG_ON(urb->transfer_buffer_length < (24 + (width * 2)));
877 /* calculate the maximum number of lines we could fit in */
878 urb_lines = (urb->transfer_buffer_length - 24) / packed_line_len;
880 /* but we might not need this many */
881 urb_lines = min(urb_lines, (height - start_line));
883 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length);
885 ufx_raw_rect(dev, urb->transfer_buffer, x, (y + start_line), width, urb_lines);
886 len = 24 + (packed_line_len * urb_lines);
888 status = ufx_submit_urb(dev, urb, len);
889 check_warn_return(status, "Error submitting URB");
891 start_line += urb_lines;
897 /* Path triggered by usermode clients who write to filesystem
898 * e.g. cat filename > /dev/fb1
899 * Not used by X Windows or text-mode console. But useful for testing.
900 * Slow because of extra copy and we must assume all pixels dirty. */
901 static ssize_t ufx_ops_write(struct fb_info *info, const char __user *buf,
902 size_t count, loff_t *ppos)
905 struct ufx_data *dev = info->par;
906 u32 offset = (u32) *ppos;
908 result = fb_sys_write(info, buf, count, ppos);
911 int start = max((int)(offset / info->fix.line_length), 0);
912 int lines = min((u32)((result / info->fix.line_length) + 1),
913 (u32)info->var.yres);
915 ufx_handle_damage(dev, 0, start, info->var.xres, lines);
921 static void ufx_ops_copyarea(struct fb_info *info,
922 const struct fb_copyarea *area)
925 struct ufx_data *dev = info->par;
927 sys_copyarea(info, area);
929 ufx_handle_damage(dev, area->dx, area->dy,
930 area->width, area->height);
933 static void ufx_ops_imageblit(struct fb_info *info,
934 const struct fb_image *image)
936 struct ufx_data *dev = info->par;
938 sys_imageblit(info, image);
940 ufx_handle_damage(dev, image->dx, image->dy,
941 image->width, image->height);
944 static void ufx_ops_fillrect(struct fb_info *info,
945 const struct fb_fillrect *rect)
947 struct ufx_data *dev = info->par;
949 sys_fillrect(info, rect);
951 ufx_handle_damage(dev, rect->dx, rect->dy, rect->width,
955 /* NOTE: fb_defio.c is holding info->fbdefio.mutex
956 * Touching ANY framebuffer memory that triggers a page fault
957 * in fb_defio will cause a deadlock, when it also tries to
958 * grab the same mutex. */
959 static void ufx_dpy_deferred_io(struct fb_info *info,
960 struct list_head *pagelist)
963 struct fb_deferred_io *fbdefio = info->fbdefio;
964 struct ufx_data *dev = info->par;
969 if (!atomic_read(&dev->usb_active))
972 /* walk the written page list and render each to device */
973 list_for_each_entry(cur, &fbdefio->pagelist, lru) {
974 /* create a rectangle of full screen width that encloses the
975 * entire dirty framebuffer page */
977 const int width = dev->info->var.xres;
978 const int y = (cur->index << PAGE_SHIFT) / (width * 2);
979 int height = (PAGE_SIZE / (width * 2)) + 1;
980 height = min(height, (int)(dev->info->var.yres - y));
982 BUG_ON(y >= dev->info->var.yres);
983 BUG_ON((y + height) > dev->info->var.yres);
985 ufx_handle_damage(dev, x, y, width, height);
989 static int ufx_ops_ioctl(struct fb_info *info, unsigned int cmd,
992 struct ufx_data *dev = info->par;
993 struct dloarea *area = NULL;
995 if (!atomic_read(&dev->usb_active))
998 /* TODO: Update X server to get this from sysfs instead */
999 if (cmd == UFX_IOCTL_RETURN_EDID) {
1000 u8 __user *edid = (u8 __user *)arg;
1001 if (copy_to_user(edid, dev->edid, dev->edid_size))
1006 /* TODO: Help propose a standard fb.h ioctl to report mmap damage */
1007 if (cmd == UFX_IOCTL_REPORT_DAMAGE) {
1008 /* If we have a damage-aware client, turn fb_defio "off"
1009 * To avoid perf imact of unnecessary page fault handling.
1010 * Done by resetting the delay for this fb_info to a very
1011 * long period. Pages will become writable and stay that way.
1012 * Reset to normal value when all clients have closed this fb.
1015 info->fbdefio->delay = UFX_DEFIO_WRITE_DISABLE;
1017 area = (struct dloarea *)arg;
1022 if (area->x > info->var.xres)
1023 area->x = info->var.xres;
1028 if (area->y > info->var.yres)
1029 area->y = info->var.yres;
1031 ufx_handle_damage(dev, area->x, area->y, area->w, area->h);
1037 /* taken from vesafb */
1039 ufx_ops_setcolreg(unsigned regno, unsigned red, unsigned green,
1040 unsigned blue, unsigned transp, struct fb_info *info)
1044 if (regno >= info->cmap.len)
1048 if (info->var.red.offset == 10) {
1050 ((u32 *) (info->pseudo_palette))[regno] =
1051 ((red & 0xf800) >> 1) |
1052 ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11);
1055 ((u32 *) (info->pseudo_palette))[regno] =
1057 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
1064 /* It's common for several clients to have framebuffer open simultaneously.
1065 * e.g. both fbcon and X. Makes things interesting.
1066 * Assumes caller is holding info->lock (for open and release at least) */
1067 static int ufx_ops_open(struct fb_info *info, int user)
1069 struct ufx_data *dev = info->par;
1071 /* fbcon aggressively connects to first framebuffer it finds,
1072 * preventing other clients (X) from working properly. Usually
1073 * not what the user wants. Fail by default with option to enable. */
1074 if (user == 0 && !console)
1077 mutex_lock(&disconnect_mutex);
1079 /* If the USB device is gone, we don't accept new opens */
1080 if (dev->virtualized) {
1081 mutex_unlock(&disconnect_mutex);
1087 kref_get(&dev->kref);
1089 if (fb_defio && (info->fbdefio == NULL)) {
1090 /* enable defio at last moment if not disabled by client */
1092 struct fb_deferred_io *fbdefio;
1094 fbdefio = kzalloc(sizeof(struct fb_deferred_io), GFP_KERNEL);
1097 fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
1098 fbdefio->deferred_io = ufx_dpy_deferred_io;
1101 info->fbdefio = fbdefio;
1102 fb_deferred_io_init(info);
1105 pr_debug("open /dev/fb%d user=%d fb_info=%p count=%d",
1106 info->node, user, info, dev->fb_count);
1108 mutex_unlock(&disconnect_mutex);
1114 * Called when all client interfaces to start transactions have been disabled,
1115 * and all references to our device instance (ufx_data) are released.
1116 * Every transaction must have a reference, so we know are fully spun down
1118 static void ufx_free(struct kref *kref)
1120 struct ufx_data *dev = container_of(kref, struct ufx_data, kref);
1125 static void ufx_ops_destory(struct fb_info *info)
1127 struct ufx_data *dev = info->par;
1128 int node = info->node;
1130 /* Assume info structure is freed after this point */
1131 framebuffer_release(info);
1133 pr_debug("fb_info for /dev/fb%d has been freed", node);
1135 /* release reference taken by kref_init in probe() */
1136 kref_put(&dev->kref, ufx_free);
1140 static void ufx_release_urb_work(struct work_struct *work)
1142 struct urb_node *unode = container_of(work, struct urb_node,
1143 release_urb_work.work);
1145 up(&unode->dev->urbs.limit_sem);
1148 static void ufx_free_framebuffer(struct ufx_data *dev)
1150 struct fb_info *info = dev->info;
1152 if (info->cmap.len != 0)
1153 fb_dealloc_cmap(&info->cmap);
1154 if (info->monspecs.modedb)
1155 fb_destroy_modedb(info->monspecs.modedb);
1156 vfree(info->screen_base);
1158 fb_destroy_modelist(&info->modelist);
1162 /* ref taken in probe() as part of registering framebfufer */
1163 kref_put(&dev->kref, ufx_free);
1167 * Assumes caller is holding info->lock mutex (for open and release at least)
1169 static int ufx_ops_release(struct fb_info *info, int user)
1171 struct ufx_data *dev = info->par;
1173 mutex_lock(&disconnect_mutex);
1177 /* We can't free fb_info here - fbmem will touch it when we return */
1178 if (dev->virtualized && (dev->fb_count == 0))
1179 ufx_free_framebuffer(dev);
1181 if ((dev->fb_count == 0) && (info->fbdefio)) {
1182 fb_deferred_io_cleanup(info);
1183 kfree(info->fbdefio);
1184 info->fbdefio = NULL;
1185 info->fbops->fb_mmap = ufx_ops_mmap;
1188 pr_debug("released /dev/fb%d user=%d count=%d",
1189 info->node, user, dev->fb_count);
1191 kref_put(&dev->kref, ufx_free);
1193 mutex_unlock(&disconnect_mutex);
1198 /* Check whether a video mode is supported by the chip
1199 * We start from monitor's modes, so don't need to filter that here */
1200 static int ufx_is_valid_mode(struct fb_videomode *mode,
1201 struct fb_info *info)
1203 if ((mode->xres * mode->yres) > (2048 * 1152)) {
1204 pr_debug("%dx%d too many pixels",
1205 mode->xres, mode->yres);
1209 if (mode->pixclock < 5000) {
1210 pr_debug("%dx%d %dps pixel clock too fast",
1211 mode->xres, mode->yres, mode->pixclock);
1215 pr_debug("%dx%d (pixclk %dps %dMHz) valid mode", mode->xres, mode->yres,
1216 mode->pixclock, (1000000 / mode->pixclock));
1220 static void ufx_var_color_format(struct fb_var_screeninfo *var)
1222 const struct fb_bitfield red = { 11, 5, 0 };
1223 const struct fb_bitfield green = { 5, 6, 0 };
1224 const struct fb_bitfield blue = { 0, 5, 0 };
1226 var->bits_per_pixel = 16;
1232 static int ufx_ops_check_var(struct fb_var_screeninfo *var,
1233 struct fb_info *info)
1235 struct fb_videomode mode;
1237 /* TODO: support dynamically changing framebuffer size */
1238 if ((var->xres * var->yres * 2) > info->fix.smem_len)
1241 /* set device-specific elements of var unrelated to mode */
1242 ufx_var_color_format(var);
1244 fb_var_to_videomode(&mode, var);
1246 if (!ufx_is_valid_mode(&mode, info))
1252 static int ufx_ops_set_par(struct fb_info *info)
1254 struct ufx_data *dev = info->par;
1256 u16 *pix_framebuffer;
1259 pr_debug("set_par mode %dx%d", info->var.xres, info->var.yres);
1260 result = ufx_set_vid_mode(dev, &info->var);
1262 if ((result == 0) && (dev->fb_count == 0)) {
1263 /* paint greenscreen */
1264 pix_framebuffer = (u16 *) info->screen_base;
1265 for (i = 0; i < info->fix.smem_len / 2; i++)
1266 pix_framebuffer[i] = 0x37e6;
1268 ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres);
1271 /* re-enable defio if previously disabled by damage tracking */
1273 info->fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
1278 /* In order to come back from full DPMS off, we need to set the mode again */
1279 static int ufx_ops_blank(int blank_mode, struct fb_info *info)
1281 struct ufx_data *dev = info->par;
1282 ufx_set_vid_mode(dev, &info->var);
1286 static struct fb_ops ufx_ops = {
1287 .owner = THIS_MODULE,
1288 .fb_read = fb_sys_read,
1289 .fb_write = ufx_ops_write,
1290 .fb_setcolreg = ufx_ops_setcolreg,
1291 .fb_fillrect = ufx_ops_fillrect,
1292 .fb_copyarea = ufx_ops_copyarea,
1293 .fb_imageblit = ufx_ops_imageblit,
1294 .fb_mmap = ufx_ops_mmap,
1295 .fb_ioctl = ufx_ops_ioctl,
1296 .fb_open = ufx_ops_open,
1297 .fb_release = ufx_ops_release,
1298 .fb_blank = ufx_ops_blank,
1299 .fb_check_var = ufx_ops_check_var,
1300 .fb_set_par = ufx_ops_set_par,
1301 .fb_destroy = ufx_ops_destory,
1304 /* Assumes &info->lock held by caller
1305 * Assumes no active clients have framebuffer open */
1306 static int ufx_realloc_framebuffer(struct ufx_data *dev, struct fb_info *info)
1308 int retval = -ENOMEM;
1309 int old_len = info->fix.smem_len;
1311 unsigned char *old_fb = info->screen_base;
1312 unsigned char *new_fb;
1314 pr_debug("Reallocating framebuffer. Addresses will change!");
1316 new_len = info->fix.line_length * info->var.yres;
1318 if (PAGE_ALIGN(new_len) > old_len) {
1320 * Alloc system memory for virtual framebuffer
1322 new_fb = vmalloc(new_len);
1324 pr_err("Virtual framebuffer alloc failed");
1328 if (info->screen_base) {
1329 memcpy(new_fb, old_fb, old_len);
1330 vfree(info->screen_base);
1333 info->screen_base = new_fb;
1334 info->fix.smem_len = PAGE_ALIGN(new_len);
1335 info->fix.smem_start = (unsigned long) new_fb;
1336 info->flags = smscufx_info_flags;
1345 /* sets up I2C Controller for 100 Kbps, std. speed, 7-bit addr, master,
1346 * restart enabled, but no start byte, enable controller */
1347 static int ufx_i2c_init(struct ufx_data *dev)
1351 /* disable the controller before it can be reprogrammed */
1352 int status = ufx_reg_write(dev, 0x106C, 0x00);
1353 check_warn_return(status, "failed to disable I2C");
1355 /* Setup the clock count registers
1356 * (12+1) = 13 clks @ 2.5 MHz = 5.2 uS */
1357 status = ufx_reg_write(dev, 0x1018, 12);
1358 check_warn_return(status, "error writing 0x1018");
1360 /* (6+8) = 14 clks @ 2.5 MHz = 5.6 uS */
1361 status = ufx_reg_write(dev, 0x1014, 6);
1362 check_warn_return(status, "error writing 0x1014");
1364 status = ufx_reg_read(dev, 0x1000, &tmp);
1365 check_warn_return(status, "error reading 0x1000");
1367 /* set speed to std mode */
1371 /* 7-bit (not 10-bit) addressing */
1374 /* enable restart conditions and master mode */
1377 status = ufx_reg_write(dev, 0x1000, tmp);
1378 check_warn_return(status, "error writing 0x1000");
1380 /* Set normal tx using target address 0 */
1381 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000);
1382 check_warn_return(status, "error setting TX mode bits in 0x1004");
1384 /* Enable the controller */
1385 status = ufx_reg_write(dev, 0x106C, 0x01);
1386 check_warn_return(status, "failed to enable I2C");
1391 /* sets the I2C port mux and target address */
1392 static int ufx_i2c_configure(struct ufx_data *dev)
1394 int status = ufx_reg_write(dev, 0x106C, 0x00);
1395 check_warn_return(status, "failed to disable I2C");
1397 status = ufx_reg_write(dev, 0x3010, 0x00000000);
1398 check_warn_return(status, "failed to write 0x3010");
1400 /* A0h is std for any EDID, right shifted by one */
1401 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1));
1402 check_warn_return(status, "failed to set TAR bits in 0x1004");
1404 status = ufx_reg_write(dev, 0x106C, 0x01);
1405 check_warn_return(status, "failed to enable I2C");
1410 /* wait for BUSY to clear, with a timeout of 50ms with 10ms sleeps. if no
1411 * monitor is connected, there is no error except for timeout */
1412 static int ufx_i2c_wait_busy(struct ufx_data *dev)
1417 for (i = 0; i < 15; i++) {
1418 status = ufx_reg_read(dev, 0x1100, &tmp);
1419 check_warn_return(status, "0x1100 read failed");
1421 /* if BUSY is clear, check for error */
1422 if ((tmp & 0x80000000) == 0) {
1423 if (tmp & 0x20000000) {
1424 pr_warn("I2C read failed, 0x1100=0x%08x", tmp);
1431 /* perform the first 10 retries without delay */
1436 pr_warn("I2C access timed out, resetting I2C hardware");
1437 status = ufx_reg_write(dev, 0x1100, 0x40000000);
1438 check_warn_return(status, "0x1100 write failed");
1443 /* reads a 128-byte EDID block from the currently selected port and TAR */
1444 static int ufx_read_edid(struct ufx_data *dev, u8 *edid, int edid_len)
1447 u32 *edid_u32 = (u32 *)edid;
1449 BUG_ON(edid_len != EDID_LENGTH);
1451 status = ufx_i2c_configure(dev);
1453 pr_err("ufx_i2c_configure failed");
1457 memset(edid, 0xff, EDID_LENGTH);
1459 /* Read the 128-byte EDID as 2 bursts of 64 bytes */
1460 for (i = 0; i < 2; i++) {
1461 u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8);
1462 status = ufx_reg_write(dev, 0x1100, temp);
1463 check_warn_return(status, "Failed to write 0x1100");
1466 status = ufx_reg_write(dev, 0x1100, temp);
1467 check_warn_return(status, "Failed to write 0x1100");
1469 status = ufx_i2c_wait_busy(dev);
1470 check_warn_return(status, "Timeout waiting for I2C BUSY to clear");
1472 for (j = 0; j < 16; j++) {
1473 u32 data_reg_addr = 0x1110 + (j * 4);
1474 status = ufx_reg_read(dev, data_reg_addr, edid_u32++);
1475 check_warn_return(status, "Error reading i2c data");
1479 /* all FF's in the first 16 bytes indicates nothing is connected */
1480 for (i = 0; i < 16; i++) {
1481 if (edid[i] != 0xFF) {
1482 pr_debug("edid data read successfully");
1487 pr_warn("edid data contains all 0xff");
1491 /* 1) use sw default
1492 * 2) Parse into various fb_info structs
1493 * 3) Allocate virtual framebuffer memory to back highest res mode
1495 * Parses EDID into three places used by various parts of fbdev:
1496 * fb_var_screeninfo contains the timing of the monitor's preferred mode
1497 * fb_info.monspecs is full parsed EDID info, including monspecs.modedb
1498 * fb_info.modelist is a linked list of all monitor & VESA modes which work
1500 * If EDID is not readable/valid, then modelist is all VESA modes,
1501 * monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode
1502 * Returns 0 if successful */
1503 static int ufx_setup_modes(struct ufx_data *dev, struct fb_info *info,
1504 char *default_edid, size_t default_edid_size)
1506 const struct fb_videomode *default_vmode = NULL;
1508 int i, result = 0, tries = 3;
1510 if (info->dev) /* only use mutex if info has been registered */
1511 mutex_lock(&info->lock);
1513 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
1519 fb_destroy_modelist(&info->modelist);
1520 memset(&info->monspecs, 0, sizeof(info->monspecs));
1522 /* Try to (re)read EDID from hardware first
1523 * EDID data may return, but not parse as valid
1524 * Try again a few times, in case of e.g. analog cable noise */
1526 i = ufx_read_edid(dev, edid, EDID_LENGTH);
1528 if (i >= EDID_LENGTH)
1529 fb_edid_to_monspecs(edid, &info->monspecs);
1531 if (info->monspecs.modedb_len > 0) {
1538 /* If that fails, use a previously returned EDID if available */
1539 if (info->monspecs.modedb_len == 0) {
1540 pr_err("Unable to get valid EDID from device/display\n");
1543 fb_edid_to_monspecs(dev->edid, &info->monspecs);
1544 if (info->monspecs.modedb_len > 0)
1545 pr_err("Using previously queried EDID\n");
1549 /* If that fails, use the default EDID we were handed */
1550 if (info->monspecs.modedb_len == 0) {
1551 if (default_edid_size >= EDID_LENGTH) {
1552 fb_edid_to_monspecs(default_edid, &info->monspecs);
1553 if (info->monspecs.modedb_len > 0) {
1554 memcpy(edid, default_edid, default_edid_size);
1556 dev->edid_size = default_edid_size;
1557 pr_err("Using default/backup EDID\n");
1562 /* If we've got modes, let's pick a best default mode */
1563 if (info->monspecs.modedb_len > 0) {
1565 for (i = 0; i < info->monspecs.modedb_len; i++) {
1566 if (ufx_is_valid_mode(&info->monspecs.modedb[i], info))
1567 fb_add_videomode(&info->monspecs.modedb[i],
1569 else /* if we've removed top/best mode */
1570 info->monspecs.misc &= ~FB_MISC_1ST_DETAIL;
1573 default_vmode = fb_find_best_display(&info->monspecs,
1577 /* If everything else has failed, fall back to safe default mode */
1578 if (default_vmode == NULL) {
1580 struct fb_videomode fb_vmode = {0};
1582 /* Add the standard VESA modes to our modelist
1583 * Since we don't have EDID, there may be modes that
1584 * overspec monitor and/or are incorrect aspect ratio, etc.
1585 * But at least the user has a chance to choose
1587 for (i = 0; i < VESA_MODEDB_SIZE; i++) {
1588 if (ufx_is_valid_mode((struct fb_videomode *)
1589 &vesa_modes[i], info))
1590 fb_add_videomode(&vesa_modes[i],
1594 /* default to resolution safe for projectors
1595 * (since they are most common case without EDID)
1597 fb_vmode.xres = 800;
1598 fb_vmode.yres = 600;
1599 fb_vmode.refresh = 60;
1600 default_vmode = fb_find_nearest_mode(&fb_vmode,
1604 /* If we have good mode and no active clients */
1605 if ((default_vmode != NULL) && (dev->fb_count == 0)) {
1607 fb_videomode_to_var(&info->var, default_vmode);
1608 ufx_var_color_format(&info->var);
1610 /* with mode size info, we can now alloc our framebuffer */
1611 memcpy(&info->fix, &ufx_fix, sizeof(ufx_fix));
1612 info->fix.line_length = info->var.xres *
1613 (info->var.bits_per_pixel / 8);
1615 result = ufx_realloc_framebuffer(dev, info);
1621 if (edid && (dev->edid != edid))
1625 mutex_unlock(&info->lock);
1630 static int ufx_usb_probe(struct usb_interface *interface,
1631 const struct usb_device_id *id)
1633 struct usb_device *usbdev;
1634 struct ufx_data *dev;
1635 struct fb_info *info = NULL;
1636 int retval = -ENOMEM;
1637 u32 id_rev, fpga_rev;
1639 /* usb initialization */
1640 usbdev = interface_to_usbdev(interface);
1643 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1645 dev_err(&usbdev->dev, "ufx_usb_probe: failed alloc of dev struct\n");
1649 /* we need to wait for both usb and fbdev to spin down on disconnect */
1650 kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */
1651 kref_get(&dev->kref); /* matching kref_put in free_framebuffer_work */
1654 dev->gdev = &usbdev->dev; /* our generic struct device * */
1655 usb_set_intfdata(interface, dev);
1657 dev_dbg(dev->gdev, "%s %s - serial #%s\n",
1658 usbdev->manufacturer, usbdev->product, usbdev->serial);
1659 dev_dbg(dev->gdev, "vid_%04x&pid_%04x&rev_%04x driver's ufx_data struct at %p\n",
1660 usbdev->descriptor.idVendor, usbdev->descriptor.idProduct,
1661 usbdev->descriptor.bcdDevice, dev);
1662 dev_dbg(dev->gdev, "console enable=%d\n", console);
1663 dev_dbg(dev->gdev, "fb_defio enable=%d\n", fb_defio);
1665 if (!ufx_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) {
1667 dev_err(dev->gdev, "ufx_alloc_urb_list failed\n");
1671 /* We don't register a new USB class. Our client interface is fbdev */
1673 /* allocates framebuffer driver structure, not framebuffer memory */
1674 info = framebuffer_alloc(0, &usbdev->dev);
1677 dev_err(dev->gdev, "framebuffer_alloc failed\n");
1683 info->pseudo_palette = dev->pseudo_palette;
1684 info->fbops = &ufx_ops;
1685 INIT_LIST_HEAD(&info->modelist);
1687 retval = fb_alloc_cmap(&info->cmap, 256, 0);
1689 dev_err(dev->gdev, "fb_alloc_cmap failed %x\n", retval);
1693 retval = ufx_reg_read(dev, 0x3000, &id_rev);
1694 check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval);
1695 dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev);
1697 retval = ufx_reg_read(dev, 0x3004, &fpga_rev);
1698 check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval);
1699 dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev);
1701 dev_dbg(dev->gdev, "resetting device");
1702 retval = ufx_lite_reset(dev);
1703 check_warn_goto_error(retval, "error %d resetting device", retval);
1705 dev_dbg(dev->gdev, "configuring system clock");
1706 retval = ufx_config_sys_clk(dev);
1707 check_warn_goto_error(retval, "error %d configuring system clock", retval);
1709 dev_dbg(dev->gdev, "configuring DDR2 controller");
1710 retval = ufx_config_ddr2(dev);
1711 check_warn_goto_error(retval, "error %d initialising DDR2 controller", retval);
1713 dev_dbg(dev->gdev, "configuring I2C controller");
1714 retval = ufx_i2c_init(dev);
1715 check_warn_goto_error(retval, "error %d initialising I2C controller", retval);
1717 dev_dbg(dev->gdev, "selecting display mode");
1718 retval = ufx_setup_modes(dev, info, NULL, 0);
1719 check_warn_goto_error(retval, "unable to find common mode for display and adapter");
1721 retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001);
1722 check_warn_goto_error(retval, "error %d enabling graphics engine", retval);
1724 /* ready to begin using device */
1725 atomic_set(&dev->usb_active, 1);
1727 dev_dbg(dev->gdev, "checking var");
1728 retval = ufx_ops_check_var(&info->var, info);
1729 check_warn_goto_error(retval, "error %d ufx_ops_check_var", retval);
1731 dev_dbg(dev->gdev, "setting par");
1732 retval = ufx_ops_set_par(info);
1733 check_warn_goto_error(retval, "error %d ufx_ops_set_par", retval);
1735 dev_dbg(dev->gdev, "registering framebuffer");
1736 retval = register_framebuffer(info);
1737 check_warn_goto_error(retval, "error %d register_framebuffer", retval);
1739 dev_info(dev->gdev, "SMSC UDX USB device /dev/fb%d attached. %dx%d resolution."
1740 " Using %dK framebuffer memory\n", info->node,
1741 info->var.xres, info->var.yres, info->fix.smem_len >> 10);
1748 if (info->cmap.len != 0)
1749 fb_dealloc_cmap(&info->cmap);
1750 if (info->monspecs.modedb)
1751 fb_destroy_modedb(info->monspecs.modedb);
1752 vfree(info->screen_base);
1754 fb_destroy_modelist(&info->modelist);
1756 framebuffer_release(info);
1759 kref_put(&dev->kref, ufx_free); /* ref for framebuffer */
1760 kref_put(&dev->kref, ufx_free); /* last ref from kref_init */
1762 /* dev has been deallocated. Do not dereference */
1768 static void ufx_usb_disconnect(struct usb_interface *interface)
1770 struct ufx_data *dev;
1771 struct fb_info *info;
1773 mutex_lock(&disconnect_mutex);
1775 dev = usb_get_intfdata(interface);
1778 pr_debug("USB disconnect starting\n");
1780 /* we virtualize until all fb clients release. Then we free */
1781 dev->virtualized = true;
1783 /* When non-active we'll update virtual framebuffer, but no new urbs */
1784 atomic_set(&dev->usb_active, 0);
1786 usb_set_intfdata(interface, NULL);
1788 /* if clients still have us open, will be freed on last close */
1789 if (dev->fb_count == 0)
1790 ufx_free_framebuffer(dev);
1792 /* this function will wait for all in-flight urbs to complete */
1793 if (dev->urbs.count > 0)
1794 ufx_free_urb_list(dev);
1796 pr_debug("freeing ufx_data %p", dev);
1798 unregister_framebuffer(info);
1800 mutex_unlock(&disconnect_mutex);
1803 static struct usb_driver ufx_driver = {
1805 .probe = ufx_usb_probe,
1806 .disconnect = ufx_usb_disconnect,
1807 .id_table = id_table,
1810 module_usb_driver(ufx_driver);
1812 static void ufx_urb_completion(struct urb *urb)
1814 struct urb_node *unode = urb->context;
1815 struct ufx_data *dev = unode->dev;
1816 unsigned long flags;
1818 /* sync/async unlink faults aren't errors */
1820 if (!(urb->status == -ENOENT ||
1821 urb->status == -ECONNRESET ||
1822 urb->status == -ESHUTDOWN)) {
1823 pr_err("%s - nonzero write bulk status received: %d\n",
1824 __func__, urb->status);
1825 atomic_set(&dev->lost_pixels, 1);
1829 urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */
1831 spin_lock_irqsave(&dev->urbs.lock, flags);
1832 list_add_tail(&unode->entry, &dev->urbs.list);
1833 dev->urbs.available++;
1834 spin_unlock_irqrestore(&dev->urbs.lock, flags);
1836 /* When using fb_defio, we deadlock if up() is called
1837 * while another is waiting. So queue to another process */
1839 schedule_delayed_work(&unode->release_urb_work, 0);
1841 up(&dev->urbs.limit_sem);
1844 static void ufx_free_urb_list(struct ufx_data *dev)
1846 int count = dev->urbs.count;
1847 struct list_head *node;
1848 struct urb_node *unode;
1851 unsigned long flags;
1853 pr_debug("Waiting for completes and freeing all render urbs\n");
1855 /* keep waiting and freeing, until we've got 'em all */
1857 /* Getting interrupted means a leak, but ok at shutdown*/
1858 ret = down_interruptible(&dev->urbs.limit_sem);
1862 spin_lock_irqsave(&dev->urbs.lock, flags);
1864 node = dev->urbs.list.next; /* have reserved one with sem */
1865 list_del_init(node);
1867 spin_unlock_irqrestore(&dev->urbs.lock, flags);
1869 unode = list_entry(node, struct urb_node, entry);
1872 /* Free each separately allocated piece */
1873 usb_free_coherent(urb->dev, dev->urbs.size,
1874 urb->transfer_buffer, urb->transfer_dma);
1880 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size)
1884 struct urb_node *unode;
1887 spin_lock_init(&dev->urbs.lock);
1889 dev->urbs.size = size;
1890 INIT_LIST_HEAD(&dev->urbs.list);
1893 unode = kzalloc(sizeof(struct urb_node), GFP_KERNEL);
1898 INIT_DELAYED_WORK(&unode->release_urb_work,
1899 ufx_release_urb_work);
1901 urb = usb_alloc_urb(0, GFP_KERNEL);
1908 buf = usb_alloc_coherent(dev->udev, size, GFP_KERNEL,
1909 &urb->transfer_dma);
1916 /* urb->transfer_buffer_length set to actual before submit */
1917 usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1),
1918 buf, size, ufx_urb_completion, unode);
1919 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
1921 list_add_tail(&unode->entry, &dev->urbs.list);
1926 sema_init(&dev->urbs.limit_sem, i);
1927 dev->urbs.count = i;
1928 dev->urbs.available = i;
1930 pr_debug("allocated %d %d byte urbs\n", i, (int) size);
1935 static struct urb *ufx_get_urb(struct ufx_data *dev)
1938 struct list_head *entry;
1939 struct urb_node *unode;
1940 struct urb *urb = NULL;
1941 unsigned long flags;
1943 /* Wait for an in-flight buffer to complete and get re-queued */
1944 ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT);
1946 atomic_set(&dev->lost_pixels, 1);
1947 pr_warn("wait for urb interrupted: %x available: %d\n",
1948 ret, dev->urbs.available);
1952 spin_lock_irqsave(&dev->urbs.lock, flags);
1954 BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */
1955 entry = dev->urbs.list.next;
1956 list_del_init(entry);
1957 dev->urbs.available--;
1959 spin_unlock_irqrestore(&dev->urbs.lock, flags);
1961 unode = list_entry(entry, struct urb_node, entry);
1968 static int ufx_submit_urb(struct ufx_data *dev, struct urb *urb, size_t len)
1972 BUG_ON(len > dev->urbs.size);
1974 urb->transfer_buffer_length = len; /* set to actual payload len */
1975 ret = usb_submit_urb(urb, GFP_KERNEL);
1977 ufx_urb_completion(urb); /* because no one else will */
1978 atomic_set(&dev->lost_pixels, 1);
1979 pr_err("usb_submit_urb error %x\n", ret);
1984 module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
1985 MODULE_PARM_DESC(console, "Allow fbcon to be used on this display");
1987 module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
1988 MODULE_PARM_DESC(fb_defio, "Enable fb_defio mmap support");
1990 MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
1991 MODULE_DESCRIPTION("SMSC UFX kernel framebuffer driver");
1992 MODULE_LICENSE("GPL");