drivers/watchdog/imx2_wdt.c

   1 /*
   2  * Watchdog driver for IMX2 and later processors
   3  *
   4  *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
   5  *  Copyright (C) 2014 Freescale Semiconductor, Inc.
   6  *
   7  * some parts adapted by similar drivers from Darius Augulis and Vladimir
   8  * Zapolskiy, additional improvements by Wim Van Sebroeck.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
  15  *
  16  *                      MX1:            MX2+:
  17  *                      ----            -----
  18  * Registers:           32-bit          16-bit
  19  * Stopable timer:      Yes             No
  20  * Need to enable clk:  No              Yes
  21  * Halt on suspend:     Manual          Can be automatic
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/io.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/notifier.h>
  33 #include <linux/of_address.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/reboot.h>
  36 #include <linux/regmap.h>
  37 #include <linux/timer.h>
  38 #include <linux/watchdog.h>
  39
  40 #define DRIVER_NAME "imx2-wdt"
  41
  42 #define IMX2_WDT_WCR            0x00            /* Control Register */
  43 #define IMX2_WDT_WCR_WT         (0xFF << 8)     /* -> Watchdog Timeout Field */
  44 #define IMX2_WDT_WCR_WRE        (1 << 3)        /* -> WDOG Reset Enable */
  45 #define IMX2_WDT_WCR_WDE        (1 << 2)        /* -> Watchdog Enable */
  46 #define IMX2_WDT_WCR_WDZST      (1 << 0)        /* -> Watchdog timer Suspend */
  47
  48 #define IMX2_WDT_WSR            0x02            /* Service Register */
  49 #define IMX2_WDT_SEQ1           0x5555          /* -> service sequence 1 */
  50 #define IMX2_WDT_SEQ2           0xAAAA          /* -> service sequence 2 */
  51
  52 #define IMX2_WDT_WRSR           0x04            /* Reset Status Register */
  53 #define IMX2_WDT_WRSR_TOUT      (1 << 1)        /* -> Reset due to Timeout */
  54
  55 #define IMX2_WDT_WMCR           0x08            /* Misc Register */
  56
  57 #define IMX2_WDT_MAX_TIME       128
  58 #define IMX2_WDT_DEFAULT_TIME   60              /* in seconds */
  59
  60 #define WDOG_SEC_TO_COUNT(s)    ((s * 2 - 1) << 8)
  61
  62 struct imx2_wdt_device {
  63         struct clk *clk;
  64         struct regmap *regmap;
  65         struct timer_list timer;        /* Pings the watchdog when closed */
  66         struct watchdog_device wdog;
  67         struct notifier_block restart_handler;
  68 };
  69
  70 static bool nowayout = WATCHDOG_NOWAYOUT;
  71 module_param(nowayout, bool, 0);
  72 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  73                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  74
  75
  76 static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
  77 module_param(timeout, uint, 0);
  78 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
  79                                 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
  80
  81 static const struct watchdog_info imx2_wdt_info = {
  82         .identity = "imx2+ watchdog",
  83         .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
  84 };
  85
  86 static int imx2_restart_handler(struct notifier_block *this, unsigned long mode,
  87                                 void *cmd)
  88 {
  89         unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
  90         struct imx2_wdt_device *wdev = container_of(this,
  91                                                     struct imx2_wdt_device,
  92                                                     restart_handler);
  93         /* Assert SRS signal */
  94         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  95         /*
  96          * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
  97          * written twice), we add another two writes to ensure there must be at
  98          * least two writes happen in the same one 32kHz clock period.  We save
  99          * the target check here, since the writes shouldn't be a huge burden
 100          * for other platforms.
 101          */
 102         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 103         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 104
 105         /* wait for reset to assert... */
 106         mdelay(500);
 107
 108         return NOTIFY_DONE;
 109 }
 110
 111 static inline void imx2_wdt_setup(struct watchdog_device *wdog)
 112 {
 113         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 114         u32 val;
 115
 116         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 117
 118         /* Suspend timer in low power mode, write once-only */
 119         val |= IMX2_WDT_WCR_WDZST;
 120         /* Strip the old watchdog Time-Out value */
 121         val &= ~IMX2_WDT_WCR_WT;
 122         /* Generate reset if WDOG times out */
 123         val &= ~IMX2_WDT_WCR_WRE;
 124         /* Keep Watchdog Disabled */
 125         val &= ~IMX2_WDT_WCR_WDE;
 126         /* Set the watchdog's Time-Out value */
 127         val |= WDOG_SEC_TO_COUNT(wdog->timeout);
 128
 129         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 130
 131         /* enable the watchdog */
 132         val |= IMX2_WDT_WCR_WDE;
 133         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 134 }
 135
 136 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
 137 {
 138         u32 val;
 139
 140         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 141
 142         return val & IMX2_WDT_WCR_WDE;
 143 }
 144
 145 static int imx2_wdt_ping(struct watchdog_device *wdog)
 146 {
 147         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 148
 149         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
 150         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
 151         return 0;
 152 }
 153
 154 static void imx2_wdt_timer_ping(unsigned long arg)
 155 {
 156         struct watchdog_device *wdog = (struct watchdog_device *)arg;
 157         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 158
 159         /* ping it every wdog->timeout / 2 seconds to prevent reboot */
 160         imx2_wdt_ping(wdog);
 161         mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
 162 }
 163
 164 static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
 165                                    unsigned int new_timeout)
 166 {
 167         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 168
 169         regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
 170                            WDOG_SEC_TO_COUNT(new_timeout));
 171 }
 172
 173 static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
 174                                 unsigned int new_timeout)
 175 {
 176         __imx2_wdt_set_timeout(wdog, new_timeout);
 177
 178         wdog->timeout = new_timeout;
 179         return 0;
 180 }
 181
 182 static int imx2_wdt_start(struct watchdog_device *wdog)
 183 {
 184         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 185
 186         if (imx2_wdt_is_running(wdev)) {
 187                 /* delete the timer that pings the watchdog after close */
 188                 del_timer_sync(&wdev->timer);
 189                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 190         } else
 191                 imx2_wdt_setup(wdog);
 192
 193         return imx2_wdt_ping(wdog);
 194 }
 195
 196 static int imx2_wdt_stop(struct watchdog_device *wdog)
 197 {
 198         /*
 199          * We don't need a clk_disable, it cannot be disabled once started.
 200          * We use a timer to ping the watchdog while /dev/watchdog is closed
 201          */
 202         imx2_wdt_timer_ping((unsigned long)wdog);
 203         return 0;
 204 }
 205
 206 static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
 207 {
 208         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 209
 210         if (imx2_wdt_is_running(wdev)) {
 211                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 212                 imx2_wdt_timer_ping((unsigned long)wdog);
 213         }
 214 }
 215
 216 static const struct watchdog_ops imx2_wdt_ops = {
 217         .owner = THIS_MODULE,
 218         .start = imx2_wdt_start,
 219         .stop = imx2_wdt_stop,
 220         .ping = imx2_wdt_ping,
 221         .set_timeout = imx2_wdt_set_timeout,
 222 };
 223
 224 static const struct regmap_config imx2_wdt_regmap_config = {
 225         .reg_bits = 16,
 226         .reg_stride = 2,
 227         .val_bits = 16,
 228         .max_register = 0x8,
 229 };
 230
 231 static int __init imx2_wdt_probe(struct platform_device *pdev)
 232 {
 233         struct imx2_wdt_device *wdev;
 234         struct watchdog_device *wdog;
 235         struct resource *res;
 236         void __iomem *base;
 237         int ret;
 238         u32 val;
 239
 240         wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
 241         if (!wdev)
 242                 return -ENOMEM;
 243
 244         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 245         base = devm_ioremap_resource(&pdev->dev, res);
 246         if (IS_ERR(base))
 247                 return PTR_ERR(base);
 248
 249         wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
 250                                                  &imx2_wdt_regmap_config);
 251         if (IS_ERR(wdev->regmap)) {
 252                 dev_err(&pdev->dev, "regmap init failed\n");
 253                 return PTR_ERR(wdev->regmap);
 254         }
 255
 256         wdev->clk = devm_clk_get(&pdev->dev, NULL);
 257         if (IS_ERR(wdev->clk)) {
 258                 dev_err(&pdev->dev, "can't get Watchdog clock\n");
 259                 return PTR_ERR(wdev->clk);
 260         }
 261
 262         wdog                    = &wdev->wdog;
 263         wdog->info              = &imx2_wdt_info;
 264         wdog->ops               = &imx2_wdt_ops;
 265         wdog->min_timeout       = 1;
 266         wdog->max_timeout       = IMX2_WDT_MAX_TIME;
 267         wdog->parent            = &pdev->dev;
 268
 269         ret = clk_prepare_enable(wdev->clk);
 270         if (ret)
 271                 return ret;
 272
 273         regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
 274         wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
 275
 276         wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
 277         if (wdog->timeout != timeout)
 278                 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
 279                          timeout, wdog->timeout);
 280
 281         platform_set_drvdata(pdev, wdog);
 282         watchdog_set_drvdata(wdog, wdev);
 283         watchdog_set_nowayout(wdog, nowayout);
 284         watchdog_init_timeout(wdog, timeout, &pdev->dev);
 285
 286         setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
 287
 288         imx2_wdt_ping_if_active(wdog);
 289
 290         /*
 291          * Disable the watchdog power down counter at boot. Otherwise the power
 292          * down counter will pull down the #WDOG interrupt line for one clock
 293          * cycle.
 294          */
 295         regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
 296
 297         ret = watchdog_register_device(wdog);
 298         if (ret) {
 299                 dev_err(&pdev->dev, "cannot register watchdog device\n");
 300                 goto disable_clk;
 301         }
 302
 303         wdev->restart_handler.notifier_call = imx2_restart_handler;
 304         wdev->restart_handler.priority = 128;
 305         ret = register_restart_handler(&wdev->restart_handler);
 306         if (ret)
 307                 dev_err(&pdev->dev, "cannot register restart handler\n");
 308
 309         dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
 310                  wdog->timeout, nowayout);
 311
 312         return 0;
 313
 314 disable_clk:
 315         clk_disable_unprepare(wdev->clk);
 316         return ret;
 317 }
 318
 319 static int __exit imx2_wdt_remove(struct platform_device *pdev)
 320 {
 321         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 322         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 323
 324         unregister_restart_handler(&wdev->restart_handler);
 325
 326         watchdog_unregister_device(wdog);
 327
 328         if (imx2_wdt_is_running(wdev)) {
 329                 del_timer_sync(&wdev->timer);
 330                 imx2_wdt_ping(wdog);
 331                 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
 332         }
 333         return 0;
 334 }
 335
 336 static void imx2_wdt_shutdown(struct platform_device *pdev)
 337 {
 338         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 339         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 340
 341         if (imx2_wdt_is_running(wdev)) {
 342                 /*
 343                  * We are running, we need to delete the timer but will
 344                  * give max timeout before reboot will take place
 345                  */
 346                 del_timer_sync(&wdev->timer);
 347                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 348                 imx2_wdt_ping(wdog);
 349                 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
 350         }
 351 }
 352
 353 #ifdef CONFIG_PM_SLEEP
 354 /* Disable watchdog if it is active or non-active but still running */
 355 static int imx2_wdt_suspend(struct device *dev)
 356 {
 357         struct watchdog_device *wdog = dev_get_drvdata(dev);
 358         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 359
 360         /* The watchdog IP block is running */
 361         if (imx2_wdt_is_running(wdev)) {
 362                 /*
 363                  * Don't update wdog->timeout, we'll restore the current value
 364                  * during resume.
 365                  */
 366                 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 367                 imx2_wdt_ping(wdog);
 368
 369                 /* The watchdog is not active */
 370                 if (!watchdog_active(wdog))
 371                         del_timer_sync(&wdev->timer);
 372         }
 373
 374         clk_disable_unprepare(wdev->clk);
 375
 376         return 0;
 377 }
 378
 379 /* Enable watchdog and configure it if necessary */
 380 static int imx2_wdt_resume(struct device *dev)
 381 {
 382         struct watchdog_device *wdog = dev_get_drvdata(dev);
 383         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 384         int ret;
 385
 386         ret = clk_prepare_enable(wdev->clk);
 387         if (ret)
 388                 return ret;
 389
 390         if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
 391                 /*
 392                  * If the watchdog is still active and resumes
 393                  * from deep sleep state, need to restart the
 394                  * watchdog again.
 395                  */
 396                 imx2_wdt_setup(wdog);
 397                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 398                 imx2_wdt_ping(wdog);
 399         } else if (imx2_wdt_is_running(wdev)) {
 400                 /* Resuming from non-deep sleep state. */
 401                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 402                 imx2_wdt_ping(wdog);
 403                 /*
 404                  * But the watchdog is not active, then start
 405                  * the timer again.
 406                  */
 407                 if (!watchdog_active(wdog))
 408                         mod_timer(&wdev->timer,
 409                                   jiffies + wdog->timeout * HZ / 2);
 410         }
 411
 412         return 0;
 413 }
 414 #endif
 415
 416 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
 417                          imx2_wdt_resume);
 418
 419 static const struct of_device_id imx2_wdt_dt_ids[] = {
 420         { .compatible = "fsl,imx21-wdt", },
 421         { /* sentinel */ }
 422 };
 423 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
 424
 425 static struct platform_driver imx2_wdt_driver = {
 426         .remove         = __exit_p(imx2_wdt_remove),
 427         .shutdown       = imx2_wdt_shutdown,
 428         .driver         = {
 429                 .name   = DRIVER_NAME,
 430                 .pm     = &imx2_wdt_pm_ops,
 431                 .of_match_table = imx2_wdt_dt_ids,
 432         },
 433 };
 434
 435 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
 436
 437 MODULE_AUTHOR("Wolfram Sang");
 438 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
 439 MODULE_LICENSE("GPL v2");
 440 MODULE_ALIAS("platform:" DRIVER_NAME);