include/linux/rtsx_usb.h

   1 /* Driver for Realtek RTS5139 USB card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  *
  17  * Author:
  18  *   Roger Tseng <rogerable@realtek.com>
  19  */
  20
  21 #ifndef __RTSX_USB_H
  22 #define __RTSX_USB_H
  23
  24 #include <linux/usb.h>
  25
  26 /* related module names */
  27 #define RTSX_USB_SD_CARD        0
  28 #define RTSX_USB_MS_CARD        1
  29
  30 /* endpoint numbers */
  31 #define EP_BULK_OUT             1
  32 #define EP_BULK_IN              2
  33 #define EP_INTR_IN              3
  34
  35 /* USB vendor requests */
  36 #define RTSX_USB_REQ_REG_OP     0x00
  37 #define RTSX_USB_REQ_POLL       0x02
  38
  39 /* miscellaneous parameters */
  40 #define MIN_DIV_N               60
  41 #define MAX_DIV_N               120
  42
  43 #define MAX_PHASE               15
  44 #define RX_TUNING_CNT           3
  45
  46 #define QFN24                   0
  47 #define LQFP48                  1
  48 #define CHECK_PKG(ucr, pkg)     ((ucr)->package == (pkg))
  49
  50 /* data structures */
  51 struct rtsx_ucr {
  52         u16                     vendor_id;
  53         u16                     product_id;
  54
  55         int                     package;
  56         u8                      ic_version;
  57         bool                    is_rts5179;
  58
  59         unsigned int            cur_clk;
  60
  61         u8                      *cmd_buf;
  62         unsigned int            cmd_idx;
  63         u8                      *rsp_buf;
  64
  65         struct usb_device       *pusb_dev;
  66         struct usb_interface    *pusb_intf;
  67         struct usb_sg_request   current_sg;
  68
  69         struct timer_list       sg_timer;
  70         struct mutex            dev_mutex;
  71 };
  72
  73 /* buffer size */
  74 #define IOBUF_SIZE              1024
  75
  76 /* prototypes of exported functions */
  77 extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
  78
  79 extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
  80 extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
  81                 u8 data);
  82
  83 extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
  84                 u8 data);
  85 extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
  86                 u8 *data);
  87
  88 extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
  89                 u16 reg_addr, u8 mask, u8 data);
  90 extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
  91 extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
  92 extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
  93                               void *buf, unsigned int len, int use_sg,
  94                               unsigned int *act_len, int timeout);
  95
  96 extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
  97 extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
  98 extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
  99                 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
 100 extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
 101
 102 /* card status */
 103 #define SD_CD           0x01
 104 #define MS_CD           0x02
 105 #define XD_CD           0x04
 106 #define CD_MASK         (SD_CD | MS_CD | XD_CD)
 107 #define SD_WP           0x08
 108
 109 /* reader command field offset & parameters */
 110 #define READ_REG_CMD            0
 111 #define WRITE_REG_CMD           1
 112 #define CHECK_REG_CMD           2
 113
 114 #define PACKET_TYPE             4
 115 #define CNT_H                   5
 116 #define CNT_L                   6
 117 #define STAGE_FLAG              7
 118 #define CMD_OFFSET              8
 119 #define SEQ_WRITE_DATA_OFFSET   12
 120
 121 #define BATCH_CMD               0
 122 #define SEQ_READ                1
 123 #define SEQ_WRITE               2
 124
 125 #define STAGE_R                 0x01
 126 #define STAGE_DI                0x02
 127 #define STAGE_DO                0x04
 128 #define STAGE_MS_STATUS         0x08
 129 #define STAGE_XD_STATUS         0x10
 130 #define MODE_C                  0x00
 131 #define MODE_CR                 (STAGE_R)
 132 #define MODE_CDIR               (STAGE_R | STAGE_DI)
 133 #define MODE_CDOR               (STAGE_R | STAGE_DO)
 134
 135 #define EP0_OP_SHIFT            14
 136 #define EP0_READ_REG_CMD        2
 137 #define EP0_WRITE_REG_CMD       3
 138
 139 #define rtsx_usb_cmd_hdr_tag(ucr)               \
 140         do {                                    \
 141                 ucr->cmd_buf[0] = 'R';          \
 142                 ucr->cmd_buf[1] = 'T';          \
 143                 ucr->cmd_buf[2] = 'C';          \
 144                 ucr->cmd_buf[3] = 'R';          \
 145         } while (0)
 146
 147 static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
 148 {
 149         rtsx_usb_cmd_hdr_tag(ucr);
 150         ucr->cmd_idx = 0;
 151         ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
 152 }
 153
 154 /* internal register address */
 155 #define FPDCTL                          0xFC00
 156 #define SSC_DIV_N_0                     0xFC07
 157 #define SSC_CTL1                        0xFC09
 158 #define SSC_CTL2                        0xFC0A
 159 #define CFG_MODE                        0xFC0E
 160 #define CFG_MODE_1                      0xFC0F
 161 #define RCCTL                           0xFC14
 162 #define SOF_WDOG                        0xFC28
 163 #define SYS_DUMMY0                      0xFC30
 164
 165 #define MS_BLKEND                       0xFD30
 166 #define MS_READ_START                   0xFD31
 167 #define MS_READ_COUNT                   0xFD32
 168 #define MS_WRITE_START                  0xFD33
 169 #define MS_WRITE_COUNT                  0xFD34
 170 #define MS_COMMAND                      0xFD35
 171 #define MS_OLD_BLOCK_0                  0xFD36
 172 #define MS_OLD_BLOCK_1                  0xFD37
 173 #define MS_NEW_BLOCK_0                  0xFD38
 174 #define MS_NEW_BLOCK_1                  0xFD39
 175 #define MS_LOG_BLOCK_0                  0xFD3A
 176 #define MS_LOG_BLOCK_1                  0xFD3B
 177 #define MS_BUS_WIDTH                    0xFD3C
 178 #define MS_PAGE_START                   0xFD3D
 179 #define MS_PAGE_LENGTH                  0xFD3E
 180 #define MS_CFG                          0xFD40
 181 #define MS_TPC                          0xFD41
 182 #define MS_TRANS_CFG                    0xFD42
 183 #define MS_TRANSFER                     0xFD43
 184 #define MS_INT_REG                      0xFD44
 185 #define MS_BYTE_CNT                     0xFD45
 186 #define MS_SECTOR_CNT_L                 0xFD46
 187 #define MS_SECTOR_CNT_H                 0xFD47
 188 #define MS_DBUS_H                       0xFD48
 189
 190 #define CARD_DMA1_CTL                   0xFD5C
 191 #define CARD_PULL_CTL1                  0xFD60
 192 #define CARD_PULL_CTL2                  0xFD61
 193 #define CARD_PULL_CTL3                  0xFD62
 194 #define CARD_PULL_CTL4                  0xFD63
 195 #define CARD_PULL_CTL5                  0xFD64
 196 #define CARD_PULL_CTL6                  0xFD65
 197 #define CARD_EXIST                      0xFD6F
 198 #define CARD_INT_PEND                   0xFD71
 199
 200 #define LDO_POWER_CFG                   0xFD7B
 201
 202 #define SD_CFG1                         0xFDA0
 203 #define SD_CFG2                         0xFDA1
 204 #define SD_CFG3                         0xFDA2
 205 #define SD_STAT1                        0xFDA3
 206 #define SD_STAT2                        0xFDA4
 207 #define SD_BUS_STAT                     0xFDA5
 208 #define SD_PAD_CTL                      0xFDA6
 209 #define SD_SAMPLE_POINT_CTL             0xFDA7
 210 #define SD_PUSH_POINT_CTL               0xFDA8
 211 #define SD_CMD0                         0xFDA9
 212 #define SD_CMD1                         0xFDAA
 213 #define SD_CMD2                         0xFDAB
 214 #define SD_CMD3                         0xFDAC
 215 #define SD_CMD4                         0xFDAD
 216 #define SD_CMD5                         0xFDAE
 217 #define SD_BYTE_CNT_L                   0xFDAF
 218 #define SD_BYTE_CNT_H                   0xFDB0
 219 #define SD_BLOCK_CNT_L                  0xFDB1
 220 #define SD_BLOCK_CNT_H                  0xFDB2
 221 #define SD_TRANSFER                     0xFDB3
 222 #define SD_CMD_STATE                    0xFDB5
 223 #define SD_DATA_STATE                   0xFDB6
 224 #define SD_VPCLK0_CTL                   0xFC2A
 225 #define SD_VPCLK1_CTL                   0xFC2B
 226 #define SD_DCMPS0_CTL                   0xFC2C
 227 #define SD_DCMPS1_CTL                   0xFC2D
 228
 229 #define CARD_DMA1_CTL                   0xFD5C
 230
 231 #define HW_VERSION                      0xFC01
 232
 233 #define SSC_CLK_FPGA_SEL                0xFC02
 234 #define CLK_DIV                         0xFC03
 235 #define SFSM_ED                         0xFC04
 236
 237 #define CD_DEGLITCH_WIDTH               0xFC20
 238 #define CD_DEGLITCH_EN                  0xFC21
 239 #define AUTO_DELINK_EN                  0xFC23
 240
 241 #define FPGA_PULL_CTL                   0xFC1D
 242 #define CARD_CLK_SOURCE                 0xFC2E
 243
 244 #define CARD_SHARE_MODE                 0xFD51
 245 #define CARD_DRIVE_SEL                  0xFD52
 246 #define CARD_STOP                       0xFD53
 247 #define CARD_OE                         0xFD54
 248 #define CARD_AUTO_BLINK                 0xFD55
 249 #define CARD_GPIO                       0xFD56
 250 #define SD30_DRIVE_SEL                  0xFD57
 251
 252 #define CARD_DATA_SOURCE                0xFD5D
 253 #define CARD_SELECT                     0xFD5E
 254
 255 #define CARD_CLK_EN                     0xFD79
 256 #define CARD_PWR_CTL                    0xFD7A
 257
 258 #define OCPCTL                          0xFD80
 259 #define OCPPARA1                        0xFD81
 260 #define OCPPARA2                        0xFD82
 261 #define OCPSTAT                         0xFD83
 262
 263 #define HS_USB_STAT                     0xFE01
 264 #define HS_VCONTROL                     0xFE26
 265 #define HS_VSTAIN                       0xFE27
 266 #define HS_VLOADM                       0xFE28
 267 #define HS_VSTAOUT                      0xFE29
 268
 269 #define MC_IRQ                          0xFF00
 270 #define MC_IRQEN                        0xFF01
 271 #define MC_FIFO_CTL                     0xFF02
 272 #define MC_FIFO_BC0                     0xFF03
 273 #define MC_FIFO_BC1                     0xFF04
 274 #define MC_FIFO_STAT                    0xFF05
 275 #define MC_FIFO_MODE                    0xFF06
 276 #define MC_FIFO_RD_PTR0                 0xFF07
 277 #define MC_FIFO_RD_PTR1                 0xFF08
 278 #define MC_DMA_CTL                      0xFF10
 279 #define MC_DMA_TC0                      0xFF11
 280 #define MC_DMA_TC1                      0xFF12
 281 #define MC_DMA_TC2                      0xFF13
 282 #define MC_DMA_TC3                      0xFF14
 283 #define MC_DMA_RST                      0xFF15
 284
 285 #define RBUF_SIZE_MASK                  0xFBFF
 286 #define RBUF_BASE                       0xF000
 287 #define PPBUF_BASE1                     0xF800
 288 #define PPBUF_BASE2                     0xFA00
 289
 290 /* internal register value macros */
 291 #define POWER_OFF                       0x03
 292 #define PARTIAL_POWER_ON                0x02
 293 #define POWER_ON                        0x00
 294 #define POWER_MASK                      0x03
 295 #define LDO3318_PWR_MASK                0x0C
 296 #define LDO_ON                          0x00
 297 #define LDO_SUSPEND                     0x08
 298 #define LDO_OFF                         0x0C
 299 #define DV3318_AUTO_PWR_OFF             0x10
 300 #define FORCE_LDO_POWERB                0x60
 301
 302 /* LDO_POWER_CFG */
 303 #define TUNE_SD18_MASK                  0x1C
 304 #define TUNE_SD18_1V7                   0x00
 305 #define TUNE_SD18_1V8                   (0x01 << 2)
 306 #define TUNE_SD18_1V9                   (0x02 << 2)
 307 #define TUNE_SD18_2V0                   (0x03 << 2)
 308 #define TUNE_SD18_2V7                   (0x04 << 2)
 309 #define TUNE_SD18_2V8                   (0x05 << 2)
 310 #define TUNE_SD18_2V9                   (0x06 << 2)
 311 #define TUNE_SD18_3V3                   (0x07 << 2)
 312
 313 /* CLK_DIV */
 314 #define CLK_CHANGE                      0x80
 315 #define CLK_DIV_1                       0x00
 316 #define CLK_DIV_2                       0x01
 317 #define CLK_DIV_4                       0x02
 318 #define CLK_DIV_8                       0x03
 319
 320 #define SSC_POWER_MASK                  0x01
 321 #define SSC_POWER_DOWN                  0x01
 322 #define SSC_POWER_ON                    0x00
 323
 324 #define FPGA_VER                        0x80
 325 #define HW_VER_MASK                     0x0F
 326
 327 #define EXTEND_DMA1_ASYNC_SIGNAL        0x02
 328
 329 /* CFG_MODE*/
 330 #define XTAL_FREE                       0x80
 331 #define CLK_MODE_MASK                   0x03
 332 #define CLK_MODE_12M_XTAL               0x00
 333 #define CLK_MODE_NON_XTAL               0x01
 334 #define CLK_MODE_24M_OSC                0x02
 335 #define CLK_MODE_48M_OSC                0x03
 336
 337 /* CFG_MODE_1*/
 338 #define RTS5179                         0x02
 339
 340 #define NYET_EN                         0x01
 341 #define NYET_MSAK                       0x01
 342
 343 #define SD30_DRIVE_MASK                 0x07
 344 #define SD20_DRIVE_MASK                 0x03
 345
 346 #define DISABLE_SD_CD                   0x08
 347 #define DISABLE_MS_CD                   0x10
 348 #define DISABLE_XD_CD                   0x20
 349 #define SD_CD_DEGLITCH_EN               0x01
 350 #define MS_CD_DEGLITCH_EN               0x02
 351 #define XD_CD_DEGLITCH_EN               0x04
 352
 353 #define CARD_SHARE_LQFP48               0x04
 354 #define CARD_SHARE_QFN24                0x00
 355 #define CARD_SHARE_LQFP_SEL             0x04
 356 #define CARD_SHARE_XD                   0x00
 357 #define CARD_SHARE_SD                   0x01
 358 #define CARD_SHARE_MS                   0x02
 359 #define CARD_SHARE_MASK                 0x03
 360
 361
 362 /* SD30_DRIVE_SEL */
 363 #define DRIVER_TYPE_A                   0x05
 364 #define DRIVER_TYPE_B                   0x03
 365 #define DRIVER_TYPE_C                   0x02
 366 #define DRIVER_TYPE_D                   0x01
 367
 368 /* SD_BUS_STAT */
 369 #define SD_CLK_TOGGLE_EN                0x80
 370 #define SD_CLK_FORCE_STOP               0x40
 371 #define SD_DAT3_STATUS                  0x10
 372 #define SD_DAT2_STATUS                  0x08
 373 #define SD_DAT1_STATUS                  0x04
 374 #define SD_DAT0_STATUS                  0x02
 375 #define SD_CMD_STATUS                   0x01
 376
 377 /* SD_PAD_CTL */
 378 #define SD_IO_USING_1V8                 0x80
 379 #define SD_IO_USING_3V3                 0x7F
 380 #define TYPE_A_DRIVING                  0x00
 381 #define TYPE_B_DRIVING                  0x01
 382 #define TYPE_C_DRIVING                  0x02
 383 #define TYPE_D_DRIVING                  0x03
 384
 385 /* CARD_CLK_EN */
 386 #define SD_CLK_EN                       0x04
 387 #define MS_CLK_EN                       0x08
 388
 389 /* CARD_SELECT */
 390 #define SD_MOD_SEL                      2
 391 #define MS_MOD_SEL                      3
 392
 393 /* CARD_SHARE_MODE */
 394 #define CARD_SHARE_LQFP48               0x04
 395 #define CARD_SHARE_QFN24                0x00
 396 #define CARD_SHARE_LQFP_SEL             0x04
 397 #define CARD_SHARE_XD                   0x00
 398 #define CARD_SHARE_SD                   0x01
 399 #define CARD_SHARE_MS                   0x02
 400 #define CARD_SHARE_MASK                 0x03
 401
 402 /* SSC_CTL1 */
 403 #define SSC_RSTB                        0x80
 404 #define SSC_8X_EN                       0x40
 405 #define SSC_FIX_FRAC                    0x20
 406 #define SSC_SEL_1M                      0x00
 407 #define SSC_SEL_2M                      0x08
 408 #define SSC_SEL_4M                      0x10
 409 #define SSC_SEL_8M                      0x18
 410
 411 /* SSC_CTL2 */
 412 #define SSC_DEPTH_MASK                  0x03
 413 #define SSC_DEPTH_DISALBE               0x00
 414 #define SSC_DEPTH_2M                    0x01
 415 #define SSC_DEPTH_1M                    0x02
 416 #define SSC_DEPTH_512K                  0x03
 417
 418 /* SD_VPCLK0_CTL */
 419 #define PHASE_CHANGE                    0x80
 420 #define PHASE_NOT_RESET                 0x40
 421
 422 /* SD_TRANSFER */
 423 #define SD_TRANSFER_START               0x80
 424 #define SD_TRANSFER_END                 0x40
 425 #define SD_STAT_IDLE                    0x20
 426 #define SD_TRANSFER_ERR                 0x10
 427 #define SD_TM_NORMAL_WRITE              0x00
 428 #define SD_TM_AUTO_WRITE_3              0x01
 429 #define SD_TM_AUTO_WRITE_4              0x02
 430 #define SD_TM_AUTO_READ_3               0x05
 431 #define SD_TM_AUTO_READ_4               0x06
 432 #define SD_TM_CMD_RSP                   0x08
 433 #define SD_TM_AUTO_WRITE_1              0x09
 434 #define SD_TM_AUTO_WRITE_2              0x0A
 435 #define SD_TM_NORMAL_READ               0x0C
 436 #define SD_TM_AUTO_READ_1               0x0D
 437 #define SD_TM_AUTO_READ_2               0x0E
 438 #define SD_TM_AUTO_TUNING               0x0F
 439
 440 /* SD_CFG1 */
 441 #define SD_CLK_DIVIDE_0                 0x00
 442 #define SD_CLK_DIVIDE_256               0xC0
 443 #define SD_CLK_DIVIDE_128               0x80
 444 #define SD_CLK_DIVIDE_MASK              0xC0
 445 #define SD_BUS_WIDTH_1BIT               0x00
 446 #define SD_BUS_WIDTH_4BIT               0x01
 447 #define SD_BUS_WIDTH_8BIT               0x02
 448 #define SD_ASYNC_FIFO_RST               0x10
 449 #define SD_20_MODE                      0x00
 450 #define SD_DDR_MODE                     0x04
 451 #define SD_30_MODE                      0x08
 452
 453 /* SD_CFG2 */
 454 #define SD_CALCULATE_CRC7               0x00
 455 #define SD_NO_CALCULATE_CRC7            0x80
 456 #define SD_CHECK_CRC16                  0x00
 457 #define SD_NO_CHECK_CRC16               0x40
 458 #define SD_WAIT_CRC_TO_EN               0x20
 459 #define SD_WAIT_BUSY_END                0x08
 460 #define SD_NO_WAIT_BUSY_END             0x00
 461 #define SD_CHECK_CRC7                   0x00
 462 #define SD_NO_CHECK_CRC7                0x04
 463 #define SD_RSP_LEN_0                    0x00
 464 #define SD_RSP_LEN_6                    0x01
 465 #define SD_RSP_LEN_17                   0x02
 466 #define SD_RSP_TYPE_R0                  0x04
 467 #define SD_RSP_TYPE_R1                  0x01
 468 #define SD_RSP_TYPE_R1b                 0x09
 469 #define SD_RSP_TYPE_R2                  0x02
 470 #define SD_RSP_TYPE_R3                  0x05
 471 #define SD_RSP_TYPE_R4                  0x05
 472 #define SD_RSP_TYPE_R5                  0x01
 473 #define SD_RSP_TYPE_R6                  0x01
 474 #define SD_RSP_TYPE_R7                  0x01
 475
 476 /* SD_STAT1 */
 477 #define SD_CRC7_ERR                     0x80
 478 #define SD_CRC16_ERR                    0x40
 479 #define SD_CRC_WRITE_ERR                0x20
 480 #define SD_CRC_WRITE_ERR_MASK           0x1C
 481 #define GET_CRC_TIME_OUT                0x02
 482 #define SD_TUNING_COMPARE_ERR           0x01
 483
 484 /* SD_DATA_STATE */
 485 #define SD_DATA_IDLE                    0x80
 486
 487 /* CARD_DATA_SOURCE */
 488 #define PINGPONG_BUFFER                 0x01
 489 #define RING_BUFFER                     0x00
 490
 491 /* CARD_OE */
 492 #define SD_OUTPUT_EN                    0x04
 493 #define MS_OUTPUT_EN                    0x08
 494
 495 /* CARD_STOP */
 496 #define SD_STOP                         0x04
 497 #define MS_STOP                         0x08
 498 #define SD_CLR_ERR                      0x40
 499 #define MS_CLR_ERR                      0x80
 500
 501 /* CARD_CLK_SOURCE */
 502 #define CRC_FIX_CLK                     (0x00 << 0)
 503 #define CRC_VAR_CLK0                    (0x01 << 0)
 504 #define CRC_VAR_CLK1                    (0x02 << 0)
 505 #define SD30_FIX_CLK                    (0x00 << 2)
 506 #define SD30_VAR_CLK0                   (0x01 << 2)
 507 #define SD30_VAR_CLK1                   (0x02 << 2)
 508 #define SAMPLE_FIX_CLK                  (0x00 << 4)
 509 #define SAMPLE_VAR_CLK0                 (0x01 << 4)
 510 #define SAMPLE_VAR_CLK1                 (0x02 << 4)
 511
 512 /* SD_SAMPLE_POINT_CTL */
 513 #define DDR_FIX_RX_DAT                  0x00
 514 #define DDR_VAR_RX_DAT                  0x80
 515 #define DDR_FIX_RX_DAT_EDGE             0x00
 516 #define DDR_FIX_RX_DAT_14_DELAY         0x40
 517 #define DDR_FIX_RX_CMD                  0x00
 518 #define DDR_VAR_RX_CMD                  0x20
 519 #define DDR_FIX_RX_CMD_POS_EDGE         0x00
 520 #define DDR_FIX_RX_CMD_14_DELAY         0x10
 521 #define SD20_RX_POS_EDGE                0x00
 522 #define SD20_RX_14_DELAY                0x08
 523 #define SD20_RX_SEL_MASK                0x08
 524
 525 /* SD_PUSH_POINT_CTL */
 526 #define DDR_FIX_TX_CMD_DAT              0x00
 527 #define DDR_VAR_TX_CMD_DAT              0x80
 528 #define DDR_FIX_TX_DAT_14_TSU           0x00
 529 #define DDR_FIX_TX_DAT_12_TSU           0x40
 530 #define DDR_FIX_TX_CMD_NEG_EDGE         0x00
 531 #define DDR_FIX_TX_CMD_14_AHEAD         0x20
 532 #define SD20_TX_NEG_EDGE                0x00
 533 #define SD20_TX_14_AHEAD                0x10
 534 #define SD20_TX_SEL_MASK                0x10
 535 #define DDR_VAR_SDCLK_POL_SWAP          0x01
 536
 537 /* MS_CFG */
 538 #define SAMPLE_TIME_RISING              0x00
 539 #define SAMPLE_TIME_FALLING             0x80
 540 #define PUSH_TIME_DEFAULT               0x00
 541 #define PUSH_TIME_ODD                   0x40
 542 #define NO_EXTEND_TOGGLE                0x00
 543 #define EXTEND_TOGGLE_CHK               0x20
 544 #define MS_BUS_WIDTH_1                  0x00
 545 #define MS_BUS_WIDTH_4                  0x10
 546 #define MS_BUS_WIDTH_8                  0x18
 547 #define MS_2K_SECTOR_MODE               0x04
 548 #define MS_512_SECTOR_MODE              0x00
 549 #define MS_TOGGLE_TIMEOUT_EN            0x00
 550 #define MS_TOGGLE_TIMEOUT_DISEN         0x01
 551 #define MS_NO_CHECK_INT                 0x02
 552
 553 /* MS_TRANS_CFG */
 554 #define WAIT_INT                        0x80
 555 #define NO_WAIT_INT                     0x00
 556 #define NO_AUTO_READ_INT_REG            0x00
 557 #define AUTO_READ_INT_REG               0x40
 558 #define MS_CRC16_ERR                    0x20
 559 #define MS_RDY_TIMEOUT                  0x10
 560 #define MS_INT_CMDNK                    0x08
 561 #define MS_INT_BREQ                     0x04
 562 #define MS_INT_ERR                      0x02
 563 #define MS_INT_CED                      0x01
 564
 565 /* MS_TRANSFER */
 566 #define MS_TRANSFER_START               0x80
 567 #define MS_TRANSFER_END                 0x40
 568 #define MS_TRANSFER_ERR                 0x20
 569 #define MS_BS_STATE                     0x10
 570 #define MS_TM_READ_BYTES                0x00
 571 #define MS_TM_NORMAL_READ               0x01
 572 #define MS_TM_WRITE_BYTES               0x04
 573 #define MS_TM_NORMAL_WRITE              0x05
 574 #define MS_TM_AUTO_READ                 0x08
 575 #define MS_TM_AUTO_WRITE                0x0C
 576 #define MS_TM_SET_CMD                   0x06
 577 #define MS_TM_COPY_PAGE                 0x07
 578 #define MS_TM_MULTI_READ                0x02
 579 #define MS_TM_MULTI_WRITE               0x03
 580
 581 /* MC_FIFO_CTL */
 582 #define FIFO_FLUSH                      0x01
 583
 584 /* MC_DMA_RST */
 585 #define DMA_RESET  0x01
 586
 587 /* MC_DMA_CTL */
 588 #define DMA_TC_EQ_0                     0x80
 589 #define DMA_DIR_TO_CARD                 0x00
 590 #define DMA_DIR_FROM_CARD               0x02
 591 #define DMA_EN                          0x01
 592 #define DMA_128                         (0 << 2)
 593 #define DMA_256                         (1 << 2)
 594 #define DMA_512                         (2 << 2)
 595 #define DMA_1024                        (3 << 2)
 596 #define DMA_PACK_SIZE_MASK              0x0C
 597
 598 /* CARD_INT_PEND */
 599 #define XD_INT                          0x10
 600 #define MS_INT                          0x08
 601 #define SD_INT                          0x04
 602
 603 /* LED operations*/
 604 static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
 605 {
 606         return  rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
 607 }
 608
 609 static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
 610 {
 611         return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
 612 }
 613
 614 /* HW error clearing */
 615 static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
 616 {
 617         rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
 618 }
 619
 620 static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
 621 {
 622         rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
 623                         FIFO_FLUSH, FIFO_FLUSH);
 624         rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
 625 }
 626 #endif /* __RTS51139_H */