1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
10 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
12 /* SDW Broadcast Device Number */
13 #define SDW_BROADCAST_DEV_NUM 15
15 /* SDW Enumeration Device Number */
16 #define SDW_ENUM_DEV_NUM 0
18 /* SDW Group Device Numbers */
19 #define SDW_GROUP12_DEV_NUM 12
20 #define SDW_GROUP13_DEV_NUM 13
22 /* SDW Master Device Number, not supported yet */
23 #define SDW_MASTER_DEV_NUM 14
25 #define SDW_NUM_DEV_ID_REGISTERS 6
26 /* frame shape defines */
29 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
30 * fill hole with 0, one more dummy entry is added
32 #define SDW_FRAME_ROWS 24
33 #define SDW_FRAME_COLS 8
34 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
36 #define SDW_FRAME_CTRL_BITS 48
37 #define SDW_MAX_DEVICES 11
39 #define SDW_VALID_PORT_RANGE(n) (n <= 14 && n >= 1)
41 #define SDW_DAI_ID_RANGE_START 100
42 #define SDW_DAI_ID_RANGE_END 200
45 * enum sdw_slave_status - Slave status
46 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
47 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
48 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
49 * @SDW_SLAVE_RESERVED: Reserved for future use
51 enum sdw_slave_status {
52 SDW_SLAVE_UNATTACHED = 0,
53 SDW_SLAVE_ATTACHED = 1,
55 SDW_SLAVE_RESERVED = 3,
59 * enum sdw_command_response - Command response as defined by SDW spec
60 * @SDW_CMD_OK: cmd was successful
61 * @SDW_CMD_IGNORED: cmd was ignored
62 * @SDW_CMD_FAIL: cmd was NACKed
63 * @SDW_CMD_TIMEOUT: cmd timedout
64 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
66 * NOTE: The enum is different than actual Spec as response in the Spec is
67 * combination of ACK/NAK bits
69 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
71 enum sdw_command_response {
76 SDW_CMD_FAIL_OTHER = 4,
80 * enum sdw_stream_type: data stream type
82 * @SDW_STREAM_PCM: PCM data stream
83 * @SDW_STREAM_PDM: PDM data stream
85 * spec doesn't define this, but is used in implementation
87 enum sdw_stream_type {
93 * enum sdw_data_direction: Data direction
95 * @SDW_DATA_DIR_RX: Data into Port
96 * @SDW_DATA_DIR_TX: Data out of Port
98 enum sdw_data_direction {
104 * SDW properties, defined in MIPI DisCo spec v1.0
106 enum sdw_clk_stop_reset_behave {
107 SDW_CLK_STOP_KEEP_STATUS = 1,
111 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
113 * @SDW_P15_READ_IGNORED: Read is ignored
114 * @SDW_P15_CMD_OK: Command is ok
116 enum sdw_p15_behave {
117 SDW_P15_READ_IGNORED = 0,
122 * enum sdw_dpn_type - Data port types
123 * @SDW_DPN_FULL: Full Data Port is supported
124 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
125 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
126 * are not implemented.
127 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
128 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
137 * enum sdw_clk_stop_mode - Clock Stop modes
138 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
140 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
141 * not capable of continuing operation seamlessly when the clock restarts
143 enum sdw_clk_stop_mode {
144 SDW_CLK_STOP_MODE0 = 0,
145 SDW_CLK_STOP_MODE1 = 1,
149 * struct sdw_dp0_prop - DP0 properties
150 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
152 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
154 * @num_words: number of wordlengths supported
155 * @words: wordlengths supported
156 * @flow_controlled: Slave implementation results in an OK_NotReady
158 * @simple_ch_prep_sm: If channel prepare sequence is required
159 * @device_interrupts: If implementation-defined interrupts are supported
161 * The wordlengths are specified by Spec as max, min AND number of
162 * discrete values, implementation can define based on the wordlengths they
165 struct sdw_dp0_prop {
170 bool flow_controlled;
171 bool simple_ch_prep_sm;
172 bool device_interrupts;
176 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
177 * @bus_min_freq: Minimum bus frequency, in Hz
178 * @bus_max_freq: Maximum bus frequency, in Hz
179 * @bus_num_freq: Number of discrete frequencies supported
180 * @bus_freq: Discrete bus frequencies, in Hz
181 * @min_freq: Minimum sampling frequency, in Hz
182 * @max_freq: Maximum sampling bus frequency, in Hz
183 * @num_freq: Number of discrete sampling frequency supported
184 * @freq: Discrete sampling frequencies, in Hz
185 * @prep_ch_behave: Specifies the dependencies between Channel Prepare
186 * sequence and bus clock configuration
187 * If 0, Channel Prepare can happen at any Bus clock rate
188 * If 1, Channel Prepare sequence shall happen only after Bus clock is
189 * changed to a frequency supported by this mode or compatible modes
190 * described by the next field
191 * @glitchless: Bitmap describing possible glitchless transitions from this
192 * Audio Mode to other Audio Modes
194 struct sdw_dpn_audio_mode {
208 * struct sdw_dpn_prop - Data Port DPn properties
210 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
212 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
214 * @num_words: Number of discrete supported wordlengths
215 * @words: Discrete supported wordlength
216 * @type: Data port type. Full, Simplified or Reduced
217 * @max_grouping: Maximum number of samples that can be grouped together for
219 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
221 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
222 * @device_interrupts: If set, each bit corresponds to support for
223 * implementation-defined interrupts
224 * @max_ch: Maximum channels supported
225 * @min_ch: Minimum channels supported
226 * @num_ch: Number of discrete channels supported
227 * @ch: Discrete channels supported
228 * @num_ch_combinations: Number of channel combinations supported
229 * @ch_combinations: Channel combinations supported
230 * @modes: SDW mode supported
231 * @max_async_buffer: Number of samples that this port can buffer in
233 * @block_pack_mode: Type of block port mode supported
234 * @port_encoding: Payload Channel Sample encoding schemes supported
235 * @audio_modes: Audio modes supported
237 struct sdw_dpn_prop {
243 enum sdw_dpn_type type;
245 bool simple_ch_prep_sm;
247 u32 device_interrupts;
252 u32 num_ch_combinations;
253 u32 *ch_combinations;
255 u32 max_async_buffer;
256 bool block_pack_mode;
258 struct sdw_dpn_audio_mode *audio_modes;
262 * struct sdw_slave_prop - SoundWire Slave properties
263 * @mipi_revision: Spec version of the implementation
264 * @wake_capable: Wake-up events are supported
265 * @test_mode_capable: If test mode is supported
266 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
267 * @simple_clk_stop_capable: Simple clock mode is supported
268 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
269 * Machine transitions, in milliseconds
270 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
271 * transitions, in milliseconds
272 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
273 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
274 * @high_PHY_capable: Slave is HighPHY capable
275 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
277 * @bank_delay_support: Slave implements bank delay/bridge support registers
278 * SCP_BankDelay and SCP_NextFrame
279 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
281 * @lane_control_support: Slave supports lane control
282 * @master_count: Number of Masters present on this Slave
283 * @source_ports: Bitmap identifying source ports
284 * @sink_ports: Bitmap identifying sink ports
285 * @dp0_prop: Data Port 0 properties
286 * @src_dpn_prop: Source Data Port N properties
287 * @sink_dpn_prop: Sink Data Port N properties
289 struct sdw_slave_prop {
292 bool test_mode_capable;
294 bool simple_clk_stop_capable;
295 u32 clk_stop_timeout;
297 enum sdw_clk_stop_reset_behave reset_behave;
298 bool high_PHY_capable;
300 bool bank_delay_support;
301 enum sdw_p15_behave p15_behave;
302 bool lane_control_support;
306 struct sdw_dp0_prop *dp0_prop;
307 struct sdw_dpn_prop *src_dpn_prop;
308 struct sdw_dpn_prop *sink_dpn_prop;
312 * struct sdw_master_prop - Master properties
313 * @revision: MIPI spec version of the implementation
314 * @master_count: Number of masters
315 * @clk_stop_mode: Bitmap for Clock Stop modes supported
316 * @max_freq: Maximum Bus clock frequency, in Hz
317 * @num_clk_gears: Number of clock gears supported
318 * @clk_gears: Clock gears supported
319 * @num_freq: Number of clock frequencies supported, in Hz
320 * @freq: Clock frequencies supported, in Hz
321 * @default_frame_rate: Controller default Frame rate, in Hz
322 * @default_row: Number of rows
323 * @default_col: Number of columns
324 * @dynamic_frame: Dynamic frame supported
325 * @err_threshold: Number of times that software may retry sending a single
327 * @dpn_prop: Data Port N properties
329 struct sdw_master_prop {
332 enum sdw_clk_stop_mode clk_stop_mode;
338 u32 default_frame_rate;
343 struct sdw_dpn_prop *dpn_prop;
346 int sdw_master_read_prop(struct sdw_bus *bus);
347 int sdw_slave_read_prop(struct sdw_slave *slave);
350 * SDW Slave Structures and APIs
354 * struct sdw_slave_id - Slave ID
355 * @mfg_id: MIPI Manufacturer ID
356 * @part_id: Device Part ID
357 * @class_id: MIPI Class ID, unused now.
358 * Currently a placeholder in MIPI SoundWire Spec
359 * @unique_id: Device unique ID
360 * @sdw_version: SDW version implemented
362 * The order of the IDs here does not follow the DisCo spec definitions
364 struct sdw_slave_id {
373 * struct sdw_slave_intr_status - Slave interrupt status
374 * @control_port: control port status
375 * @port: data port status
377 struct sdw_slave_intr_status {
383 * sdw_reg_bank - SoundWire register banks
384 * @SDW_BANK0: Soundwire register bank 0
385 * @SDW_BANK1: Soundwire register bank 1
393 * struct sdw_bus_conf: Bus configuration
395 * @clk_freq: Clock frequency, in Hz
396 * @num_rows: Number of rows in frame
397 * @num_cols: Number of columns in frame
398 * @bank: Next register bank
400 struct sdw_bus_conf {
401 unsigned int clk_freq;
402 unsigned int num_rows;
403 unsigned int num_cols;
408 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
411 * @ch_mask: Active channel mask
412 * @prepare: Prepare (true) /de-prepare (false) channel
413 * @bank: Register bank, which bank Slave/Master driver should program for
414 * implementation defined registers. This is always updated to next_bank
415 * value read from bus params.
418 struct sdw_prepare_ch {
420 unsigned int ch_mask;
426 * enum sdw_port_prep_ops: Prepare operations for Data Port
428 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
429 * @SDW_OPS_PORT_PREP: Prepare operation for the Port
430 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
432 enum sdw_port_prep_ops {
433 SDW_OPS_PORT_PRE_PREP = 0,
434 SDW_OPS_PORT_PREP = 1,
435 SDW_OPS_PORT_POST_PREP = 2,
439 * struct sdw_bus_params: Structure holding bus configuration
441 * @curr_bank: Current bank in use (BANK0/BANK1)
442 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
444 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
445 * @curr_dr_freq: Current double rate clock frequency, in Hz
446 * @bandwidth: Current bandwidth
447 * @col: Active columns
450 struct sdw_bus_params {
451 enum sdw_reg_bank curr_bank;
452 enum sdw_reg_bank next_bank;
453 unsigned int max_dr_freq;
454 unsigned int curr_dr_freq;
455 unsigned int bandwidth;
461 * struct sdw_slave_ops: Slave driver callback ops
463 * @read_prop: Read Slave properties
464 * @interrupt_callback: Device interrupt notification (invoked in thread
466 * @update_status: Update Slave status
467 * @bus_config: Update the bus config for Slave
468 * @port_prep: Prepare the port with parameters
470 struct sdw_slave_ops {
471 int (*read_prop)(struct sdw_slave *sdw);
472 int (*interrupt_callback)(struct sdw_slave *slave,
473 struct sdw_slave_intr_status *status);
474 int (*update_status)(struct sdw_slave *slave,
475 enum sdw_slave_status status);
476 int (*bus_config)(struct sdw_slave *slave,
477 struct sdw_bus_params *params);
478 int (*port_prep)(struct sdw_slave *slave,
479 struct sdw_prepare_ch *prepare_ch,
480 enum sdw_port_prep_ops pre_ops);
484 * struct sdw_slave - SoundWire Slave
485 * @id: MIPI device ID
487 * @status: Status reported by the Slave
489 * @ops: Slave callback ops
490 * @prop: Slave properties
491 * @node: node for bus list
492 * @port_ready: Port ready completion flag for each Slave port
493 * @dev_num: Device Number assigned by Bus
496 struct sdw_slave_id id;
498 enum sdw_slave_status status;
500 const struct sdw_slave_ops *ops;
501 struct sdw_slave_prop prop;
502 struct list_head node;
503 struct completion *port_ready;
507 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
512 int (*probe)(struct sdw_slave *sdw,
513 const struct sdw_device_id *id);
514 int (*remove)(struct sdw_slave *sdw);
515 void (*shutdown)(struct sdw_slave *sdw);
517 const struct sdw_device_id *id_table;
518 const struct sdw_slave_ops *ops;
520 struct device_driver driver;
523 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
524 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
525 .driver_data = (unsigned long)(_drv_data) }
527 int sdw_handle_slave_status(struct sdw_bus *bus,
528 enum sdw_slave_status status[]);
531 * SDW master structures and APIs
535 * struct sdw_port_params: Data Port parameters
538 * @bps: Word length of the Port
539 * @flow_mode: Port Data flow mode
540 * @data_mode: Test modes or normal mode
542 * This is used to program the Data Port based on Data Port stream
545 struct sdw_port_params {
548 unsigned int flow_mode;
549 unsigned int data_mode;
553 * struct sdw_transport_params: Data Port Transport Parameters
555 * @blk_grp_ctrl_valid: Port implements block group control
557 * @blk_grp_ctrl: Block group control value
558 * @sample_interval: Sample interval
559 * @offset1: Blockoffset of the payload data
560 * @offset2: Blockoffset of the payload data
561 * @hstart: Horizontal start of the payload data
562 * @hstop: Horizontal stop of the payload data
563 * @blk_pkg_mode: Block per channel or block per port
564 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
565 * data lane is supported in bus
567 * This is used to program the Data Port based on Data Port transport
568 * parameters. All these parameters are banked and can be modified
569 * during a bank switch without any artifacts in audio stream.
571 struct sdw_transport_params {
572 bool blk_grp_ctrl_valid;
573 unsigned int port_num;
574 unsigned int blk_grp_ctrl;
575 unsigned int sample_interval;
576 unsigned int offset1;
577 unsigned int offset2;
580 unsigned int blk_pkg_mode;
581 unsigned int lane_ctrl;
585 * struct sdw_enable_ch: Enable/disable Data Port channel
588 * @ch_mask: Active channel mask
589 * @enable: Enable (true) /disable (false) channel
591 struct sdw_enable_ch {
592 unsigned int port_num;
593 unsigned int ch_mask;
598 * struct sdw_master_port_ops: Callback functions from bus to Master
599 * driver to set Master Data ports.
601 * @dpn_set_port_params: Set the Port parameters for the Master Port.
603 * @dpn_set_port_transport_params: Set transport parameters for the Master
604 * Port. Mandatory callback
605 * @dpn_port_prep: Port prepare operations for the Master Data Port.
606 * @dpn_port_enable_ch: Enable the channels of Master Port.
608 struct sdw_master_port_ops {
609 int (*dpn_set_port_params)(struct sdw_bus *bus,
610 struct sdw_port_params *port_params,
612 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
613 struct sdw_transport_params *transport_params,
614 enum sdw_reg_bank bank);
615 int (*dpn_port_prep)(struct sdw_bus *bus,
616 struct sdw_prepare_ch *prepare_ch);
617 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
618 struct sdw_enable_ch *enable_ch, unsigned int bank);
624 * struct sdw_defer - SDW deffered message
625 * @length: message length
626 * @complete: message completion
631 struct completion complete;
636 * struct sdw_master_ops - Master driver ops
637 * @read_prop: Read Master properties
638 * @xfer_msg: Transfer message callback
639 * @xfer_msg_defer: Defer version of transfer message callback
640 * @reset_page_addr: Reset the SCP page address registers
641 * @set_bus_conf: Set the bus configuration
642 * @pre_bank_switch: Callback for pre bank switch
643 * @post_bank_switch: Callback for post bank switch
645 struct sdw_master_ops {
646 int (*read_prop)(struct sdw_bus *bus);
648 enum sdw_command_response (*xfer_msg)
649 (struct sdw_bus *bus, struct sdw_msg *msg);
650 enum sdw_command_response (*xfer_msg_defer)
651 (struct sdw_bus *bus, struct sdw_msg *msg,
652 struct sdw_defer *defer);
653 enum sdw_command_response (*reset_page_addr)
654 (struct sdw_bus *bus, unsigned int dev_num);
655 int (*set_bus_conf)(struct sdw_bus *bus,
656 struct sdw_bus_params *params);
657 int (*pre_bank_switch)(struct sdw_bus *bus);
658 int (*post_bank_switch)(struct sdw_bus *bus);
663 * struct sdw_bus - SoundWire bus
664 * @dev: Master linux device
665 * @link_id: Link id number, can be 0 to N, unique for each Master
666 * @slaves: list of Slaves on this bus
667 * @assigned: Bitmap for Slave device numbers.
668 * Bit set implies used number, bit clear implies unused number.
669 * @bus_lock: bus lock
670 * @msg_lock: message lock
671 * @ops: Master callback ops
672 * @port_ops: Master port callback ops
673 * @params: Current bus parameters
674 * @prop: Master properties
675 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
676 * is used to compute and program bus bandwidth, clock, frame shape,
677 * transport and port parameters
678 * @defer_msg: Defer message
679 * @clk_stop_timeout: Clock stop timeout computed
680 * @bank_switch_timeout: Bank switch timeout computed
684 unsigned int link_id;
685 struct list_head slaves;
686 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
687 struct mutex bus_lock;
688 struct mutex msg_lock;
689 const struct sdw_master_ops *ops;
690 const struct sdw_master_port_ops *port_ops;
691 struct sdw_bus_params params;
692 struct sdw_master_prop prop;
693 struct list_head m_rt_list;
694 struct sdw_defer defer_msg;
695 unsigned int clk_stop_timeout;
696 u32 bank_switch_timeout;
699 int sdw_add_bus_master(struct sdw_bus *bus);
700 void sdw_delete_bus_master(struct sdw_bus *bus);
703 * sdw_port_config: Master or Slave Port configuration
706 * @ch_mask: channels mask for port
708 struct sdw_port_config {
710 unsigned int ch_mask;
714 * sdw_stream_config: Master or Slave stream configuration
716 * @frame_rate: Audio frame rate of the stream, in Hz
717 * @ch_count: Channel count of the stream
718 * @bps: Number of bits per audio sample
719 * @direction: Data direction
720 * @type: Stream type PCM or PDM
722 struct sdw_stream_config {
723 unsigned int frame_rate;
724 unsigned int ch_count;
726 enum sdw_data_direction direction;
727 enum sdw_stream_type type;
731 * sdw_stream_state: Stream states
733 * @SDW_STREAM_ALLOCATED: New stream allocated.
734 * @SDW_STREAM_CONFIGURED: Stream configured
735 * @SDW_STREAM_PREPARED: Stream prepared
736 * @SDW_STREAM_ENABLED: Stream enabled
737 * @SDW_STREAM_DISABLED: Stream disabled
738 * @SDW_STREAM_DEPREPARED: Stream de-prepared
739 * @SDW_STREAM_RELEASED: Stream released
741 enum sdw_stream_state {
742 SDW_STREAM_ALLOCATED = 0,
743 SDW_STREAM_CONFIGURED = 1,
744 SDW_STREAM_PREPARED = 2,
745 SDW_STREAM_ENABLED = 3,
746 SDW_STREAM_DISABLED = 4,
747 SDW_STREAM_DEPREPARED = 5,
748 SDW_STREAM_RELEASED = 6,
752 * sdw_stream_params: Stream parameters
754 * @rate: Sampling frequency, in Hz
755 * @ch_count: Number of channels
756 * @bps: bits per channel sample
758 struct sdw_stream_params {
760 unsigned int ch_count;
765 * sdw_stream_runtime: Runtime stream parameters
767 * @name: SoundWire stream name
768 * @params: Stream parameters
769 * @state: Current state of the stream
770 * @type: Stream type PCM or PDM
771 * @m_rt: Master runtime
773 struct sdw_stream_runtime {
775 struct sdw_stream_params params;
776 enum sdw_stream_state state;
777 enum sdw_stream_type type;
778 struct sdw_master_runtime *m_rt;
781 struct sdw_stream_runtime *sdw_alloc_stream(char *stream_name);
782 void sdw_release_stream(struct sdw_stream_runtime *stream);
783 int sdw_stream_add_master(struct sdw_bus *bus,
784 struct sdw_stream_config *stream_config,
785 struct sdw_port_config *port_config,
786 unsigned int num_ports,
787 struct sdw_stream_runtime *stream);
788 int sdw_stream_add_slave(struct sdw_slave *slave,
789 struct sdw_stream_config *stream_config,
790 struct sdw_port_config *port_config,
791 unsigned int num_ports,
792 struct sdw_stream_runtime *stream);
793 int sdw_stream_remove_master(struct sdw_bus *bus,
794 struct sdw_stream_runtime *stream);
795 int sdw_stream_remove_slave(struct sdw_slave *slave,
796 struct sdw_stream_runtime *stream);
797 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
798 int sdw_enable_stream(struct sdw_stream_runtime *stream);
799 int sdw_disable_stream(struct sdw_stream_runtime *stream);
800 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
802 /* messaging and data APIs */
804 int sdw_read(struct sdw_slave *slave, u32 addr);
805 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
806 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
807 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
809 #endif /* __SOUNDWIRE_H */