2 * Copyright (C) 2005 David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
18 #include <linux/device.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/slab.h>
21 #include <linux/kthread.h>
22 #include <linux/completion.h>
23 #include <linux/scatterlist.h>
26 struct property_entry;
27 struct spi_controller;
29 struct spi_flash_read_message;
32 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
33 * and SPI infrastructure.
35 extern struct bus_type spi_bus_type;
38 * struct spi_statistics - statistics for spi transfers
39 * @lock: lock protecting this structure
41 * @messages: number of spi-messages handled
42 * @transfers: number of spi_transfers handled
43 * @errors: number of errors during spi_transfer
44 * @timedout: number of timeouts during spi_transfer
46 * @spi_sync: number of times spi_sync is used
47 * @spi_sync_immediate:
48 * number of times spi_sync is executed immediately
49 * in calling context without queuing and scheduling
50 * @spi_async: number of times spi_async is used
52 * @bytes: number of bytes transferred to/from device
53 * @bytes_tx: number of bytes sent to device
54 * @bytes_rx: number of bytes received from device
56 * @transfer_bytes_histo:
57 * transfer bytes histogramm
59 * @transfers_split_maxsize:
60 * number of transfers that have been split because of
63 struct spi_statistics {
64 spinlock_t lock; /* lock for the whole structure */
66 unsigned long messages;
67 unsigned long transfers;
69 unsigned long timedout;
71 unsigned long spi_sync;
72 unsigned long spi_sync_immediate;
73 unsigned long spi_async;
75 unsigned long long bytes;
76 unsigned long long bytes_rx;
77 unsigned long long bytes_tx;
79 #define SPI_STATISTICS_HISTO_SIZE 17
80 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE];
82 unsigned long transfers_split_maxsize;
85 void spi_statistics_add_transfer_stats(struct spi_statistics *stats,
86 struct spi_transfer *xfer,
87 struct spi_controller *ctlr);
89 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \
91 unsigned long flags; \
92 spin_lock_irqsave(&(stats)->lock, flags); \
93 (stats)->field += count; \
94 spin_unlock_irqrestore(&(stats)->lock, flags); \
97 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \
98 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1)
101 * struct spi_device - Controller side proxy for an SPI slave device
102 * @dev: Driver model representation of the device.
103 * @controller: SPI controller used with the device.
104 * @master: Copy of controller, for backwards compatibility.
105 * @max_speed_hz: Maximum clock rate to be used with this chip
106 * (on this board); may be changed by the device's driver.
107 * The spi_transfer.speed_hz can override this for each transfer.
108 * @chip_select: Chipselect, distinguishing chips handled by @controller.
109 * @mode: The spi mode defines how data is clocked out and in.
110 * This may be changed by the device's driver.
111 * The "active low" default for chipselect mode can be overridden
112 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for
113 * each word in a transfer (by specifying SPI_LSB_FIRST).
114 * @bits_per_word: Data transfers involve one or more words; word sizes
115 * like eight or 12 bits are common. In-memory wordsizes are
116 * powers of two bytes (e.g. 20 bit samples use 32 bits).
117 * This may be changed by the device's driver, or left at the
118 * default (0) indicating protocol words are eight bit bytes.
119 * The spi_transfer.bits_per_word can override this for each transfer.
120 * @irq: Negative, or the number passed to request_irq() to receive
121 * interrupts from this device.
122 * @controller_state: Controller's runtime state
123 * @controller_data: Board-specific definitions for controller, such as
124 * FIFO initialization parameters; from board_info.controller_data
125 * @modalias: Name of the driver to use with this device, or an alias
126 * for that name. This appears in the sysfs "modalias" attribute
127 * for driver coldplugging, and in uevents used for hotplugging
128 * @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when
129 * when not using a GPIO line)
131 * @statistics: statistics for the spi_device
133 * A @spi_device is used to interchange data between an SPI slave
134 * (usually a discrete chip) and CPU memory.
136 * In @dev, the platform_data is used to hold information about this
137 * device that's meaningful to the device's protocol driver, but not
138 * to its controller. One example might be an identifier for a chip
139 * variant with slightly different functionality; another might be
140 * information about how this particular board wires the chip's pins.
144 struct spi_controller *controller;
145 struct spi_controller *master; /* compatibility layer */
150 #define SPI_CPHA 0x01 /* clock phase */
151 #define SPI_CPOL 0x02 /* clock polarity */
152 #define SPI_MODE_0 (0|0) /* (original MicroWire) */
153 #define SPI_MODE_1 (0|SPI_CPHA)
154 #define SPI_MODE_2 (SPI_CPOL|0)
155 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
156 #define SPI_CS_HIGH 0x04 /* chipselect active high? */
157 #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
158 #define SPI_3WIRE 0x10 /* SI/SO signals shared */
159 #define SPI_LOOP 0x20 /* loopback mode */
160 #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
161 #define SPI_READY 0x80 /* slave pulls low to pause */
162 #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
163 #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
164 #define SPI_RX_DUAL 0x400 /* receive with 2 wires */
165 #define SPI_RX_QUAD 0x800 /* receive with 4 wires */
167 void *controller_state;
168 void *controller_data;
169 char modalias[SPI_NAME_SIZE];
170 int cs_gpio; /* chip select gpio */
173 struct spi_statistics statistics;
176 * likely need more hooks for more protocol options affecting how
177 * the controller talks to each chip, like:
178 * - memory packing (12 bit samples into low bits, others zeroed)
180 * - drop chipselect after each word
181 * - chipselect delays
186 static inline struct spi_device *to_spi_device(struct device *dev)
188 return dev ? container_of(dev, struct spi_device, dev) : NULL;
191 /* most drivers won't need to care about device refcounting */
192 static inline struct spi_device *spi_dev_get(struct spi_device *spi)
194 return (spi && get_device(&spi->dev)) ? spi : NULL;
197 static inline void spi_dev_put(struct spi_device *spi)
200 put_device(&spi->dev);
203 /* ctldata is for the bus_controller driver's runtime state */
204 static inline void *spi_get_ctldata(struct spi_device *spi)
206 return spi->controller_state;
209 static inline void spi_set_ctldata(struct spi_device *spi, void *state)
211 spi->controller_state = state;
214 /* device driver data */
216 static inline void spi_set_drvdata(struct spi_device *spi, void *data)
218 dev_set_drvdata(&spi->dev, data);
221 static inline void *spi_get_drvdata(struct spi_device *spi)
223 return dev_get_drvdata(&spi->dev);
230 * struct spi_driver - Host side "protocol" driver
231 * @id_table: List of SPI devices supported by this driver
232 * @probe: Binds this driver to the spi device. Drivers can verify
233 * that the device is actually present, and may need to configure
234 * characteristics (such as bits_per_word) which weren't needed for
235 * the initial configuration done during system setup.
236 * @remove: Unbinds this driver from the spi device
237 * @shutdown: Standard shutdown callback used during system state
238 * transitions such as powerdown/halt and kexec
239 * @driver: SPI device drivers should initialize the name and owner
240 * field of this structure.
242 * This represents the kind of device driver that uses SPI messages to
243 * interact with the hardware at the other end of a SPI link. It's called
244 * a "protocol" driver because it works through messages rather than talking
245 * directly to SPI hardware (which is what the underlying SPI controller
246 * driver does to pass those messages). These protocols are defined in the
247 * specification for the device(s) supported by the driver.
249 * As a rule, those device protocols represent the lowest level interface
250 * supported by a driver, and it will support upper level interfaces too.
251 * Examples of such upper levels include frameworks like MTD, networking,
252 * MMC, RTC, filesystem character device nodes, and hardware monitoring.
255 const struct spi_device_id *id_table;
256 int (*probe)(struct spi_device *spi);
257 int (*remove)(struct spi_device *spi);
258 void (*shutdown)(struct spi_device *spi);
259 struct device_driver driver;
262 static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
264 return drv ? container_of(drv, struct spi_driver, driver) : NULL;
267 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv);
270 * spi_unregister_driver - reverse effect of spi_register_driver
271 * @sdrv: the driver to unregister
274 static inline void spi_unregister_driver(struct spi_driver *sdrv)
277 driver_unregister(&sdrv->driver);
280 /* use a define to avoid include chaining to get THIS_MODULE */
281 #define spi_register_driver(driver) \
282 __spi_register_driver(THIS_MODULE, driver)
285 * module_spi_driver() - Helper macro for registering a SPI driver
286 * @__spi_driver: spi_driver struct
288 * Helper macro for SPI drivers which do not do anything special in module
289 * init/exit. This eliminates a lot of boilerplate. Each module may only
290 * use this macro once, and calling it replaces module_init() and module_exit()
292 #define module_spi_driver(__spi_driver) \
293 module_driver(__spi_driver, spi_register_driver, \
294 spi_unregister_driver)
297 * struct spi_controller - interface to SPI master or slave controller
298 * @dev: device interface to this driver
299 * @list: link with the global spi_controller list
300 * @bus_num: board-specific (and often SOC-specific) identifier for a
301 * given SPI controller.
302 * @num_chipselect: chipselects are used to distinguish individual
303 * SPI slaves, and are numbered from zero to num_chipselects.
304 * each slave has a chipselect signal, but it's common that not
305 * every chipselect is connected to a slave.
306 * @dma_alignment: SPI controller constraint on DMA buffers alignment.
307 * @mode_bits: flags understood by this controller driver
308 * @bits_per_word_mask: A mask indicating which values of bits_per_word are
309 * supported by the driver. Bit n indicates that a bits_per_word n+1 is
310 * supported. If set, the SPI core will reject any transfer with an
311 * unsupported bits_per_word. If not set, this value is simply ignored,
312 * and it's up to the individual driver to perform any validation.
313 * @min_speed_hz: Lowest supported transfer speed
314 * @max_speed_hz: Highest supported transfer speed
315 * @flags: other constraints relevant to this driver
316 * @slave: indicates that this is an SPI slave controller
317 * @max_transfer_size: function that returns the max transfer size for
318 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
319 * @max_message_size: function that returns the max message size for
320 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
321 * @io_mutex: mutex for physical bus access
322 * @bus_lock_spinlock: spinlock for SPI bus locking
323 * @bus_lock_mutex: mutex for exclusion of multiple callers
324 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
325 * @setup: updates the device mode and clocking records used by a
326 * device's SPI controller; protocol code may call this. This
327 * must fail if an unrecognized or unsupported mode is requested.
328 * It's always safe to call this unless transfers are pending on
329 * the device whose settings are being modified.
330 * @transfer: adds a message to the controller's transfer queue.
331 * @cleanup: frees controller-specific state
332 * @can_dma: determine whether this controller supports DMA
333 * @queued: whether this controller is providing an internal message queue
334 * @kworker: thread struct for message pump
335 * @kworker_task: pointer to task for message pump kworker thread
336 * @pump_messages: work struct for scheduling work to the message pump
337 * @queue_lock: spinlock to syncronise access to message queue
338 * @queue: message queue
339 * @idling: the device is entering idle state
340 * @cur_msg: the currently in-flight message
341 * @cur_msg_prepared: spi_prepare_message was called for the currently
343 * @cur_msg_mapped: message has been mapped for DMA
344 * @xfer_completion: used by core transfer_one_message()
345 * @busy: message pump is busy
346 * @running: message pump is running
347 * @rt: whether this queue is set to run as a realtime task
348 * @auto_runtime_pm: the core should ensure a runtime PM reference is held
349 * while the hardware is prepared, using the parent
350 * device for the spidev
351 * @max_dma_len: Maximum length of a DMA transfer for the device.
352 * @prepare_transfer_hardware: a message will soon arrive from the queue
353 * so the subsystem requests the driver to prepare the transfer hardware
354 * by issuing this call
355 * @transfer_one_message: the subsystem calls the driver to transfer a single
356 * message while queuing transfers that arrive in the meantime. When the
357 * driver is finished with this message, it must call
358 * spi_finalize_current_message() so the subsystem can issue the next
360 * @unprepare_transfer_hardware: there are currently no more messages on the
361 * queue so the subsystem notifies the driver that it may relax the
362 * hardware by issuing this call
363 * @set_cs: set the logic level of the chip select line. May be called
364 * from interrupt context.
365 * @prepare_message: set up the controller to transfer a single message,
366 * for example doing DMA mapping. Called from threaded
368 * @transfer_one: transfer a single spi_transfer.
369 * - return 0 if the transfer is finished,
370 * - return 1 if the transfer is still in progress. When
371 * the driver is finished with this transfer it must
372 * call spi_finalize_current_transfer() so the subsystem
373 * can issue the next transfer. Note: transfer_one and
374 * transfer_one_message are mutually exclusive; when both
375 * are set, the generic subsystem does not call your
376 * transfer_one callback.
377 * @handle_err: the subsystem calls the driver to handle an error that occurs
378 * in the generic implementation of transfer_one_message().
379 * @unprepare_message: undo any work done by prepare_message().
380 * @slave_abort: abort the ongoing transfer request on an SPI slave controller
381 * @spi_flash_read: to support spi-controller hardwares that provide
382 * accelerated interface to read from flash devices.
383 * @spi_flash_can_dma: analogous to can_dma() interface, but for
384 * controllers implementing spi_flash_read.
385 * @flash_read_supported: spi device supports flash read
386 * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS
387 * number. Any individual value may be -ENOENT for CS lines that
388 * are not GPIOs (driven by the SPI controller itself).
389 * @statistics: statistics for the spi_controller
390 * @dma_tx: DMA transmit channel
391 * @dma_rx: DMA receive channel
392 * @dummy_rx: dummy receive buffer for full-duplex devices
393 * @dummy_tx: dummy transmit buffer for full-duplex devices
394 * @fw_translate_cs: If the boot firmware uses different numbering scheme
395 * what Linux expects, this optional hook can be used to translate
398 * Each SPI controller can communicate with one or more @spi_device
399 * children. These make a small bus, sharing MOSI, MISO and SCK signals
400 * but not chip select signals. Each device may be configured to use a
401 * different clock rate, since those shared signals are ignored unless
402 * the chip is selected.
404 * The driver for an SPI controller manages access to those devices through
405 * a queue of spi_message transactions, copying data between CPU memory and
406 * an SPI slave device. For each such message it queues, it calls the
407 * message's completion function when the transaction completes.
409 struct spi_controller {
412 struct list_head list;
414 /* other than negative (== assign one dynamically), bus_num is fully
415 * board-specific. usually that simplifies to being SOC-specific.
416 * example: one SOC has three SPI controllers, numbered 0..2,
417 * and one board's schematics might show it using SPI-2. software
418 * would normally use bus_num=2 for that controller.
422 /* chipselects will be integral to many controllers; some others
423 * might use board-specific GPIOs.
427 /* some SPI controllers pose alignment requirements on DMAable
428 * buffers; let protocol drivers know about these requirements.
432 /* spi_device.mode flags understood by this controller driver */
435 /* bitmask of supported bits_per_word for transfers */
436 u32 bits_per_word_mask;
437 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
438 #define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
439 #define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1))
441 /* limits on transfer speed */
445 /* other constraints relevant to this driver */
447 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */
448 #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */
449 #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */
450 #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */
451 #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */
453 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */
455 /* flag indicating this is a non-devres managed controller */
458 /* flag indicating this is an SPI slave controller */
462 * on some hardware transfer / message size may be constrained
463 * the limit may depend on device transfer settings
465 size_t (*max_transfer_size)(struct spi_device *spi);
466 size_t (*max_message_size)(struct spi_device *spi);
469 struct mutex io_mutex;
471 /* lock and mutex for SPI bus locking */
472 spinlock_t bus_lock_spinlock;
473 struct mutex bus_lock_mutex;
475 /* flag indicating that the SPI bus is locked for exclusive use */
478 /* Setup mode and clock, etc (spi driver may call many times).
480 * IMPORTANT: this may be called when transfers to another
481 * device are active. DO NOT UPDATE SHARED REGISTERS in ways
482 * which could break those transfers.
484 int (*setup)(struct spi_device *spi);
486 /* bidirectional bulk transfers
488 * + The transfer() method may not sleep; its main role is
489 * just to add the message to the queue.
490 * + For now there's no remove-from-queue operation, or
491 * any other request management
492 * + To a given spi_device, message queueing is pure fifo
494 * + The controller's main job is to process its message queue,
495 * selecting a chip (for masters), then transferring data
496 * + If there are multiple spi_device children, the i/o queue
497 * arbitration algorithm is unspecified (round robin, fifo,
498 * priority, reservations, preemption, etc)
500 * + Chipselect stays active during the entire message
501 * (unless modified by spi_transfer.cs_change != 0).
502 * + The message transfers use clock and SPI mode parameters
503 * previously established by setup() for this device
505 int (*transfer)(struct spi_device *spi,
506 struct spi_message *mesg);
508 /* called on release() to free memory provided by spi_controller */
509 void (*cleanup)(struct spi_device *spi);
512 * Used to enable core support for DMA handling, if can_dma()
513 * exists and returns true then the transfer will be mapped
514 * prior to transfer_one() being called. The driver should
515 * not modify or store xfer and dma_tx and dma_rx must be set
516 * while the device is prepared.
518 bool (*can_dma)(struct spi_controller *ctlr,
519 struct spi_device *spi,
520 struct spi_transfer *xfer);
523 * These hooks are for drivers that want to use the generic
524 * controller transfer queueing mechanism. If these are used, the
525 * transfer() function above must NOT be specified by the driver.
526 * Over time we expect SPI drivers to be phased over to this API.
529 struct kthread_worker kworker;
530 struct task_struct *kworker_task;
531 struct kthread_work pump_messages;
532 spinlock_t queue_lock;
533 struct list_head queue;
534 struct spi_message *cur_msg;
539 bool auto_runtime_pm;
540 bool cur_msg_prepared;
542 struct completion xfer_completion;
545 int (*prepare_transfer_hardware)(struct spi_controller *ctlr);
546 int (*transfer_one_message)(struct spi_controller *ctlr,
547 struct spi_message *mesg);
548 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr);
549 int (*prepare_message)(struct spi_controller *ctlr,
550 struct spi_message *message);
551 int (*unprepare_message)(struct spi_controller *ctlr,
552 struct spi_message *message);
553 int (*slave_abort)(struct spi_controller *ctlr);
554 int (*spi_flash_read)(struct spi_device *spi,
555 struct spi_flash_read_message *msg);
556 bool (*spi_flash_can_dma)(struct spi_device *spi,
557 struct spi_flash_read_message *msg);
558 bool (*flash_read_supported)(struct spi_device *spi);
561 * These hooks are for drivers that use a generic implementation
562 * of transfer_one_message() provied by the core.
564 void (*set_cs)(struct spi_device *spi, bool enable);
565 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi,
566 struct spi_transfer *transfer);
567 void (*handle_err)(struct spi_controller *ctlr,
568 struct spi_message *message);
570 /* gpio chip select */
574 struct spi_statistics statistics;
576 /* DMA channels for use with core dmaengine helpers */
577 struct dma_chan *dma_tx;
578 struct dma_chan *dma_rx;
580 /* dummy data for full duplex devices */
584 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
587 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr)
589 return dev_get_drvdata(&ctlr->dev);
592 static inline void spi_controller_set_devdata(struct spi_controller *ctlr,
595 dev_set_drvdata(&ctlr->dev, data);
598 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr)
600 if (!ctlr || !get_device(&ctlr->dev))
605 static inline void spi_controller_put(struct spi_controller *ctlr)
608 put_device(&ctlr->dev);
611 static inline bool spi_controller_is_slave(struct spi_controller *ctlr)
613 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave;
616 /* PM calls that need to be issued by the driver */
617 extern int spi_controller_suspend(struct spi_controller *ctlr);
618 extern int spi_controller_resume(struct spi_controller *ctlr);
620 /* Calls the driver make to interact with the message queue */
621 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr);
622 extern void spi_finalize_current_message(struct spi_controller *ctlr);
623 extern void spi_finalize_current_transfer(struct spi_controller *ctlr);
625 /* the spi driver core manages memory for the spi_controller classdev */
626 extern struct spi_controller *__spi_alloc_controller(struct device *host,
627 unsigned int size, bool slave);
629 static inline struct spi_controller *spi_alloc_master(struct device *host,
632 return __spi_alloc_controller(host, size, false);
635 static inline struct spi_controller *spi_alloc_slave(struct device *host,
638 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
641 return __spi_alloc_controller(host, size, true);
644 struct spi_controller *__devm_spi_alloc_controller(struct device *dev,
648 static inline struct spi_controller *devm_spi_alloc_master(struct device *dev,
651 return __devm_spi_alloc_controller(dev, size, false);
654 static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev,
657 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
660 return __devm_spi_alloc_controller(dev, size, true);
663 extern int spi_register_controller(struct spi_controller *ctlr);
664 extern int devm_spi_register_controller(struct device *dev,
665 struct spi_controller *ctlr);
666 extern void spi_unregister_controller(struct spi_controller *ctlr);
668 extern struct spi_controller *spi_busnum_to_master(u16 busnum);
671 * SPI resource management while processing a SPI message
674 typedef void (*spi_res_release_t)(struct spi_controller *ctlr,
675 struct spi_message *msg,
679 * struct spi_res - spi resource management structure
681 * @release: release code called prior to freeing this resource
682 * @data: extra data allocated for the specific use-case
684 * this is based on ideas from devres, but focused on life-cycle
685 * management during spi_message processing
688 struct list_head entry;
689 spi_res_release_t release;
690 unsigned long long data[]; /* guarantee ull alignment */
693 extern void *spi_res_alloc(struct spi_device *spi,
694 spi_res_release_t release,
695 size_t size, gfp_t gfp);
696 extern void spi_res_add(struct spi_message *message, void *res);
697 extern void spi_res_free(void *res);
699 extern void spi_res_release(struct spi_controller *ctlr,
700 struct spi_message *message);
702 /*---------------------------------------------------------------------------*/
705 * I/O INTERFACE between SPI controller and protocol drivers
707 * Protocol drivers use a queue of spi_messages, each transferring data
708 * between the controller and memory buffers.
710 * The spi_messages themselves consist of a series of read+write transfer
711 * segments. Those segments always read the same number of bits as they
712 * write; but one or the other is easily ignored by passing a null buffer
713 * pointer. (This is unlike most types of I/O API, because SPI hardware
716 * NOTE: Allocation of spi_transfer and spi_message memory is entirely
717 * up to the protocol driver, which guarantees the integrity of both (as
718 * well as the data buffers) for as long as the message is queued.
722 * struct spi_transfer - a read/write buffer pair
723 * @tx_buf: data to be written (dma-safe memory), or NULL
724 * @rx_buf: data to be read (dma-safe memory), or NULL
725 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
726 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
727 * @tx_nbits: number of bits used for writing. If 0 the default
728 * (SPI_NBITS_SINGLE) is used.
729 * @rx_nbits: number of bits used for reading. If 0 the default
730 * (SPI_NBITS_SINGLE) is used.
731 * @len: size of rx and tx buffers (in bytes)
732 * @speed_hz: Select a speed other than the device default for this
733 * transfer. If 0 the default (from @spi_device) is used.
734 * @bits_per_word: select a bits_per_word other than the device default
735 * for this transfer. If 0 the default (from @spi_device) is used.
736 * @cs_change: affects chipselect after this transfer completes
737 * @delay_usecs: microseconds to delay after this transfer before
738 * (optionally) changing the chipselect status, then starting
739 * the next transfer or completing this @spi_message.
740 * @transfer_list: transfers are sequenced through @spi_message.transfers
741 * @tx_sg: Scatterlist for transmit, currently not for client use
742 * @rx_sg: Scatterlist for receive, currently not for client use
744 * SPI transfers always write the same number of bytes as they read.
745 * Protocol drivers should always provide @rx_buf and/or @tx_buf.
746 * In some cases, they may also want to provide DMA addresses for
747 * the data being transferred; that may reduce overhead, when the
748 * underlying driver uses dma.
750 * If the transmit buffer is null, zeroes will be shifted out
751 * while filling @rx_buf. If the receive buffer is null, the data
752 * shifted in will be discarded. Only "len" bytes shift out (or in).
753 * It's an error to try to shift out a partial word. (For example, by
754 * shifting out three bytes with word size of sixteen or twenty bits;
755 * the former uses two bytes per word, the latter uses four bytes.)
757 * In-memory data values are always in native CPU byte order, translated
758 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
759 * for example when bits_per_word is sixteen, buffers are 2N bytes long
760 * (@len = 2N) and hold N sixteen bit words in CPU byte order.
762 * When the word size of the SPI transfer is not a power-of-two multiple
763 * of eight bits, those in-memory words include extra bits. In-memory
764 * words are always seen by protocol drivers as right-justified, so the
765 * undefined (rx) or unused (tx) bits are always the most significant bits.
767 * All SPI transfers start with the relevant chipselect active. Normally
768 * it stays selected until after the last transfer in a message. Drivers
769 * can affect the chipselect signal using cs_change.
771 * (i) If the transfer isn't the last one in the message, this flag is
772 * used to make the chipselect briefly go inactive in the middle of the
773 * message. Toggling chipselect in this way may be needed to terminate
774 * a chip command, letting a single spi_message perform all of group of
775 * chip transactions together.
777 * (ii) When the transfer is the last one in the message, the chip may
778 * stay selected until the next transfer. On multi-device SPI busses
779 * with nothing blocking messages going to other devices, this is just
780 * a performance hint; starting a message to another device deselects
781 * this one. But in other cases, this can be used to ensure correctness.
782 * Some devices need protocol transactions to be built from a series of
783 * spi_message submissions, where the content of one message is determined
784 * by the results of previous messages and where the whole transaction
785 * ends when the chipselect goes intactive.
787 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
788 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
789 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
790 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
792 * The code that submits an spi_message (and its spi_transfers)
793 * to the lower layers is responsible for managing its memory.
794 * Zero-initialize every field you don't set up explicitly, to
795 * insulate against future API updates. After you submit a message
796 * and its transfers, ignore them until its completion callback.
798 struct spi_transfer {
799 /* it's ok if tx_buf == rx_buf (right?)
800 * for MicroWire, one buffer must be null
801 * buffers must work with dma_*map_single() calls, unless
802 * spi_message.is_dma_mapped reports a pre-existing mapping
810 struct sg_table tx_sg;
811 struct sg_table rx_sg;
813 unsigned cs_change:1;
816 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
817 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
818 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
823 struct list_head transfer_list;
827 * struct spi_message - one multi-segment SPI transaction
828 * @transfers: list of transfer segments in this transaction
829 * @spi: SPI device to which the transaction is queued
830 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual
831 * addresses for each transfer buffer
832 * @complete: called to report transaction completions
833 * @context: the argument to complete() when it's called
834 * @frame_length: the total number of bytes in the message
835 * @actual_length: the total number of bytes that were transferred in all
836 * successful segments
837 * @status: zero for success, else negative errno
838 * @queue: for use by whichever driver currently owns the message
839 * @state: for use by whichever driver currently owns the message
840 * @resources: for resource management when the spi message is processed
842 * A @spi_message is used to execute an atomic sequence of data transfers,
843 * each represented by a struct spi_transfer. The sequence is "atomic"
844 * in the sense that no other spi_message may use that SPI bus until that
845 * sequence completes. On some systems, many such sequences can execute as
846 * as single programmed DMA transfer. On all systems, these messages are
847 * queued, and might complete after transactions to other devices. Messages
848 * sent to a given spi_device are always executed in FIFO order.
850 * The code that submits an spi_message (and its spi_transfers)
851 * to the lower layers is responsible for managing its memory.
852 * Zero-initialize every field you don't set up explicitly, to
853 * insulate against future API updates. After you submit a message
854 * and its transfers, ignore them until its completion callback.
857 struct list_head transfers;
859 struct spi_device *spi;
861 unsigned is_dma_mapped:1;
863 /* REVISIT: we might want a flag affecting the behavior of the
864 * last transfer ... allowing things like "read 16 bit length L"
865 * immediately followed by "read L bytes". Basically imposing
866 * a specific message scheduling algorithm.
868 * Some controller drivers (message-at-a-time queue processing)
869 * could provide that as their default scheduling algorithm. But
870 * others (with multi-message pipelines) could need a flag to
871 * tell them about such special cases.
874 /* completion is reported through a callback */
875 void (*complete)(void *context);
877 unsigned frame_length;
878 unsigned actual_length;
881 /* for optional use by whatever driver currently owns the
882 * spi_message ... between calls to spi_async and then later
883 * complete(), that's the spi_controller controller driver.
885 struct list_head queue;
888 /* list of spi_res reources when the spi message is processed */
889 struct list_head resources;
892 static inline void spi_message_init_no_memset(struct spi_message *m)
894 INIT_LIST_HEAD(&m->transfers);
895 INIT_LIST_HEAD(&m->resources);
898 static inline void spi_message_init(struct spi_message *m)
900 memset(m, 0, sizeof *m);
901 spi_message_init_no_memset(m);
905 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
907 list_add_tail(&t->transfer_list, &m->transfers);
911 spi_transfer_del(struct spi_transfer *t)
913 list_del(&t->transfer_list);
917 * spi_message_init_with_transfers - Initialize spi_message and append transfers
918 * @m: spi_message to be initialized
919 * @xfers: An array of spi transfers
920 * @num_xfers: Number of items in the xfer array
922 * This function initializes the given spi_message and adds each spi_transfer in
923 * the given array to the message.
926 spi_message_init_with_transfers(struct spi_message *m,
927 struct spi_transfer *xfers, unsigned int num_xfers)
932 for (i = 0; i < num_xfers; ++i)
933 spi_message_add_tail(&xfers[i], m);
936 /* It's fine to embed message and transaction structures in other data
937 * structures so long as you don't free them while they're in use.
940 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
942 struct spi_message *m;
944 m = kzalloc(sizeof(struct spi_message)
945 + ntrans * sizeof(struct spi_transfer),
949 struct spi_transfer *t = (struct spi_transfer *)(m + 1);
951 spi_message_init_no_memset(m);
952 for (i = 0; i < ntrans; i++, t++)
953 spi_message_add_tail(t, m);
958 static inline void spi_message_free(struct spi_message *m)
963 extern int spi_setup(struct spi_device *spi);
964 extern int spi_async(struct spi_device *spi, struct spi_message *message);
965 extern int spi_async_locked(struct spi_device *spi,
966 struct spi_message *message);
967 extern int spi_slave_abort(struct spi_device *spi);
970 spi_max_message_size(struct spi_device *spi)
972 struct spi_controller *ctlr = spi->controller;
974 if (!ctlr->max_message_size)
976 return ctlr->max_message_size(spi);
980 spi_max_transfer_size(struct spi_device *spi)
982 struct spi_controller *ctlr = spi->controller;
983 size_t tr_max = SIZE_MAX;
984 size_t msg_max = spi_max_message_size(spi);
986 if (ctlr->max_transfer_size)
987 tr_max = ctlr->max_transfer_size(spi);
989 /* transfer size limit must not be greater than messsage size limit */
990 return min(tr_max, msg_max);
993 /*---------------------------------------------------------------------------*/
995 /* SPI transfer replacement methods which make use of spi_res */
997 struct spi_replaced_transfers;
998 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr,
999 struct spi_message *msg,
1000 struct spi_replaced_transfers *res);
1002 * struct spi_replaced_transfers - structure describing the spi_transfer
1003 * replacements that have occurred
1004 * so that they can get reverted
1005 * @release: some extra release code to get executed prior to
1006 * relasing this structure
1007 * @extradata: pointer to some extra data if requested or NULL
1008 * @replaced_transfers: transfers that have been replaced and which need
1010 * @replaced_after: the transfer after which the @replaced_transfers
1011 * are to get re-inserted
1012 * @inserted: number of transfers inserted
1013 * @inserted_transfers: array of spi_transfers of array-size @inserted,
1014 * that have been replacing replaced_transfers
1016 * note: that @extradata will point to @inserted_transfers[@inserted]
1017 * if some extra allocation is requested, so alignment will be the same
1018 * as for spi_transfers
1020 struct spi_replaced_transfers {
1021 spi_replaced_release_t release;
1023 struct list_head replaced_transfers;
1024 struct list_head *replaced_after;
1026 struct spi_transfer inserted_transfers[];
1029 extern struct spi_replaced_transfers *spi_replace_transfers(
1030 struct spi_message *msg,
1031 struct spi_transfer *xfer_first,
1034 spi_replaced_release_t release,
1035 size_t extradatasize,
1038 /*---------------------------------------------------------------------------*/
1040 /* SPI transfer transformation methods */
1042 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr,
1043 struct spi_message *msg,
1047 /*---------------------------------------------------------------------------*/
1049 /* All these synchronous SPI transfer routines are utilities layered
1050 * over the core async transfer primitive. Here, "synchronous" means
1051 * they will sleep uninterruptibly until the async transfer completes.
1054 extern int spi_sync(struct spi_device *spi, struct spi_message *message);
1055 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message);
1056 extern int spi_bus_lock(struct spi_controller *ctlr);
1057 extern int spi_bus_unlock(struct spi_controller *ctlr);
1060 * spi_sync_transfer - synchronous SPI data transfer
1061 * @spi: device with which data will be exchanged
1062 * @xfers: An array of spi_transfers
1063 * @num_xfers: Number of items in the xfer array
1064 * Context: can sleep
1066 * Does a synchronous SPI data transfer of the given spi_transfer array.
1068 * For more specific semantics see spi_sync().
1070 * Return: Return: zero on success, else a negative error code.
1073 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers,
1074 unsigned int num_xfers)
1076 struct spi_message msg;
1078 spi_message_init_with_transfers(&msg, xfers, num_xfers);
1080 return spi_sync(spi, &msg);
1084 * spi_write - SPI synchronous write
1085 * @spi: device to which data will be written
1087 * @len: data buffer size
1088 * Context: can sleep
1090 * This function writes the buffer @buf.
1091 * Callable only from contexts that can sleep.
1093 * Return: zero on success, else a negative error code.
1096 spi_write(struct spi_device *spi, const void *buf, size_t len)
1098 struct spi_transfer t = {
1103 return spi_sync_transfer(spi, &t, 1);
1107 * spi_read - SPI synchronous read
1108 * @spi: device from which data will be read
1110 * @len: data buffer size
1111 * Context: can sleep
1113 * This function reads the buffer @buf.
1114 * Callable only from contexts that can sleep.
1116 * Return: zero on success, else a negative error code.
1119 spi_read(struct spi_device *spi, void *buf, size_t len)
1121 struct spi_transfer t = {
1126 return spi_sync_transfer(spi, &t, 1);
1129 /* this copies txbuf and rxbuf data; for small transfers only! */
1130 extern int spi_write_then_read(struct spi_device *spi,
1131 const void *txbuf, unsigned n_tx,
1132 void *rxbuf, unsigned n_rx);
1135 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1136 * @spi: device with which data will be exchanged
1137 * @cmd: command to be written before data is read back
1138 * Context: can sleep
1140 * Callable only from contexts that can sleep.
1142 * Return: the (unsigned) eight bit number returned by the
1143 * device, or else a negative error code.
1145 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
1150 status = spi_write_then_read(spi, &cmd, 1, &result, 1);
1152 /* return negative errno or unsigned value */
1153 return (status < 0) ? status : result;
1157 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1158 * @spi: device with which data will be exchanged
1159 * @cmd: command to be written before data is read back
1160 * Context: can sleep
1162 * The number is returned in wire-order, which is at least sometimes
1165 * Callable only from contexts that can sleep.
1167 * Return: the (unsigned) sixteen bit number returned by the
1168 * device, or else a negative error code.
1170 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
1175 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1177 /* return negative errno or unsigned value */
1178 return (status < 0) ? status : result;
1182 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1183 * @spi: device with which data will be exchanged
1184 * @cmd: command to be written before data is read back
1185 * Context: can sleep
1187 * This function is similar to spi_w8r16, with the exception that it will
1188 * convert the read 16 bit data word from big-endian to native endianness.
1190 * Callable only from contexts that can sleep.
1192 * Return: the (unsigned) sixteen bit number returned by the device in cpu
1193 * endianness, or else a negative error code.
1195 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd)
1201 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1205 return be16_to_cpu(result);
1209 * struct spi_flash_read_message - flash specific information for
1210 * spi-masters that provide accelerated flash read interfaces
1211 * @buf: buffer to read data
1212 * @from: offset within the flash from where data is to be read
1213 * @len: length of data to be read
1214 * @retlen: actual length of data read
1215 * @read_opcode: read_opcode to be used to communicate with flash
1216 * @addr_width: number of address bytes
1217 * @dummy_bytes: number of dummy bytes
1218 * @opcode_nbits: number of lines to send opcode
1219 * @addr_nbits: number of lines to send address
1220 * @data_nbits: number of lines for data
1221 * @rx_sg: Scatterlist for receive data read from flash
1222 * @cur_msg_mapped: message has been mapped for DMA
1224 struct spi_flash_read_message {
1235 struct sg_table rx_sg;
1236 bool cur_msg_mapped;
1239 /* SPI core interface for flash read support */
1240 static inline bool spi_flash_read_supported(struct spi_device *spi)
1242 return spi->controller->spi_flash_read &&
1243 (!spi->controller->flash_read_supported ||
1244 spi->controller->flash_read_supported(spi));
1247 int spi_flash_read(struct spi_device *spi,
1248 struct spi_flash_read_message *msg);
1250 /*---------------------------------------------------------------------------*/
1253 * INTERFACE between board init code and SPI infrastructure.
1255 * No SPI driver ever sees these SPI device table segments, but
1256 * it's how the SPI core (or adapters that get hotplugged) grows
1257 * the driver model tree.
1259 * As a rule, SPI devices can't be probed. Instead, board init code
1260 * provides a table listing the devices which are present, with enough
1261 * information to bind and set up the device's driver. There's basic
1262 * support for nonstatic configurations too; enough to handle adding
1263 * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1267 * struct spi_board_info - board-specific template for a SPI device
1268 * @modalias: Initializes spi_device.modalias; identifies the driver.
1269 * @platform_data: Initializes spi_device.platform_data; the particular
1270 * data stored there is driver-specific.
1271 * @properties: Additional device properties for the device.
1272 * @controller_data: Initializes spi_device.controller_data; some
1273 * controllers need hints about hardware setup, e.g. for DMA.
1274 * @irq: Initializes spi_device.irq; depends on how the board is wired.
1275 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
1276 * from the chip datasheet and board-specific signal quality issues.
1277 * @bus_num: Identifies which spi_controller parents the spi_device; unused
1278 * by spi_new_device(), and otherwise depends on board wiring.
1279 * @chip_select: Initializes spi_device.chip_select; depends on how
1280 * the board is wired.
1281 * @mode: Initializes spi_device.mode; based on the chip datasheet, board
1282 * wiring (some devices support both 3WIRE and standard modes), and
1283 * possibly presence of an inverter in the chipselect path.
1285 * When adding new SPI devices to the device tree, these structures serve
1286 * as a partial device template. They hold information which can't always
1287 * be determined by drivers. Information that probe() can establish (such
1288 * as the default transfer wordsize) is not included here.
1290 * These structures are used in two places. Their primary role is to
1291 * be stored in tables of board-specific device descriptors, which are
1292 * declared early in board initialization and then used (much later) to
1293 * populate a controller's device tree after the that controller's driver
1294 * initializes. A secondary (and atypical) role is as a parameter to
1295 * spi_new_device() call, which happens after those controller drivers
1296 * are active in some dynamic board configuration models.
1298 struct spi_board_info {
1299 /* the device name and module name are coupled, like platform_bus;
1300 * "modalias" is normally the driver name.
1302 * platform_data goes to spi_device.dev.platform_data,
1303 * controller_data goes to spi_device.controller_data,
1304 * device properties are copied and attached to spi_device,
1307 char modalias[SPI_NAME_SIZE];
1308 const void *platform_data;
1309 const struct property_entry *properties;
1310 void *controller_data;
1313 /* slower signaling on noisy or low voltage boards */
1317 /* bus_num is board specific and matches the bus_num of some
1318 * spi_controller that will probably be registered later.
1320 * chip_select reflects how this chip is wired to that master;
1321 * it's less than num_chipselect.
1326 /* mode becomes spi_device.mode, and is essential for chips
1327 * where the default of SPI_CS_HIGH = 0 is wrong.
1331 /* ... may need additional spi_device chip config data here.
1332 * avoid stuff protocol drivers can set; but include stuff
1333 * needed to behave without being bound to a driver:
1334 * - quirks like clock rate mattering when not selected
1340 spi_register_board_info(struct spi_board_info const *info, unsigned n);
1342 /* board init code may ignore whether SPI is configured or not */
1344 spi_register_board_info(struct spi_board_info const *info, unsigned n)
1349 /* If you're hotplugging an adapter with devices (parport, usb, etc)
1350 * use spi_new_device() to describe each device. You can also call
1351 * spi_unregister_device() to start making that device vanish, but
1352 * normally that would be handled by spi_unregister_controller().
1354 * You can also use spi_alloc_device() and spi_add_device() to use a two
1355 * stage registration sequence for each spi_device. This gives the caller
1356 * some more control over the spi_device structure before it is registered,
1357 * but requires that caller to initialize fields that would otherwise
1358 * be defined using the board info.
1360 extern struct spi_device *
1361 spi_alloc_device(struct spi_controller *ctlr);
1364 spi_add_device(struct spi_device *spi);
1366 extern struct spi_device *
1367 spi_new_device(struct spi_controller *, struct spi_board_info *);
1369 extern void spi_unregister_device(struct spi_device *spi);
1371 extern const struct spi_device_id *
1372 spi_get_device_id(const struct spi_device *sdev);
1375 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer)
1377 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);
1381 /* Compatibility layer */
1382 #define spi_master spi_controller
1384 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX
1385 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX
1386 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX
1387 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX
1388 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX
1390 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr)
1391 #define spi_master_set_devdata(_ctlr, _data) \
1392 spi_controller_set_devdata(_ctlr, _data)
1393 #define spi_master_get(_ctlr) spi_controller_get(_ctlr)
1394 #define spi_master_put(_ctlr) spi_controller_put(_ctlr)
1395 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr)
1396 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr)
1398 #define spi_register_master(_ctlr) spi_register_controller(_ctlr)
1399 #define devm_spi_register_master(_dev, _ctlr) \
1400 devm_spi_register_controller(_dev, _ctlr)
1401 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr)
1403 #endif /* __LINUX_SPI_H */