sound/pci/asihpi/hpi6205.c

   1 /******************************************************************************
   2
   3     AudioScience HPI driver
   4     Copyright (C) 1997-2014  AudioScience Inc. <support@audioscience.com>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of version 2 of the GNU General Public License as
   8     published by the Free Software Foundation;
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18
  19  Hardware Programming Interface (HPI) for AudioScience
  20  ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters.
  21  These PCI and PCIe bus adapters are based on a
  22  TMS320C6205 PCI bus mastering DSP,
  23  and (except ASI50xx) TI TMS320C6xxx floating point DSP
  24
  25  Exported function:
  26  void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
  27
  28 (C) Copyright AudioScience Inc. 1998-2010
  29 *******************************************************************************/
  30 #define SOURCEFILE_NAME "hpi6205.c"
  31
  32 #include "hpi_internal.h"
  33 #include "hpimsginit.h"
  34 #include "hpidebug.h"
  35 #include "hpi6205.h"
  36 #include "hpidspcd.h"
  37 #include "hpicmn.h"
  38
  39 /*****************************************************************************/
  40 /* HPI6205 specific error codes */
  41 #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */
  42
  43 /* operational/messaging errors */
  44 #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT     1015
  45 #define HPI6205_ERROR_MSG_RESP_TIMEOUT          1016
  46
  47 /* initialization/bootload errors */
  48 #define HPI6205_ERROR_6205_NO_IRQ       1002
  49 #define HPI6205_ERROR_6205_INIT_FAILED  1003
  50 #define HPI6205_ERROR_6205_REG          1006
  51 #define HPI6205_ERROR_6205_DSPPAGE      1007
  52 #define HPI6205_ERROR_C6713_HPIC        1009
  53 #define HPI6205_ERROR_C6713_HPIA        1010
  54 #define HPI6205_ERROR_C6713_PLL         1011
  55 #define HPI6205_ERROR_DSP_INTMEM        1012
  56 #define HPI6205_ERROR_DSP_EXTMEM        1013
  57 #define HPI6205_ERROR_DSP_PLD           1014
  58 #define HPI6205_ERROR_6205_EEPROM       1017
  59 #define HPI6205_ERROR_DSP_EMIF1         1018
  60 #define HPI6205_ERROR_DSP_EMIF2         1019
  61 #define HPI6205_ERROR_DSP_EMIF3         1020
  62 #define HPI6205_ERROR_DSP_EMIF4         1021
  63
  64 /*****************************************************************************/
  65 /* for C6205 PCI i/f */
  66 /* Host Status Register (HSR) bitfields */
  67 #define C6205_HSR_INTSRC        0x01
  68 #define C6205_HSR_INTAVAL       0x02
  69 #define C6205_HSR_INTAM         0x04
  70 #define C6205_HSR_CFGERR        0x08
  71 #define C6205_HSR_EEREAD        0x10
  72 /* Host-to-DSP Control Register (HDCR) bitfields */
  73 #define C6205_HDCR_WARMRESET    0x01
  74 #define C6205_HDCR_DSPINT       0x02
  75 #define C6205_HDCR_PCIBOOT      0x04
  76 /* DSP Page Register (DSPP) bitfields, */
  77 /* defines 4 Mbyte page that BAR0 points to */
  78 #define C6205_DSPP_MAP1         0x400
  79
  80 /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP.
  81  * BAR1 maps to non-prefetchable 8 Mbyte memory block
  82  * of DSP memory mapped registers (starting at 0x01800000).
  83  * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this
  84  * needs to be added to the BAR1 base address set in the PCI config reg
  85  */
  86 #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
  87 #define C6205_BAR1_HSR  (C6205_BAR1_PCI_IO_OFFSET)
  88 #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4)
  89 #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
  90
  91 /* used to control LED (revA) and reset C6713 (revB) */
  92 #define C6205_BAR0_TIMER1_CTL (0x01980000L)
  93
  94 /* For first 6713 in CE1 space, using DA17,16,2 */
  95 #define HPICL_ADDR      0x01400000L
  96 #define HPICH_ADDR      0x01400004L
  97 #define HPIAL_ADDR      0x01410000L
  98 #define HPIAH_ADDR      0x01410004L
  99 #define HPIDIL_ADDR     0x01420000L
 100 #define HPIDIH_ADDR     0x01420004L
 101 #define HPIDL_ADDR      0x01430000L
 102 #define HPIDH_ADDR      0x01430004L
 103
 104 #define C6713_EMIF_GCTL         0x01800000
 105 #define C6713_EMIF_CE1          0x01800004
 106 #define C6713_EMIF_CE0          0x01800008
 107 #define C6713_EMIF_CE2          0x01800010
 108 #define C6713_EMIF_CE3          0x01800014
 109 #define C6713_EMIF_SDRAMCTL     0x01800018
 110 #define C6713_EMIF_SDRAMTIMING  0x0180001C
 111 #define C6713_EMIF_SDRAMEXT     0x01800020
 112
 113 struct hpi_hw_obj {
 114         /* PCI registers */
 115         __iomem u32 *prHSR;
 116         __iomem u32 *prHDCR;
 117         __iomem u32 *prDSPP;
 118
 119         u32 dsp_page;
 120
 121         struct consistent_dma_area h_locked_mem;
 122         struct bus_master_interface *p_interface_buffer;
 123
 124         u16 flag_outstream_just_reset[HPI_MAX_STREAMS];
 125         /* a non-NULL handle means there is an HPI allocated buffer */
 126         struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS];
 127         struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS];
 128         /* non-zero size means a buffer exists, may be external */
 129         u32 instream_host_buffer_size[HPI_MAX_STREAMS];
 130         u32 outstream_host_buffer_size[HPI_MAX_STREAMS];
 131
 132         struct consistent_dma_area h_control_cache;
 133         struct hpi_control_cache *p_cache;
 134 };
 135
 136 /*****************************************************************************/
 137 /* local prototypes */
 138
 139 #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write)
 140
 141 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us);
 142
 143 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd);
 144
 145 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
 146         u32 *pos_error_code);
 147
 148 static u16 message_response_sequence(struct hpi_adapter_obj *pao,
 149         struct hpi_message *phm, struct hpi_response *phr);
 150
 151 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
 152         struct hpi_response *phr);
 153
 154 #define HPI6205_TIMEOUT 1000000
 155
 156 static void subsys_create_adapter(struct hpi_message *phm,
 157         struct hpi_response *phr);
 158 static void adapter_delete(struct hpi_adapter_obj *pao,
 159         struct hpi_message *phm, struct hpi_response *phr);
 160
 161 static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
 162         u32 *pos_error_code);
 163
 164 static void delete_adapter_obj(struct hpi_adapter_obj *pao);
 165
 166 static int adapter_irq_query_and_clear(struct hpi_adapter_obj *pao,
 167         u32 message);
 168
 169 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
 170         struct hpi_message *phm, struct hpi_response *phr);
 171
 172 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
 173         struct hpi_message *phm, struct hpi_response *phr);
 174
 175 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
 176         struct hpi_message *phm, struct hpi_response *phr);
 177 static void outstream_write(struct hpi_adapter_obj *pao,
 178         struct hpi_message *phm, struct hpi_response *phr);
 179
 180 static void outstream_get_info(struct hpi_adapter_obj *pao,
 181         struct hpi_message *phm, struct hpi_response *phr);
 182
 183 static void outstream_start(struct hpi_adapter_obj *pao,
 184         struct hpi_message *phm, struct hpi_response *phr);
 185
 186 static void outstream_open(struct hpi_adapter_obj *pao,
 187         struct hpi_message *phm, struct hpi_response *phr);
 188
 189 static void outstream_reset(struct hpi_adapter_obj *pao,
 190         struct hpi_message *phm, struct hpi_response *phr);
 191
 192 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
 193         struct hpi_message *phm, struct hpi_response *phr);
 194
 195 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
 196         struct hpi_message *phm, struct hpi_response *phr);
 197
 198 static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
 199         struct hpi_message *phm, struct hpi_response *phr);
 200
 201 static void instream_read(struct hpi_adapter_obj *pao,
 202         struct hpi_message *phm, struct hpi_response *phr);
 203
 204 static void instream_get_info(struct hpi_adapter_obj *pao,
 205         struct hpi_message *phm, struct hpi_response *phr);
 206
 207 static void instream_start(struct hpi_adapter_obj *pao,
 208         struct hpi_message *phm, struct hpi_response *phr);
 209
 210 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
 211         u32 address);
 212
 213 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
 214         int dsp_index, u32 address, u32 data);
 215
 216 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
 217         int dsp_index);
 218
 219 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
 220         u32 address, u32 length);
 221
 222 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
 223         int dsp_index);
 224
 225 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
 226         int dsp_index);
 227
 228 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
 229
 230 /*****************************************************************************/
 231
 232 static void subsys_message(struct hpi_adapter_obj *pao,
 233         struct hpi_message *phm, struct hpi_response *phr)
 234 {
 235         switch (phm->function) {
 236         case HPI_SUBSYS_CREATE_ADAPTER:
 237                 subsys_create_adapter(phm, phr);
 238                 break;
 239         default:
 240                 phr->error = HPI_ERROR_INVALID_FUNC;
 241                 break;
 242         }
 243 }
 244
 245 static void control_message(struct hpi_adapter_obj *pao,
 246         struct hpi_message *phm, struct hpi_response *phr)
 247 {
 248
 249         struct hpi_hw_obj *phw = pao->priv;
 250         u16 pending_cache_error = 0;
 251
 252         switch (phm->function) {
 253         case HPI_CONTROL_GET_STATE:
 254                 if (pao->has_control_cache) {
 255                         rmb();  /* make sure we see updates DMAed from DSP */
 256                         if (hpi_check_control_cache(phw->p_cache, phm, phr)) {
 257                                 break;
 258                         } else if (phm->u.c.attribute == HPI_METER_PEAK) {
 259                                 pending_cache_error =
 260                                         HPI_ERROR_CONTROL_CACHING;
 261                         }
 262                 }
 263                 hw_message(pao, phm, phr);
 264                 if (pending_cache_error && !phr->error)
 265                         phr->error = pending_cache_error;
 266                 break;
 267         case HPI_CONTROL_GET_INFO:
 268                 hw_message(pao, phm, phr);
 269                 break;
 270         case HPI_CONTROL_SET_STATE:
 271                 hw_message(pao, phm, phr);
 272                 if (pao->has_control_cache)
 273                         hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm,
 274                                 phr);
 275                 break;
 276         default:
 277                 phr->error = HPI_ERROR_INVALID_FUNC;
 278                 break;
 279         }
 280 }
 281
 282 static void adapter_message(struct hpi_adapter_obj *pao,
 283         struct hpi_message *phm, struct hpi_response *phr)
 284 {
 285         switch (phm->function) {
 286         case HPI_ADAPTER_DELETE:
 287                 adapter_delete(pao, phm, phr);
 288                 break;
 289         default:
 290                 hw_message(pao, phm, phr);
 291                 break;
 292         }
 293 }
 294
 295 static void outstream_message(struct hpi_adapter_obj *pao,
 296         struct hpi_message *phm, struct hpi_response *phr)
 297 {
 298
 299         if (phm->obj_index >= HPI_MAX_STREAMS) {
 300                 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
 301                 HPI_DEBUG_LOG(WARNING,
 302                         "Message referencing invalid stream %d "
 303                         "on adapter index %d\n", phm->obj_index,
 304                         phm->adapter_index);
 305                 return;
 306         }
 307
 308         switch (phm->function) {
 309         case HPI_OSTREAM_WRITE:
 310                 outstream_write(pao, phm, phr);
 311                 break;
 312         case HPI_OSTREAM_GET_INFO:
 313                 outstream_get_info(pao, phm, phr);
 314                 break;
 315         case HPI_OSTREAM_HOSTBUFFER_ALLOC:
 316                 outstream_host_buffer_allocate(pao, phm, phr);
 317                 break;
 318         case HPI_OSTREAM_HOSTBUFFER_GET_INFO:
 319                 outstream_host_buffer_get_info(pao, phm, phr);
 320                 break;
 321         case HPI_OSTREAM_HOSTBUFFER_FREE:
 322                 outstream_host_buffer_free(pao, phm, phr);
 323                 break;
 324         case HPI_OSTREAM_START:
 325                 outstream_start(pao, phm, phr);
 326                 break;
 327         case HPI_OSTREAM_OPEN:
 328                 outstream_open(pao, phm, phr);
 329                 break;
 330         case HPI_OSTREAM_RESET:
 331                 outstream_reset(pao, phm, phr);
 332                 break;
 333         default:
 334                 hw_message(pao, phm, phr);
 335                 break;
 336         }
 337 }
 338
 339 static void instream_message(struct hpi_adapter_obj *pao,
 340         struct hpi_message *phm, struct hpi_response *phr)
 341 {
 342
 343         if (phm->obj_index >= HPI_MAX_STREAMS) {
 344                 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
 345                 HPI_DEBUG_LOG(WARNING,
 346                         "Message referencing invalid stream %d "
 347                         "on adapter index %d\n", phm->obj_index,
 348                         phm->adapter_index);
 349                 return;
 350         }
 351
 352         switch (phm->function) {
 353         case HPI_ISTREAM_READ:
 354                 instream_read(pao, phm, phr);
 355                 break;
 356         case HPI_ISTREAM_GET_INFO:
 357                 instream_get_info(pao, phm, phr);
 358                 break;
 359         case HPI_ISTREAM_HOSTBUFFER_ALLOC:
 360                 instream_host_buffer_allocate(pao, phm, phr);
 361                 break;
 362         case HPI_ISTREAM_HOSTBUFFER_GET_INFO:
 363                 instream_host_buffer_get_info(pao, phm, phr);
 364                 break;
 365         case HPI_ISTREAM_HOSTBUFFER_FREE:
 366                 instream_host_buffer_free(pao, phm, phr);
 367                 break;
 368         case HPI_ISTREAM_START:
 369                 instream_start(pao, phm, phr);
 370                 break;
 371         default:
 372                 hw_message(pao, phm, phr);
 373                 break;
 374         }
 375 }
 376
 377 /*****************************************************************************/
 378 /** Entry point to this HPI backend
 379  * All calls to the HPI start here
 380  */
 381 static
 382 void _HPI_6205(struct hpi_adapter_obj *pao, struct hpi_message *phm,
 383         struct hpi_response *phr)
 384 {
 385         if (pao && (pao->dsp_crashed >= 10)
 386                 && (phm->function != HPI_ADAPTER_DEBUG_READ)) {
 387                 /* allow last resort debug read even after crash */
 388                 hpi_init_response(phr, phm->object, phm->function,
 389                         HPI_ERROR_DSP_HARDWARE);
 390                 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", phm->object,
 391                         phm->function);
 392                 return;
 393         }
 394
 395         /* Init default response  */
 396         if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
 397                 phr->error = HPI_ERROR_PROCESSING_MESSAGE;
 398
 399         HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
 400         switch (phm->type) {
 401         case HPI_TYPE_REQUEST:
 402                 switch (phm->object) {
 403                 case HPI_OBJ_SUBSYSTEM:
 404                         subsys_message(pao, phm, phr);
 405                         break;
 406
 407                 case HPI_OBJ_ADAPTER:
 408                         adapter_message(pao, phm, phr);
 409                         break;
 410
 411                 case HPI_OBJ_CONTROL:
 412                         control_message(pao, phm, phr);
 413                         break;
 414
 415                 case HPI_OBJ_OSTREAM:
 416                         outstream_message(pao, phm, phr);
 417                         break;
 418
 419                 case HPI_OBJ_ISTREAM:
 420                         instream_message(pao, phm, phr);
 421                         break;
 422
 423                 default:
 424                         hw_message(pao, phm, phr);
 425                         break;
 426                 }
 427                 break;
 428
 429         default:
 430                 phr->error = HPI_ERROR_INVALID_TYPE;
 431                 break;
 432         }
 433 }
 434
 435 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
 436 {
 437         struct hpi_adapter_obj *pao = NULL;
 438
 439         if (phm->object != HPI_OBJ_SUBSYSTEM) {
 440                 /* normal messages must have valid adapter index */
 441                 pao = hpi_find_adapter(phm->adapter_index);
 442         } else {
 443                 /* subsys messages don't address an adapter */
 444                 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
 445                 return;
 446         }
 447
 448         if (pao)
 449                 _HPI_6205(pao, phm, phr);
 450         else
 451                 hpi_init_response(phr, phm->object, phm->function,
 452                         HPI_ERROR_BAD_ADAPTER_NUMBER);
 453 }
 454
 455 /*****************************************************************************/
 456 /* SUBSYSTEM */
 457
 458 /** Create an adapter object and initialise it based on resource information
 459  * passed in in the message
 460  * *** NOTE - you cannot use this function AND the FindAdapters function at the
 461  * same time, the application must use only one of them to get the adapters ***
 462  */
 463 static void subsys_create_adapter(struct hpi_message *phm,
 464         struct hpi_response *phr)
 465 {
 466         /* create temp adapter obj, because we don't know what index yet */
 467         struct hpi_adapter_obj ao;
 468         u32 os_error_code;
 469         u16 err;
 470
 471         HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
 472
 473         memset(&ao, 0, sizeof(ao));
 474
 475         ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
 476         if (!ao.priv) {
 477                 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
 478                 phr->error = HPI_ERROR_MEMORY_ALLOC;
 479                 return;
 480         }
 481
 482         ao.pci = *phm->u.s.resource.r.pci;
 483         err = create_adapter_obj(&ao, &os_error_code);
 484         if (err) {
 485                 delete_adapter_obj(&ao);
 486                 if (err >= HPI_ERROR_BACKEND_BASE) {
 487                         phr->error = HPI_ERROR_DSP_BOOTLOAD;
 488                         phr->specific_error = err;
 489                 } else {
 490                         phr->error = err;
 491                 }
 492                 phr->u.s.data = os_error_code;
 493                 return;
 494         }
 495
 496         phr->u.s.adapter_type = ao.type;
 497         phr->u.s.adapter_index = ao.index;
 498         phr->error = 0;
 499 }
 500
 501 /** delete an adapter - required by WDM driver */
 502 static void adapter_delete(struct hpi_adapter_obj *pao,
 503         struct hpi_message *phm, struct hpi_response *phr)
 504 {
 505         struct hpi_hw_obj *phw;
 506
 507         if (!pao) {
 508                 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
 509                 return;
 510         }
 511         phw = pao->priv;
 512         /* reset adapter h/w */
 513         /* Reset C6713 #1 */
 514         boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
 515         /* reset C6205 */
 516         iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
 517
 518         delete_adapter_obj(pao);
 519         hpi_delete_adapter(pao);
 520         phr->error = 0;
 521 }
 522
 523 /** Create adapter object
 524   allocate buffers, bootload DSPs, initialise control cache
 525 */
 526 static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
 527         u32 *pos_error_code)
 528 {
 529         struct hpi_hw_obj *phw = pao->priv;
 530         struct bus_master_interface *interface;
 531         u32 phys_addr;
 532         int i;
 533         u16 err;
 534
 535         /* init error reporting */
 536         pao->dsp_crashed = 0;
 537
 538         for (i = 0; i < HPI_MAX_STREAMS; i++)
 539                 phw->flag_outstream_just_reset[i] = 1;
 540
 541         /* The C6205 memory area 1 is 8Mbyte window into DSP registers */
 542         phw->prHSR =
 543                 pao->pci.ap_mem_base[1] +
 544                 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]);
 545         phw->prHDCR =
 546                 pao->pci.ap_mem_base[1] +
 547                 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]);
 548         phw->prDSPP =
 549                 pao->pci.ap_mem_base[1] +
 550                 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
 551
 552         pao->has_control_cache = 0;
 553
 554         if (hpios_locked_mem_alloc(&phw->h_locked_mem,
 555                         sizeof(struct bus_master_interface),
 556                         pao->pci.pci_dev))
 557                 phw->p_interface_buffer = NULL;
 558         else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
 559                         (void *)&phw->p_interface_buffer))
 560                 phw->p_interface_buffer = NULL;
 561
 562         HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
 563                 phw->p_interface_buffer);
 564
 565         if (phw->p_interface_buffer) {
 566                 memset((void *)phw->p_interface_buffer, 0,
 567                         sizeof(struct bus_master_interface));
 568                 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN;
 569         }
 570
 571         err = adapter_boot_load_dsp(pao, pos_error_code);
 572         if (err) {
 573                 HPI_DEBUG_LOG(ERROR, "DSP code load failed\n");
 574                 /* no need to clean up as SubSysCreateAdapter */
 575                 /* calls DeleteAdapter on error. */
 576                 return err;
 577         }
 578         HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
 579
 580         /* allow boot load even if mem alloc wont work */
 581         if (!phw->p_interface_buffer)
 582                 return HPI_ERROR_MEMORY_ALLOC;
 583
 584         interface = phw->p_interface_buffer;
 585
 586         /* make sure the DSP has started ok */
 587         if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
 588                 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
 589                 return HPI6205_ERROR_6205_INIT_FAILED;
 590         }
 591         /* Note that *pao, *phw are zeroed after allocation,
 592          * so pointers and flags are NULL by default.
 593          * Allocate bus mastering control cache buffer and tell the DSP about it
 594          */
 595         if (interface->control_cache.number_of_controls) {
 596                 u8 *p_control_cache_virtual;
 597
 598                 err = hpios_locked_mem_alloc(&phw->h_control_cache,
 599                         interface->control_cache.size_in_bytes,
 600                         pao->pci.pci_dev);
 601                 if (!err)
 602                         err = hpios_locked_mem_get_virt_addr(&phw->
 603                                 h_control_cache,
 604                                 (void *)&p_control_cache_virtual);
 605                 if (!err) {
 606                         memset(p_control_cache_virtual, 0,
 607                                 interface->control_cache.size_in_bytes);
 608
 609                         phw->p_cache =
 610                                 hpi_alloc_control_cache(interface->
 611                                 control_cache.number_of_controls,
 612                                 interface->control_cache.size_in_bytes,
 613                                 p_control_cache_virtual);
 614
 615                         if (!phw->p_cache)
 616                                 err = HPI_ERROR_MEMORY_ALLOC;
 617                 }
 618                 if (!err) {
 619                         err = hpios_locked_mem_get_phys_addr(&phw->
 620                                 h_control_cache, &phys_addr);
 621                         interface->control_cache.physical_address32 =
 622                                 phys_addr;
 623                 }
 624
 625                 if (!err)
 626                         pao->has_control_cache = 1;
 627                 else {
 628                         if (hpios_locked_mem_valid(&phw->h_control_cache))
 629                                 hpios_locked_mem_free(&phw->h_control_cache);
 630                         pao->has_control_cache = 0;
 631                 }
 632         }
 633         send_dsp_command(phw, H620_HIF_IDLE);
 634
 635         {
 636                 struct hpi_message hm;
 637                 struct hpi_response hr;
 638
 639                 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
 640                 memset(&hm, 0, sizeof(hm));
 641                 /* wAdapterIndex == version == 0 */
 642                 hm.type = HPI_TYPE_REQUEST;
 643                 hm.size = sizeof(hm);
 644                 hm.object = HPI_OBJ_ADAPTER;
 645                 hm.function = HPI_ADAPTER_GET_INFO;
 646
 647                 memset(&hr, 0, sizeof(hr));
 648                 hr.size = sizeof(hr);
 649
 650                 err = message_response_sequence(pao, &hm, &hr);
 651                 if (err) {
 652                         HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
 653                                 err);
 654                         return err;
 655                 }
 656                 if (hr.error)
 657                         return hr.error;
 658
 659                 pao->type = hr.u.ax.info.adapter_type;
 660                 pao->index = hr.u.ax.info.adapter_index;
 661
 662                 HPI_DEBUG_LOG(VERBOSE,
 663                         "got adapter info type %x index %d serial %d\n",
 664                         hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index,
 665                         hr.u.ax.info.serial_number);
 666         }
 667
 668         if (phw->p_cache)
 669                 phw->p_cache->adap_idx = pao->index;
 670
 671         HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
 672
 673         pao->irq_query_and_clear = adapter_irq_query_and_clear;
 674         pao->instream_host_buffer_status =
 675                 phw->p_interface_buffer->instream_host_buffer_status;
 676         pao->outstream_host_buffer_status =
 677                 phw->p_interface_buffer->outstream_host_buffer_status;
 678
 679         return hpi_add_adapter(pao);
 680 }
 681
 682 /** Free memory areas allocated by adapter
 683  * this routine is called from AdapterDelete,
 684   * and SubSysCreateAdapter if duplicate index
 685 */
 686 static void delete_adapter_obj(struct hpi_adapter_obj *pao)
 687 {
 688         struct hpi_hw_obj *phw = pao->priv;
 689         int i;
 690
 691         if (hpios_locked_mem_valid(&phw->h_control_cache)) {
 692                 hpios_locked_mem_free(&phw->h_control_cache);
 693                 hpi_free_control_cache(phw->p_cache);
 694         }
 695
 696         if (hpios_locked_mem_valid(&phw->h_locked_mem)) {
 697                 hpios_locked_mem_free(&phw->h_locked_mem);
 698                 phw->p_interface_buffer = NULL;
 699         }
 700
 701         for (i = 0; i < HPI_MAX_STREAMS; i++)
 702                 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) {
 703                         hpios_locked_mem_free(&phw->instream_host_buffers[i]);
 704                         /*?phw->InStreamHostBuffers[i] = NULL; */
 705                         phw->instream_host_buffer_size[i] = 0;
 706                 }
 707
 708         for (i = 0; i < HPI_MAX_STREAMS; i++)
 709                 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
 710                         hpios_locked_mem_free(&phw->outstream_host_buffers
 711                                 [i]);
 712                         phw->outstream_host_buffer_size[i] = 0;
 713                 }
 714         kfree(phw);
 715 }
 716
 717 /*****************************************************************************/
 718 /* Adapter functions */
 719 static int adapter_irq_query_and_clear(struct hpi_adapter_obj *pao,
 720         u32 message)
 721 {
 722         struct hpi_hw_obj *phw = pao->priv;
 723         u32 hsr = 0;
 724
 725         hsr = ioread32(phw->prHSR);
 726         if (hsr & C6205_HSR_INTSRC) {
 727                 /* reset the interrupt from the DSP */
 728                 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
 729                 return HPI_IRQ_MIXER;
 730         }
 731
 732         return HPI_IRQ_NONE;
 733 }
 734
 735 /*****************************************************************************/
 736 /* OutStream Host buffer functions */
 737
 738 /** Allocate or attach buffer for busmastering
 739 */
 740 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
 741         struct hpi_message *phm, struct hpi_response *phr)
 742 {
 743         u16 err = 0;
 744         u32 command = phm->u.d.u.buffer.command;
 745         struct hpi_hw_obj *phw = pao->priv;
 746         struct bus_master_interface *interface = phw->p_interface_buffer;
 747
 748         hpi_init_response(phr, phm->object, phm->function, 0);
 749
 750         if (command == HPI_BUFFER_CMD_EXTERNAL
 751                 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
 752                 /* ALLOC phase, allocate a buffer with power of 2 size,
 753                    get its bus address for PCI bus mastering
 754                  */
 755                 phm->u.d.u.buffer.buffer_size =
 756                         roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
 757                 /* return old size and allocated size,
 758                    so caller can detect change */
 759                 phr->u.d.u.stream_info.data_available =
 760                         phw->outstream_host_buffer_size[phm->obj_index];
 761                 phr->u.d.u.stream_info.buffer_size =
 762                         phm->u.d.u.buffer.buffer_size;
 763
 764                 if (phw->outstream_host_buffer_size[phm->obj_index] ==
 765                         phm->u.d.u.buffer.buffer_size) {
 766                         /* Same size, no action required */
 767                         return;
 768                 }
 769
 770                 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
 771                                         obj_index]))
 772                         hpios_locked_mem_free(&phw->outstream_host_buffers
 773                                 [phm->obj_index]);
 774
 775                 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
 776                         [phm->obj_index], phm->u.d.u.buffer.buffer_size,
 777                         pao->pci.pci_dev);
 778
 779                 if (err) {
 780                         phr->error = HPI_ERROR_INVALID_DATASIZE;
 781                         phw->outstream_host_buffer_size[phm->obj_index] = 0;
 782                         return;
 783                 }
 784
 785                 err = hpios_locked_mem_get_phys_addr
 786                         (&phw->outstream_host_buffers[phm->obj_index],
 787                         &phm->u.d.u.buffer.pci_address);
 788                 /* get the phys addr into msg for single call alloc caller
 789                  * needs to do this for split alloc (or use the same message)
 790                  * return the phy address for split alloc in the respose too
 791                  */
 792                 phr->u.d.u.stream_info.auxiliary_data_available =
 793                         phm->u.d.u.buffer.pci_address;
 794
 795                 if (err) {
 796                         hpios_locked_mem_free(&phw->outstream_host_buffers
 797                                 [phm->obj_index]);
 798                         phw->outstream_host_buffer_size[phm->obj_index] = 0;
 799                         phr->error = HPI_ERROR_MEMORY_ALLOC;
 800                         return;
 801                 }
 802         }
 803
 804         if (command == HPI_BUFFER_CMD_EXTERNAL
 805                 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
 806                 /* GRANT phase.  Set up the BBM status, tell the DSP about
 807                    the buffer so it can start using BBM.
 808                  */
 809                 struct hpi_hostbuffer_status *status;
 810
 811                 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
 812                                 buffer_size - 1)) {
 813                         HPI_DEBUG_LOG(ERROR,
 814                                 "Buffer size must be 2^N not %d\n",
 815                                 phm->u.d.u.buffer.buffer_size);
 816                         phr->error = HPI_ERROR_INVALID_DATASIZE;
 817                         return;
 818                 }
 819                 phw->outstream_host_buffer_size[phm->obj_index] =
 820                         phm->u.d.u.buffer.buffer_size;
 821                 status = &interface->outstream_host_buffer_status[phm->
 822                         obj_index];
 823                 status->samples_processed = 0;
 824                 status->stream_state = HPI_STATE_STOPPED;
 825                 status->dsp_index = 0;
 826                 status->host_index = status->dsp_index;
 827                 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
 828                 status->auxiliary_data_available = 0;
 829
 830                 hw_message(pao, phm, phr);
 831
 832                 if (phr->error
 833                         && hpios_locked_mem_valid(&phw->
 834                                 outstream_host_buffers[phm->obj_index])) {
 835                         hpios_locked_mem_free(&phw->outstream_host_buffers
 836                                 [phm->obj_index]);
 837                         phw->outstream_host_buffer_size[phm->obj_index] = 0;
 838                 }
 839         }
 840 }
 841
 842 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
 843         struct hpi_message *phm, struct hpi_response *phr)
 844 {
 845         struct hpi_hw_obj *phw = pao->priv;
 846         struct bus_master_interface *interface = phw->p_interface_buffer;
 847         struct hpi_hostbuffer_status *status;
 848         u8 *p_bbm_data;
 849
 850         if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
 851                                 obj_index])) {
 852                 if (hpios_locked_mem_get_virt_addr(&phw->
 853                                 outstream_host_buffers[phm->obj_index],
 854                                 (void *)&p_bbm_data)) {
 855                         phr->error = HPI_ERROR_INVALID_OPERATION;
 856                         return;
 857                 }
 858                 status = &interface->outstream_host_buffer_status[phm->
 859                         obj_index];
 860                 hpi_init_response(phr, HPI_OBJ_OSTREAM,
 861                         HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0);
 862                 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
 863                 phr->u.d.u.hostbuffer_info.p_status = status;
 864         } else {
 865                 hpi_init_response(phr, HPI_OBJ_OSTREAM,
 866                         HPI_OSTREAM_HOSTBUFFER_GET_INFO,
 867                         HPI_ERROR_INVALID_OPERATION);
 868         }
 869 }
 870
 871 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
 872         struct hpi_message *phm, struct hpi_response *phr)
 873 {
 874         struct hpi_hw_obj *phw = pao->priv;
 875         u32 command = phm->u.d.u.buffer.command;
 876
 877         if (phw->outstream_host_buffer_size[phm->obj_index]) {
 878                 if (command == HPI_BUFFER_CMD_EXTERNAL
 879                         || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
 880                         phw->outstream_host_buffer_size[phm->obj_index] = 0;
 881                         hw_message(pao, phm, phr);
 882                         /* Tell adapter to stop using the host buffer. */
 883                 }
 884                 if (command == HPI_BUFFER_CMD_EXTERNAL
 885                         || command == HPI_BUFFER_CMD_INTERNAL_FREE)
 886                         hpios_locked_mem_free(&phw->outstream_host_buffers
 887                                 [phm->obj_index]);
 888         }
 889         /* Should HPI_ERROR_INVALID_OPERATION be returned
 890            if no host buffer is allocated? */
 891         else
 892                 hpi_init_response(phr, HPI_OBJ_OSTREAM,
 893                         HPI_OSTREAM_HOSTBUFFER_FREE, 0);
 894
 895 }
 896
 897 static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status)
 898 {
 899         return status->size_in_bytes - (status->host_index -
 900                 status->dsp_index);
 901 }
 902
 903 static void outstream_write(struct hpi_adapter_obj *pao,
 904         struct hpi_message *phm, struct hpi_response *phr)
 905 {
 906         struct hpi_hw_obj *phw = pao->priv;
 907         struct bus_master_interface *interface = phw->p_interface_buffer;
 908         struct hpi_hostbuffer_status *status;
 909         u32 space_available;
 910
 911         if (!phw->outstream_host_buffer_size[phm->obj_index]) {
 912                 /* there  is no BBM buffer, write via message */
 913                 hw_message(pao, phm, phr);
 914                 return;
 915         }
 916
 917         hpi_init_response(phr, phm->object, phm->function, 0);
 918         status = &interface->outstream_host_buffer_status[phm->obj_index];
 919
 920         space_available = outstream_get_space_available(status);
 921         if (space_available < phm->u.d.u.data.data_size) {
 922                 phr->error = HPI_ERROR_INVALID_DATASIZE;
 923                 return;
 924         }
 925
 926         /* HostBuffers is used to indicate host buffer is internally allocated.
 927            otherwise, assumed external, data written externally */
 928         if (phm->u.d.u.data.pb_data
 929                 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
 930                                 obj_index])) {
 931                 u8 *p_bbm_data;
 932                 u32 l_first_write;
 933                 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
 934
 935                 if (hpios_locked_mem_get_virt_addr(&phw->
 936                                 outstream_host_buffers[phm->obj_index],
 937                                 (void *)&p_bbm_data)) {
 938                         phr->error = HPI_ERROR_INVALID_OPERATION;
 939                         return;
 940                 }
 941
 942                 /* either all data,
 943                    or enough to fit from current to end of BBM buffer */
 944                 l_first_write =
 945                         min(phm->u.d.u.data.data_size,
 946                         status->size_in_bytes -
 947                         (status->host_index & (status->size_in_bytes - 1)));
 948
 949                 memcpy(p_bbm_data +
 950                         (status->host_index & (status->size_in_bytes - 1)),
 951                         p_app_data, l_first_write);
 952                 /* remaining data if any */
 953                 memcpy(p_bbm_data, p_app_data + l_first_write,
 954                         phm->u.d.u.data.data_size - l_first_write);
 955         }
 956
 957         /*
 958          * This version relies on the DSP code triggering an OStream buffer
 959          * update immediately following a SET_FORMAT call. The host has
 960          * already written data into the BBM buffer, but the DSP won't know
 961          * about it until dwHostIndex is adjusted.
 962          */
 963         if (phw->flag_outstream_just_reset[phm->obj_index]) {
 964                 /* Format can only change after reset. Must tell DSP. */
 965                 u16 function = phm->function;
 966                 phw->flag_outstream_just_reset[phm->obj_index] = 0;
 967                 phm->function = HPI_OSTREAM_SET_FORMAT;
 968                 hw_message(pao, phm, phr);      /* send the format to the DSP */
 969                 phm->function = function;
 970                 if (phr->error)
 971                         return;
 972         }
 973
 974         status->host_index += phm->u.d.u.data.data_size;
 975 }
 976
 977 static void outstream_get_info(struct hpi_adapter_obj *pao,
 978         struct hpi_message *phm, struct hpi_response *phr)
 979 {
 980         struct hpi_hw_obj *phw = pao->priv;
 981         struct bus_master_interface *interface = phw->p_interface_buffer;
 982         struct hpi_hostbuffer_status *status;
 983
 984         if (!phw->outstream_host_buffer_size[phm->obj_index]) {
 985                 hw_message(pao, phm, phr);
 986                 return;
 987         }
 988
 989         hpi_init_response(phr, phm->object, phm->function, 0);
 990
 991         status = &interface->outstream_host_buffer_status[phm->obj_index];
 992
 993         phr->u.d.u.stream_info.state = (u16)status->stream_state;
 994         phr->u.d.u.stream_info.samples_transferred =
 995                 status->samples_processed;
 996         phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
 997         phr->u.d.u.stream_info.data_available =
 998                 status->size_in_bytes - outstream_get_space_available(status);
 999         phr->u.d.u.stream_info.auxiliary_data_available =
1000                 status->auxiliary_data_available;
1001 }
1002
1003 static void outstream_start(struct hpi_adapter_obj *pao,
1004         struct hpi_message *phm, struct hpi_response *phr)
1005 {
1006         hw_message(pao, phm, phr);
1007 }
1008
1009 static void outstream_reset(struct hpi_adapter_obj *pao,
1010         struct hpi_message *phm, struct hpi_response *phr)
1011 {
1012         struct hpi_hw_obj *phw = pao->priv;
1013         phw->flag_outstream_just_reset[phm->obj_index] = 1;
1014         hw_message(pao, phm, phr);
1015 }
1016
1017 static void outstream_open(struct hpi_adapter_obj *pao,
1018         struct hpi_message *phm, struct hpi_response *phr)
1019 {
1020         outstream_reset(pao, phm, phr);
1021 }
1022
1023 /*****************************************************************************/
1024 /* InStream Host buffer functions */
1025
1026 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
1027         struct hpi_message *phm, struct hpi_response *phr)
1028 {
1029         u16 err = 0;
1030         u32 command = phm->u.d.u.buffer.command;
1031         struct hpi_hw_obj *phw = pao->priv;
1032         struct bus_master_interface *interface = phw->p_interface_buffer;
1033
1034         hpi_init_response(phr, phm->object, phm->function, 0);
1035
1036         if (command == HPI_BUFFER_CMD_EXTERNAL
1037                 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
1038
1039                 phm->u.d.u.buffer.buffer_size =
1040                         roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
1041                 phr->u.d.u.stream_info.data_available =
1042                         phw->instream_host_buffer_size[phm->obj_index];
1043                 phr->u.d.u.stream_info.buffer_size =
1044                         phm->u.d.u.buffer.buffer_size;
1045
1046                 if (phw->instream_host_buffer_size[phm->obj_index] ==
1047                         phm->u.d.u.buffer.buffer_size) {
1048                         /* Same size, no action required */
1049                         return;
1050                 }
1051
1052                 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1053                                         obj_index]))
1054                         hpios_locked_mem_free(&phw->instream_host_buffers
1055                                 [phm->obj_index]);
1056
1057                 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
1058                                 obj_index], phm->u.d.u.buffer.buffer_size,
1059                         pao->pci.pci_dev);
1060
1061                 if (err) {
1062                         phr->error = HPI_ERROR_INVALID_DATASIZE;
1063                         phw->instream_host_buffer_size[phm->obj_index] = 0;
1064                         return;
1065                 }
1066
1067                 err = hpios_locked_mem_get_phys_addr
1068                         (&phw->instream_host_buffers[phm->obj_index],
1069                         &phm->u.d.u.buffer.pci_address);
1070                 /* get the phys addr into msg for single call alloc. Caller
1071                    needs to do this for split alloc so return the phy address */
1072                 phr->u.d.u.stream_info.auxiliary_data_available =
1073                         phm->u.d.u.buffer.pci_address;
1074                 if (err) {
1075                         hpios_locked_mem_free(&phw->instream_host_buffers
1076                                 [phm->obj_index]);
1077                         phw->instream_host_buffer_size[phm->obj_index] = 0;
1078                         phr->error = HPI_ERROR_MEMORY_ALLOC;
1079                         return;
1080                 }
1081         }
1082
1083         if (command == HPI_BUFFER_CMD_EXTERNAL
1084                 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
1085                 struct hpi_hostbuffer_status *status;
1086
1087                 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
1088                                 buffer_size - 1)) {
1089                         HPI_DEBUG_LOG(ERROR,
1090                                 "Buffer size must be 2^N not %d\n",
1091                                 phm->u.d.u.buffer.buffer_size);
1092                         phr->error = HPI_ERROR_INVALID_DATASIZE;
1093                         return;
1094                 }
1095
1096                 phw->instream_host_buffer_size[phm->obj_index] =
1097                         phm->u.d.u.buffer.buffer_size;
1098                 status = &interface->instream_host_buffer_status[phm->
1099                         obj_index];
1100                 status->samples_processed = 0;
1101                 status->stream_state = HPI_STATE_STOPPED;
1102                 status->dsp_index = 0;
1103                 status->host_index = status->dsp_index;
1104                 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
1105                 status->auxiliary_data_available = 0;
1106
1107                 hw_message(pao, phm, phr);
1108
1109                 if (phr->error
1110                         && hpios_locked_mem_valid(&phw->
1111                                 instream_host_buffers[phm->obj_index])) {
1112                         hpios_locked_mem_free(&phw->instream_host_buffers
1113                                 [phm->obj_index]);
1114                         phw->instream_host_buffer_size[phm->obj_index] = 0;
1115                 }
1116         }
1117 }
1118
1119 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
1120         struct hpi_message *phm, struct hpi_response *phr)
1121 {
1122         struct hpi_hw_obj *phw = pao->priv;
1123         struct bus_master_interface *interface = phw->p_interface_buffer;
1124         struct hpi_hostbuffer_status *status;
1125         u8 *p_bbm_data;
1126
1127         if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1128                                 obj_index])) {
1129                 if (hpios_locked_mem_get_virt_addr(&phw->
1130                                 instream_host_buffers[phm->obj_index],
1131                                 (void *)&p_bbm_data)) {
1132                         phr->error = HPI_ERROR_INVALID_OPERATION;
1133                         return;
1134                 }
1135                 status = &interface->instream_host_buffer_status[phm->
1136                         obj_index];
1137                 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1138                         HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0);
1139                 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
1140                 phr->u.d.u.hostbuffer_info.p_status = status;
1141         } else {
1142                 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1143                         HPI_ISTREAM_HOSTBUFFER_GET_INFO,
1144                         HPI_ERROR_INVALID_OPERATION);
1145         }
1146 }
1147
1148 static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
1149         struct hpi_message *phm, struct hpi_response *phr)
1150 {
1151         struct hpi_hw_obj *phw = pao->priv;
1152         u32 command = phm->u.d.u.buffer.command;
1153
1154         if (phw->instream_host_buffer_size[phm->obj_index]) {
1155                 if (command == HPI_BUFFER_CMD_EXTERNAL
1156                         || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
1157                         phw->instream_host_buffer_size[phm->obj_index] = 0;
1158                         hw_message(pao, phm, phr);
1159                 }
1160
1161                 if (command == HPI_BUFFER_CMD_EXTERNAL
1162                         || command == HPI_BUFFER_CMD_INTERNAL_FREE)
1163                         hpios_locked_mem_free(&phw->instream_host_buffers
1164                                 [phm->obj_index]);
1165
1166         } else {
1167                 /* Should HPI_ERROR_INVALID_OPERATION be returned
1168                    if no host buffer is allocated? */
1169                 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1170                         HPI_ISTREAM_HOSTBUFFER_FREE, 0);
1171
1172         }
1173
1174 }
1175
1176 static void instream_start(struct hpi_adapter_obj *pao,
1177         struct hpi_message *phm, struct hpi_response *phr)
1178 {
1179         hw_message(pao, phm, phr);
1180 }
1181
1182 static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status)
1183 {
1184         return status->dsp_index - status->host_index;
1185 }
1186
1187 static void instream_read(struct hpi_adapter_obj *pao,
1188         struct hpi_message *phm, struct hpi_response *phr)
1189 {
1190         struct hpi_hw_obj *phw = pao->priv;
1191         struct bus_master_interface *interface = phw->p_interface_buffer;
1192         struct hpi_hostbuffer_status *status;
1193         u32 data_available;
1194         u8 *p_bbm_data;
1195         u32 l_first_read;
1196         u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
1197
1198         if (!phw->instream_host_buffer_size[phm->obj_index]) {
1199                 hw_message(pao, phm, phr);
1200                 return;
1201         }
1202         hpi_init_response(phr, phm->object, phm->function, 0);
1203
1204         status = &interface->instream_host_buffer_status[phm->obj_index];
1205         data_available = instream_get_bytes_available(status);
1206         if (data_available < phm->u.d.u.data.data_size) {
1207                 phr->error = HPI_ERROR_INVALID_DATASIZE;
1208                 return;
1209         }
1210
1211         if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1212                                 obj_index])) {
1213                 if (hpios_locked_mem_get_virt_addr(&phw->
1214                                 instream_host_buffers[phm->obj_index],
1215                                 (void *)&p_bbm_data)) {
1216                         phr->error = HPI_ERROR_INVALID_OPERATION;
1217                         return;
1218                 }
1219
1220                 /* either all data,
1221                    or enough to fit from current to end of BBM buffer */
1222                 l_first_read =
1223                         min(phm->u.d.u.data.data_size,
1224                         status->size_in_bytes -
1225                         (status->host_index & (status->size_in_bytes - 1)));
1226
1227                 memcpy(p_app_data,
1228                         p_bbm_data +
1229                         (status->host_index & (status->size_in_bytes - 1)),
1230                         l_first_read);
1231                 /* remaining data if any */
1232                 memcpy(p_app_data + l_first_read, p_bbm_data,
1233                         phm->u.d.u.data.data_size - l_first_read);
1234         }
1235         status->host_index += phm->u.d.u.data.data_size;
1236 }
1237
1238 static void instream_get_info(struct hpi_adapter_obj *pao,
1239         struct hpi_message *phm, struct hpi_response *phr)
1240 {
1241         struct hpi_hw_obj *phw = pao->priv;
1242         struct bus_master_interface *interface = phw->p_interface_buffer;
1243         struct hpi_hostbuffer_status *status;
1244         if (!phw->instream_host_buffer_size[phm->obj_index]) {
1245                 hw_message(pao, phm, phr);
1246                 return;
1247         }
1248
1249         status = &interface->instream_host_buffer_status[phm->obj_index];
1250
1251         hpi_init_response(phr, phm->object, phm->function, 0);
1252
1253         phr->u.d.u.stream_info.state = (u16)status->stream_state;
1254         phr->u.d.u.stream_info.samples_transferred =
1255                 status->samples_processed;
1256         phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
1257         phr->u.d.u.stream_info.data_available =
1258                 instream_get_bytes_available(status);
1259         phr->u.d.u.stream_info.auxiliary_data_available =
1260                 status->auxiliary_data_available;
1261 }
1262
1263 /*****************************************************************************/
1264 /* LOW-LEVEL */
1265 #define HPI6205_MAX_FILES_TO_LOAD 2
1266
1267 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
1268         u32 *pos_error_code)
1269 {
1270         struct hpi_hw_obj *phw = pao->priv;
1271         struct dsp_code dsp_code;
1272         u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
1273         u32 temp;
1274         int dsp = 0, i = 0;
1275         u16 err = 0;
1276
1277         boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
1278
1279         boot_code_id[1] = pao->pci.pci_dev->subsystem_device;
1280         boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]);
1281
1282         /* fix up cases where bootcode id[1] != subsys id */
1283         switch (boot_code_id[1]) {
1284         case HPI_ADAPTER_FAMILY_ASI(0x5000):
1285                 boot_code_id[0] = boot_code_id[1];
1286                 boot_code_id[1] = 0;
1287                 break;
1288         case HPI_ADAPTER_FAMILY_ASI(0x5300):
1289         case HPI_ADAPTER_FAMILY_ASI(0x5400):
1290         case HPI_ADAPTER_FAMILY_ASI(0x6300):
1291                 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400);
1292                 break;
1293         case HPI_ADAPTER_FAMILY_ASI(0x5500):
1294         case HPI_ADAPTER_FAMILY_ASI(0x5600):
1295         case HPI_ADAPTER_FAMILY_ASI(0x6500):
1296                 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600);
1297                 break;
1298         case HPI_ADAPTER_FAMILY_ASI(0x8800):
1299                 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900);
1300                 break;
1301         default:
1302                 break;
1303         }
1304
1305         /* reset DSP by writing a 1 to the WARMRESET bit */
1306         temp = C6205_HDCR_WARMRESET;
1307         iowrite32(temp, phw->prHDCR);
1308         hpios_delay_micro_seconds(1000);
1309
1310         /* check that PCI i/f was configured by EEPROM */
1311         temp = ioread32(phw->prHSR);
1312         if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
1313                 C6205_HSR_EEREAD)
1314                 return HPI6205_ERROR_6205_EEPROM;
1315         temp |= 0x04;
1316         /* disable PINTA interrupt */
1317         iowrite32(temp, phw->prHSR);
1318
1319         /* check control register reports PCI boot mode */
1320         temp = ioread32(phw->prHDCR);
1321         if (!(temp & C6205_HDCR_PCIBOOT))
1322                 return HPI6205_ERROR_6205_REG;
1323
1324         /* try writing a few numbers to the DSP page register */
1325         /* and reading them back. */
1326         temp = 3;
1327         iowrite32(temp, phw->prDSPP);
1328         if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1329                 return HPI6205_ERROR_6205_DSPPAGE;
1330         temp = 2;
1331         iowrite32(temp, phw->prDSPP);
1332         if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1333                 return HPI6205_ERROR_6205_DSPPAGE;
1334         temp = 1;
1335         iowrite32(temp, phw->prDSPP);
1336         if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1337                 return HPI6205_ERROR_6205_DSPPAGE;
1338         /* reset DSP page to the correct number */
1339         temp = 0;
1340         iowrite32(temp, phw->prDSPP);
1341         if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1342                 return HPI6205_ERROR_6205_DSPPAGE;
1343         phw->dsp_page = 0;
1344
1345         /* release 6713 from reset before 6205 is bootloaded.
1346            This ensures that the EMIF is inactive,
1347            and the 6713 HPI gets the correct bootmode etc
1348          */
1349         if (boot_code_id[1] != 0) {
1350                 /* DSP 1 is a C6713 */
1351                 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */
1352                 boot_loader_write_mem32(pao, 0, 0x018C0024, 0x00002202);
1353                 hpios_delay_micro_seconds(100);
1354                 /* Reset the 6713 #1 - revB */
1355                 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
1356                 /* value of bit 3 is unknown after DSP reset, other bits shoudl be 0 */
1357                 if (0 != (boot_loader_read_mem32(pao, 0,
1358                                         (C6205_BAR0_TIMER1_CTL)) & ~8))
1359                         return HPI6205_ERROR_6205_REG;
1360                 hpios_delay_micro_seconds(100);
1361
1362                 /* Release C6713 from reset - revB */
1363                 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4);
1364                 if (4 != (boot_loader_read_mem32(pao, 0,
1365                                         (C6205_BAR0_TIMER1_CTL)) & ~8))
1366                         return HPI6205_ERROR_6205_REG;
1367                 hpios_delay_micro_seconds(100);
1368         }
1369
1370         for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) {
1371                 /* is there a DSP to load? */
1372                 if (boot_code_id[dsp] == 0)
1373                         continue;
1374
1375                 err = boot_loader_config_emif(pao, dsp);
1376                 if (err)
1377                         return err;
1378
1379                 err = boot_loader_test_internal_memory(pao, dsp);
1380                 if (err)
1381                         return err;
1382
1383                 err = boot_loader_test_external_memory(pao, dsp);
1384                 if (err)
1385                         return err;
1386
1387                 err = boot_loader_test_pld(pao, dsp);
1388                 if (err)
1389                         return err;
1390
1391                 /* write the DSP code down into the DSPs memory */
1392                 err = hpi_dsp_code_open(boot_code_id[dsp], pao->pci.pci_dev,
1393                         &dsp_code, pos_error_code);
1394                 if (err)
1395                         return err;
1396
1397                 while (1) {
1398                         u32 length;
1399                         u32 address;
1400                         u32 type;
1401                         u32 *pcode;
1402
1403                         err = hpi_dsp_code_read_word(&dsp_code, &length);
1404                         if (err)
1405                                 break;
1406                         if (length == 0xFFFFFFFF)
1407                                 break;  /* end of code */
1408
1409                         err = hpi_dsp_code_read_word(&dsp_code, &address);
1410                         if (err)
1411                                 break;
1412                         err = hpi_dsp_code_read_word(&dsp_code, &type);
1413                         if (err)
1414                                 break;
1415                         err = hpi_dsp_code_read_block(length, &dsp_code,
1416                                 &pcode);
1417                         if (err)
1418                                 break;
1419                         for (i = 0; i < (int)length; i++) {
1420                                 boot_loader_write_mem32(pao, dsp, address,
1421                                         *pcode);
1422                                 /* dummy read every 4 words */
1423                                 /* for 6205 advisory 1.4.4 */
1424                                 if (i % 4 == 0)
1425                                         boot_loader_read_mem32(pao, dsp,
1426                                                 address);
1427                                 pcode++;
1428                                 address += 4;
1429                         }
1430
1431                 }
1432                 if (err) {
1433                         hpi_dsp_code_close(&dsp_code);
1434                         return err;
1435                 }
1436
1437                 /* verify code */
1438                 hpi_dsp_code_rewind(&dsp_code);
1439                 while (1) {
1440                         u32 length = 0;
1441                         u32 address = 0;
1442                         u32 type = 0;
1443                         u32 *pcode = NULL;
1444                         u32 data = 0;
1445
1446                         hpi_dsp_code_read_word(&dsp_code, &length);
1447                         if (length == 0xFFFFFFFF)
1448                                 break;  /* end of code */
1449
1450                         hpi_dsp_code_read_word(&dsp_code, &address);
1451                         hpi_dsp_code_read_word(&dsp_code, &type);
1452                         hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1453
1454                         for (i = 0; i < (int)length; i++) {
1455                                 data = boot_loader_read_mem32(pao, dsp,
1456                                         address);
1457                                 if (data != *pcode) {
1458                                         err = 0;
1459                                         break;
1460                                 }
1461                                 pcode++;
1462                                 address += 4;
1463                         }
1464                         if (err)
1465                                 break;
1466                 }
1467                 hpi_dsp_code_close(&dsp_code);
1468                 if (err)
1469                         return err;
1470         }
1471
1472         /* After bootloading all DSPs, start DSP0 running
1473          * The DSP0 code will handle starting and synchronizing with its slaves
1474          */
1475         if (phw->p_interface_buffer) {
1476                 /* we need to tell the card the physical PCI address */
1477                 u32 physicalPC_iaddress;
1478                 struct bus_master_interface *interface =
1479                         phw->p_interface_buffer;
1480                 u32 host_mailbox_address_on_dsp;
1481                 u32 physicalPC_iaddress_verify = 0;
1482                 int time_out = 10;
1483                 /* set ack so we know when DSP is ready to go */
1484                 /* (dwDspAck will be changed to HIF_RESET) */
1485                 interface->dsp_ack = H620_HIF_UNKNOWN;
1486                 wmb();  /* ensure ack is written before dsp writes back */
1487
1488                 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
1489                         &physicalPC_iaddress);
1490
1491                 /* locate the host mailbox on the DSP. */
1492                 host_mailbox_address_on_dsp = 0x80000000;
1493                 while ((physicalPC_iaddress != physicalPC_iaddress_verify)
1494                         && time_out--) {
1495                         boot_loader_write_mem32(pao, 0,
1496                                 host_mailbox_address_on_dsp,
1497                                 physicalPC_iaddress);
1498                         physicalPC_iaddress_verify =
1499                                 boot_loader_read_mem32(pao, 0,
1500                                 host_mailbox_address_on_dsp);
1501                 }
1502         }
1503         HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");
1504         /* enable interrupts */
1505         temp = ioread32(phw->prHSR);
1506         temp &= ~(u32)C6205_HSR_INTAM;
1507         iowrite32(temp, phw->prHSR);
1508
1509         /* start code running... */
1510         temp = ioread32(phw->prHDCR);
1511         temp |= (u32)C6205_HDCR_DSPINT;
1512         iowrite32(temp, phw->prHDCR);
1513
1514         /* give the DSP 10ms to start up */
1515         hpios_delay_micro_seconds(10000);
1516         return err;
1517
1518 }
1519
1520 /*****************************************************************************/
1521 /* Bootloader utility functions */
1522
1523 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
1524         u32 address)
1525 {
1526         struct hpi_hw_obj *phw = pao->priv;
1527         u32 data = 0;
1528         __iomem u32 *p_data;
1529
1530         if (dsp_index == 0) {
1531                 /* DSP 0 is always C6205 */
1532                 if ((address >= 0x01800000) & (address < 0x02000000)) {
1533                         /* BAR1 register access */
1534                         p_data = pao->pci.ap_mem_base[1] +
1535                                 (address & 0x007fffff) /
1536                                 sizeof(*pao->pci.ap_mem_base[1]);
1537                         /* HPI_DEBUG_LOG(WARNING,
1538                            "BAR1 access %08x\n", dwAddress); */
1539                 } else {
1540                         u32 dw4M_page = address >> 22L;
1541                         if (dw4M_page != phw->dsp_page) {
1542                                 phw->dsp_page = dw4M_page;
1543                                 /* *INDENT OFF* */
1544                                 iowrite32(phw->dsp_page, phw->prDSPP);
1545                                 /* *INDENT-ON* */
1546                         }
1547                         address &= 0x3fffff;    /* address within 4M page */
1548                         /* BAR0 memory access */
1549                         p_data = pao->pci.ap_mem_base[0] +
1550                                 address / sizeof(u32);
1551                 }
1552                 data = ioread32(p_data);
1553         } else if (dsp_index == 1) {
1554                 /* DSP 1 is a C6713 */
1555                 u32 lsb;
1556                 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1557                 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1558                 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
1559                 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
1560                 data = (data << 16) | (lsb & 0xFFFF);
1561         }
1562         return data;
1563 }
1564
1565 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
1566         int dsp_index, u32 address, u32 data)
1567 {
1568         struct hpi_hw_obj *phw = pao->priv;
1569         __iomem u32 *p_data;
1570         /*      u32 dwVerifyData=0; */
1571
1572         if (dsp_index == 0) {
1573                 /* DSP 0 is always C6205 */
1574                 if ((address >= 0x01800000) & (address < 0x02000000)) {
1575                         /* BAR1 - DSP  register access using */
1576                         /* Non-prefetchable PCI access */
1577                         p_data = pao->pci.ap_mem_base[1] +
1578                                 (address & 0x007fffff) /
1579                                 sizeof(*pao->pci.ap_mem_base[1]);
1580                 } else {
1581                         /* BAR0 access - all of DSP memory using */
1582                         /* pre-fetchable PCI access */
1583                         u32 dw4M_page = address >> 22L;
1584                         if (dw4M_page != phw->dsp_page) {
1585                                 phw->dsp_page = dw4M_page;
1586                                 /* *INDENT-OFF* */
1587                                 iowrite32(phw->dsp_page, phw->prDSPP);
1588                                 /* *INDENT-ON* */
1589                         }
1590                         address &= 0x3fffff;    /* address within 4M page */
1591                         p_data = pao->pci.ap_mem_base[0] +
1592                                 address / sizeof(u32);
1593                 }
1594                 iowrite32(data, p_data);
1595         } else if (dsp_index == 1) {
1596                 /* DSP 1 is a C6713 */
1597                 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1598                 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1599
1600                 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1601                 boot_loader_read_mem32(pao, 0, 0);
1602
1603                 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
1604                 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
1605
1606                 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1607                 boot_loader_read_mem32(pao, 0, 0);
1608         }
1609 }
1610
1611 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
1612 {
1613         if (dsp_index == 0) {
1614                 u32 setting;
1615
1616                 /* DSP 0 is always C6205 */
1617
1618                 /* Set the EMIF */
1619                 /* memory map of C6205 */
1620                 /* 00000000-0000FFFF    16Kx32 internal program */
1621                 /* 00400000-00BFFFFF    CE0     2Mx32 SDRAM running @ 100MHz */
1622
1623                 /* EMIF config */
1624                 /*------------ */
1625                 /* Global EMIF control */
1626                 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779);
1627 #define WS_OFS 28
1628 #define WST_OFS 22
1629 #define WH_OFS 20
1630 #define RS_OFS 16
1631 #define RST_OFS 8
1632 #define MTYPE_OFS 4
1633 #define RH_OFS 0
1634
1635                 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
1636                 setting = 0x00000030;
1637                 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
1638                 if (setting != boot_loader_read_mem32(pao, dsp_index,
1639                                 0x01800008))
1640                         return HPI6205_ERROR_DSP_EMIF1;
1641
1642                 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
1643                 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1644                 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
1645                 /* WST should be 71, but 63  is max possible */
1646                 setting =
1647                         (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
1648                         (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1649                         (2L << MTYPE_OFS);
1650                 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
1651                 if (setting != boot_loader_read_mem32(pao, dsp_index,
1652                                 0x01800004))
1653                         return HPI6205_ERROR_DSP_EMIF2;
1654
1655                 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
1656                 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1657                 /* plenty of wait states */
1658                 setting =
1659                         (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
1660                         (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1661                         (2L << MTYPE_OFS);
1662                 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
1663                 if (setting != boot_loader_read_mem32(pao, dsp_index,
1664                                 0x01800010))
1665                         return HPI6205_ERROR_DSP_EMIF3;
1666
1667                 /* EMIF CE3 setup - 32 bit async. */
1668                 /* This is the PLD on the ASI5000 cards only */
1669                 setting =
1670                         (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
1671                         (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
1672                         (2L << MTYPE_OFS);
1673                 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
1674                 if (setting != boot_loader_read_mem32(pao, dsp_index,
1675                                 0x01800014))
1676                         return HPI6205_ERROR_DSP_EMIF4;
1677
1678                 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
1679                 /*  need to use this else DSP code crashes? */
1680                 boot_loader_write_mem32(pao, dsp_index, 0x01800018,
1681                         0x07117000);
1682
1683                 /* EMIF SDRAM Refresh Timing */
1684                 /* EMIF SDRAM timing  (orig = 0x410, emulator = 0x61a) */
1685                 boot_loader_write_mem32(pao, dsp_index, 0x0180001C,
1686                         0x00000410);
1687
1688         } else if (dsp_index == 1) {
1689                 /* test access to the C6713s HPI registers */
1690                 u32 write_data = 0, read_data = 0, i = 0;
1691
1692                 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
1693                 write_data = 1;
1694                 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
1695                 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
1696                 /* C67 HPI is on lower 16bits of 32bit EMIF */
1697                 read_data =
1698                         0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
1699                 if (write_data != read_data) {
1700                         HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
1701                                 read_data);
1702                         return HPI6205_ERROR_C6713_HPIC;
1703                 }
1704                 /* HPIA - walking ones test */
1705                 write_data = 1;
1706                 for (i = 0; i < 32; i++) {
1707                         boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
1708                                 write_data);
1709                         boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
1710                                 (write_data >> 16));
1711                         read_data =
1712                                 0xFFFF & boot_loader_read_mem32(pao, 0,
1713                                 HPIAL_ADDR);
1714                         read_data =
1715                                 read_data | ((0xFFFF &
1716                                         boot_loader_read_mem32(pao, 0,
1717                                                 HPIAH_ADDR))
1718                                 << 16);
1719                         if (read_data != write_data) {
1720                                 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
1721                                         write_data, read_data);
1722                                 return HPI6205_ERROR_C6713_HPIA;
1723                         }
1724                         write_data = write_data << 1;
1725                 }
1726
1727                 /* setup C67x PLL
1728                  *  ** C6713 datasheet says we cannot program PLL from HPI,
1729                  * and indeed if we try to set the PLL multiply from the HPI,
1730                  * the PLL does not seem to lock, so we enable the PLL and
1731                  * use the default multiply of x 7, which for a 27MHz clock
1732                  * gives a DSP speed of 189MHz
1733                  */
1734                 /* bypass PLL */
1735                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);
1736                 hpios_delay_micro_seconds(1000);
1737                 /* EMIF = 189/3=63MHz */
1738                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002);
1739                 /* peri = 189/2 */
1740                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001);
1741                 /* cpu  = 189/1 */
1742                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);
1743                 hpios_delay_micro_seconds(1000);
1744                 /* ** SGT test to take GPO3 high when we start the PLL */
1745                 /* and low when the delay is completed */
1746                 /* FSX0 <- '1' (GPO3) */
1747                 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A);
1748                 /* PLL not bypassed */
1749                 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);
1750                 hpios_delay_micro_seconds(1000);
1751                 /* FSX0 <- '0' (GPO3) */
1752                 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);
1753
1754                 /* 6205 EMIF CE1 resetup - 32 bit async. */
1755                 /* Now 6713 #1 is running at 189MHz can reduce waitstates */
1756                 boot_loader_write_mem32(pao, 0, 0x01800004,     /* CE1 */
1757                         (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) |
1758                         (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) |
1759                         (2L << MTYPE_OFS));
1760
1761                 hpios_delay_micro_seconds(1000);
1762
1763                 /* check that we can read one of the PLL registers */
1764                 /* PLL should not be bypassed! */
1765                 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
1766                         != 0x0001) {
1767                         return HPI6205_ERROR_C6713_PLL;
1768                 }
1769                 /* setup C67x EMIF  (note this is the only use of
1770                    BAR1 via BootLoader_WriteMem32) */
1771                 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
1772                         0x000034A8);
1773
1774                 /* EMIF CE0 setup - 2Mx32 Sync DRAM
1775                    31..28       Wr setup
1776                    27..22       Wr strobe
1777                    21..20       Wr hold
1778                    19..16       Rd setup
1779                    15..14       -
1780                    13..8        Rd strobe
1781                    7..4         MTYPE   0011            Sync DRAM 32bits
1782                    3            Wr hold MSB
1783                    2..0         Rd hold
1784                  */
1785                 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
1786                         0x00000030);
1787
1788                 /* EMIF SDRAM Extension
1789                    0x00
1790                    31-21        0000b 0000b 000b
1791                    20           WR2RD = 2cycles-1  = 1b
1792
1793                    19-18        WR2DEAC = 3cycle-1 = 10b
1794                    17           WR2WR = 2cycle-1   = 1b
1795                    16-15        R2WDQM = 4cycle-1  = 11b
1796                    14-12        RD2WR = 6cycles-1  = 101b
1797
1798                    11-10        RD2DEAC = 4cycle-1 = 11b
1799                    9            RD2RD = 2cycle-1   = 1b
1800                    8-7          THZP = 3cycle-1    = 10b
1801                    6-5          TWR  = 2cycle-1    = 01b (tWR = 17ns)
1802                    4            TRRD = 2cycle      = 0b  (tRRD = 14ns)
1803                    3-1          TRAS = 5cycle-1    = 100b (Tras=42ns)
1804                    1            CAS latency = 3cyc = 1b
1805                    (for Micron 2M32-7 operating at 100MHz)
1806                  */
1807                 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
1808                         0x001BDF29);
1809
1810                 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
1811                    31           -       0b       -
1812                    30           SDBSZ   1b              4 bank
1813                    29..28       SDRSZ   00b             11 row address pins
1814
1815                    27..26       SDCSZ   01b             8 column address pins
1816                    25           RFEN    1b              refersh enabled
1817                    24           INIT    1b              init SDRAM!
1818
1819                    23..20       TRCD    0001b                   (Trcd/Tcyc)-1 = (20/10)-1 = 1
1820
1821                    19..16       TRP     0001b                   (Trp/Tcyc)-1 = (20/10)-1 = 1
1822
1823                    15..12       TRC     0110b                   (Trc/Tcyc)-1 = (70/10)-1 = 6
1824
1825                    11..0        -       0000b 0000b 0000b
1826                  */
1827                 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
1828                         0x47116000);
1829
1830                 /* SDRAM refresh timing
1831                    Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A
1832                  */
1833                 boot_loader_write_mem32(pao, dsp_index,
1834                         C6713_EMIF_SDRAMTIMING, 0x00000410);
1835
1836                 hpios_delay_micro_seconds(1000);
1837         } else if (dsp_index == 2) {
1838                 /* DSP 2 is a C6713 */
1839         }
1840
1841         return 0;
1842 }
1843
1844 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
1845         u32 start_address, u32 length)
1846 {
1847         u32 i = 0, j = 0;
1848         u32 test_addr = 0;
1849         u32 test_data = 0, data = 0;
1850
1851         length = 1000;
1852
1853         /* for 1st word, test each bit in the 32bit word, */
1854         /* dwLength specifies number of 32bit words to test */
1855         /*for(i=0; i<dwLength; i++) */
1856         i = 0;
1857         {
1858                 test_addr = start_address + i * 4;
1859                 test_data = 0x00000001;
1860                 for (j = 0; j < 32; j++) {
1861                         boot_loader_write_mem32(pao, dsp_index, test_addr,
1862                                 test_data);
1863                         data = boot_loader_read_mem32(pao, dsp_index,
1864                                 test_addr);
1865                         if (data != test_data) {
1866                                 HPI_DEBUG_LOG(VERBOSE,
1867                                         "Memtest error details  "
1868                                         "%08x %08x %08x %i\n", test_addr,
1869                                         test_data, data, dsp_index);
1870                                 return 1;       /* error */
1871                         }
1872                         test_data = test_data << 1;
1873                 }       /* for(j) */
1874         }       /* for(i) */
1875
1876         /* for the next 100 locations test each location, leaving it as zero */
1877         /* write a zero to the next word in memory before we read */
1878         /* the previous write to make sure every memory location is unique */
1879         for (i = 0; i < 100; i++) {
1880                 test_addr = start_address + i * 4;
1881                 test_data = 0xA5A55A5A;
1882                 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
1883                 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
1884                 data = boot_loader_read_mem32(pao, dsp_index, test_addr);
1885                 if (data != test_data) {
1886                         HPI_DEBUG_LOG(VERBOSE,
1887                                 "Memtest error details  "
1888                                 "%08x %08x %08x %i\n", test_addr, test_data,
1889                                 data, dsp_index);
1890                         return 1;       /* error */
1891                 }
1892                 /* leave location as zero */
1893                 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1894         }
1895
1896         /* zero out entire memory block */
1897         for (i = 0; i < length; i++) {
1898                 test_addr = start_address + i * 4;
1899                 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1900         }
1901         return 0;
1902 }
1903
1904 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
1905         int dsp_index)
1906 {
1907         int err = 0;
1908         if (dsp_index == 0) {
1909                 /* DSP 0 is a C6205 */
1910                 /* 64K prog mem */
1911                 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1912                         0x10000);
1913                 if (!err)
1914                         /* 64K data mem */
1915                         err = boot_loader_test_memory(pao, dsp_index,
1916                                 0x80000000, 0x10000);
1917         } else if (dsp_index == 1) {
1918                 /* DSP 1 is a C6713 */
1919                 /* 192K internal mem */
1920                 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1921                         0x30000);
1922                 if (!err)
1923                         /* 64K internal mem / L2 cache */
1924                         err = boot_loader_test_memory(pao, dsp_index,
1925                                 0x00030000, 0x10000);
1926         }
1927
1928         if (err)
1929                 return HPI6205_ERROR_DSP_INTMEM;
1930         else
1931                 return 0;
1932 }
1933
1934 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
1935         int dsp_index)
1936 {
1937         u32 dRAM_start_address = 0;
1938         u32 dRAM_size = 0;
1939
1940         if (dsp_index == 0) {
1941                 /* only test for SDRAM if an ASI5000 card */
1942                 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1943                         /* DSP 0 is always C6205 */
1944                         dRAM_start_address = 0x00400000;
1945                         dRAM_size = 0x200000;
1946                         /*dwDRAMinc=1024; */
1947                 } else
1948                         return 0;
1949         } else if (dsp_index == 1) {
1950                 /* DSP 1 is a C6713 */
1951                 dRAM_start_address = 0x80000000;
1952                 dRAM_size = 0x200000;
1953                 /*dwDRAMinc=1024; */
1954         }
1955
1956         if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
1957                         dRAM_size))
1958                 return HPI6205_ERROR_DSP_EXTMEM;
1959         return 0;
1960 }
1961
1962 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
1963 {
1964         u32 data = 0;
1965         if (dsp_index == 0) {
1966                 /* only test for DSP0 PLD on ASI5000 card */
1967                 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1968                         /* PLD is located at CE3=0x03000000 */
1969                         data = boot_loader_read_mem32(pao, dsp_index,
1970                                 0x03000008);
1971                         if ((data & 0xF) != 0x5)
1972                                 return HPI6205_ERROR_DSP_PLD;
1973                         data = boot_loader_read_mem32(pao, dsp_index,
1974                                 0x0300000C);
1975                         if ((data & 0xF) != 0xA)
1976                                 return HPI6205_ERROR_DSP_PLD;
1977                 }
1978         } else if (dsp_index == 1) {
1979                 /* DSP 1 is a C6713 */
1980                 if (pao->pci.pci_dev->subsystem_device == 0x8700) {
1981                         /* PLD is located at CE1=0x90000000 */
1982                         data = boot_loader_read_mem32(pao, dsp_index,
1983                                 0x90000010);
1984                         if ((data & 0xFF) != 0xAA)
1985                                 return HPI6205_ERROR_DSP_PLD;
1986                         /* 8713 - LED on */
1987                         boot_loader_write_mem32(pao, dsp_index, 0x90000000,
1988                                 0x02);
1989                 }
1990         }
1991         return 0;
1992 }
1993
1994 /** Transfer data to or from DSP
1995  nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA
1996 */
1997 static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data,
1998         u32 data_size, int operation)
1999 {
2000         struct hpi_hw_obj *phw = pao->priv;
2001         u32 data_transferred = 0;
2002         u16 err = 0;
2003         u32 temp2;
2004         struct bus_master_interface *interface = phw->p_interface_buffer;
2005
2006         if (!p_data)
2007                 return HPI_ERROR_INVALID_DATA_POINTER;
2008
2009         data_size &= ~3L;       /* round data_size down to nearest 4 bytes */
2010
2011         /* make sure state is IDLE */
2012         if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT))
2013                 return HPI_ERROR_DSP_HARDWARE;
2014
2015         while (data_transferred < data_size) {
2016                 u32 this_copy = data_size - data_transferred;
2017
2018                 if (this_copy > HPI6205_SIZEOF_DATA)
2019                         this_copy = HPI6205_SIZEOF_DATA;
2020
2021                 if (operation == H620_HIF_SEND_DATA)
2022                         memcpy((void *)&interface->u.b_data[0],
2023                                 &p_data[data_transferred], this_copy);
2024
2025                 interface->transfer_size_in_bytes = this_copy;
2026
2027                 /* DSP must change this back to nOperation */
2028                 interface->dsp_ack = H620_HIF_IDLE;
2029                 send_dsp_command(phw, operation);
2030
2031                 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
2032                 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2033                         HPI6205_TIMEOUT - temp2, this_copy);
2034
2035                 if (!temp2) {
2036                         /* timed out */
2037                         HPI_DEBUG_LOG(ERROR,
2038                                 "Timed out waiting for " "state %d got %d\n",
2039                                 operation, interface->dsp_ack);
2040
2041                         break;
2042                 }
2043                 if (operation == H620_HIF_GET_DATA)
2044                         memcpy(&p_data[data_transferred],
2045                                 (void *)&interface->u.b_data[0], this_copy);
2046
2047                 data_transferred += this_copy;
2048         }
2049         if (interface->dsp_ack != operation)
2050                 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n",
2051                         interface->dsp_ack, operation);
2052         /*                      err=HPI_ERROR_DSP_HARDWARE; */
2053
2054         send_dsp_command(phw, H620_HIF_IDLE);
2055
2056         return err;
2057 }
2058
2059 /* wait for up to timeout_us microseconds for the DSP
2060    to signal state by DMA into dwDspAck
2061 */
2062 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us)
2063 {
2064         struct bus_master_interface *interface = phw->p_interface_buffer;
2065         int t = timeout_us / 4;
2066
2067         rmb();  /* ensure interface->dsp_ack is up to date */
2068         while ((interface->dsp_ack != state) && --t) {
2069                 hpios_delay_micro_seconds(4);
2070                 rmb();  /* DSP changes dsp_ack by DMA */
2071         }
2072
2073         /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */
2074         return t * 4;
2075 }
2076
2077 /* set the busmaster interface to cmd, then interrupt the DSP */
2078 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd)
2079 {
2080         struct bus_master_interface *interface = phw->p_interface_buffer;
2081         u32 r;
2082
2083         interface->host_cmd = cmd;
2084         wmb();  /* DSP gets state by DMA, make sure it is written to memory */
2085         /* before we interrupt the DSP */
2086         r = ioread32(phw->prHDCR);
2087         r |= (u32)C6205_HDCR_DSPINT;
2088         iowrite32(r, phw->prHDCR);
2089         r &= ~(u32)C6205_HDCR_DSPINT;
2090         iowrite32(r, phw->prHDCR);
2091 }
2092
2093 static unsigned int message_count;
2094
2095 static u16 message_response_sequence(struct hpi_adapter_obj *pao,
2096         struct hpi_message *phm, struct hpi_response *phr)
2097 {
2098         u32 time_out, time_out2;
2099         struct hpi_hw_obj *phw = pao->priv;
2100         struct bus_master_interface *interface = phw->p_interface_buffer;
2101         u16 err = 0;
2102
2103         message_count++;
2104         if (phm->size > sizeof(interface->u.message_buffer)) {
2105                 phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL;
2106                 phr->specific_error = sizeof(interface->u.message_buffer);
2107                 phr->size = sizeof(struct hpi_response_header);
2108                 HPI_DEBUG_LOG(ERROR,
2109                         "message len %d too big for buffer %zd \n", phm->size,
2110                         sizeof(interface->u.message_buffer));
2111                 return 0;
2112         }
2113
2114         /* Assume buffer of type struct bus_master_interface_62
2115            is allocated "noncacheable" */
2116
2117         if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2118                 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
2119                 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2120         }
2121
2122         memcpy(&interface->u.message_buffer, phm, phm->size);
2123         /* signal we want a response */
2124         send_dsp_command(phw, H620_HIF_GET_RESP);
2125
2126         time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
2127
2128         if (!time_out2) {
2129                 HPI_DEBUG_LOG(ERROR,
2130                         "(%u) Timed out waiting for " "GET_RESP state [%x]\n",
2131                         message_count, interface->dsp_ack);
2132         } else {
2133                 HPI_DEBUG_LOG(VERBOSE,
2134                         "(%u) transition to GET_RESP after %u\n",
2135                         message_count, HPI6205_TIMEOUT - time_out2);
2136         }
2137         /* spin waiting on HIF interrupt flag (end of msg process) */
2138         time_out = HPI6205_TIMEOUT;
2139
2140         /* read the result */
2141         if (time_out) {
2142                 if (interface->u.response_buffer.response.size <= phr->size)
2143                         memcpy(phr, &interface->u.response_buffer,
2144                                 interface->u.response_buffer.response.size);
2145                 else {
2146                         HPI_DEBUG_LOG(ERROR,
2147                                 "response len %d too big for buffer %d\n",
2148                                 interface->u.response_buffer.response.size,
2149                                 phr->size);
2150                         memcpy(phr, &interface->u.response_buffer,
2151                                 sizeof(struct hpi_response_header));
2152                         phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
2153                         phr->specific_error =
2154                                 interface->u.response_buffer.response.size;
2155                         phr->size = sizeof(struct hpi_response_header);
2156                 }
2157         }
2158         /* set interface back to idle */
2159         send_dsp_command(phw, H620_HIF_IDLE);
2160
2161         if (!time_out || !time_out2) {
2162                 HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
2163                 return HPI6205_ERROR_MSG_RESP_TIMEOUT;
2164         }
2165         /* special case for adapter close - */
2166         /* wait for the DSP to indicate it is idle */
2167         if (phm->function == HPI_ADAPTER_CLOSE) {
2168                 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2169                         HPI_DEBUG_LOG(DEBUG,
2170                                 "Timeout waiting for idle "
2171                                 "(on adapter_close)\n");
2172                         return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2173                 }
2174         }
2175         err = hpi_validate_response(phm, phr);
2176         return err;
2177 }
2178
2179 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
2180         struct hpi_response *phr)
2181 {
2182
2183         u16 err = 0;
2184
2185         hpios_dsplock_lock(pao);
2186
2187         err = message_response_sequence(pao, phm, phr);
2188
2189         /* maybe an error response */
2190         if (err) {
2191                 /* something failed in the HPI/DSP interface */
2192                 if (err >= HPI_ERROR_BACKEND_BASE) {
2193                         phr->error = HPI_ERROR_DSP_COMMUNICATION;
2194                         phr->specific_error = err;
2195                 } else {
2196                         phr->error = err;
2197                 }
2198
2199                 pao->dsp_crashed++;
2200
2201                 /* just the header of the response is valid */
2202                 phr->size = sizeof(struct hpi_response_header);
2203                 goto err;
2204         } else
2205                 pao->dsp_crashed = 0;
2206
2207         if (phr->error != 0)    /* something failed in the DSP */
2208                 goto err;
2209
2210         switch (phm->function) {
2211         case HPI_OSTREAM_WRITE:
2212         case HPI_ISTREAM_ANC_WRITE:
2213                 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2214                         phm->u.d.u.data.data_size, H620_HIF_SEND_DATA);
2215                 break;
2216
2217         case HPI_ISTREAM_READ:
2218         case HPI_OSTREAM_ANC_READ:
2219                 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2220                         phm->u.d.u.data.data_size, H620_HIF_GET_DATA);
2221                 break;
2222
2223         }
2224         phr->error = err;
2225
2226 err:
2227         hpios_dsplock_unlock(pao);
2228
2229         return;
2230 }