sound/pci/ctxfi/cthw20k2.c

   1 /**
   2  * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
   3  *
   4  * This source file is released under GPL v2 license (no other versions).
   5  * See the COPYING file included in the main directory of this source
   6  * distribution for the license terms and conditions.
   7  *
   8  * @File        cthw20k2.c
   9  *
  10  * @Brief
  11  * This file contains the implementation of hardware access method for 20k2.
  12  *
  13  * @Author      Liu Chun
  14  * @Date        May 14 2008
  15  *
  16  */
  17
  18 #include <linux/types.h>
  19 #include <linux/slab.h>
  20 #include <linux/pci.h>
  21 #include <linux/io.h>
  22 #include <linux/string.h>
  23 #include <linux/kernel.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include "cthw20k2.h"
  27 #include "ct20k2reg.h"
  28
  29 struct hw20k2 {
  30         struct hw hw;
  31         /* for i2c */
  32         unsigned char dev_id;
  33         unsigned char addr_size;
  34         unsigned char data_size;
  35
  36         int mic_source;
  37 };
  38
  39 static u32 hw_read_20kx(struct hw *hw, u32 reg);
  40 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
  41
  42 /*
  43  * Type definition block.
  44  * The layout of control structures can be directly applied on 20k2 chip.
  45  */
  46
  47 /*
  48  * SRC control block definitions.
  49  */
  50
  51 /* SRC resource control block */
  52 #define SRCCTL_STATE    0x00000007
  53 #define SRCCTL_BM       0x00000008
  54 #define SRCCTL_RSR      0x00000030
  55 #define SRCCTL_SF       0x000001C0
  56 #define SRCCTL_WR       0x00000200
  57 #define SRCCTL_PM       0x00000400
  58 #define SRCCTL_ROM      0x00001800
  59 #define SRCCTL_VO       0x00002000
  60 #define SRCCTL_ST       0x00004000
  61 #define SRCCTL_IE       0x00008000
  62 #define SRCCTL_ILSZ     0x000F0000
  63 #define SRCCTL_BP       0x00100000
  64
  65 #define SRCCCR_CISZ     0x000007FF
  66 #define SRCCCR_CWA      0x001FF800
  67 #define SRCCCR_D        0x00200000
  68 #define SRCCCR_RS       0x01C00000
  69 #define SRCCCR_NAL      0x3E000000
  70 #define SRCCCR_RA       0xC0000000
  71
  72 #define SRCCA_CA        0x0FFFFFFF
  73 #define SRCCA_RS        0xE0000000
  74
  75 #define SRCSA_SA        0x0FFFFFFF
  76
  77 #define SRCLA_LA        0x0FFFFFFF
  78
  79 /* Mixer Parameter Ring ram Low and Hight register.
  80  * Fixed-point value in 8.24 format for parameter channel */
  81 #define MPRLH_PITCH     0xFFFFFFFF
  82
  83 /* SRC resource register dirty flags */
  84 union src_dirty {
  85         struct {
  86                 u16 ctl:1;
  87                 u16 ccr:1;
  88                 u16 sa:1;
  89                 u16 la:1;
  90                 u16 ca:1;
  91                 u16 mpr:1;
  92                 u16 czbfs:1;    /* Clear Z-Buffers */
  93                 u16 rsv:9;
  94         } bf;
  95         u16 data;
  96 };
  97
  98 struct src_rsc_ctrl_blk {
  99         unsigned int    ctl;
 100         unsigned int    ccr;
 101         unsigned int    ca;
 102         unsigned int    sa;
 103         unsigned int    la;
 104         unsigned int    mpr;
 105         union src_dirty dirty;
 106 };
 107
 108 /* SRC manager control block */
 109 union src_mgr_dirty {
 110         struct {
 111                 u16 enb0:1;
 112                 u16 enb1:1;
 113                 u16 enb2:1;
 114                 u16 enb3:1;
 115                 u16 enb4:1;
 116                 u16 enb5:1;
 117                 u16 enb6:1;
 118                 u16 enb7:1;
 119                 u16 enbsa:1;
 120                 u16 rsv:7;
 121         } bf;
 122         u16 data;
 123 };
 124
 125 struct src_mgr_ctrl_blk {
 126         unsigned int            enbsa;
 127         unsigned int            enb[8];
 128         union src_mgr_dirty     dirty;
 129 };
 130
 131 /* SRCIMP manager control block */
 132 #define SRCAIM_ARC      0x00000FFF
 133 #define SRCAIM_NXT      0x00FF0000
 134 #define SRCAIM_SRC      0xFF000000
 135
 136 struct srcimap {
 137         unsigned int srcaim;
 138         unsigned int idx;
 139 };
 140
 141 /* SRCIMP manager register dirty flags */
 142 union srcimp_mgr_dirty {
 143         struct {
 144                 u16 srcimap:1;
 145                 u16 rsv:15;
 146         } bf;
 147         u16 data;
 148 };
 149
 150 struct srcimp_mgr_ctrl_blk {
 151         struct srcimap          srcimap;
 152         union srcimp_mgr_dirty  dirty;
 153 };
 154
 155 /*
 156  * Function implementation block.
 157  */
 158
 159 static int src_get_rsc_ctrl_blk(void **rblk)
 160 {
 161         struct src_rsc_ctrl_blk *blk;
 162
 163         *rblk = NULL;
 164         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 165         if (!blk)
 166                 return -ENOMEM;
 167
 168         *rblk = blk;
 169
 170         return 0;
 171 }
 172
 173 static int src_put_rsc_ctrl_blk(void *blk)
 174 {
 175         kfree(blk);
 176
 177         return 0;
 178 }
 179
 180 static int src_set_state(void *blk, unsigned int state)
 181 {
 182         struct src_rsc_ctrl_blk *ctl = blk;
 183
 184         set_field(&ctl->ctl, SRCCTL_STATE, state);
 185         ctl->dirty.bf.ctl = 1;
 186         return 0;
 187 }
 188
 189 static int src_set_bm(void *blk, unsigned int bm)
 190 {
 191         struct src_rsc_ctrl_blk *ctl = blk;
 192
 193         set_field(&ctl->ctl, SRCCTL_BM, bm);
 194         ctl->dirty.bf.ctl = 1;
 195         return 0;
 196 }
 197
 198 static int src_set_rsr(void *blk, unsigned int rsr)
 199 {
 200         struct src_rsc_ctrl_blk *ctl = blk;
 201
 202         set_field(&ctl->ctl, SRCCTL_RSR, rsr);
 203         ctl->dirty.bf.ctl = 1;
 204         return 0;
 205 }
 206
 207 static int src_set_sf(void *blk, unsigned int sf)
 208 {
 209         struct src_rsc_ctrl_blk *ctl = blk;
 210
 211         set_field(&ctl->ctl, SRCCTL_SF, sf);
 212         ctl->dirty.bf.ctl = 1;
 213         return 0;
 214 }
 215
 216 static int src_set_wr(void *blk, unsigned int wr)
 217 {
 218         struct src_rsc_ctrl_blk *ctl = blk;
 219
 220         set_field(&ctl->ctl, SRCCTL_WR, wr);
 221         ctl->dirty.bf.ctl = 1;
 222         return 0;
 223 }
 224
 225 static int src_set_pm(void *blk, unsigned int pm)
 226 {
 227         struct src_rsc_ctrl_blk *ctl = blk;
 228
 229         set_field(&ctl->ctl, SRCCTL_PM, pm);
 230         ctl->dirty.bf.ctl = 1;
 231         return 0;
 232 }
 233
 234 static int src_set_rom(void *blk, unsigned int rom)
 235 {
 236         struct src_rsc_ctrl_blk *ctl = blk;
 237
 238         set_field(&ctl->ctl, SRCCTL_ROM, rom);
 239         ctl->dirty.bf.ctl = 1;
 240         return 0;
 241 }
 242
 243 static int src_set_vo(void *blk, unsigned int vo)
 244 {
 245         struct src_rsc_ctrl_blk *ctl = blk;
 246
 247         set_field(&ctl->ctl, SRCCTL_VO, vo);
 248         ctl->dirty.bf.ctl = 1;
 249         return 0;
 250 }
 251
 252 static int src_set_st(void *blk, unsigned int st)
 253 {
 254         struct src_rsc_ctrl_blk *ctl = blk;
 255
 256         set_field(&ctl->ctl, SRCCTL_ST, st);
 257         ctl->dirty.bf.ctl = 1;
 258         return 0;
 259 }
 260
 261 static int src_set_ie(void *blk, unsigned int ie)
 262 {
 263         struct src_rsc_ctrl_blk *ctl = blk;
 264
 265         set_field(&ctl->ctl, SRCCTL_IE, ie);
 266         ctl->dirty.bf.ctl = 1;
 267         return 0;
 268 }
 269
 270 static int src_set_ilsz(void *blk, unsigned int ilsz)
 271 {
 272         struct src_rsc_ctrl_blk *ctl = blk;
 273
 274         set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
 275         ctl->dirty.bf.ctl = 1;
 276         return 0;
 277 }
 278
 279 static int src_set_bp(void *blk, unsigned int bp)
 280 {
 281         struct src_rsc_ctrl_blk *ctl = blk;
 282
 283         set_field(&ctl->ctl, SRCCTL_BP, bp);
 284         ctl->dirty.bf.ctl = 1;
 285         return 0;
 286 }
 287
 288 static int src_set_cisz(void *blk, unsigned int cisz)
 289 {
 290         struct src_rsc_ctrl_blk *ctl = blk;
 291
 292         set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
 293         ctl->dirty.bf.ccr = 1;
 294         return 0;
 295 }
 296
 297 static int src_set_ca(void *blk, unsigned int ca)
 298 {
 299         struct src_rsc_ctrl_blk *ctl = blk;
 300
 301         set_field(&ctl->ca, SRCCA_CA, ca);
 302         ctl->dirty.bf.ca = 1;
 303         return 0;
 304 }
 305
 306 static int src_set_sa(void *blk, unsigned int sa)
 307 {
 308         struct src_rsc_ctrl_blk *ctl = blk;
 309
 310         set_field(&ctl->sa, SRCSA_SA, sa);
 311         ctl->dirty.bf.sa = 1;
 312         return 0;
 313 }
 314
 315 static int src_set_la(void *blk, unsigned int la)
 316 {
 317         struct src_rsc_ctrl_blk *ctl = blk;
 318
 319         set_field(&ctl->la, SRCLA_LA, la);
 320         ctl->dirty.bf.la = 1;
 321         return 0;
 322 }
 323
 324 static int src_set_pitch(void *blk, unsigned int pitch)
 325 {
 326         struct src_rsc_ctrl_blk *ctl = blk;
 327
 328         set_field(&ctl->mpr, MPRLH_PITCH, pitch);
 329         ctl->dirty.bf.mpr = 1;
 330         return 0;
 331 }
 332
 333 static int src_set_clear_zbufs(void *blk, unsigned int clear)
 334 {
 335         ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
 336         return 0;
 337 }
 338
 339 static int src_set_dirty(void *blk, unsigned int flags)
 340 {
 341         ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
 342         return 0;
 343 }
 344
 345 static int src_set_dirty_all(void *blk)
 346 {
 347         ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
 348         return 0;
 349 }
 350
 351 #define AR_SLOT_SIZE            4096
 352 #define AR_SLOT_BLOCK_SIZE      16
 353 #define AR_PTS_PITCH            6
 354 #define AR_PARAM_SRC_OFFSET     0x60
 355
 356 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
 357 {
 358         return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
 359                         - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
 360
 361 }
 362
 363 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
 364 {
 365         struct src_rsc_ctrl_blk *ctl = blk;
 366         int i;
 367
 368         if (ctl->dirty.bf.czbfs) {
 369                 /* Clear Z-Buffer registers */
 370                 for (i = 0; i < 8; i++)
 371                         hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
 372
 373                 for (i = 0; i < 4; i++)
 374                         hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
 375
 376                 for (i = 0; i < 8; i++)
 377                         hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
 378
 379                 ctl->dirty.bf.czbfs = 0;
 380         }
 381         if (ctl->dirty.bf.mpr) {
 382                 /* Take the parameter mixer resource in the same group as that
 383                  * the idx src is in for simplicity. Unlike src, all conjugate
 384                  * parameter mixer resources must be programmed for
 385                  * corresponding conjugate src resources. */
 386                 unsigned int pm_idx = src_param_pitch_mixer(idx);
 387                 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
 388                 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
 389                 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
 390                 ctl->dirty.bf.mpr = 0;
 391         }
 392         if (ctl->dirty.bf.sa) {
 393                 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
 394                 ctl->dirty.bf.sa = 0;
 395         }
 396         if (ctl->dirty.bf.la) {
 397                 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
 398                 ctl->dirty.bf.la = 0;
 399         }
 400         if (ctl->dirty.bf.ca) {
 401                 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
 402                 ctl->dirty.bf.ca = 0;
 403         }
 404
 405         /* Write srccf register */
 406         hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
 407
 408         if (ctl->dirty.bf.ccr) {
 409                 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
 410                 ctl->dirty.bf.ccr = 0;
 411         }
 412         if (ctl->dirty.bf.ctl) {
 413                 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
 414                 ctl->dirty.bf.ctl = 0;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
 421 {
 422         struct src_rsc_ctrl_blk *ctl = blk;
 423
 424         ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
 425         ctl->dirty.bf.ca = 0;
 426
 427         return get_field(ctl->ca, SRCCA_CA);
 428 }
 429
 430 static unsigned int src_get_dirty(void *blk)
 431 {
 432         return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
 433 }
 434
 435 static unsigned int src_dirty_conj_mask(void)
 436 {
 437         return 0x20;
 438 }
 439
 440 static int src_mgr_enbs_src(void *blk, unsigned int idx)
 441 {
 442         ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
 443         ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
 444         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
 445         return 0;
 446 }
 447
 448 static int src_mgr_enb_src(void *blk, unsigned int idx)
 449 {
 450         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
 451         ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
 452         return 0;
 453 }
 454
 455 static int src_mgr_dsb_src(void *blk, unsigned int idx)
 456 {
 457         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
 458         ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
 459         return 0;
 460 }
 461
 462 static int src_mgr_commit_write(struct hw *hw, void *blk)
 463 {
 464         struct src_mgr_ctrl_blk *ctl = blk;
 465         int i;
 466         unsigned int ret;
 467
 468         if (ctl->dirty.bf.enbsa) {
 469                 do {
 470                         ret = hw_read_20kx(hw, SRC_ENBSTAT);
 471                 } while (ret & 0x1);
 472                 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
 473                 ctl->dirty.bf.enbsa = 0;
 474         }
 475         for (i = 0; i < 8; i++) {
 476                 if ((ctl->dirty.data & (0x1 << i))) {
 477                         hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
 478                         ctl->dirty.data &= ~(0x1 << i);
 479                 }
 480         }
 481
 482         return 0;
 483 }
 484
 485 static int src_mgr_get_ctrl_blk(void **rblk)
 486 {
 487         struct src_mgr_ctrl_blk *blk;
 488
 489         *rblk = NULL;
 490         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 491         if (!blk)
 492                 return -ENOMEM;
 493
 494         *rblk = blk;
 495
 496         return 0;
 497 }
 498
 499 static int src_mgr_put_ctrl_blk(void *blk)
 500 {
 501         kfree(blk);
 502
 503         return 0;
 504 }
 505
 506 static int srcimp_mgr_get_ctrl_blk(void **rblk)
 507 {
 508         struct srcimp_mgr_ctrl_blk *blk;
 509
 510         *rblk = NULL;
 511         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 512         if (!blk)
 513                 return -ENOMEM;
 514
 515         *rblk = blk;
 516
 517         return 0;
 518 }
 519
 520 static int srcimp_mgr_put_ctrl_blk(void *blk)
 521 {
 522         kfree(blk);
 523
 524         return 0;
 525 }
 526
 527 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
 528 {
 529         struct srcimp_mgr_ctrl_blk *ctl = blk;
 530
 531         set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
 532         ctl->dirty.bf.srcimap = 1;
 533         return 0;
 534 }
 535
 536 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
 537 {
 538         struct srcimp_mgr_ctrl_blk *ctl = blk;
 539
 540         set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
 541         ctl->dirty.bf.srcimap = 1;
 542         return 0;
 543 }
 544
 545 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
 546 {
 547         struct srcimp_mgr_ctrl_blk *ctl = blk;
 548
 549         set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
 550         ctl->dirty.bf.srcimap = 1;
 551         return 0;
 552 }
 553
 554 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
 555 {
 556         ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
 557         ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
 558         return 0;
 559 }
 560
 561 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
 562 {
 563         struct srcimp_mgr_ctrl_blk *ctl = blk;
 564
 565         if (ctl->dirty.bf.srcimap) {
 566                 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
 567                                                 ctl->srcimap.srcaim);
 568                 ctl->dirty.bf.srcimap = 0;
 569         }
 570
 571         return 0;
 572 }
 573
 574 /*
 575  * AMIXER control block definitions.
 576  */
 577
 578 #define AMOPLO_M        0x00000003
 579 #define AMOPLO_IV       0x00000004
 580 #define AMOPLO_X        0x0003FFF0
 581 #define AMOPLO_Y        0xFFFC0000
 582
 583 #define AMOPHI_SADR     0x000000FF
 584 #define AMOPHI_SE       0x80000000
 585
 586 /* AMIXER resource register dirty flags */
 587 union amixer_dirty {
 588         struct {
 589                 u16 amoplo:1;
 590                 u16 amophi:1;
 591                 u16 rsv:14;
 592         } bf;
 593         u16 data;
 594 };
 595
 596 /* AMIXER resource control block */
 597 struct amixer_rsc_ctrl_blk {
 598         unsigned int            amoplo;
 599         unsigned int            amophi;
 600         union amixer_dirty      dirty;
 601 };
 602
 603 static int amixer_set_mode(void *blk, unsigned int mode)
 604 {
 605         struct amixer_rsc_ctrl_blk *ctl = blk;
 606
 607         set_field(&ctl->amoplo, AMOPLO_M, mode);
 608         ctl->dirty.bf.amoplo = 1;
 609         return 0;
 610 }
 611
 612 static int amixer_set_iv(void *blk, unsigned int iv)
 613 {
 614         struct amixer_rsc_ctrl_blk *ctl = blk;
 615
 616         set_field(&ctl->amoplo, AMOPLO_IV, iv);
 617         ctl->dirty.bf.amoplo = 1;
 618         return 0;
 619 }
 620
 621 static int amixer_set_x(void *blk, unsigned int x)
 622 {
 623         struct amixer_rsc_ctrl_blk *ctl = blk;
 624
 625         set_field(&ctl->amoplo, AMOPLO_X, x);
 626         ctl->dirty.bf.amoplo = 1;
 627         return 0;
 628 }
 629
 630 static int amixer_set_y(void *blk, unsigned int y)
 631 {
 632         struct amixer_rsc_ctrl_blk *ctl = blk;
 633
 634         set_field(&ctl->amoplo, AMOPLO_Y, y);
 635         ctl->dirty.bf.amoplo = 1;
 636         return 0;
 637 }
 638
 639 static int amixer_set_sadr(void *blk, unsigned int sadr)
 640 {
 641         struct amixer_rsc_ctrl_blk *ctl = blk;
 642
 643         set_field(&ctl->amophi, AMOPHI_SADR, sadr);
 644         ctl->dirty.bf.amophi = 1;
 645         return 0;
 646 }
 647
 648 static int amixer_set_se(void *blk, unsigned int se)
 649 {
 650         struct amixer_rsc_ctrl_blk *ctl = blk;
 651
 652         set_field(&ctl->amophi, AMOPHI_SE, se);
 653         ctl->dirty.bf.amophi = 1;
 654         return 0;
 655 }
 656
 657 static int amixer_set_dirty(void *blk, unsigned int flags)
 658 {
 659         ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
 660         return 0;
 661 }
 662
 663 static int amixer_set_dirty_all(void *blk)
 664 {
 665         ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
 666         return 0;
 667 }
 668
 669 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
 670 {
 671         struct amixer_rsc_ctrl_blk *ctl = blk;
 672
 673         if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
 674                 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
 675                 ctl->dirty.bf.amoplo = 0;
 676                 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
 677                 ctl->dirty.bf.amophi = 0;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int amixer_get_y(void *blk)
 684 {
 685         struct amixer_rsc_ctrl_blk *ctl = blk;
 686
 687         return get_field(ctl->amoplo, AMOPLO_Y);
 688 }
 689
 690 static unsigned int amixer_get_dirty(void *blk)
 691 {
 692         return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
 693 }
 694
 695 static int amixer_rsc_get_ctrl_blk(void **rblk)
 696 {
 697         struct amixer_rsc_ctrl_blk *blk;
 698
 699         *rblk = NULL;
 700         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 701         if (!blk)
 702                 return -ENOMEM;
 703
 704         *rblk = blk;
 705
 706         return 0;
 707 }
 708
 709 static int amixer_rsc_put_ctrl_blk(void *blk)
 710 {
 711         kfree(blk);
 712
 713         return 0;
 714 }
 715
 716 static int amixer_mgr_get_ctrl_blk(void **rblk)
 717 {
 718         *rblk = NULL;
 719
 720         return 0;
 721 }
 722
 723 static int amixer_mgr_put_ctrl_blk(void *blk)
 724 {
 725         return 0;
 726 }
 727
 728 /*
 729  * DAIO control block definitions.
 730  */
 731
 732 /* Receiver Sample Rate Tracker Control register */
 733 #define SRTCTL_SRCO     0x000000FF
 734 #define SRTCTL_SRCM     0x0000FF00
 735 #define SRTCTL_RSR      0x00030000
 736 #define SRTCTL_DRAT     0x00300000
 737 #define SRTCTL_EC       0x01000000
 738 #define SRTCTL_ET       0x10000000
 739
 740 /* DAIO Receiver register dirty flags */
 741 union dai_dirty {
 742         struct {
 743                 u16 srt:1;
 744                 u16 rsv:15;
 745         } bf;
 746         u16 data;
 747 };
 748
 749 /* DAIO Receiver control block */
 750 struct dai_ctrl_blk {
 751         unsigned int    srt;
 752         union dai_dirty dirty;
 753 };
 754
 755 /* Audio Input Mapper RAM */
 756 #define AIM_ARC         0x00000FFF
 757 #define AIM_NXT         0x007F0000
 758
 759 struct daoimap {
 760         unsigned int aim;
 761         unsigned int idx;
 762 };
 763
 764 /* Audio Transmitter Control and Status register */
 765 #define ATXCTL_EN       0x00000001
 766 #define ATXCTL_MODE     0x00000010
 767 #define ATXCTL_CD       0x00000020
 768 #define ATXCTL_RAW      0x00000100
 769 #define ATXCTL_MT       0x00000200
 770 #define ATXCTL_NUC      0x00003000
 771 #define ATXCTL_BEN      0x00010000
 772 #define ATXCTL_BMUX     0x00700000
 773 #define ATXCTL_B24      0x01000000
 774 #define ATXCTL_CPF      0x02000000
 775 #define ATXCTL_RIV      0x10000000
 776 #define ATXCTL_LIV      0x20000000
 777 #define ATXCTL_RSAT     0x40000000
 778 #define ATXCTL_LSAT     0x80000000
 779
 780 /* XDIF Transmitter register dirty flags */
 781 union dao_dirty {
 782         struct {
 783                 u16 atxcsl:1;
 784                 u16 rsv:15;
 785         } bf;
 786         u16 data;
 787 };
 788
 789 /* XDIF Transmitter control block */
 790 struct dao_ctrl_blk {
 791         /* XDIF Transmitter Channel Status Low Register */
 792         unsigned int    atxcsl;
 793         union dao_dirty dirty;
 794 };
 795
 796 /* Audio Receiver Control register */
 797 #define ARXCTL_EN       0x00000001
 798
 799 /* DAIO manager register dirty flags */
 800 union daio_mgr_dirty {
 801         struct {
 802                 u32 atxctl:8;
 803                 u32 arxctl:8;
 804                 u32 daoimap:1;
 805                 u32 rsv:15;
 806         } bf;
 807         u32 data;
 808 };
 809
 810 /* DAIO manager control block */
 811 struct daio_mgr_ctrl_blk {
 812         struct daoimap          daoimap;
 813         unsigned int            txctl[8];
 814         unsigned int            rxctl[8];
 815         union daio_mgr_dirty    dirty;
 816 };
 817
 818 static int dai_srt_set_srco(void *blk, unsigned int src)
 819 {
 820         struct dai_ctrl_blk *ctl = blk;
 821
 822         set_field(&ctl->srt, SRTCTL_SRCO, src);
 823         ctl->dirty.bf.srt = 1;
 824         return 0;
 825 }
 826
 827 static int dai_srt_set_srcm(void *blk, unsigned int src)
 828 {
 829         struct dai_ctrl_blk *ctl = blk;
 830
 831         set_field(&ctl->srt, SRTCTL_SRCM, src);
 832         ctl->dirty.bf.srt = 1;
 833         return 0;
 834 }
 835
 836 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
 837 {
 838         struct dai_ctrl_blk *ctl = blk;
 839
 840         set_field(&ctl->srt, SRTCTL_RSR, rsr);
 841         ctl->dirty.bf.srt = 1;
 842         return 0;
 843 }
 844
 845 static int dai_srt_set_drat(void *blk, unsigned int drat)
 846 {
 847         struct dai_ctrl_blk *ctl = blk;
 848
 849         set_field(&ctl->srt, SRTCTL_DRAT, drat);
 850         ctl->dirty.bf.srt = 1;
 851         return 0;
 852 }
 853
 854 static int dai_srt_set_ec(void *blk, unsigned int ec)
 855 {
 856         struct dai_ctrl_blk *ctl = blk;
 857
 858         set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
 859         ctl->dirty.bf.srt = 1;
 860         return 0;
 861 }
 862
 863 static int dai_srt_set_et(void *blk, unsigned int et)
 864 {
 865         struct dai_ctrl_blk *ctl = blk;
 866
 867         set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
 868         ctl->dirty.bf.srt = 1;
 869         return 0;
 870 }
 871
 872 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
 873 {
 874         struct dai_ctrl_blk *ctl = blk;
 875
 876         if (ctl->dirty.bf.srt) {
 877                 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
 878                 ctl->dirty.bf.srt = 0;
 879         }
 880
 881         return 0;
 882 }
 883
 884 static int dai_get_ctrl_blk(void **rblk)
 885 {
 886         struct dai_ctrl_blk *blk;
 887
 888         *rblk = NULL;
 889         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 890         if (!blk)
 891                 return -ENOMEM;
 892
 893         *rblk = blk;
 894
 895         return 0;
 896 }
 897
 898 static int dai_put_ctrl_blk(void *blk)
 899 {
 900         kfree(blk);
 901
 902         return 0;
 903 }
 904
 905 static int dao_set_spos(void *blk, unsigned int spos)
 906 {
 907         ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
 908         ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
 909         return 0;
 910 }
 911
 912 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
 913 {
 914         struct dao_ctrl_blk *ctl = blk;
 915
 916         if (ctl->dirty.bf.atxcsl) {
 917                 if (idx < 4) {
 918                         /* S/PDIF SPOSx */
 919                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
 920                                                         ctl->atxcsl);
 921                 }
 922                 ctl->dirty.bf.atxcsl = 0;
 923         }
 924
 925         return 0;
 926 }
 927
 928 static int dao_get_spos(void *blk, unsigned int *spos)
 929 {
 930         *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
 931         return 0;
 932 }
 933
 934 static int dao_get_ctrl_blk(void **rblk)
 935 {
 936         struct dao_ctrl_blk *blk;
 937
 938         *rblk = NULL;
 939         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 940         if (!blk)
 941                 return -ENOMEM;
 942
 943         *rblk = blk;
 944
 945         return 0;
 946 }
 947
 948 static int dao_put_ctrl_blk(void *blk)
 949 {
 950         kfree(blk);
 951
 952         return 0;
 953 }
 954
 955 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
 956 {
 957         struct daio_mgr_ctrl_blk *ctl = blk;
 958
 959         set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
 960         ctl->dirty.bf.arxctl |= (0x1 << idx);
 961         return 0;
 962 }
 963
 964 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
 965 {
 966         struct daio_mgr_ctrl_blk *ctl = blk;
 967
 968         set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
 969
 970         ctl->dirty.bf.arxctl |= (0x1 << idx);
 971         return 0;
 972 }
 973
 974 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
 975 {
 976         struct daio_mgr_ctrl_blk *ctl = blk;
 977
 978         set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
 979         ctl->dirty.bf.atxctl |= (0x1 << idx);
 980         return 0;
 981 }
 982
 983 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
 984 {
 985         struct daio_mgr_ctrl_blk *ctl = blk;
 986
 987         set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
 988         ctl->dirty.bf.atxctl |= (0x1 << idx);
 989         return 0;
 990 }
 991
 992 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
 993 {
 994         struct daio_mgr_ctrl_blk *ctl = blk;
 995
 996         if (idx < 4) {
 997                 /* S/PDIF output */
 998                 switch ((conf & 0xf)) {
 999                 case 1:
1000                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
1001                         break;
1002                 case 2:
1003                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
1004                         break;
1005                 case 4:
1006                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
1007                         break;
1008                 case 8:
1009                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1010                         break;
1011                 default:
1012                         break;
1013                 }
1014                 /* CDIF */
1015                 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1016                 /* Non-audio */
1017                 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1018                 /* Non-audio */
1019                 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1020                 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1021                           ((conf >> 3) & 0x1) ? 0 : 0);
1022                 ctl->dirty.bf.atxctl |= (0x1 << idx);
1023         } else {
1024                 /* I2S output */
1025                 /*idx %= 4; */
1026         }
1027         return 0;
1028 }
1029
1030 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1031 {
1032         struct daio_mgr_ctrl_blk *ctl = blk;
1033
1034         set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1035         ctl->dirty.bf.daoimap = 1;
1036         return 0;
1037 }
1038
1039 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1040 {
1041         struct daio_mgr_ctrl_blk *ctl = blk;
1042
1043         set_field(&ctl->daoimap.aim, AIM_NXT, next);
1044         ctl->dirty.bf.daoimap = 1;
1045         return 0;
1046 }
1047
1048 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1049 {
1050         ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1051         ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1052         return 0;
1053 }
1054
1055 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1056 {
1057         struct daio_mgr_ctrl_blk *ctl = blk;
1058         unsigned int data;
1059         int i;
1060
1061         for (i = 0; i < 8; i++) {
1062                 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1063                         data = ctl->txctl[i];
1064                         hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1065                         ctl->dirty.bf.atxctl &= ~(0x1 << i);
1066                         mdelay(1);
1067                 }
1068                 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1069                         data = ctl->rxctl[i];
1070                         hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1071                         ctl->dirty.bf.arxctl &= ~(0x1 << i);
1072                         mdelay(1);
1073                 }
1074         }
1075         if (ctl->dirty.bf.daoimap) {
1076                 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1077                                                 ctl->daoimap.aim);
1078                 ctl->dirty.bf.daoimap = 0;
1079         }
1080
1081         return 0;
1082 }
1083
1084 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1085 {
1086         struct daio_mgr_ctrl_blk *blk;
1087         int i;
1088
1089         *rblk = NULL;
1090         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1091         if (!blk)
1092                 return -ENOMEM;
1093
1094         for (i = 0; i < 8; i++) {
1095                 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1096                 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1097         }
1098
1099         *rblk = blk;
1100
1101         return 0;
1102 }
1103
1104 static int daio_mgr_put_ctrl_blk(void *blk)
1105 {
1106         kfree(blk);
1107
1108         return 0;
1109 }
1110
1111 /* Timer interrupt */
1112 static int set_timer_irq(struct hw *hw, int enable)
1113 {
1114         hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1115         return 0;
1116 }
1117
1118 static int set_timer_tick(struct hw *hw, unsigned int ticks)
1119 {
1120         if (ticks)
1121                 ticks |= TIMR_IE | TIMR_IP;
1122         hw_write_20kx(hw, TIMR, ticks);
1123         return 0;
1124 }
1125
1126 static unsigned int get_wc(struct hw *hw)
1127 {
1128         return hw_read_20kx(hw, WC);
1129 }
1130
1131 /* Card hardware initialization block */
1132 struct dac_conf {
1133         unsigned int msr; /* master sample rate in rsrs */
1134 };
1135
1136 struct adc_conf {
1137         unsigned int msr;       /* master sample rate in rsrs */
1138         unsigned char input;    /* the input source of ADC */
1139         unsigned char mic20db;  /* boost mic by 20db if input is microphone */
1140 };
1141
1142 struct daio_conf {
1143         unsigned int msr; /* master sample rate in rsrs */
1144 };
1145
1146 struct trn_conf {
1147         unsigned long vm_pgt_phys;
1148 };
1149
1150 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1151 {
1152         u32 data;
1153         int i;
1154
1155         /* Program I2S with proper sample rate and enable the correct I2S
1156          * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1157         if (1 == info->msr) {
1158                 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1159                 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1160                 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1161         } else if (2 == info->msr) {
1162                 if (hw->model != CTSB1270) {
1163                         hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1164                 } else {
1165                         /* PCM4220 on Titanium HD is different. */
1166                         hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111);
1167                 }
1168                 /* Specify all playing 96khz
1169                  * EA [0]       - Enabled
1170                  * RTA [4:5]    - 96kHz
1171                  * EB [8]       - Enabled
1172                  * RTB [12:13]  - 96kHz
1173                  * EC [16]      - Enabled
1174                  * RTC [20:21]  - 96kHz
1175                  * ED [24]      - Enabled
1176                  * RTD [28:29]  - 96kHz */
1177                 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1178                 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1179         } else if ((4 == info->msr) && (hw->model == CTSB1270)) {
1180                 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111);
1181                 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121);
1182                 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1183         } else {
1184                 dev_alert(hw->card->dev,
1185                           "ERROR!!! Invalid sampling rate!!!\n");
1186                 return -EINVAL;
1187         }
1188
1189         for (i = 0; i < 8; i++) {
1190                 if (i <= 3) {
1191                         /* This comment looks wrong since loop is over 4  */
1192                         /* channels and emu20k2 supports 4 spdif IOs.     */
1193                         /* 1st 3 channels are SPDIFs (SB0960) */
1194                         if (i == 3)
1195                                 data = 0x1001001;
1196                         else
1197                                 data = 0x1000001;
1198
1199                         hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1200                         hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1201
1202                         /* Initialize the SPDIF Out Channel status registers.
1203                          * The value specified here is based on the typical
1204                          * values provided in the specification, namely: Clock
1205                          * Accuracy of 1000ppm, Sample Rate of 48KHz,
1206                          * unspecified source number, Generation status = 1,
1207                          * Category code = 0x12 (Digital Signal Mixer),
1208                          * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1209                          * (indicating that we're transmitting digital audio,
1210                          * and the Professional Use bit is 0. */
1211
1212                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1213                                         0x02109204); /* Default to 48kHz */
1214
1215                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1216                 } else {
1217                         /* Again, loop is over 4 channels not 5. */
1218                         /* Next 5 channels are I2S (SB0960) */
1219                         data = 0x11;
1220                         hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
1221                         if (2 == info->msr) {
1222                                 /* Four channels per sample period */
1223                                 data |= 0x1000;
1224                         } else if (4 == info->msr) {
1225                                 /* FIXME: check this against the chip spec */
1226                                 data |= 0x2000;
1227                         }
1228                         hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
1229                 }
1230         }
1231
1232         return 0;
1233 }
1234
1235 /* TRANSPORT operations */
1236 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1237 {
1238         u32 vmctl, data;
1239         u32 ptp_phys_low, ptp_phys_high;
1240         int i;
1241
1242         /* Set up device page table */
1243         if ((~0UL) == info->vm_pgt_phys) {
1244                 dev_alert(hw->card->dev,
1245                           "Wrong device page table page address!!!\n");
1246                 return -1;
1247         }
1248
1249         vmctl = 0x80000C0F;  /* 32-bit, 4k-size page */
1250         ptp_phys_low = (u32)info->vm_pgt_phys;
1251         ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1252         if (sizeof(void *) == 8) /* 64bit address */
1253                 vmctl |= (3 << 8);
1254         /* Write page table physical address to all PTPAL registers */
1255         for (i = 0; i < 64; i++) {
1256                 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1257                 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1258         }
1259         /* Enable virtual memory transfer */
1260         hw_write_20kx(hw, VMEM_CTL, vmctl);
1261         /* Enable transport bus master and queueing of request */
1262         hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1263         hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1264         /* Enable transport ring */
1265         data = hw_read_20kx(hw, TRANSPORT_ENB);
1266         hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1267
1268         return 0;
1269 }
1270
1271 /* Card initialization */
1272 #define GCTL_AIE        0x00000001
1273 #define GCTL_UAA        0x00000002
1274 #define GCTL_DPC        0x00000004
1275 #define GCTL_DBP        0x00000008
1276 #define GCTL_ABP        0x00000010
1277 #define GCTL_TBP        0x00000020
1278 #define GCTL_SBP        0x00000040
1279 #define GCTL_FBP        0x00000080
1280 #define GCTL_ME         0x00000100
1281 #define GCTL_AID        0x00001000
1282
1283 #define PLLCTL_SRC      0x00000007
1284 #define PLLCTL_SPE      0x00000008
1285 #define PLLCTL_RD       0x000000F0
1286 #define PLLCTL_FD       0x0001FF00
1287 #define PLLCTL_OD       0x00060000
1288 #define PLLCTL_B        0x00080000
1289 #define PLLCTL_AS       0x00100000
1290 #define PLLCTL_LF       0x03E00000
1291 #define PLLCTL_SPS      0x1C000000
1292 #define PLLCTL_AD       0x60000000
1293
1294 #define PLLSTAT_CCS     0x00000007
1295 #define PLLSTAT_SPL     0x00000008
1296 #define PLLSTAT_CRD     0x000000F0
1297 #define PLLSTAT_CFD     0x0001FF00
1298 #define PLLSTAT_SL      0x00020000
1299 #define PLLSTAT_FAS     0x00040000
1300 #define PLLSTAT_B       0x00080000
1301 #define PLLSTAT_PD      0x00100000
1302 #define PLLSTAT_OCA     0x00200000
1303 #define PLLSTAT_NCA     0x00400000
1304
1305 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1306 {
1307         unsigned int pllenb;
1308         unsigned int pllctl;
1309         unsigned int pllstat;
1310         int i;
1311
1312         pllenb = 0xB;
1313         hw_write_20kx(hw, PLL_ENB, pllenb);
1314         pllctl = 0x20C00000;
1315         set_field(&pllctl, PLLCTL_B, 0);
1316         set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4);
1317         set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1);
1318         hw_write_20kx(hw, PLL_CTL, pllctl);
1319         mdelay(40);
1320
1321         pllctl = hw_read_20kx(hw, PLL_CTL);
1322         set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2);
1323         hw_write_20kx(hw, PLL_CTL, pllctl);
1324         mdelay(40);
1325
1326         for (i = 0; i < 1000; i++) {
1327                 pllstat = hw_read_20kx(hw, PLL_STAT);
1328                 if (get_field(pllstat, PLLSTAT_PD))
1329                         continue;
1330
1331                 if (get_field(pllstat, PLLSTAT_B) !=
1332                                         get_field(pllctl, PLLCTL_B))
1333                         continue;
1334
1335                 if (get_field(pllstat, PLLSTAT_CCS) !=
1336                                         get_field(pllctl, PLLCTL_SRC))
1337                         continue;
1338
1339                 if (get_field(pllstat, PLLSTAT_CRD) !=
1340                                         get_field(pllctl, PLLCTL_RD))
1341                         continue;
1342
1343                 if (get_field(pllstat, PLLSTAT_CFD) !=
1344                                         get_field(pllctl, PLLCTL_FD))
1345                         continue;
1346
1347                 break;
1348         }
1349         if (i >= 1000) {
1350                 dev_alert(hw->card->dev,
1351                           "PLL initialization failed!!!\n");
1352                 return -EBUSY;
1353         }
1354
1355         return 0;
1356 }
1357
1358 static int hw_auto_init(struct hw *hw)
1359 {
1360         unsigned int gctl;
1361         int i;
1362
1363         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1364         set_field(&gctl, GCTL_AIE, 0);
1365         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1366         set_field(&gctl, GCTL_AIE, 1);
1367         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1368         mdelay(10);
1369         for (i = 0; i < 400000; i++) {
1370                 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1371                 if (get_field(gctl, GCTL_AID))
1372                         break;
1373         }
1374         if (!get_field(gctl, GCTL_AID)) {
1375                 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
1376                 return -EBUSY;
1377         }
1378
1379         return 0;
1380 }
1381
1382 /* DAC operations */
1383
1384 #define CS4382_MC1              0x1
1385 #define CS4382_MC2              0x2
1386 #define CS4382_MC3              0x3
1387 #define CS4382_FC               0x4
1388 #define CS4382_IC               0x5
1389 #define CS4382_XC1              0x6
1390 #define CS4382_VCA1             0x7
1391 #define CS4382_VCB1             0x8
1392 #define CS4382_XC2              0x9
1393 #define CS4382_VCA2             0xA
1394 #define CS4382_VCB2             0xB
1395 #define CS4382_XC3              0xC
1396 #define CS4382_VCA3             0xD
1397 #define CS4382_VCB3             0xE
1398 #define CS4382_XC4              0xF
1399 #define CS4382_VCA4             0x10
1400 #define CS4382_VCB4             0x11
1401 #define CS4382_CREV             0x12
1402
1403 /* I2C status */
1404 #define STATE_LOCKED            0x00
1405 #define STATE_UNLOCKED          0xAA
1406 #define DATA_READY              0x800000    /* Used with I2C_IF_STATUS */
1407 #define DATA_ABORT              0x10000     /* Used with I2C_IF_STATUS */
1408
1409 #define I2C_STATUS_DCM  0x00000001
1410 #define I2C_STATUS_BC   0x00000006
1411 #define I2C_STATUS_APD  0x00000008
1412 #define I2C_STATUS_AB   0x00010000
1413 #define I2C_STATUS_DR   0x00800000
1414
1415 #define I2C_ADDRESS_PTAD        0x0000FFFF
1416 #define I2C_ADDRESS_SLAD        0x007F0000
1417
1418 struct regs_cs4382 {
1419         u32 mode_control_1;
1420         u32 mode_control_2;
1421         u32 mode_control_3;
1422
1423         u32 filter_control;
1424         u32 invert_control;
1425
1426         u32 mix_control_P1;
1427         u32 vol_control_A1;
1428         u32 vol_control_B1;
1429
1430         u32 mix_control_P2;
1431         u32 vol_control_A2;
1432         u32 vol_control_B2;
1433
1434         u32 mix_control_P3;
1435         u32 vol_control_A3;
1436         u32 vol_control_B3;
1437
1438         u32 mix_control_P4;
1439         u32 vol_control_A4;
1440         u32 vol_control_B4;
1441 };
1442
1443 static int hw20k2_i2c_unlock_full_access(struct hw *hw)
1444 {
1445         u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] =  {0xB3, 0xD4};
1446
1447         /* Send keys for forced BIOS mode */
1448         hw_write_20kx(hw, I2C_IF_WLOCK,
1449                         UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1450         hw_write_20kx(hw, I2C_IF_WLOCK,
1451                         UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1452         /* Check whether the chip is unlocked */
1453         if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1454                 return 0;
1455
1456         return -1;
1457 }
1458
1459 static int hw20k2_i2c_lock_chip(struct hw *hw)
1460 {
1461         /* Write twice */
1462         hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1463         hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1464         if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1465                 return 0;
1466
1467         return -1;
1468 }
1469
1470 static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
1471 {
1472         struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1473         int err;
1474         unsigned int i2c_status;
1475         unsigned int i2c_addr;
1476
1477         err = hw20k2_i2c_unlock_full_access(hw);
1478         if (err < 0)
1479                 return err;
1480
1481         hw20k2->addr_size = addr_size;
1482         hw20k2->data_size = data_size;
1483         hw20k2->dev_id = dev_id;
1484
1485         i2c_addr = 0;
1486         set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
1487
1488         hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1489
1490         i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1491
1492         set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */
1493
1494         hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1495
1496         return 0;
1497 }
1498
1499 static int hw20k2_i2c_uninit(struct hw *hw)
1500 {
1501         unsigned int i2c_status;
1502         unsigned int i2c_addr;
1503
1504         i2c_addr = 0;
1505         set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1506
1507         hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1508
1509         i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1510
1511         set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */
1512
1513         hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1514
1515         return hw20k2_i2c_lock_chip(hw);
1516 }
1517
1518 static int hw20k2_i2c_wait_data_ready(struct hw *hw)
1519 {
1520         int i = 0x400000;
1521         unsigned int ret;
1522
1523         do {
1524                 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1525         } while ((!(ret & DATA_READY)) && --i);
1526
1527         return i;
1528 }
1529
1530 static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
1531 {
1532         struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1533         unsigned int i2c_status;
1534
1535         i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1536         set_field(&i2c_status, I2C_STATUS_BC,
1537                   (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
1538         hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1539         if (!hw20k2_i2c_wait_data_ready(hw))
1540                 return -1;
1541
1542         hw_write_20kx(hw, I2C_IF_WDATA, addr);
1543         if (!hw20k2_i2c_wait_data_ready(hw))
1544                 return -1;
1545
1546         /* Force a read operation */
1547         hw_write_20kx(hw, I2C_IF_RDATA, 0);
1548         if (!hw20k2_i2c_wait_data_ready(hw))
1549                 return -1;
1550
1551         *datap = hw_read_20kx(hw, I2C_IF_RDATA);
1552
1553         return 0;
1554 }
1555
1556 static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
1557 {
1558         struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1559         unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
1560         unsigned int i2c_status;
1561
1562         i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1563
1564         set_field(&i2c_status, I2C_STATUS_BC,
1565                   (4 == (hw20k2->addr_size + hw20k2->data_size)) ?
1566                   0 : (hw20k2->addr_size + hw20k2->data_size));
1567
1568         hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1569         hw20k2_i2c_wait_data_ready(hw);
1570         /* Dummy write to trigger the write operation */
1571         hw_write_20kx(hw, I2C_IF_WDATA, 0);
1572         hw20k2_i2c_wait_data_ready(hw);
1573
1574         /* This is the real data */
1575         hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
1576         hw20k2_i2c_wait_data_ready(hw);
1577
1578         return 0;
1579 }
1580
1581 static void hw_dac_stop(struct hw *hw)
1582 {
1583         u32 data;
1584         data = hw_read_20kx(hw, GPIO_DATA);
1585         data &= 0xFFFFFFFD;
1586         hw_write_20kx(hw, GPIO_DATA, data);
1587         mdelay(10);
1588 }
1589
1590 static void hw_dac_start(struct hw *hw)
1591 {
1592         u32 data;
1593         data = hw_read_20kx(hw, GPIO_DATA);
1594         data |= 0x2;
1595         hw_write_20kx(hw, GPIO_DATA, data);
1596         mdelay(50);
1597 }
1598
1599 static void hw_dac_reset(struct hw *hw)
1600 {
1601         hw_dac_stop(hw);
1602         hw_dac_start(hw);
1603 }
1604
1605 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1606 {
1607         int err;
1608         u32 data;
1609         int i;
1610         struct regs_cs4382 cs_read = {0};
1611         struct regs_cs4382 cs_def = {
1612                                    0x00000001,  /* Mode Control 1 */
1613                                    0x00000000,  /* Mode Control 2 */
1614                                    0x00000084,  /* Mode Control 3 */
1615                                    0x00000000,  /* Filter Control */
1616                                    0x00000000,  /* Invert Control */
1617                                    0x00000024,  /* Mixing Control Pair 1 */
1618                                    0x00000000,  /* Vol Control A1 */
1619                                    0x00000000,  /* Vol Control B1 */
1620                                    0x00000024,  /* Mixing Control Pair 2 */
1621                                    0x00000000,  /* Vol Control A2 */
1622                                    0x00000000,  /* Vol Control B2 */
1623                                    0x00000024,  /* Mixing Control Pair 3 */
1624                                    0x00000000,  /* Vol Control A3 */
1625                                    0x00000000,  /* Vol Control B3 */
1626                                    0x00000024,  /* Mixing Control Pair 4 */
1627                                    0x00000000,  /* Vol Control A4 */
1628                                    0x00000000   /* Vol Control B4 */
1629                                  };
1630
1631         if (hw->model == CTSB1270) {
1632                 hw_dac_stop(hw);
1633                 data = hw_read_20kx(hw, GPIO_DATA);
1634                 data &= ~0x0600;
1635                 if (1 == info->msr)
1636                         data |= 0x0000; /* Single Speed Mode 0-50kHz */
1637                 else if (2 == info->msr)
1638                         data |= 0x0200; /* Double Speed Mode 50-100kHz */
1639                 else
1640                         data |= 0x0600; /* Quad Speed Mode 100-200kHz */
1641                 hw_write_20kx(hw, GPIO_DATA, data);
1642                 hw_dac_start(hw);
1643                 return 0;
1644         }
1645
1646         /* Set DAC reset bit as output */
1647         data = hw_read_20kx(hw, GPIO_CTRL);
1648         data |= 0x02;
1649         hw_write_20kx(hw, GPIO_CTRL, data);
1650
1651         err = hw20k2_i2c_init(hw, 0x18, 1, 1);
1652         if (err < 0)
1653                 goto End;
1654
1655         for (i = 0; i < 2; i++) {
1656                 /* Reset DAC twice just in-case the chip
1657                  * didn't initialized properly */
1658                 hw_dac_reset(hw);
1659                 hw_dac_reset(hw);
1660
1661                 if (hw20k2_i2c_read(hw, CS4382_MC1,  &cs_read.mode_control_1))
1662                         continue;
1663
1664                 if (hw20k2_i2c_read(hw, CS4382_MC2,  &cs_read.mode_control_2))
1665                         continue;
1666
1667                 if (hw20k2_i2c_read(hw, CS4382_MC3,  &cs_read.mode_control_3))
1668                         continue;
1669
1670                 if (hw20k2_i2c_read(hw, CS4382_FC,   &cs_read.filter_control))
1671                         continue;
1672
1673                 if (hw20k2_i2c_read(hw, CS4382_IC,   &cs_read.invert_control))
1674                         continue;
1675
1676                 if (hw20k2_i2c_read(hw, CS4382_XC1,  &cs_read.mix_control_P1))
1677                         continue;
1678
1679                 if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
1680                         continue;
1681
1682                 if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
1683                         continue;
1684
1685                 if (hw20k2_i2c_read(hw, CS4382_XC2,  &cs_read.mix_control_P2))
1686                         continue;
1687
1688                 if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
1689                         continue;
1690
1691                 if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
1692                         continue;
1693
1694                 if (hw20k2_i2c_read(hw, CS4382_XC3,  &cs_read.mix_control_P3))
1695                         continue;
1696
1697                 if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
1698                         continue;
1699
1700                 if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
1701                         continue;
1702
1703                 if (hw20k2_i2c_read(hw, CS4382_XC4,  &cs_read.mix_control_P4))
1704                         continue;
1705
1706                 if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
1707                         continue;
1708
1709                 if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
1710                         continue;
1711
1712                 if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
1713                         continue;
1714                 else
1715                         break;
1716         }
1717
1718         if (i >= 2)
1719                 goto End;
1720
1721         /* Note: Every I2C write must have some delay.
1722          * This is not a requirement but the delay works here... */
1723         hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
1724         hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
1725         if (1 == info->msr) {
1726                 hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
1727                 hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
1728                 hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
1729                 hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
1730         } else if (2 == info->msr) {
1731                 hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
1732                 hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
1733                 hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
1734                 hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
1735         } else {
1736                 hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
1737                 hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
1738                 hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
1739                 hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
1740         }
1741
1742         return 0;
1743 End:
1744
1745         hw20k2_i2c_uninit(hw);
1746         return -1;
1747 }
1748
1749 /* ADC operations */
1750 #define MAKE_WM8775_ADDR(addr, data)    (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1751 #define MAKE_WM8775_DATA(data)  (u32)(data&0xFF)
1752
1753 #define WM8775_IC       0x0B
1754 #define WM8775_MMC      0x0C
1755 #define WM8775_AADCL    0x0E
1756 #define WM8775_AADCR    0x0F
1757 #define WM8775_ADCMC    0x15
1758 #define WM8775_RESET    0x17
1759
1760 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1761 {
1762         u32 data;
1763         if (hw->model == CTSB1270) {
1764                 /* Titanium HD has two ADC chips, one for line in and one */
1765                 /* for MIC. We don't need to switch the ADC input. */
1766                 return 1;
1767         }
1768         data = hw_read_20kx(hw, GPIO_DATA);
1769         switch (type) {
1770         case ADC_MICIN:
1771                 data = (data & (0x1 << 14)) ? 1 : 0;
1772                 break;
1773         case ADC_LINEIN:
1774                 data = (data & (0x1 << 14)) ? 0 : 1;
1775                 break;
1776         default:
1777                 data = 0;
1778         }
1779         return data;
1780 }
1781
1782 #define MIC_BOOST_0DB 0xCF
1783 #define MIC_BOOST_STEPS_PER_DB 2
1784
1785 static void hw_wm8775_input_select(struct hw *hw, u8 input, s8 gain_in_db)
1786 {
1787         u32 adcmc, gain;
1788
1789         if (input > 3)
1790                 input = 3;
1791
1792         adcmc = ((u32)1 << input) | 0x100; /* Link L+R gain... */
1793
1794         hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, adcmc),
1795                                 MAKE_WM8775_DATA(adcmc));
1796
1797         if (gain_in_db < -103)
1798                 gain_in_db = -103;
1799         if (gain_in_db > 24)
1800                 gain_in_db = 24;
1801
1802         gain = gain_in_db * MIC_BOOST_STEPS_PER_DB + MIC_BOOST_0DB;
1803
1804         hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, gain),
1805                                 MAKE_WM8775_DATA(gain));
1806         /* ...so there should be no need for the following. */
1807         hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, gain),
1808                                 MAKE_WM8775_DATA(gain));
1809 }
1810
1811 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1812 {
1813         u32 data;
1814         data = hw_read_20kx(hw, GPIO_DATA);
1815         switch (type) {
1816         case ADC_MICIN:
1817                 data |= (0x1 << 14);
1818                 hw_write_20kx(hw, GPIO_DATA, data);
1819                 hw_wm8775_input_select(hw, 0, 20); /* Mic, 20dB */
1820                 break;
1821         case ADC_LINEIN:
1822                 data &= ~(0x1 << 14);
1823                 hw_write_20kx(hw, GPIO_DATA, data);
1824                 hw_wm8775_input_select(hw, 1, 0); /* Line-in, 0dB */
1825                 break;
1826         default:
1827                 break;
1828         }
1829
1830         return 0;
1831 }
1832
1833 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1834 {
1835         int err;
1836         u32 data, ctl;
1837
1838         /*  Set ADC reset bit as output */
1839         data = hw_read_20kx(hw, GPIO_CTRL);
1840         data |= (0x1 << 15);
1841         hw_write_20kx(hw, GPIO_CTRL, data);
1842
1843         /* Initialize I2C */
1844         err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
1845         if (err < 0) {
1846                 dev_alert(hw->card->dev, "Failure to acquire I2C!!!\n");
1847                 goto error;
1848         }
1849
1850         /* Reset the ADC (reset is active low). */
1851         data = hw_read_20kx(hw, GPIO_DATA);
1852         data &= ~(0x1 << 15);
1853         hw_write_20kx(hw, GPIO_DATA, data);
1854
1855         if (hw->model == CTSB1270) {
1856                 /* Set up the PCM4220 ADC on Titanium HD */
1857                 data &= ~0x0C;
1858                 if (1 == info->msr)
1859                         data |= 0x00; /* Single Speed Mode 32-50kHz */
1860                 else if (2 == info->msr)
1861                         data |= 0x08; /* Double Speed Mode 50-108kHz */
1862                 else
1863                         data |= 0x04; /* Quad Speed Mode 108kHz-216kHz */
1864                 hw_write_20kx(hw, GPIO_DATA, data);
1865         }
1866
1867         mdelay(10);
1868         /* Return the ADC to normal operation. */
1869         data |= (0x1 << 15);
1870         hw_write_20kx(hw, GPIO_DATA, data);
1871         mdelay(50);
1872
1873         /* I2C write to register offset 0x0B to set ADC LRCLK polarity */
1874         /* invert bit, interface format to I2S, word length to 24-bit, */
1875         /* enable ADC high pass filter. Fixes bug 5323?         */
1876         hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26),
1877                          MAKE_WM8775_DATA(0x26));
1878
1879         /* Set the master mode (256fs) */
1880         if (1 == info->msr) {
1881                 /* slave mode, 128x oversampling 256fs */
1882                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1883                                                 MAKE_WM8775_DATA(0x02));
1884         } else if ((2 == info->msr) || (4 == info->msr)) {
1885                 /* slave mode, 64x oversampling, 256fs */
1886                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1887                                                 MAKE_WM8775_DATA(0x0A));
1888         } else {
1889                 dev_alert(hw->card->dev,
1890                           "Invalid master sampling rate (msr %d)!!!\n",
1891                           info->msr);
1892                 err = -EINVAL;
1893                 goto error;
1894         }
1895
1896         if (hw->model != CTSB1270) {
1897                 /* Configure GPIO bit 14 change to line-in/mic-in */
1898                 ctl = hw_read_20kx(hw, GPIO_CTRL);
1899                 ctl |= 0x1 << 14;
1900                 hw_write_20kx(hw, GPIO_CTRL, ctl);
1901                 hw_adc_input_select(hw, ADC_LINEIN);
1902         } else {
1903                 hw_wm8775_input_select(hw, 0, 0);
1904         }
1905
1906         return 0;
1907 error:
1908         hw20k2_i2c_uninit(hw);
1909         return err;
1910 }
1911
1912 static struct capabilities hw_capabilities(struct hw *hw)
1913 {
1914         struct capabilities cap;
1915
1916         cap.digit_io_switch = 0;
1917         cap.dedicated_mic = hw->model == CTSB1270;
1918         cap.output_switch = hw->model == CTSB1270;
1919         cap.mic_source_switch = hw->model == CTSB1270;
1920
1921         return cap;
1922 }
1923
1924 static int hw_output_switch_get(struct hw *hw)
1925 {
1926         u32 data = hw_read_20kx(hw, GPIO_EXT_DATA);
1927
1928         switch (data & 0x30) {
1929         case 0x00:
1930              return 0;
1931         case 0x10:
1932              return 1;
1933         case 0x20:
1934              return 2;
1935         default:
1936              return 3;
1937         }
1938 }
1939
1940 static int hw_output_switch_put(struct hw *hw, int position)
1941 {
1942         u32 data;
1943
1944         if (position == hw_output_switch_get(hw))
1945                 return 0;
1946
1947         /* Mute line and headphones (intended for anti-pop). */
1948         data = hw_read_20kx(hw, GPIO_DATA);
1949         data |= (0x03 << 11);
1950         hw_write_20kx(hw, GPIO_DATA, data);
1951
1952         data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30;
1953         switch (position) {
1954         case 0:
1955                 break;
1956         case 1:
1957                 data |= 0x10;
1958                 break;
1959         default:
1960                 data |= 0x20;
1961         }
1962         hw_write_20kx(hw, GPIO_EXT_DATA, data);
1963
1964         /* Unmute line and headphones. */
1965         data = hw_read_20kx(hw, GPIO_DATA);
1966         data &= ~(0x03 << 11);
1967         hw_write_20kx(hw, GPIO_DATA, data);
1968
1969         return 1;
1970 }
1971
1972 static int hw_mic_source_switch_get(struct hw *hw)
1973 {
1974         struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1975
1976         return hw20k2->mic_source;
1977 }
1978
1979 static int hw_mic_source_switch_put(struct hw *hw, int position)
1980 {
1981         struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1982
1983         if (position == hw20k2->mic_source)
1984                 return 0;
1985
1986         switch (position) {
1987         case 0:
1988                 hw_wm8775_input_select(hw, 0, 0); /* Mic, 0dB */
1989                 break;
1990         case 1:
1991                 hw_wm8775_input_select(hw, 1, 0); /* FP Mic, 0dB */
1992                 break;
1993         case 2:
1994                 hw_wm8775_input_select(hw, 3, 0); /* Aux Ext, 0dB */
1995                 break;
1996         default:
1997                 return 0;
1998         }
1999
2000         hw20k2->mic_source = position;
2001
2002         return 1;
2003 }
2004
2005 static irqreturn_t ct_20k2_interrupt(int irq, void *dev_id)
2006 {
2007         struct hw *hw = dev_id;
2008         unsigned int status;
2009
2010         status = hw_read_20kx(hw, GIP);
2011         if (!status)
2012                 return IRQ_NONE;
2013
2014         if (hw->irq_callback)
2015                 hw->irq_callback(hw->irq_callback_data, status);
2016
2017         hw_write_20kx(hw, GIP, status);
2018         return IRQ_HANDLED;
2019 }
2020
2021 static int hw_card_start(struct hw *hw)
2022 {
2023         int err = 0;
2024         struct pci_dev *pci = hw->pci;
2025         unsigned int gctl;
2026         const unsigned int dma_bits = BITS_PER_LONG;
2027
2028         err = pci_enable_device(pci);
2029         if (err < 0)
2030                 return err;
2031
2032         /* Set DMA transfer mask */
2033         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
2034                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
2035         } else {
2036                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
2037                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
2038         }
2039
2040         if (!hw->io_base) {
2041                 err = pci_request_regions(pci, "XFi");
2042                 if (err < 0)
2043                         goto error1;
2044
2045                 hw->io_base = pci_resource_start(hw->pci, 2);
2046                 hw->mem_base = ioremap(hw->io_base,
2047                                        pci_resource_len(hw->pci, 2));
2048                 if (!hw->mem_base) {
2049                         err = -ENOENT;
2050                         goto error2;
2051                 }
2052         }
2053
2054         /* Switch to 20k2 mode from UAA mode. */
2055         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
2056         set_field(&gctl, GCTL_UAA, 0);
2057         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
2058
2059         if (hw->irq < 0) {
2060                 err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED,
2061                                   KBUILD_MODNAME, hw);
2062                 if (err < 0) {
2063                         dev_err(hw->card->dev,
2064                                 "XFi: Cannot get irq %d\n", pci->irq);
2065                         goto error2;
2066                 }
2067                 hw->irq = pci->irq;
2068         }
2069
2070         pci_set_master(pci);
2071
2072         return 0;
2073
2074 /*error3:
2075         iounmap((void *)hw->mem_base);
2076         hw->mem_base = (unsigned long)NULL;*/
2077 error2:
2078         pci_release_regions(pci);
2079         hw->io_base = 0;
2080 error1:
2081         pci_disable_device(pci);
2082         return err;
2083 }
2084
2085 static int hw_card_stop(struct hw *hw)
2086 {
2087         unsigned int data;
2088
2089         /* disable transport bus master and queueing of request */
2090         hw_write_20kx(hw, TRANSPORT_CTL, 0x00);
2091
2092         /* disable pll */
2093         data = hw_read_20kx(hw, PLL_ENB);
2094         hw_write_20kx(hw, PLL_ENB, (data & (~0x07)));
2095
2096         /* TODO: Disable interrupt and so on... */
2097         return 0;
2098 }
2099
2100 static int hw_card_shutdown(struct hw *hw)
2101 {
2102         if (hw->irq >= 0)
2103                 free_irq(hw->irq, hw);
2104
2105         hw->irq = -1;
2106         iounmap(hw->mem_base);
2107         hw->mem_base = NULL;
2108
2109         if (hw->io_base)
2110                 pci_release_regions(hw->pci);
2111
2112         hw->io_base = 0;
2113
2114         pci_disable_device(hw->pci);
2115
2116         return 0;
2117 }
2118
2119 static int hw_card_init(struct hw *hw, struct card_conf *info)
2120 {
2121         int err;
2122         unsigned int gctl;
2123         u32 data = 0;
2124         struct dac_conf dac_info = {0};
2125         struct adc_conf adc_info = {0};
2126         struct daio_conf daio_info = {0};
2127         struct trn_conf trn_info = {0};
2128
2129         /* Get PCI io port/memory base address and
2130          * do 20kx core switch if needed. */
2131         err = hw_card_start(hw);
2132         if (err)
2133                 return err;
2134
2135         /* PLL init */
2136         err = hw_pll_init(hw, info->rsr);
2137         if (err < 0)
2138                 return err;
2139
2140         /* kick off auto-init */
2141         err = hw_auto_init(hw);
2142         if (err < 0)
2143                 return err;
2144
2145         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
2146         set_field(&gctl, GCTL_DBP, 1);
2147         set_field(&gctl, GCTL_TBP, 1);
2148         set_field(&gctl, GCTL_FBP, 1);
2149         set_field(&gctl, GCTL_DPC, 0);
2150         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
2151
2152         /* Reset all global pending interrupts */
2153         hw_write_20kx(hw, GIE, 0);
2154         /* Reset all SRC pending interrupts */
2155         hw_write_20kx(hw, SRC_IP, 0);
2156
2157         if (hw->model != CTSB1270) {
2158                 /* TODO: detect the card ID and configure GPIO accordingly. */
2159                 /* Configures GPIO (0xD802 0x98028) */
2160                 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
2161                 /* Configures GPIO (SB0880) */
2162                 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
2163                 hw_write_20kx(hw, GPIO_CTRL, 0xD802);
2164         } else {
2165                 hw_write_20kx(hw, GPIO_CTRL, 0x9E5F);
2166         }
2167         /* Enable audio ring */
2168         hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
2169
2170         trn_info.vm_pgt_phys = info->vm_pgt_phys;
2171         err = hw_trn_init(hw, &trn_info);
2172         if (err < 0)
2173                 return err;
2174
2175         daio_info.msr = info->msr;
2176         err = hw_daio_init(hw, &daio_info);
2177         if (err < 0)
2178                 return err;
2179
2180         dac_info.msr = info->msr;
2181         err = hw_dac_init(hw, &dac_info);
2182         if (err < 0)
2183                 return err;
2184
2185         adc_info.msr = info->msr;
2186         adc_info.input = ADC_LINEIN;
2187         adc_info.mic20db = 0;
2188         err = hw_adc_init(hw, &adc_info);
2189         if (err < 0)
2190                 return err;
2191
2192         data = hw_read_20kx(hw, SRC_MCTL);
2193         data |= 0x1; /* Enables input from the audio ring */
2194         hw_write_20kx(hw, SRC_MCTL, data);
2195
2196         return 0;
2197 }
2198
2199 #ifdef CONFIG_PM_SLEEP
2200 static int hw_suspend(struct hw *hw)
2201 {
2202         hw_card_stop(hw);
2203         return 0;
2204 }
2205
2206 static int hw_resume(struct hw *hw, struct card_conf *info)
2207 {
2208         /* Re-initialize card hardware. */
2209         return hw_card_init(hw, info);
2210 }
2211 #endif
2212
2213 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2214 {
2215         return readl(hw->mem_base + reg);
2216 }
2217
2218 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2219 {
2220         writel(data, hw->mem_base + reg);
2221 }
2222
2223 static struct hw ct20k2_preset = {
2224         .irq = -1,
2225
2226         .card_init = hw_card_init,
2227         .card_stop = hw_card_stop,
2228         .pll_init = hw_pll_init,
2229         .is_adc_source_selected = hw_is_adc_input_selected,
2230         .select_adc_source = hw_adc_input_select,
2231         .capabilities = hw_capabilities,
2232         .output_switch_get = hw_output_switch_get,
2233         .output_switch_put = hw_output_switch_put,
2234         .mic_source_switch_get = hw_mic_source_switch_get,
2235         .mic_source_switch_put = hw_mic_source_switch_put,
2236 #ifdef CONFIG_PM_SLEEP
2237         .suspend = hw_suspend,
2238         .resume = hw_resume,
2239 #endif
2240
2241         .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2242         .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2243         .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2244         .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2245         .src_set_state = src_set_state,
2246         .src_set_bm = src_set_bm,
2247         .src_set_rsr = src_set_rsr,
2248         .src_set_sf = src_set_sf,
2249         .src_set_wr = src_set_wr,
2250         .src_set_pm = src_set_pm,
2251         .src_set_rom = src_set_rom,
2252         .src_set_vo = src_set_vo,
2253         .src_set_st = src_set_st,
2254         .src_set_ie = src_set_ie,
2255         .src_set_ilsz = src_set_ilsz,
2256         .src_set_bp = src_set_bp,
2257         .src_set_cisz = src_set_cisz,
2258         .src_set_ca = src_set_ca,
2259         .src_set_sa = src_set_sa,
2260         .src_set_la = src_set_la,
2261         .src_set_pitch = src_set_pitch,
2262         .src_set_dirty = src_set_dirty,
2263         .src_set_clear_zbufs = src_set_clear_zbufs,
2264         .src_set_dirty_all = src_set_dirty_all,
2265         .src_commit_write = src_commit_write,
2266         .src_get_ca = src_get_ca,
2267         .src_get_dirty = src_get_dirty,
2268         .src_dirty_conj_mask = src_dirty_conj_mask,
2269         .src_mgr_enbs_src = src_mgr_enbs_src,
2270         .src_mgr_enb_src = src_mgr_enb_src,
2271         .src_mgr_dsb_src = src_mgr_dsb_src,
2272         .src_mgr_commit_write = src_mgr_commit_write,
2273
2274         .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2275         .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2276         .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2277         .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2278         .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2279         .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2280         .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2281
2282         .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2283         .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2284         .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2285         .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2286         .amixer_set_mode = amixer_set_mode,
2287         .amixer_set_iv = amixer_set_iv,
2288         .amixer_set_x = amixer_set_x,
2289         .amixer_set_y = amixer_set_y,
2290         .amixer_set_sadr = amixer_set_sadr,
2291         .amixer_set_se = amixer_set_se,
2292         .amixer_set_dirty = amixer_set_dirty,
2293         .amixer_set_dirty_all = amixer_set_dirty_all,
2294         .amixer_commit_write = amixer_commit_write,
2295         .amixer_get_y = amixer_get_y,
2296         .amixer_get_dirty = amixer_get_dirty,
2297
2298         .dai_get_ctrl_blk = dai_get_ctrl_blk,
2299         .dai_put_ctrl_blk = dai_put_ctrl_blk,
2300         .dai_srt_set_srco = dai_srt_set_srco,
2301         .dai_srt_set_srcm = dai_srt_set_srcm,
2302         .dai_srt_set_rsr = dai_srt_set_rsr,
2303         .dai_srt_set_drat = dai_srt_set_drat,
2304         .dai_srt_set_ec = dai_srt_set_ec,
2305         .dai_srt_set_et = dai_srt_set_et,
2306         .dai_commit_write = dai_commit_write,
2307
2308         .dao_get_ctrl_blk = dao_get_ctrl_blk,
2309         .dao_put_ctrl_blk = dao_put_ctrl_blk,
2310         .dao_set_spos = dao_set_spos,
2311         .dao_commit_write = dao_commit_write,
2312         .dao_get_spos = dao_get_spos,
2313
2314         .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2315         .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2316         .daio_mgr_enb_dai = daio_mgr_enb_dai,
2317         .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2318         .daio_mgr_enb_dao = daio_mgr_enb_dao,
2319         .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2320         .daio_mgr_dao_init = daio_mgr_dao_init,
2321         .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2322         .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2323         .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2324         .daio_mgr_commit_write = daio_mgr_commit_write,
2325
2326         .set_timer_irq = set_timer_irq,
2327         .set_timer_tick = set_timer_tick,
2328         .get_wc = get_wc,
2329 };
2330
2331 int create_20k2_hw_obj(struct hw **rhw)
2332 {
2333         struct hw20k2 *hw20k2;
2334
2335         *rhw = NULL;
2336         hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL);
2337         if (!hw20k2)
2338                 return -ENOMEM;
2339
2340         hw20k2->hw = ct20k2_preset;
2341         *rhw = &hw20k2->hw;
2342
2343         return 0;
2344 }
2345
2346 int destroy_20k2_hw_obj(struct hw *hw)
2347 {
2348         if (hw->io_base)
2349                 hw_card_shutdown(hw);
2350
2351         kfree(hw);
2352         return 0;
2353 }