sound/pci/hda/hda_tegra.c

   1 /*
   2  *
   3  * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  *
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/clocksource.h>
  21 #include <linux/completion.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mutex.h>
  31 #include <linux/of_device.h>
  32 #include <linux/slab.h>
  33 #include <linux/time.h>
  34
  35 #include <sound/core.h>
  36 #include <sound/initval.h>
  37
  38 #include "hda_codec.h"
  39 #include "hda_controller.h"
  40
  41 /* Defines for Nvidia Tegra HDA support */
  42 #define HDA_BAR0           0x8000
  43
  44 #define HDA_CFG_CMD        0x1004
  45 #define HDA_CFG_BAR0       0x1010
  46
  47 #define HDA_ENABLE_IO_SPACE       (1 << 0)
  48 #define HDA_ENABLE_MEM_SPACE      (1 << 1)
  49 #define HDA_ENABLE_BUS_MASTER     (1 << 2)
  50 #define HDA_ENABLE_SERR           (1 << 8)
  51 #define HDA_DISABLE_INTR          (1 << 10)
  52 #define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
  53 #define HDA_BAR0_FINAL_PROGRAM    (1 << 14)
  54
  55 /* IPFS */
  56 #define HDA_IPFS_CONFIG           0x180
  57 #define HDA_IPFS_EN_FPCI          0x1
  58
  59 #define HDA_IPFS_FPCI_BAR0        0x80
  60 #define HDA_FPCI_BAR0_START       0x40
  61
  62 #define HDA_IPFS_INTR_MASK        0x188
  63 #define HDA_IPFS_EN_INTR          (1 << 16)
  64
  65 /* max number of SDs */
  66 #define NUM_CAPTURE_SD 1
  67 #define NUM_PLAYBACK_SD 1
  68
  69 struct hda_tegra {
  70         struct azx chip;
  71         struct device *dev;
  72         struct clk *hda_clk;
  73         struct clk *hda2codec_2x_clk;
  74         struct clk *hda2hdmi_clk;
  75         void __iomem *regs;
  76         struct work_struct probe_work;
  77 };
  78
  79 #ifdef CONFIG_PM
  80 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  81 module_param(power_save, bint, 0644);
  82 MODULE_PARM_DESC(power_save,
  83                  "Automatic power-saving timeout (in seconds, 0 = disable).");
  84 #else
  85 #define power_save      0
  86 #endif
  87
  88 /*
  89  * DMA page allocation ops.
  90  */
  91 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size,
  92                            struct snd_dma_buffer *buf)
  93 {
  94         return snd_dma_alloc_pages(type, bus->dev, size, buf);
  95 }
  96
  97 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
  98 {
  99         snd_dma_free_pages(buf);
 100 }
 101
 102 static int substream_alloc_pages(struct azx *chip,
 103                                  struct snd_pcm_substream *substream,
 104                                  size_t size)
 105 {
 106         return snd_pcm_lib_malloc_pages(substream, size);
 107 }
 108
 109 static int substream_free_pages(struct azx *chip,
 110                                 struct snd_pcm_substream *substream)
 111 {
 112         return snd_pcm_lib_free_pages(substream);
 113 }
 114
 115 /*
 116  * Register access ops. Tegra HDA register access is DWORD only.
 117  */
 118 static void hda_tegra_writel(u32 value, u32 __iomem *addr)
 119 {
 120         writel(value, addr);
 121 }
 122
 123 static u32 hda_tegra_readl(u32 __iomem *addr)
 124 {
 125         return readl(addr);
 126 }
 127
 128 static void hda_tegra_writew(u16 value, u16 __iomem  *addr)
 129 {
 130         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 131         void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
 132         u32 v;
 133
 134         v = readl(dword_addr);
 135         v &= ~(0xffff << shift);
 136         v |= value << shift;
 137         writel(v, dword_addr);
 138 }
 139
 140 static u16 hda_tegra_readw(u16 __iomem *addr)
 141 {
 142         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 143         void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
 144         u32 v;
 145
 146         v = readl(dword_addr);
 147         return (v >> shift) & 0xffff;
 148 }
 149
 150 static void hda_tegra_writeb(u8 value, u8 __iomem *addr)
 151 {
 152         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 153         void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
 154         u32 v;
 155
 156         v = readl(dword_addr);
 157         v &= ~(0xff << shift);
 158         v |= value << shift;
 159         writel(v, dword_addr);
 160 }
 161
 162 static u8 hda_tegra_readb(u8 __iomem *addr)
 163 {
 164         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 165         void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
 166         u32 v;
 167
 168         v = readl(dword_addr);
 169         return (v >> shift) & 0xff;
 170 }
 171
 172 static const struct hdac_io_ops hda_tegra_io_ops = {
 173         .reg_writel = hda_tegra_writel,
 174         .reg_readl = hda_tegra_readl,
 175         .reg_writew = hda_tegra_writew,
 176         .reg_readw = hda_tegra_readw,
 177         .reg_writeb = hda_tegra_writeb,
 178         .reg_readb = hda_tegra_readb,
 179         .dma_alloc_pages = dma_alloc_pages,
 180         .dma_free_pages = dma_free_pages,
 181 };
 182
 183 static const struct hda_controller_ops hda_tegra_ops = {
 184         .substream_alloc_pages = substream_alloc_pages,
 185         .substream_free_pages = substream_free_pages,
 186 };
 187
 188 static void hda_tegra_init(struct hda_tegra *hda)
 189 {
 190         u32 v;
 191
 192         /* Enable PCI access */
 193         v = readl(hda->regs + HDA_IPFS_CONFIG);
 194         v |= HDA_IPFS_EN_FPCI;
 195         writel(v, hda->regs + HDA_IPFS_CONFIG);
 196
 197         /* Enable MEM/IO space and bus master */
 198         v = readl(hda->regs + HDA_CFG_CMD);
 199         v &= ~HDA_DISABLE_INTR;
 200         v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
 201                 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
 202         writel(v, hda->regs + HDA_CFG_CMD);
 203
 204         writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
 205         writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
 206         writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
 207
 208         v = readl(hda->regs + HDA_IPFS_INTR_MASK);
 209         v |= HDA_IPFS_EN_INTR;
 210         writel(v, hda->regs + HDA_IPFS_INTR_MASK);
 211 }
 212
 213 static int hda_tegra_enable_clocks(struct hda_tegra *data)
 214 {
 215         int rc;
 216
 217         rc = clk_prepare_enable(data->hda_clk);
 218         if (rc)
 219                 return rc;
 220         rc = clk_prepare_enable(data->hda2codec_2x_clk);
 221         if (rc)
 222                 goto disable_hda;
 223         rc = clk_prepare_enable(data->hda2hdmi_clk);
 224         if (rc)
 225                 goto disable_codec_2x;
 226
 227         return 0;
 228
 229 disable_codec_2x:
 230         clk_disable_unprepare(data->hda2codec_2x_clk);
 231 disable_hda:
 232         clk_disable_unprepare(data->hda_clk);
 233         return rc;
 234 }
 235
 236 #ifdef CONFIG_PM_SLEEP
 237 static void hda_tegra_disable_clocks(struct hda_tegra *data)
 238 {
 239         clk_disable_unprepare(data->hda2hdmi_clk);
 240         clk_disable_unprepare(data->hda2codec_2x_clk);
 241         clk_disable_unprepare(data->hda_clk);
 242 }
 243
 244 /*
 245  * power management
 246  */
 247 static int hda_tegra_suspend(struct device *dev)
 248 {
 249         struct snd_card *card = dev_get_drvdata(dev);
 250         struct azx *chip = card->private_data;
 251         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 252         struct hdac_bus *bus = azx_bus(chip);
 253
 254         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 255
 256         azx_stop_chip(chip);
 257         synchronize_irq(bus->irq);
 258         azx_enter_link_reset(chip);
 259         hda_tegra_disable_clocks(hda);
 260
 261         return 0;
 262 }
 263
 264 static int hda_tegra_resume(struct device *dev)
 265 {
 266         struct snd_card *card = dev_get_drvdata(dev);
 267         struct azx *chip = card->private_data;
 268         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 269
 270         hda_tegra_enable_clocks(hda);
 271
 272         hda_tegra_init(hda);
 273
 274         azx_init_chip(chip, 1);
 275
 276         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 277
 278         return 0;
 279 }
 280 #endif /* CONFIG_PM_SLEEP */
 281
 282 static const struct dev_pm_ops hda_tegra_pm = {
 283         SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
 284 };
 285
 286 static int hda_tegra_dev_disconnect(struct snd_device *device)
 287 {
 288         struct azx *chip = device->device_data;
 289
 290         chip->bus.shutdown = 1;
 291         return 0;
 292 }
 293
 294 /*
 295  * destructor
 296  */
 297 static int hda_tegra_dev_free(struct snd_device *device)
 298 {
 299         struct azx *chip = device->device_data;
 300         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 301
 302         cancel_work_sync(&hda->probe_work);
 303         if (azx_bus(chip)->chip_init) {
 304                 azx_stop_all_streams(chip);
 305                 azx_stop_chip(chip);
 306         }
 307
 308         azx_free_stream_pages(chip);
 309         azx_free_streams(chip);
 310         snd_hdac_bus_exit(azx_bus(chip));
 311
 312         return 0;
 313 }
 314
 315 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
 316 {
 317         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 318         struct hdac_bus *bus = azx_bus(chip);
 319         struct device *dev = hda->dev;
 320         struct resource *res;
 321         int err;
 322
 323         hda->hda_clk = devm_clk_get(dev, "hda");
 324         if (IS_ERR(hda->hda_clk)) {
 325                 dev_err(dev, "failed to get hda clock\n");
 326                 return PTR_ERR(hda->hda_clk);
 327         }
 328         hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
 329         if (IS_ERR(hda->hda2codec_2x_clk)) {
 330                 dev_err(dev, "failed to get hda2codec_2x clock\n");
 331                 return PTR_ERR(hda->hda2codec_2x_clk);
 332         }
 333         hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
 334         if (IS_ERR(hda->hda2hdmi_clk)) {
 335                 dev_err(dev, "failed to get hda2hdmi clock\n");
 336                 return PTR_ERR(hda->hda2hdmi_clk);
 337         }
 338
 339         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 340         hda->regs = devm_ioremap_resource(dev, res);
 341         if (IS_ERR(hda->regs))
 342                 return PTR_ERR(hda->regs);
 343
 344         bus->remap_addr = hda->regs + HDA_BAR0;
 345         bus->addr = res->start + HDA_BAR0;
 346
 347         err = hda_tegra_enable_clocks(hda);
 348         if (err) {
 349                 dev_err(dev, "failed to get enable clocks\n");
 350                 return err;
 351         }
 352
 353         hda_tegra_init(hda);
 354
 355         return 0;
 356 }
 357
 358 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
 359 {
 360         struct hdac_bus *bus = azx_bus(chip);
 361         struct snd_card *card = chip->card;
 362         int err;
 363         unsigned short gcap;
 364         int irq_id = platform_get_irq(pdev, 0);
 365
 366         if (irq_id < 0)
 367                 return irq_id;
 368
 369         err = hda_tegra_init_chip(chip, pdev);
 370         if (err)
 371                 return err;
 372
 373         err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
 374                              IRQF_SHARED, KBUILD_MODNAME, chip);
 375         if (err) {
 376                 dev_err(chip->card->dev,
 377                         "unable to request IRQ %d, disabling device\n",
 378                         irq_id);
 379                 return err;
 380         }
 381         bus->irq = irq_id;
 382
 383         synchronize_irq(bus->irq);
 384
 385         gcap = azx_readw(chip, GCAP);
 386         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
 387
 388         /* read number of streams from GCAP register instead of using
 389          * hardcoded value
 390          */
 391         chip->capture_streams = (gcap >> 8) & 0x0f;
 392         chip->playback_streams = (gcap >> 12) & 0x0f;
 393         if (!chip->playback_streams && !chip->capture_streams) {
 394                 /* gcap didn't give any info, switching to old method */
 395                 chip->playback_streams = NUM_PLAYBACK_SD;
 396                 chip->capture_streams = NUM_CAPTURE_SD;
 397         }
 398         chip->capture_index_offset = 0;
 399         chip->playback_index_offset = chip->capture_streams;
 400         chip->num_streams = chip->playback_streams + chip->capture_streams;
 401
 402         /* initialize streams */
 403         err = azx_init_streams(chip);
 404         if (err < 0) {
 405                 dev_err(card->dev, "failed to initialize streams: %d\n", err);
 406                 return err;
 407         }
 408
 409         err = azx_alloc_stream_pages(chip);
 410         if (err < 0) {
 411                 dev_err(card->dev, "failed to allocate stream pages: %d\n",
 412                         err);
 413                 return err;
 414         }
 415
 416         /* initialize chip */
 417         azx_init_chip(chip, 1);
 418
 419         /* codec detection */
 420         if (!bus->codec_mask) {
 421                 dev_err(card->dev, "no codecs found!\n");
 422                 return -ENODEV;
 423         }
 424
 425         strcpy(card->driver, "tegra-hda");
 426         strcpy(card->shortname, "tegra-hda");
 427         snprintf(card->longname, sizeof(card->longname),
 428                  "%s at 0x%lx irq %i",
 429                  card->shortname, bus->addr, bus->irq);
 430
 431         return 0;
 432 }
 433
 434 /*
 435  * constructor
 436  */
 437
 438 static void hda_tegra_probe_work(struct work_struct *work);
 439
 440 static int hda_tegra_create(struct snd_card *card,
 441                             unsigned int driver_caps,
 442                             struct hda_tegra *hda)
 443 {
 444         static struct snd_device_ops ops = {
 445                 .dev_disconnect = hda_tegra_dev_disconnect,
 446                 .dev_free = hda_tegra_dev_free,
 447         };
 448         struct azx *chip;
 449         int err;
 450
 451         chip = &hda->chip;
 452
 453         mutex_init(&chip->open_mutex);
 454         chip->card = card;
 455         chip->ops = &hda_tegra_ops;
 456         chip->driver_caps = driver_caps;
 457         chip->driver_type = driver_caps & 0xff;
 458         chip->dev_index = 0;
 459         INIT_LIST_HEAD(&chip->pcm_list);
 460
 461         chip->codec_probe_mask = -1;
 462
 463         chip->single_cmd = false;
 464         chip->snoop = true;
 465
 466         INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
 467
 468         err = azx_bus_init(chip, NULL, &hda_tegra_io_ops);
 469         if (err < 0)
 470                 return err;
 471
 472         chip->bus.needs_damn_long_delay = 1;
 473
 474         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
 475         if (err < 0) {
 476                 dev_err(card->dev, "Error creating device\n");
 477                 return err;
 478         }
 479
 480         return 0;
 481 }
 482
 483 static const struct of_device_id hda_tegra_match[] = {
 484         { .compatible = "nvidia,tegra30-hda" },
 485         {},
 486 };
 487 MODULE_DEVICE_TABLE(of, hda_tegra_match);
 488
 489 static int hda_tegra_probe(struct platform_device *pdev)
 490 {
 491         const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR;
 492         struct snd_card *card;
 493         struct azx *chip;
 494         struct hda_tegra *hda;
 495         int err;
 496
 497         hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
 498         if (!hda)
 499                 return -ENOMEM;
 500         hda->dev = &pdev->dev;
 501         chip = &hda->chip;
 502
 503         err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
 504                            THIS_MODULE, 0, &card);
 505         if (err < 0) {
 506                 dev_err(&pdev->dev, "Error creating card!\n");
 507                 return err;
 508         }
 509
 510         err = hda_tegra_create(card, driver_flags, hda);
 511         if (err < 0)
 512                 goto out_free;
 513         card->private_data = chip;
 514
 515         dev_set_drvdata(&pdev->dev, card);
 516         schedule_work(&hda->probe_work);
 517
 518         return 0;
 519
 520 out_free:
 521         snd_card_free(card);
 522         return err;
 523 }
 524
 525 static void hda_tegra_probe_work(struct work_struct *work)
 526 {
 527         struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
 528         struct azx *chip = &hda->chip;
 529         struct platform_device *pdev = to_platform_device(hda->dev);
 530         int err;
 531
 532         err = hda_tegra_first_init(chip, pdev);
 533         if (err < 0)
 534                 goto out_free;
 535
 536         /* create codec instances */
 537         err = azx_probe_codecs(chip, 0);
 538         if (err < 0)
 539                 goto out_free;
 540
 541         err = azx_codec_configure(chip);
 542         if (err < 0)
 543                 goto out_free;
 544
 545         err = snd_card_register(chip->card);
 546         if (err < 0)
 547                 goto out_free;
 548
 549         chip->running = 1;
 550         snd_hda_set_power_save(&chip->bus, power_save * 1000);
 551
 552  out_free:
 553         return; /* no error return from async probe */
 554 }
 555
 556 static int hda_tegra_remove(struct platform_device *pdev)
 557 {
 558         return snd_card_free(dev_get_drvdata(&pdev->dev));
 559 }
 560
 561 static void hda_tegra_shutdown(struct platform_device *pdev)
 562 {
 563         struct snd_card *card = dev_get_drvdata(&pdev->dev);
 564         struct azx *chip;
 565
 566         if (!card)
 567                 return;
 568         chip = card->private_data;
 569         if (chip && chip->running)
 570                 azx_stop_chip(chip);
 571 }
 572
 573 static struct platform_driver tegra_platform_hda = {
 574         .driver = {
 575                 .name = "tegra-hda",
 576                 .pm = &hda_tegra_pm,
 577                 .of_match_table = hda_tegra_match,
 578         },
 579         .probe = hda_tegra_probe,
 580         .remove = hda_tegra_remove,
 581         .shutdown = hda_tegra_shutdown,
 582 };
 583 module_platform_driver(tegra_platform_hda);
 584
 585 MODULE_DESCRIPTION("Tegra HDA bus driver");
 586 MODULE_LICENSE("GPL v2");