3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <linux/pm_runtime.h>
37 #include <sound/core.h>
38 #include <sound/jack.h>
39 #include <sound/asoundef.h>
40 #include <sound/tlv.h>
41 #include <sound/hdaudio.h>
42 #include <sound/hda_i915.h>
43 #include <sound/hda_chmap.h>
44 #include "hda_codec.h"
45 #include "hda_local.h"
48 static bool static_hdmi_pcm;
49 module_param(static_hdmi_pcm, bool, 0644);
50 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
52 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
53 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
54 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
55 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
56 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
57 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
58 ((codec)->core.vendor_id == 0x80862800))
59 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
60 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
61 || is_skylake(codec) || is_broxton(codec) \
62 || is_kabylake(codec)) || is_geminilake(codec) \
63 || is_cannonlake(codec)
64 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
65 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
66 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
68 struct hdmi_spec_per_cvt {
71 unsigned int channels_min;
72 unsigned int channels_max;
78 /* max. connections to a widget */
79 #define HDA_MAX_CONNECTIONS 32
81 struct hdmi_spec_per_pin {
84 /* pin idx, different device entries on the same pin use the same idx */
87 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
91 struct hda_codec *codec;
92 struct hdmi_eld sink_eld;
94 struct delayed_work work;
95 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
96 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
98 bool setup; /* the stream has been set up by prepare callback */
99 int channels; /* current number of channels */
101 bool chmap_set; /* channel-map override by ALSA API? */
102 unsigned char chmap[8]; /* ALSA API channel-map */
103 #ifdef CONFIG_SND_PROC_FS
104 struct snd_info_entry *proc_entry;
108 /* operations used by generic code that can be overridden by patches */
110 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
111 unsigned char *buf, int *eld_size);
113 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
114 int ca, int active_channels, int conn_type);
116 /* enable/disable HBR (HD passthrough) */
117 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
119 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
120 hda_nid_t pin_nid, u32 stream_tag, int format);
122 void (*pin_cvt_fixup)(struct hda_codec *codec,
123 struct hdmi_spec_per_pin *per_pin,
129 struct snd_jack *jack;
130 struct snd_kcontrol *eld_ctl;
135 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
136 hda_nid_t cvt_nids[4]; /* only for haswell fix */
139 * num_pins is the number of virtual pins
140 * for example, there are 3 pins, and each pin
141 * has 4 device entries, then the num_pins is 12
145 * num_nids is the number of real pins
146 * In the above example, num_nids is 3
150 * dev_num is the number of device entries
152 * In the above example, dev_num is 4
155 struct snd_array pins; /* struct hdmi_spec_per_pin */
156 struct hdmi_pcm pcm_rec[16];
157 struct mutex pcm_lock;
158 /* pcm_bitmap means which pcms have been assigned to pins*/
159 unsigned long pcm_bitmap;
160 int pcm_used; /* counter of pcm_rec[] */
161 /* bitmap shows whether the pcm is opened in user space
162 * bit 0 means the first playback PCM (PCM3);
163 * bit 1 means the second playback PCM, and so on.
165 unsigned long pcm_in_use;
167 struct hdmi_eld temp_eld;
173 * Non-generic VIA/NVIDIA specific
175 struct hda_multi_out multiout;
176 struct hda_pcm_stream pcm_playback;
178 /* i915/powerwell (Haswell+/Valleyview+) specific */
179 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
180 struct i915_audio_component_audio_ops i915_audio_ops;
182 struct hdac_chmap chmap;
183 hda_nid_t vendor_nid;
186 #ifdef CONFIG_SND_HDA_I915
187 static inline bool codec_has_acomp(struct hda_codec *codec)
189 struct hdmi_spec *spec = codec->spec;
190 return spec->use_acomp_notifier;
193 #define codec_has_acomp(codec) false
196 struct hdmi_audio_infoframe {
203 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
207 u8 LFEPBL01_LSV36_DM_INH7;
210 struct dp_audio_infoframe {
213 u8 ver; /* 0x11 << 2 */
215 u8 CC02_CT47; /* match with HDMI infoframe from this on */
219 u8 LFEPBL01_LSV36_DM_INH7;
222 union audio_infoframe {
223 struct hdmi_audio_infoframe hdmi;
224 struct dp_audio_infoframe dp;
232 #define get_pin(spec, idx) \
233 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
234 #define get_cvt(spec, idx) \
235 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
236 /* obtain hdmi_pcm object assigned to idx */
237 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
238 /* obtain hda_pcm object assigned to idx */
239 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
241 static int pin_id_to_pin_index(struct hda_codec *codec,
242 hda_nid_t pin_nid, int dev_id)
244 struct hdmi_spec *spec = codec->spec;
246 struct hdmi_spec_per_pin *per_pin;
249 * (dev_id == -1) means it is NON-MST pin
250 * return the first virtual pin on this port
255 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
256 per_pin = get_pin(spec, pin_idx);
257 if ((per_pin->pin_nid == pin_nid) &&
258 (per_pin->dev_id == dev_id))
262 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
266 static int hinfo_to_pcm_index(struct hda_codec *codec,
267 struct hda_pcm_stream *hinfo)
269 struct hdmi_spec *spec = codec->spec;
272 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
273 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
276 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
280 static int hinfo_to_pin_index(struct hda_codec *codec,
281 struct hda_pcm_stream *hinfo)
283 struct hdmi_spec *spec = codec->spec;
284 struct hdmi_spec_per_pin *per_pin;
287 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
288 per_pin = get_pin(spec, pin_idx);
290 per_pin->pcm->pcm->stream == hinfo)
294 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
298 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
302 struct hdmi_spec_per_pin *per_pin;
304 for (i = 0; i < spec->num_pins; i++) {
305 per_pin = get_pin(spec, i);
306 if (per_pin->pcm_idx == pcm_idx)
312 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
314 struct hdmi_spec *spec = codec->spec;
317 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
318 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
321 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
325 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_info *uinfo)
328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
329 struct hdmi_spec *spec = codec->spec;
330 struct hdmi_spec_per_pin *per_pin;
331 struct hdmi_eld *eld;
334 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
336 pcm_idx = kcontrol->private_value;
337 mutex_lock(&spec->pcm_lock);
338 per_pin = pcm_idx_to_pin(spec, pcm_idx);
340 /* no pin is bound to the pcm */
344 eld = &per_pin->sink_eld;
345 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
348 mutex_unlock(&spec->pcm_lock);
352 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
353 struct snd_ctl_elem_value *ucontrol)
355 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
356 struct hdmi_spec *spec = codec->spec;
357 struct hdmi_spec_per_pin *per_pin;
358 struct hdmi_eld *eld;
362 pcm_idx = kcontrol->private_value;
363 mutex_lock(&spec->pcm_lock);
364 per_pin = pcm_idx_to_pin(spec, pcm_idx);
366 /* no pin is bound to the pcm */
367 memset(ucontrol->value.bytes.data, 0,
368 ARRAY_SIZE(ucontrol->value.bytes.data));
372 eld = &per_pin->sink_eld;
373 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
374 eld->eld_size > ELD_MAX_SIZE) {
380 memset(ucontrol->value.bytes.data, 0,
381 ARRAY_SIZE(ucontrol->value.bytes.data));
383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
387 mutex_unlock(&spec->pcm_lock);
391 static const struct snd_kcontrol_new eld_bytes_ctl = {
392 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
393 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
395 .info = hdmi_eld_ctl_info,
396 .get = hdmi_eld_ctl_get,
399 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
402 struct snd_kcontrol *kctl;
403 struct hdmi_spec *spec = codec->spec;
406 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
409 kctl->private_value = pcm_idx;
410 kctl->id.device = device;
412 /* no pin nid is associated with the kctl now
413 * tbd: associate pin nid to eld ctl later
415 err = snd_hda_ctl_add(codec, 0, kctl);
419 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
424 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
425 int *packet_index, int *byte_index)
429 val = snd_hda_codec_read(codec, pin_nid, 0,
430 AC_VERB_GET_HDMI_DIP_INDEX, 0);
432 *packet_index = val >> 5;
433 *byte_index = val & 0x1f;
437 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
438 int packet_index, int byte_index)
442 val = (packet_index << 5) | (byte_index & 0x1f);
444 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
447 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
450 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
453 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
455 struct hdmi_spec *spec = codec->spec;
459 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
460 snd_hda_codec_write(codec, pin_nid, 0,
461 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
463 if (spec->dyn_pin_out)
464 /* Disable pin out until stream is active */
467 /* Enable pin out: some machines with GM965 gets broken output
468 * when the pin is disabled or changed while using with HDMI
472 snd_hda_codec_write(codec, pin_nid, 0,
473 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
480 #ifdef CONFIG_SND_PROC_FS
481 static void print_eld_info(struct snd_info_entry *entry,
482 struct snd_info_buffer *buffer)
484 struct hdmi_spec_per_pin *per_pin = entry->private_data;
486 mutex_lock(&per_pin->lock);
487 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
488 mutex_unlock(&per_pin->lock);
491 static void write_eld_info(struct snd_info_entry *entry,
492 struct snd_info_buffer *buffer)
494 struct hdmi_spec_per_pin *per_pin = entry->private_data;
496 mutex_lock(&per_pin->lock);
497 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
498 mutex_unlock(&per_pin->lock);
501 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
504 struct hda_codec *codec = per_pin->codec;
505 struct snd_info_entry *entry;
508 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
509 err = snd_card_proc_new(codec->card, name, &entry);
513 snd_info_set_text_ops(entry, per_pin, print_eld_info);
514 entry->c.text.write = write_eld_info;
515 entry->mode |= S_IWUSR;
516 per_pin->proc_entry = entry;
521 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
523 if (!per_pin->codec->bus->shutdown) {
524 snd_info_free_entry(per_pin->proc_entry);
525 per_pin->proc_entry = NULL;
529 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
534 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
540 * Audio InfoFrame routines
544 * Enable Audio InfoFrame Transmission
546 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
549 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
550 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
555 * Disable Audio InfoFrame Transmission
557 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
560 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
561 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
565 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
567 #ifdef CONFIG_SND_DEBUG_VERBOSE
571 size = snd_hdmi_get_eld_size(codec, pin_nid);
572 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
574 for (i = 0; i < 8; i++) {
575 size = snd_hda_codec_read(codec, pin_nid, 0,
576 AC_VERB_GET_HDMI_DIP_SIZE, i);
577 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
582 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
588 for (i = 0; i < 8; i++) {
589 size = snd_hda_codec_read(codec, pin_nid, 0,
590 AC_VERB_GET_HDMI_DIP_SIZE, i);
594 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
595 for (j = 1; j < 1000; j++) {
596 hdmi_write_dip_byte(codec, pin_nid, 0x0);
597 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
599 codec_dbg(codec, "dip index %d: %d != %d\n",
601 if (bi == 0) /* byte index wrapped around */
605 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
611 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
613 u8 *bytes = (u8 *)hdmi_ai;
617 hdmi_ai->checksum = 0;
619 for (i = 0; i < sizeof(*hdmi_ai); i++)
622 hdmi_ai->checksum = -sum;
625 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
631 hdmi_debug_dip_size(codec, pin_nid);
632 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
634 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
635 for (i = 0; i < size; i++)
636 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
639 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
645 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
649 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
650 for (i = 0; i < size; i++) {
651 val = snd_hda_codec_read(codec, pin_nid, 0,
652 AC_VERB_GET_HDMI_DIP_DATA, 0);
660 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
662 int ca, int active_channels,
665 union audio_infoframe ai;
667 memset(&ai, 0, sizeof(ai));
668 if (conn_type == 0) { /* HDMI */
669 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
671 hdmi_ai->type = 0x84;
674 hdmi_ai->CC02_CT47 = active_channels - 1;
676 hdmi_checksum_audio_infoframe(hdmi_ai);
677 } else if (conn_type == 1) { /* DisplayPort */
678 struct dp_audio_infoframe *dp_ai = &ai.dp;
682 dp_ai->ver = 0x11 << 2;
683 dp_ai->CC02_CT47 = active_channels - 1;
686 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
692 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
693 * sizeof(*dp_ai) to avoid partial match/update problems when
694 * the user switches between HDMI/DP monitors.
696 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
699 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
701 active_channels, ca);
702 hdmi_stop_infoframe_trans(codec, pin_nid);
703 hdmi_fill_audio_infoframe(codec, pin_nid,
704 ai.bytes, sizeof(ai));
705 hdmi_start_infoframe_trans(codec, pin_nid);
709 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
710 struct hdmi_spec_per_pin *per_pin,
713 struct hdmi_spec *spec = codec->spec;
714 struct hdac_chmap *chmap = &spec->chmap;
715 hda_nid_t pin_nid = per_pin->pin_nid;
716 int channels = per_pin->channels;
718 struct hdmi_eld *eld;
724 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
725 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
726 snd_hda_codec_write(codec, pin_nid, 0,
727 AC_VERB_SET_AMP_GAIN_MUTE,
730 eld = &per_pin->sink_eld;
732 ca = snd_hdac_channel_allocation(&codec->core,
733 eld->info.spk_alloc, channels,
734 per_pin->chmap_set, non_pcm, per_pin->chmap);
736 active_channels = snd_hdac_get_active_channels(ca);
738 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
742 * always configure channel mapping, it may have been changed by the
743 * user in the meantime
745 snd_hdac_setup_channel_mapping(&spec->chmap,
746 pin_nid, non_pcm, ca, channels,
747 per_pin->chmap, per_pin->chmap_set);
749 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
750 eld->info.conn_type);
752 per_pin->non_pcm = non_pcm;
759 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
761 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
764 struct hdmi_spec *spec = codec->spec;
765 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
769 mutex_lock(&spec->pcm_lock);
770 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
771 snd_hda_jack_report_sync(codec);
772 mutex_unlock(&spec->pcm_lock);
775 static void jack_callback(struct hda_codec *codec,
776 struct hda_jack_callback *jack)
778 /* hda_jack don't support DP MST */
779 check_presence_and_report(codec, jack->nid, 0);
782 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
784 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
785 struct hda_jack_tbl *jack;
786 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
789 * assume DP MST uses dyn_pcm_assign and acomp and
791 * if DP MST supports unsol event, below code need
794 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
797 jack->jack_dirty = 1;
800 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
801 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
802 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
804 /* hda_jack don't support DP MST */
805 check_presence_and_report(codec, jack->nid, 0);
808 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
810 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
811 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
812 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
813 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
816 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
831 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
833 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
834 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
836 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
837 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
842 hdmi_intrinsic_event(codec, res);
844 hdmi_non_intrinsic_event(codec, res);
847 static void haswell_verify_D0(struct hda_codec *codec,
848 hda_nid_t cvt_nid, hda_nid_t nid)
852 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
853 * thus pins could only choose converter 0 for use. Make sure the
854 * converters are in correct power state */
855 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
856 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
858 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
859 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
862 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
863 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
864 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
872 /* HBR should be Non-PCM, 8 channels */
873 #define is_hbr_format(format) \
874 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
876 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
879 int pinctl, new_pinctl;
881 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
882 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
883 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
886 return hbr ? -EINVAL : 0;
888 new_pinctl = pinctl & ~AC_PINCTL_EPT;
890 new_pinctl |= AC_PINCTL_EPT_HBR;
892 new_pinctl |= AC_PINCTL_EPT_NATIVE;
895 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
897 pinctl == new_pinctl ? "" : "new-",
900 if (pinctl != new_pinctl)
901 snd_hda_codec_write(codec, pin_nid, 0,
902 AC_VERB_SET_PIN_WIDGET_CONTROL,
910 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
911 hda_nid_t pin_nid, u32 stream_tag, int format)
913 struct hdmi_spec *spec = codec->spec;
917 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
920 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
924 if (is_haswell_plus(codec)) {
927 * on recent platforms IEC Coding Type is required for HBR
928 * support, read current Digital Converter settings and set
929 * ICT bitfield if needed.
931 param = snd_hda_codec_read(codec, cvt_nid, 0,
932 AC_VERB_GET_DIGI_CONVERT_1, 0);
934 param = (param >> 16) & ~(AC_DIG3_ICT);
936 /* on recent platforms ICT mode is required for HBR support */
937 if (is_hbr_format(format))
940 snd_hda_codec_write(codec, cvt_nid, 0,
941 AC_VERB_SET_DIGI_CONVERT_3, param);
944 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
948 /* Try to find an available converter
949 * If pin_idx is less then zero, just try to find an available converter.
950 * Otherwise, try to find an available converter and get the cvt mux index
953 static int hdmi_choose_cvt(struct hda_codec *codec,
954 int pin_idx, int *cvt_id)
956 struct hdmi_spec *spec = codec->spec;
957 struct hdmi_spec_per_pin *per_pin;
958 struct hdmi_spec_per_cvt *per_cvt = NULL;
959 int cvt_idx, mux_idx = 0;
961 /* pin_idx < 0 means no pin will be bound to the converter */
965 per_pin = get_pin(spec, pin_idx);
967 /* Dynamically assign converter to stream */
968 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
969 per_cvt = get_cvt(spec, cvt_idx);
971 /* Must not already be assigned */
972 if (per_cvt->assigned)
976 /* Must be in pin's mux's list of converters */
977 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
978 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
980 /* Not in mux list */
981 if (mux_idx == per_pin->num_mux_nids)
986 /* No free converters */
987 if (cvt_idx == spec->num_cvts)
991 per_pin->mux_idx = mux_idx;
999 /* Assure the pin select the right convetor */
1000 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1001 struct hdmi_spec_per_pin *per_pin)
1003 hda_nid_t pin_nid = per_pin->pin_nid;
1006 mux_idx = per_pin->mux_idx;
1007 curr = snd_hda_codec_read(codec, pin_nid, 0,
1008 AC_VERB_GET_CONNECT_SEL, 0);
1009 if (curr != mux_idx)
1010 snd_hda_codec_write_cache(codec, pin_nid, 0,
1011 AC_VERB_SET_CONNECT_SEL,
1015 /* get the mux index for the converter of the pins
1016 * converter's mux index is the same for all pins on Intel platform
1018 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1023 for (i = 0; i < spec->num_cvts; i++)
1024 if (spec->cvt_nids[i] == cvt_nid)
1029 /* Intel HDMI workaround to fix audio routing issue:
1030 * For some Intel display codecs, pins share the same connection list.
1031 * So a conveter can be selected by multiple pins and playback on any of these
1032 * pins will generate sound on the external display, because audio flows from
1033 * the same converter to the display pipeline. Also muting one pin may make
1034 * other pins have no sound output.
1035 * So this function assures that an assigned converter for a pin is not selected
1036 * by any other pins.
1038 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1040 int dev_id, int mux_idx)
1042 struct hdmi_spec *spec = codec->spec;
1045 struct hdmi_spec_per_cvt *per_cvt;
1046 struct hdmi_spec_per_pin *per_pin;
1049 /* configure the pins connections */
1050 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1054 per_pin = get_pin(spec, pin_idx);
1056 * pin not connected to monitor
1057 * no need to operate on it
1062 if ((per_pin->pin_nid == pin_nid) &&
1063 (per_pin->dev_id == dev_id))
1067 * if per_pin->dev_id >= dev_num,
1068 * snd_hda_get_dev_select() will fail,
1069 * and the following operation is unpredictable.
1070 * So skip this situation.
1072 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1073 if (per_pin->dev_id >= dev_num)
1076 nid = per_pin->pin_nid;
1079 * Calling this function should not impact
1080 * on the device entry selection
1081 * So let's save the dev id for each pin,
1082 * and restore it when return
1084 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1085 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1086 curr = snd_hda_codec_read(codec, nid, 0,
1087 AC_VERB_GET_CONNECT_SEL, 0);
1088 if (curr != mux_idx) {
1089 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1094 /* choose an unassigned converter. The conveters in the
1095 * connection list are in the same order as in the codec.
1097 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1098 per_cvt = get_cvt(spec, cvt_idx);
1099 if (!per_cvt->assigned) {
1101 "choose cvt %d for pin nid %d\n",
1103 snd_hda_codec_write_cache(codec, nid, 0,
1104 AC_VERB_SET_CONNECT_SEL,
1109 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1113 /* A wrapper of intel_not_share_asigned_cvt() */
1114 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1115 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1118 struct hdmi_spec *spec = codec->spec;
1120 /* On Intel platform, the mapping of converter nid to
1121 * mux index of the pins are always the same.
1122 * The pin nid may be 0, this means all pins will not
1123 * share the converter.
1125 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1127 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1130 /* skeleton caller of pin_cvt_fixup ops */
1131 static void pin_cvt_fixup(struct hda_codec *codec,
1132 struct hdmi_spec_per_pin *per_pin,
1135 struct hdmi_spec *spec = codec->spec;
1137 if (spec->ops.pin_cvt_fixup)
1138 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1141 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1142 * in dyn_pcm_assign mode.
1144 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1145 struct hda_codec *codec,
1146 struct snd_pcm_substream *substream)
1148 struct hdmi_spec *spec = codec->spec;
1149 struct snd_pcm_runtime *runtime = substream->runtime;
1150 int cvt_idx, pcm_idx;
1151 struct hdmi_spec_per_cvt *per_cvt = NULL;
1154 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1158 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1162 per_cvt = get_cvt(spec, cvt_idx);
1163 per_cvt->assigned = 1;
1164 hinfo->nid = per_cvt->cvt_nid;
1166 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1168 set_bit(pcm_idx, &spec->pcm_in_use);
1169 /* todo: setup spdif ctls assign */
1171 /* Initially set the converter's capabilities */
1172 hinfo->channels_min = per_cvt->channels_min;
1173 hinfo->channels_max = per_cvt->channels_max;
1174 hinfo->rates = per_cvt->rates;
1175 hinfo->formats = per_cvt->formats;
1176 hinfo->maxbps = per_cvt->maxbps;
1178 /* Store the updated parameters */
1179 runtime->hw.channels_min = hinfo->channels_min;
1180 runtime->hw.channels_max = hinfo->channels_max;
1181 runtime->hw.formats = hinfo->formats;
1182 runtime->hw.rates = hinfo->rates;
1184 snd_pcm_hw_constraint_step(substream->runtime, 0,
1185 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1192 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1193 struct hda_codec *codec,
1194 struct snd_pcm_substream *substream)
1196 struct hdmi_spec *spec = codec->spec;
1197 struct snd_pcm_runtime *runtime = substream->runtime;
1198 int pin_idx, cvt_idx, pcm_idx;
1199 struct hdmi_spec_per_pin *per_pin;
1200 struct hdmi_eld *eld;
1201 struct hdmi_spec_per_cvt *per_cvt = NULL;
1204 /* Validate hinfo */
1205 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1209 mutex_lock(&spec->pcm_lock);
1210 pin_idx = hinfo_to_pin_index(codec, hinfo);
1211 if (!spec->dyn_pcm_assign) {
1212 if (snd_BUG_ON(pin_idx < 0)) {
1217 /* no pin is assigned to the PCM
1218 * PA need pcm open successfully when probe
1221 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1226 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1230 per_cvt = get_cvt(spec, cvt_idx);
1231 /* Claim converter */
1232 per_cvt->assigned = 1;
1234 set_bit(pcm_idx, &spec->pcm_in_use);
1235 per_pin = get_pin(spec, pin_idx);
1236 per_pin->cvt_nid = per_cvt->cvt_nid;
1237 hinfo->nid = per_cvt->cvt_nid;
1239 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1240 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1241 AC_VERB_SET_CONNECT_SEL,
1244 /* configure unused pins to choose other converters */
1245 pin_cvt_fixup(codec, per_pin, 0);
1247 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1249 /* Initially set the converter's capabilities */
1250 hinfo->channels_min = per_cvt->channels_min;
1251 hinfo->channels_max = per_cvt->channels_max;
1252 hinfo->rates = per_cvt->rates;
1253 hinfo->formats = per_cvt->formats;
1254 hinfo->maxbps = per_cvt->maxbps;
1256 eld = &per_pin->sink_eld;
1257 /* Restrict capabilities by ELD if this isn't disabled */
1258 if (!static_hdmi_pcm && eld->eld_valid) {
1259 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1260 if (hinfo->channels_min > hinfo->channels_max ||
1261 !hinfo->rates || !hinfo->formats) {
1262 per_cvt->assigned = 0;
1264 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1270 /* Store the updated parameters */
1271 runtime->hw.channels_min = hinfo->channels_min;
1272 runtime->hw.channels_max = hinfo->channels_max;
1273 runtime->hw.formats = hinfo->formats;
1274 runtime->hw.rates = hinfo->rates;
1276 snd_pcm_hw_constraint_step(substream->runtime, 0,
1277 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1279 mutex_unlock(&spec->pcm_lock);
1284 * HDA/HDMI auto parsing
1286 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1288 struct hdmi_spec *spec = codec->spec;
1289 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1290 hda_nid_t pin_nid = per_pin->pin_nid;
1292 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1294 "HDMI: pin %d wcaps %#x does not support connection list\n",
1295 pin_nid, get_wcaps(codec, pin_nid));
1299 /* all the device entries on the same pin have the same conn list */
1300 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1302 HDA_MAX_CONNECTIONS);
1307 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1308 struct hdmi_spec_per_pin *per_pin)
1312 /* try the prefer PCM */
1313 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1314 return per_pin->pin_nid_idx;
1316 /* have a second try; check the "reserved area" over num_pins */
1317 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1318 if (!test_bit(i, &spec->pcm_bitmap))
1322 /* the last try; check the empty slots in pins */
1323 for (i = 0; i < spec->num_nids; i++) {
1324 if (!test_bit(i, &spec->pcm_bitmap))
1330 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1331 struct hdmi_spec_per_pin *per_pin)
1335 /* pcm already be attached to the pin */
1338 idx = hdmi_find_pcm_slot(spec, per_pin);
1341 per_pin->pcm_idx = idx;
1342 per_pin->pcm = get_hdmi_pcm(spec, idx);
1343 set_bit(idx, &spec->pcm_bitmap);
1346 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1347 struct hdmi_spec_per_pin *per_pin)
1351 /* pcm already be detached from the pin */
1354 idx = per_pin->pcm_idx;
1355 per_pin->pcm_idx = -1;
1356 per_pin->pcm = NULL;
1357 if (idx >= 0 && idx < spec->pcm_used)
1358 clear_bit(idx, &spec->pcm_bitmap);
1361 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1362 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1366 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1367 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1372 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1374 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1375 struct hdmi_spec_per_pin *per_pin)
1377 struct hda_codec *codec = per_pin->codec;
1378 struct hda_pcm *pcm;
1379 struct hda_pcm_stream *hinfo;
1380 struct snd_pcm_substream *substream;
1384 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1385 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1390 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1393 /* hdmi audio only uses playback and one substream */
1394 hinfo = pcm->stream;
1395 substream = pcm->pcm->streams[0].substream;
1397 per_pin->cvt_nid = hinfo->nid;
1399 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1400 if (mux_idx < per_pin->num_mux_nids) {
1401 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1403 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1404 AC_VERB_SET_CONNECT_SEL,
1407 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1409 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1410 if (substream->runtime)
1411 per_pin->channels = substream->runtime->channels;
1412 per_pin->setup = true;
1413 per_pin->mux_idx = mux_idx;
1415 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1418 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1419 struct hdmi_spec_per_pin *per_pin)
1421 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1422 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1424 per_pin->chmap_set = false;
1425 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1427 per_pin->setup = false;
1428 per_pin->channels = 0;
1431 /* update per_pin ELD from the given new ELD;
1432 * setup info frame and notification accordingly
1434 static void update_eld(struct hda_codec *codec,
1435 struct hdmi_spec_per_pin *per_pin,
1436 struct hdmi_eld *eld)
1438 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1439 struct hdmi_spec *spec = codec->spec;
1440 bool old_eld_valid = pin_eld->eld_valid;
1444 /* for monitor disconnection, save pcm_idx firstly */
1445 pcm_idx = per_pin->pcm_idx;
1446 if (spec->dyn_pcm_assign) {
1447 if (eld->eld_valid) {
1448 hdmi_attach_hda_pcm(spec, per_pin);
1449 hdmi_pcm_setup_pin(spec, per_pin);
1451 hdmi_pcm_reset_pin(spec, per_pin);
1452 hdmi_detach_hda_pcm(spec, per_pin);
1455 /* if pcm_idx == -1, it means this is in monitor connection event
1456 * we can get the correct pcm_idx now.
1459 pcm_idx = per_pin->pcm_idx;
1462 snd_hdmi_show_eld(codec, &eld->info);
1464 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1465 if (eld->eld_valid && pin_eld->eld_valid)
1466 if (pin_eld->eld_size != eld->eld_size ||
1467 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1468 eld->eld_size) != 0)
1471 pin_eld->monitor_present = eld->monitor_present;
1472 pin_eld->eld_valid = eld->eld_valid;
1473 pin_eld->eld_size = eld->eld_size;
1475 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1476 pin_eld->info = eld->info;
1479 * Re-setup pin and infoframe. This is needed e.g. when
1480 * - sink is first plugged-in
1481 * - transcoder can change during stream playback on Haswell
1482 * and this can make HW reset converter selection on a pin.
1484 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1485 pin_cvt_fixup(codec, per_pin, 0);
1486 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1489 if (eld_changed && pcm_idx >= 0)
1490 snd_ctl_notify(codec->card,
1491 SNDRV_CTL_EVENT_MASK_VALUE |
1492 SNDRV_CTL_EVENT_MASK_INFO,
1493 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1496 /* update ELD and jack state via HD-audio verbs */
1497 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1500 struct hda_jack_tbl *jack;
1501 struct hda_codec *codec = per_pin->codec;
1502 struct hdmi_spec *spec = codec->spec;
1503 struct hdmi_eld *eld = &spec->temp_eld;
1504 hda_nid_t pin_nid = per_pin->pin_nid;
1506 * Always execute a GetPinSense verb here, even when called from
1507 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1508 * response's PD bit is not the real PD value, but indicates that
1509 * the real PD value changed. An older version of the HD-audio
1510 * specification worked this way. Hence, we just ignore the data in
1511 * the unsolicited response to avoid custom WARs.
1515 bool do_repoll = false;
1517 present = snd_hda_pin_sense(codec, pin_nid);
1519 mutex_lock(&per_pin->lock);
1520 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1521 if (eld->monitor_present)
1522 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1524 eld->eld_valid = false;
1527 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1528 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1530 if (eld->eld_valid) {
1531 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1532 &eld->eld_size) < 0)
1533 eld->eld_valid = false;
1535 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1537 eld->eld_valid = false;
1539 if (!eld->eld_valid && repoll)
1544 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1546 update_eld(codec, per_pin, eld);
1548 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1550 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1552 jack->block_report = !ret;
1553 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ?
1554 AC_PINSENSE_PRESENCE : 0;
1556 mutex_unlock(&per_pin->lock);
1560 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1561 struct hdmi_spec_per_pin *per_pin)
1563 struct hdmi_spec *spec = codec->spec;
1564 struct snd_jack *jack = NULL;
1565 struct hda_jack_tbl *jack_tbl;
1567 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1568 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1569 * NULL even after snd_hda_jack_tbl_clear() is called to
1570 * free snd_jack. This may cause access invalid memory
1571 * when calling snd_jack_report
1573 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1574 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1575 else if (!spec->dyn_pcm_assign) {
1577 * jack tbl doesn't support DP MST
1578 * DP MST will use dyn_pcm_assign,
1579 * so DP MST will never come here
1581 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1583 jack = jack_tbl->jack;
1588 /* update ELD and jack state via audio component */
1589 static void sync_eld_via_acomp(struct hda_codec *codec,
1590 struct hdmi_spec_per_pin *per_pin)
1592 struct hdmi_spec *spec = codec->spec;
1593 struct hdmi_eld *eld = &spec->temp_eld;
1594 struct snd_jack *jack = NULL;
1597 mutex_lock(&per_pin->lock);
1598 eld->monitor_present = false;
1599 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1600 per_pin->dev_id, &eld->monitor_present,
1601 eld->eld_buffer, ELD_MAX_SIZE);
1603 size = min(size, ELD_MAX_SIZE);
1604 if (snd_hdmi_parse_eld(codec, &eld->info,
1605 eld->eld_buffer, size) < 0)
1610 eld->eld_valid = true;
1611 eld->eld_size = size;
1613 eld->eld_valid = false;
1617 /* pcm_idx >=0 before update_eld() means it is in monitor
1618 * disconnected event. Jack must be fetched before update_eld()
1620 jack = pin_idx_to_jack(codec, per_pin);
1621 update_eld(codec, per_pin, eld);
1623 jack = pin_idx_to_jack(codec, per_pin);
1626 snd_jack_report(jack,
1627 eld->monitor_present ? SND_JACK_AVOUT : 0);
1629 mutex_unlock(&per_pin->lock);
1632 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1634 struct hda_codec *codec = per_pin->codec;
1637 /* no temporary power up/down needed for component notifier */
1638 if (!codec_has_acomp(codec)) {
1639 ret = snd_hda_power_up_pm(codec);
1640 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1641 snd_hda_power_down_pm(codec);
1646 if (codec_has_acomp(codec)) {
1647 sync_eld_via_acomp(codec, per_pin);
1648 ret = false; /* don't call snd_hda_jack_report_sync() */
1650 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1653 if (!codec_has_acomp(codec))
1654 snd_hda_power_down_pm(codec);
1659 static void hdmi_repoll_eld(struct work_struct *work)
1661 struct hdmi_spec_per_pin *per_pin =
1662 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1663 struct hda_codec *codec = per_pin->codec;
1664 struct hdmi_spec *spec = codec->spec;
1665 struct hda_jack_tbl *jack;
1667 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1669 jack->jack_dirty = 1;
1671 if (per_pin->repoll_count++ > 6)
1672 per_pin->repoll_count = 0;
1674 mutex_lock(&spec->pcm_lock);
1675 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1676 snd_hda_jack_report_sync(per_pin->codec);
1677 mutex_unlock(&spec->pcm_lock);
1680 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1683 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1685 struct hdmi_spec *spec = codec->spec;
1686 unsigned int caps, config;
1688 struct hdmi_spec_per_pin *per_pin;
1692 caps = snd_hda_query_pin_caps(codec, pin_nid);
1693 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1697 * For DP MST audio, Configuration Default is the same for
1698 * all device entries on the same pin
1700 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1701 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1705 * To simplify the implementation, malloc all
1706 * the virtual pins in the initialization statically
1708 if (is_haswell_plus(codec)) {
1710 * On Intel platforms, device entries number is
1711 * changed dynamically. If there is a DP MST
1712 * hub connected, the device entries number is 3.
1713 * Otherwise, it is 1.
1714 * Here we manually set dev_num to 3, so that
1715 * we can initialize all the device entries when
1716 * bootup statically.
1720 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1721 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1723 * spec->dev_num is the maxinum number of device entries
1724 * among all the pins
1726 spec->dev_num = (spec->dev_num > dev_num) ?
1727 spec->dev_num : dev_num;
1730 * If the platform doesn't support DP MST,
1731 * manually set dev_num to 1. This means
1732 * the pin has only one device entry.
1738 for (i = 0; i < dev_num; i++) {
1739 pin_idx = spec->num_pins;
1740 per_pin = snd_array_new(&spec->pins);
1745 if (spec->dyn_pcm_assign) {
1746 per_pin->pcm = NULL;
1747 per_pin->pcm_idx = -1;
1749 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1750 per_pin->pcm_idx = pin_idx;
1752 per_pin->pin_nid = pin_nid;
1753 per_pin->pin_nid_idx = spec->num_nids;
1754 per_pin->dev_id = i;
1755 per_pin->non_pcm = false;
1756 snd_hda_set_dev_select(codec, pin_nid, i);
1757 if (is_haswell_plus(codec))
1758 intel_haswell_fixup_connect_list(codec, pin_nid);
1759 err = hdmi_read_pin_conn(codec, pin_idx);
1769 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1771 struct hdmi_spec *spec = codec->spec;
1772 struct hdmi_spec_per_cvt *per_cvt;
1776 chans = get_wcaps(codec, cvt_nid);
1777 chans = get_wcaps_channels(chans);
1779 per_cvt = snd_array_new(&spec->cvts);
1783 per_cvt->cvt_nid = cvt_nid;
1784 per_cvt->channels_min = 2;
1786 per_cvt->channels_max = chans;
1787 if (chans > spec->chmap.channels_max)
1788 spec->chmap.channels_max = chans;
1791 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1798 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1799 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1805 static int hdmi_parse_codec(struct hda_codec *codec)
1810 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1811 if (!nid || nodes < 0) {
1812 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1816 for (i = 0; i < nodes; i++, nid++) {
1820 caps = get_wcaps(codec, nid);
1821 type = get_wcaps_type(caps);
1823 if (!(caps & AC_WCAP_DIGITAL))
1827 case AC_WID_AUD_OUT:
1828 hdmi_add_cvt(codec, nid);
1831 hdmi_add_pin(codec, nid);
1841 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1843 struct hda_spdif_out *spdif;
1846 mutex_lock(&codec->spdif_mutex);
1847 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1848 /* Add sanity check to pass klockwork check.
1849 * This should never happen.
1851 if (WARN_ON(spdif == NULL)) {
1852 mutex_unlock(&codec->spdif_mutex);
1855 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1856 mutex_unlock(&codec->spdif_mutex);
1864 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1865 struct hda_codec *codec,
1866 unsigned int stream_tag,
1867 unsigned int format,
1868 struct snd_pcm_substream *substream)
1870 hda_nid_t cvt_nid = hinfo->nid;
1871 struct hdmi_spec *spec = codec->spec;
1873 struct hdmi_spec_per_pin *per_pin;
1875 struct snd_pcm_runtime *runtime = substream->runtime;
1880 mutex_lock(&spec->pcm_lock);
1881 pin_idx = hinfo_to_pin_index(codec, hinfo);
1882 if (spec->dyn_pcm_assign && pin_idx < 0) {
1883 /* when dyn_pcm_assign and pcm is not bound to a pin
1884 * skip pin setup and return 0 to make audio playback
1887 pin_cvt_fixup(codec, NULL, cvt_nid);
1888 snd_hda_codec_setup_stream(codec, cvt_nid,
1889 stream_tag, 0, format);
1893 if (snd_BUG_ON(pin_idx < 0)) {
1897 per_pin = get_pin(spec, pin_idx);
1898 pin_nid = per_pin->pin_nid;
1900 /* Verify pin:cvt selections to avoid silent audio after S3.
1901 * After S3, the audio driver restores pin:cvt selections
1902 * but this can happen before gfx is ready and such selection
1903 * is overlooked by HW. Thus multiple pins can share a same
1904 * default convertor and mute control will affect each other,
1905 * which can cause a resumed audio playback become silent
1908 pin_cvt_fixup(codec, per_pin, 0);
1910 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1911 /* Todo: add DP1.2 MST audio support later */
1912 if (codec_has_acomp(codec))
1913 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1916 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1917 mutex_lock(&per_pin->lock);
1918 per_pin->channels = substream->runtime->channels;
1919 per_pin->setup = true;
1921 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1922 mutex_unlock(&per_pin->lock);
1923 if (spec->dyn_pin_out) {
1924 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1925 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1926 snd_hda_codec_write(codec, pin_nid, 0,
1927 AC_VERB_SET_PIN_WIDGET_CONTROL,
1931 /* snd_hda_set_dev_select() has been called before */
1932 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1933 stream_tag, format);
1935 mutex_unlock(&spec->pcm_lock);
1939 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1940 struct hda_codec *codec,
1941 struct snd_pcm_substream *substream)
1943 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1947 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1948 struct hda_codec *codec,
1949 struct snd_pcm_substream *substream)
1951 struct hdmi_spec *spec = codec->spec;
1952 int cvt_idx, pin_idx, pcm_idx;
1953 struct hdmi_spec_per_cvt *per_cvt;
1954 struct hdmi_spec_per_pin *per_pin;
1958 mutex_lock(&spec->pcm_lock);
1960 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1961 if (snd_BUG_ON(pcm_idx < 0)) {
1965 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1966 if (snd_BUG_ON(cvt_idx < 0)) {
1970 per_cvt = get_cvt(spec, cvt_idx);
1971 snd_BUG_ON(!per_cvt->assigned);
1972 per_cvt->assigned = 0;
1975 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1976 clear_bit(pcm_idx, &spec->pcm_in_use);
1977 pin_idx = hinfo_to_pin_index(codec, hinfo);
1978 if (spec->dyn_pcm_assign && pin_idx < 0)
1981 if (snd_BUG_ON(pin_idx < 0)) {
1985 per_pin = get_pin(spec, pin_idx);
1987 if (spec->dyn_pin_out) {
1988 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1989 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1990 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1991 AC_VERB_SET_PIN_WIDGET_CONTROL,
1995 mutex_lock(&per_pin->lock);
1996 per_pin->chmap_set = false;
1997 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1999 per_pin->setup = false;
2000 per_pin->channels = 0;
2001 mutex_unlock(&per_pin->lock);
2005 mutex_unlock(&spec->pcm_lock);
2010 static const struct hda_pcm_ops generic_ops = {
2011 .open = hdmi_pcm_open,
2012 .close = hdmi_pcm_close,
2013 .prepare = generic_hdmi_playback_pcm_prepare,
2014 .cleanup = generic_hdmi_playback_pcm_cleanup,
2017 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2019 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2020 struct hdmi_spec *spec = codec->spec;
2021 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2026 return per_pin->sink_eld.info.spk_alloc;
2029 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2030 unsigned char *chmap)
2032 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2033 struct hdmi_spec *spec = codec->spec;
2034 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2036 /* chmap is already set to 0 in caller */
2040 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2043 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2044 unsigned char *chmap, int prepared)
2046 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2047 struct hdmi_spec *spec = codec->spec;
2048 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2052 mutex_lock(&per_pin->lock);
2053 per_pin->chmap_set = true;
2054 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2056 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2057 mutex_unlock(&per_pin->lock);
2060 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2062 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2063 struct hdmi_spec *spec = codec->spec;
2064 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2066 return per_pin ? true:false;
2069 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2071 struct hdmi_spec *spec = codec->spec;
2075 * for non-mst mode, pcm number is the same as before
2076 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2077 * dev_num is the device entry number in a pin
2080 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2081 struct hda_pcm *info;
2082 struct hda_pcm_stream *pstr;
2084 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2088 spec->pcm_rec[idx].pcm = info;
2090 info->pcm_type = HDA_PCM_TYPE_HDMI;
2091 info->own_chmap = true;
2093 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2094 pstr->substreams = 1;
2095 pstr->ops = generic_ops;
2096 /* pcm number is less than 16 */
2097 if (spec->pcm_used >= 16)
2099 /* other pstr fields are set in open */
2105 static void free_hdmi_jack_priv(struct snd_jack *jack)
2107 struct hdmi_pcm *pcm = jack->private_data;
2112 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2113 struct hdmi_spec *spec,
2117 struct snd_jack *jack;
2120 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2125 spec->pcm_rec[pcm_idx].jack = jack;
2126 jack->private_data = &spec->pcm_rec[pcm_idx];
2127 jack->private_free = free_hdmi_jack_priv;
2131 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2133 char hdmi_str[32] = "HDMI/DP";
2134 struct hdmi_spec *spec = codec->spec;
2135 struct hdmi_spec_per_pin *per_pin;
2136 struct hda_jack_tbl *jack;
2137 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2142 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2144 if (spec->dyn_pcm_assign)
2145 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2147 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2148 /* if !dyn_pcm_assign, it must be non-MST mode.
2149 * This means pcms and pins are statically mapped.
2150 * And pcm_idx is pin_idx.
2152 per_pin = get_pin(spec, pcm_idx);
2153 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2155 strncat(hdmi_str, " Phantom",
2156 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2157 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2161 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2164 /* assign jack->jack to pcm_rec[].jack to
2165 * align with dyn_pcm_assign mode
2167 spec->pcm_rec[pcm_idx].jack = jack->jack;
2171 static int generic_hdmi_build_controls(struct hda_codec *codec)
2173 struct hdmi_spec *spec = codec->spec;
2175 int pin_idx, pcm_idx;
2177 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2178 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2179 /* no PCM: mark this for skipping permanently */
2180 set_bit(pcm_idx, &spec->pcm_bitmap);
2184 err = generic_hdmi_build_jack(codec, pcm_idx);
2188 /* create the spdif for each pcm
2189 * pin will be bound when monitor is connected
2191 if (spec->dyn_pcm_assign)
2192 err = snd_hda_create_dig_out_ctls(codec,
2193 0, spec->cvt_nids[0],
2196 struct hdmi_spec_per_pin *per_pin =
2197 get_pin(spec, pcm_idx);
2198 err = snd_hda_create_dig_out_ctls(codec,
2200 per_pin->mux_nids[0],
2205 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2207 dev = get_pcm_rec(spec, pcm_idx)->device;
2208 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2209 /* add control for ELD Bytes */
2210 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2216 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2217 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2218 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2220 pin_eld->eld_valid = false;
2221 hdmi_present_sense(per_pin, 0);
2224 /* add channel maps */
2225 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2226 struct hda_pcm *pcm;
2228 pcm = get_pcm_rec(spec, pcm_idx);
2229 if (!pcm || !pcm->pcm)
2231 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2239 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2241 struct hdmi_spec *spec = codec->spec;
2244 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2245 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2247 per_pin->codec = codec;
2248 mutex_init(&per_pin->lock);
2249 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2250 eld_proc_new(per_pin, pin_idx);
2255 static int generic_hdmi_init(struct hda_codec *codec)
2257 struct hdmi_spec *spec = codec->spec;
2260 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2261 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2262 hda_nid_t pin_nid = per_pin->pin_nid;
2263 int dev_id = per_pin->dev_id;
2265 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2266 hdmi_init_pin(codec, pin_nid);
2267 if (!codec_has_acomp(codec))
2268 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2269 codec->jackpoll_interval > 0 ?
2270 jack_callback : NULL);
2275 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2277 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2278 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2281 static void hdmi_array_free(struct hdmi_spec *spec)
2283 snd_array_free(&spec->pins);
2284 snd_array_free(&spec->cvts);
2287 static void generic_spec_free(struct hda_codec *codec)
2289 struct hdmi_spec *spec = codec->spec;
2292 hdmi_array_free(spec);
2296 codec->dp_mst = false;
2299 static void generic_hdmi_free(struct hda_codec *codec)
2301 struct hdmi_spec *spec = codec->spec;
2302 int pin_idx, pcm_idx;
2304 if (codec_has_acomp(codec))
2305 snd_hdac_i915_register_notifier(NULL);
2307 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2308 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2309 cancel_delayed_work_sync(&per_pin->work);
2310 eld_proc_free(per_pin);
2313 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2314 if (spec->pcm_rec[pcm_idx].jack == NULL)
2316 if (spec->dyn_pcm_assign)
2317 snd_device_free(codec->card,
2318 spec->pcm_rec[pcm_idx].jack);
2320 spec->pcm_rec[pcm_idx].jack = NULL;
2323 generic_spec_free(codec);
2327 static int generic_hdmi_suspend(struct hda_codec *codec)
2329 struct hdmi_spec *spec = codec->spec;
2332 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2333 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2334 cancel_delayed_work_sync(&per_pin->work);
2339 static int generic_hdmi_resume(struct hda_codec *codec)
2341 struct hdmi_spec *spec = codec->spec;
2344 codec->patch_ops.init(codec);
2345 regcache_sync(codec->core.regmap);
2347 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2348 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2349 hdmi_present_sense(per_pin, 1);
2355 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2356 .init = generic_hdmi_init,
2357 .free = generic_hdmi_free,
2358 .build_pcms = generic_hdmi_build_pcms,
2359 .build_controls = generic_hdmi_build_controls,
2360 .unsol_event = hdmi_unsol_event,
2362 .suspend = generic_hdmi_suspend,
2363 .resume = generic_hdmi_resume,
2367 static const struct hdmi_ops generic_standard_hdmi_ops = {
2368 .pin_get_eld = snd_hdmi_get_eld,
2369 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2370 .pin_hbr_setup = hdmi_pin_hbr_setup,
2371 .setup_stream = hdmi_setup_stream,
2374 /* allocate codec->spec and assign/initialize generic parser ops */
2375 static int alloc_generic_hdmi(struct hda_codec *codec)
2377 struct hdmi_spec *spec;
2379 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2383 spec->ops = generic_standard_hdmi_ops;
2384 spec->dev_num = 1; /* initialize to 1 */
2385 mutex_init(&spec->pcm_lock);
2386 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2388 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2389 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2390 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2391 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2394 hdmi_array_init(spec, 4);
2396 codec->patch_ops = generic_hdmi_patch_ops;
2401 /* generic HDMI parser */
2402 static int patch_generic_hdmi(struct hda_codec *codec)
2406 err = alloc_generic_hdmi(codec);
2410 err = hdmi_parse_codec(codec);
2412 generic_spec_free(codec);
2416 generic_hdmi_init_per_pins(codec);
2421 * Intel codec parsers and helpers
2424 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2427 struct hdmi_spec *spec = codec->spec;
2431 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2432 if (nconns == spec->num_cvts &&
2433 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2436 /* override pins connection list */
2437 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2438 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2441 #define INTEL_VENDOR_NID 0x08
2442 #define INTEL_GLK_VENDOR_NID 0x0B
2443 #define INTEL_GET_VENDOR_VERB 0xf81
2444 #define INTEL_SET_VENDOR_VERB 0x781
2445 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2446 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2448 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2451 unsigned int vendor_param;
2452 struct hdmi_spec *spec = codec->spec;
2454 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2455 INTEL_GET_VENDOR_VERB, 0);
2456 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2459 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2460 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2461 INTEL_SET_VENDOR_VERB, vendor_param);
2462 if (vendor_param == -1)
2466 snd_hda_codec_update_widgets(codec);
2469 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2471 unsigned int vendor_param;
2472 struct hdmi_spec *spec = codec->spec;
2474 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2475 INTEL_GET_VENDOR_VERB, 0);
2476 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2479 /* enable DP1.2 mode */
2480 vendor_param |= INTEL_EN_DP12;
2481 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2482 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2483 INTEL_SET_VENDOR_VERB, vendor_param);
2486 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2487 * Otherwise you may get severe h/w communication errors.
2489 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2490 unsigned int power_state)
2492 if (power_state == AC_PWRST_D0) {
2493 intel_haswell_enable_all_pins(codec, false);
2494 intel_haswell_fixup_enable_dp12(codec);
2497 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2498 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2501 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2503 struct hda_codec *codec = audio_ptr;
2507 /* we assume only from port-B to port-D */
2508 if (port < 1 || port > 3)
2511 switch (codec->core.vendor_id) {
2512 case 0x80860054: /* ILK */
2513 case 0x80862804: /* ILK */
2514 case 0x80862882: /* VLV */
2515 pin_nid = port + 0x03;
2518 pin_nid = port + 0x04;
2522 /* skip notification during system suspend (but not in runtime PM);
2523 * the state will be updated at resume
2525 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2527 /* ditto during suspend/resume process itself */
2528 if (atomic_read(&(codec)->core.in_pm))
2531 snd_hdac_i915_set_bclk(&codec->bus->core);
2532 check_presence_and_report(codec, pin_nid, dev_id);
2535 /* register i915 component pin_eld_notify callback */
2536 static void register_i915_notifier(struct hda_codec *codec)
2538 struct hdmi_spec *spec = codec->spec;
2540 spec->use_acomp_notifier = true;
2541 spec->i915_audio_ops.audio_ptr = codec;
2542 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2543 * will call pin_eld_notify with using audio_ptr pointer
2544 * We need make sure audio_ptr is really setup
2547 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2548 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2551 /* setup_stream ops override for HSW+ */
2552 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2553 hda_nid_t pin_nid, u32 stream_tag, int format)
2555 haswell_verify_D0(codec, cvt_nid, pin_nid);
2556 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2559 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2560 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2561 struct hdmi_spec_per_pin *per_pin,
2565 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2566 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2568 intel_verify_pin_cvt_connect(codec, per_pin);
2569 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2570 per_pin->dev_id, per_pin->mux_idx);
2572 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2576 /* precondition and allocation for Intel codecs */
2577 static int alloc_intel_hdmi(struct hda_codec *codec)
2581 /* requires i915 binding */
2582 if (!codec->bus->core.audio_component) {
2583 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2587 err = alloc_generic_hdmi(codec);
2590 /* no need to handle unsol events */
2591 codec->patch_ops.unsol_event = NULL;
2595 /* parse and post-process for Intel codecs */
2596 static int parse_intel_hdmi(struct hda_codec *codec)
2598 int err, retries = 3;
2601 err = hdmi_parse_codec(codec);
2602 } while (err < 0 && retries--);
2605 generic_spec_free(codec);
2609 generic_hdmi_init_per_pins(codec);
2610 register_i915_notifier(codec);
2614 /* Intel Haswell and onwards; audio component with eld notifier */
2615 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2617 struct hdmi_spec *spec;
2620 err = alloc_intel_hdmi(codec);
2624 codec->dp_mst = true;
2625 spec->dyn_pcm_assign = true;
2626 spec->vendor_nid = vendor_nid;
2628 intel_haswell_enable_all_pins(codec, true);
2629 intel_haswell_fixup_enable_dp12(codec);
2631 /* For Haswell/Broadwell, the controller is also in the power well and
2632 * can cover the codec power request, and so need not set this flag.
2634 if (!is_haswell(codec) && !is_broadwell(codec))
2635 codec->core.link_power_control = 1;
2637 codec->patch_ops.set_power_state = haswell_set_power_state;
2638 codec->depop_delay = 0;
2639 codec->auto_runtime_pm = 1;
2641 spec->ops.setup_stream = i915_hsw_setup_stream;
2642 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2644 return parse_intel_hdmi(codec);
2647 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2649 return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2652 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2654 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2657 /* Intel Baytrail and Braswell; with eld notifier */
2658 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2660 struct hdmi_spec *spec;
2663 err = alloc_intel_hdmi(codec);
2668 /* For Valleyview/Cherryview, only the display codec is in the display
2669 * power well and can use link_power ops to request/release the power.
2671 codec->core.link_power_control = 1;
2673 codec->depop_delay = 0;
2674 codec->auto_runtime_pm = 1;
2676 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2678 return parse_intel_hdmi(codec);
2681 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2682 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2686 err = alloc_intel_hdmi(codec);
2689 return parse_intel_hdmi(codec);
2693 * Shared non-generic implementations
2696 static int simple_playback_build_pcms(struct hda_codec *codec)
2698 struct hdmi_spec *spec = codec->spec;
2699 struct hda_pcm *info;
2701 struct hda_pcm_stream *pstr;
2702 struct hdmi_spec_per_cvt *per_cvt;
2704 per_cvt = get_cvt(spec, 0);
2705 chans = get_wcaps(codec, per_cvt->cvt_nid);
2706 chans = get_wcaps_channels(chans);
2708 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2711 spec->pcm_rec[0].pcm = info;
2712 info->pcm_type = HDA_PCM_TYPE_HDMI;
2713 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2714 *pstr = spec->pcm_playback;
2715 pstr->nid = per_cvt->cvt_nid;
2716 if (pstr->channels_max <= 2 && chans && chans <= 16)
2717 pstr->channels_max = chans;
2722 /* unsolicited event for jack sensing */
2723 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2726 snd_hda_jack_set_dirty_all(codec);
2727 snd_hda_jack_report_sync(codec);
2730 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2731 * as long as spec->pins[] is set correctly
2733 #define simple_hdmi_build_jack generic_hdmi_build_jack
2735 static int simple_playback_build_controls(struct hda_codec *codec)
2737 struct hdmi_spec *spec = codec->spec;
2738 struct hdmi_spec_per_cvt *per_cvt;
2741 per_cvt = get_cvt(spec, 0);
2742 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2747 return simple_hdmi_build_jack(codec, 0);
2750 static int simple_playback_init(struct hda_codec *codec)
2752 struct hdmi_spec *spec = codec->spec;
2753 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2754 hda_nid_t pin = per_pin->pin_nid;
2756 snd_hda_codec_write(codec, pin, 0,
2757 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2758 /* some codecs require to unmute the pin */
2759 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2760 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2762 snd_hda_jack_detect_enable(codec, pin);
2766 static void simple_playback_free(struct hda_codec *codec)
2768 struct hdmi_spec *spec = codec->spec;
2770 hdmi_array_free(spec);
2775 * Nvidia specific implementations
2778 #define Nv_VERB_SET_Channel_Allocation 0xF79
2779 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2780 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2781 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2783 #define nvhdmi_master_con_nid_7x 0x04
2784 #define nvhdmi_master_pin_nid_7x 0x05
2786 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2787 /*front, rear, clfe, rear_surr */
2791 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2792 /* set audio protect on */
2793 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2794 /* enable digital output on pin widget */
2795 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2799 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2800 /* set audio protect on */
2801 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2802 /* enable digital output on pin widget */
2803 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2804 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2805 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2806 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2807 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2811 #ifdef LIMITED_RATE_FMT_SUPPORT
2812 /* support only the safe format and rate */
2813 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2814 #define SUPPORTED_MAXBPS 16
2815 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2817 /* support all rates and formats */
2818 #define SUPPORTED_RATES \
2819 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2820 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2821 SNDRV_PCM_RATE_192000)
2822 #define SUPPORTED_MAXBPS 24
2823 #define SUPPORTED_FORMATS \
2824 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2827 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2829 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2833 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2835 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2839 static const unsigned int channels_2_6_8[] = {
2843 static const unsigned int channels_2_8[] = {
2847 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2848 .count = ARRAY_SIZE(channels_2_6_8),
2849 .list = channels_2_6_8,
2853 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2854 .count = ARRAY_SIZE(channels_2_8),
2855 .list = channels_2_8,
2859 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2860 struct hda_codec *codec,
2861 struct snd_pcm_substream *substream)
2863 struct hdmi_spec *spec = codec->spec;
2864 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2866 switch (codec->preset->vendor_id) {
2871 hw_constraints_channels = &hw_constraints_2_8_channels;
2874 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2880 if (hw_constraints_channels != NULL) {
2881 snd_pcm_hw_constraint_list(substream->runtime, 0,
2882 SNDRV_PCM_HW_PARAM_CHANNELS,
2883 hw_constraints_channels);
2885 snd_pcm_hw_constraint_step(substream->runtime, 0,
2886 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2889 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2892 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2893 struct hda_codec *codec,
2894 struct snd_pcm_substream *substream)
2896 struct hdmi_spec *spec = codec->spec;
2897 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2900 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2901 struct hda_codec *codec,
2902 unsigned int stream_tag,
2903 unsigned int format,
2904 struct snd_pcm_substream *substream)
2906 struct hdmi_spec *spec = codec->spec;
2907 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2908 stream_tag, format, substream);
2911 static const struct hda_pcm_stream simple_pcm_playback = {
2916 .open = simple_playback_pcm_open,
2917 .close = simple_playback_pcm_close,
2918 .prepare = simple_playback_pcm_prepare
2922 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2923 .build_controls = simple_playback_build_controls,
2924 .build_pcms = simple_playback_build_pcms,
2925 .init = simple_playback_init,
2926 .free = simple_playback_free,
2927 .unsol_event = simple_hdmi_unsol_event,
2930 static int patch_simple_hdmi(struct hda_codec *codec,
2931 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2933 struct hdmi_spec *spec;
2934 struct hdmi_spec_per_cvt *per_cvt;
2935 struct hdmi_spec_per_pin *per_pin;
2937 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2942 hdmi_array_init(spec, 1);
2944 spec->multiout.num_dacs = 0; /* no analog */
2945 spec->multiout.max_channels = 2;
2946 spec->multiout.dig_out_nid = cvt_nid;
2949 per_pin = snd_array_new(&spec->pins);
2950 per_cvt = snd_array_new(&spec->cvts);
2951 if (!per_pin || !per_cvt) {
2952 simple_playback_free(codec);
2955 per_cvt->cvt_nid = cvt_nid;
2956 per_pin->pin_nid = pin_nid;
2957 spec->pcm_playback = simple_pcm_playback;
2959 codec->patch_ops = simple_hdmi_patch_ops;
2964 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2967 unsigned int chanmask;
2968 int chan = channels ? (channels - 1) : 1;
2987 /* Set the audio infoframe channel allocation and checksum fields. The
2988 * channel count is computed implicitly by the hardware. */
2989 snd_hda_codec_write(codec, 0x1, 0,
2990 Nv_VERB_SET_Channel_Allocation, chanmask);
2992 snd_hda_codec_write(codec, 0x1, 0,
2993 Nv_VERB_SET_Info_Frame_Checksum,
2994 (0x71 - chan - chanmask));
2997 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2998 struct hda_codec *codec,
2999 struct snd_pcm_substream *substream)
3001 struct hdmi_spec *spec = codec->spec;
3004 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3005 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3006 for (i = 0; i < 4; i++) {
3007 /* set the stream id */
3008 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3009 AC_VERB_SET_CHANNEL_STREAMID, 0);
3010 /* set the stream format */
3011 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3012 AC_VERB_SET_STREAM_FORMAT, 0);
3015 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3016 * streams are disabled. */
3017 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3019 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3022 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3023 struct hda_codec *codec,
3024 unsigned int stream_tag,
3025 unsigned int format,
3026 struct snd_pcm_substream *substream)
3029 unsigned int dataDCC2, channel_id;
3031 struct hdmi_spec *spec = codec->spec;
3032 struct hda_spdif_out *spdif;
3033 struct hdmi_spec_per_cvt *per_cvt;
3035 mutex_lock(&codec->spdif_mutex);
3036 per_cvt = get_cvt(spec, 0);
3037 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3039 chs = substream->runtime->channels;
3043 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3044 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3045 snd_hda_codec_write(codec,
3046 nvhdmi_master_con_nid_7x,
3048 AC_VERB_SET_DIGI_CONVERT_1,
3049 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3051 /* set the stream id */
3052 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3053 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3055 /* set the stream format */
3056 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3057 AC_VERB_SET_STREAM_FORMAT, format);
3059 /* turn on again (if needed) */
3060 /* enable and set the channel status audio/data flag */
3061 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3062 snd_hda_codec_write(codec,
3063 nvhdmi_master_con_nid_7x,
3065 AC_VERB_SET_DIGI_CONVERT_1,
3066 spdif->ctls & 0xff);
3067 snd_hda_codec_write(codec,
3068 nvhdmi_master_con_nid_7x,
3070 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3073 for (i = 0; i < 4; i++) {
3079 /* turn off SPDIF once;
3080 *otherwise the IEC958 bits won't be updated
3082 if (codec->spdif_status_reset &&
3083 (spdif->ctls & AC_DIG1_ENABLE))
3084 snd_hda_codec_write(codec,
3085 nvhdmi_con_nids_7x[i],
3087 AC_VERB_SET_DIGI_CONVERT_1,
3088 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3089 /* set the stream id */
3090 snd_hda_codec_write(codec,
3091 nvhdmi_con_nids_7x[i],
3093 AC_VERB_SET_CHANNEL_STREAMID,
3094 (stream_tag << 4) | channel_id);
3095 /* set the stream format */
3096 snd_hda_codec_write(codec,
3097 nvhdmi_con_nids_7x[i],
3099 AC_VERB_SET_STREAM_FORMAT,
3101 /* turn on again (if needed) */
3102 /* enable and set the channel status audio/data flag */
3103 if (codec->spdif_status_reset &&
3104 (spdif->ctls & AC_DIG1_ENABLE)) {
3105 snd_hda_codec_write(codec,
3106 nvhdmi_con_nids_7x[i],
3108 AC_VERB_SET_DIGI_CONVERT_1,
3109 spdif->ctls & 0xff);
3110 snd_hda_codec_write(codec,
3111 nvhdmi_con_nids_7x[i],
3113 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3117 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3119 mutex_unlock(&codec->spdif_mutex);
3123 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3127 .nid = nvhdmi_master_con_nid_7x,
3128 .rates = SUPPORTED_RATES,
3129 .maxbps = SUPPORTED_MAXBPS,
3130 .formats = SUPPORTED_FORMATS,
3132 .open = simple_playback_pcm_open,
3133 .close = nvhdmi_8ch_7x_pcm_close,
3134 .prepare = nvhdmi_8ch_7x_pcm_prepare
3138 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3140 struct hdmi_spec *spec;
3141 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3142 nvhdmi_master_pin_nid_7x);
3146 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3147 /* override the PCM rates, etc, as the codec doesn't give full list */
3149 spec->pcm_playback.rates = SUPPORTED_RATES;
3150 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3151 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3155 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3157 struct hdmi_spec *spec = codec->spec;
3158 int err = simple_playback_build_pcms(codec);
3160 struct hda_pcm *info = get_pcm_rec(spec, 0);
3161 info->own_chmap = true;
3166 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3168 struct hdmi_spec *spec = codec->spec;
3169 struct hda_pcm *info;
3170 struct snd_pcm_chmap *chmap;
3173 err = simple_playback_build_controls(codec);
3177 /* add channel maps */
3178 info = get_pcm_rec(spec, 0);
3179 err = snd_pcm_add_chmap_ctls(info->pcm,
3180 SNDRV_PCM_STREAM_PLAYBACK,
3181 snd_pcm_alt_chmaps, 8, 0, &chmap);
3184 switch (codec->preset->vendor_id) {
3189 chmap->channel_mask = (1U << 2) | (1U << 8);
3192 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3197 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3199 struct hdmi_spec *spec;
3200 int err = patch_nvhdmi_2ch(codec);
3204 spec->multiout.max_channels = 8;
3205 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3206 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3207 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3208 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3210 /* Initialize the audio infoframe channel mask and checksum to something
3212 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3218 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3222 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3223 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3225 if (cap->ca_index == 0x00 && channels == 2)
3226 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3228 /* If the speaker allocation matches the channel count, it is OK. */
3229 if (cap->channels != channels)
3232 /* all channels are remappable freely */
3233 return SNDRV_CTL_TLVT_CHMAP_VAR;
3236 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3237 int ca, int chs, unsigned char *map)
3239 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3245 static int patch_nvhdmi(struct hda_codec *codec)
3247 struct hdmi_spec *spec;
3250 err = patch_generic_hdmi(codec);
3255 spec->dyn_pin_out = true;
3257 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3258 nvhdmi_chmap_cea_alloc_validate_get_type;
3259 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3265 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3266 * accessed using vendor-defined verbs. These registers can be used for
3267 * interoperability between the HDA and HDMI drivers.
3270 /* Audio Function Group node */
3271 #define NVIDIA_AFG_NID 0x01
3274 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3275 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3276 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3277 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3278 * additional bit (at position 30) to signal the validity of the format.
3280 * | 31 | 30 | 29 16 | 15 0 |
3281 * +---------+-------+--------+--------+
3282 * | TRIGGER | VALID | UNUSED | FORMAT |
3283 * +-----------------------------------|
3285 * Note that for the trigger bit to take effect it needs to change value
3286 * (i.e. it needs to be toggled).
3288 #define NVIDIA_GET_SCRATCH0 0xfa6
3289 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3290 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3291 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3292 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3293 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3294 #define NVIDIA_SCRATCH_VALID (1 << 6)
3296 #define NVIDIA_GET_SCRATCH1 0xfab
3297 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3298 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3299 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3300 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3303 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3304 * the format is invalidated so that the HDMI codec can be disabled.
3306 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3310 /* bits [31:30] contain the trigger and valid bits */
3311 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3312 NVIDIA_GET_SCRATCH0, 0);
3313 value = (value >> 24) & 0xff;
3315 /* bits [15:0] are used to store the HDA format */
3316 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3317 NVIDIA_SET_SCRATCH0_BYTE0,
3318 (format >> 0) & 0xff);
3319 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3320 NVIDIA_SET_SCRATCH0_BYTE1,
3321 (format >> 8) & 0xff);
3323 /* bits [16:24] are unused */
3324 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3325 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3328 * Bit 30 signals that the data is valid and hence that HDMI audio can
3332 value &= ~NVIDIA_SCRATCH_VALID;
3334 value |= NVIDIA_SCRATCH_VALID;
3337 * Whenever the trigger bit is toggled, an interrupt is raised in the
3338 * HDMI codec. The HDMI driver will use that as trigger to update its
3341 value ^= NVIDIA_SCRATCH_TRIGGER;
3343 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3344 NVIDIA_SET_SCRATCH0_BYTE3, value);
3347 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3348 struct hda_codec *codec,
3349 unsigned int stream_tag,
3350 unsigned int format,
3351 struct snd_pcm_substream *substream)
3355 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3360 /* notify the HDMI codec of the format change */
3361 tegra_hdmi_set_format(codec, format);
3366 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3367 struct hda_codec *codec,
3368 struct snd_pcm_substream *substream)
3370 /* invalidate the format in the HDMI codec */
3371 tegra_hdmi_set_format(codec, 0);
3373 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3376 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3378 struct hdmi_spec *spec = codec->spec;
3381 for (i = 0; i < spec->num_pins; i++) {
3382 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3384 if (pcm->pcm_type == type)
3391 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3393 struct hda_pcm_stream *stream;
3394 struct hda_pcm *pcm;
3397 err = generic_hdmi_build_pcms(codec);
3401 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3406 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3407 * codec about format changes.
3409 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3410 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3411 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3416 static int patch_tegra_hdmi(struct hda_codec *codec)
3418 struct hdmi_spec *spec;
3421 err = patch_generic_hdmi(codec);
3425 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3427 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3428 nvhdmi_chmap_cea_alloc_validate_get_type;
3429 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3435 * ATI/AMD-specific implementations
3438 #define is_amdhdmi_rev3_or_later(codec) \
3439 ((codec)->core.vendor_id == 0x1002aa01 && \
3440 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3441 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3443 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3444 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3445 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3446 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3447 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3448 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3449 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3450 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3451 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3452 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3453 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3454 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3455 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3456 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3457 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3458 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3459 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3460 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3461 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3462 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3463 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3464 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3465 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3466 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3467 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3469 /* AMD specific HDA cvt verbs */
3470 #define ATI_VERB_SET_RAMP_RATE 0x770
3471 #define ATI_VERB_GET_RAMP_RATE 0xf70
3473 #define ATI_OUT_ENABLE 0x1
3475 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3476 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3478 #define ATI_HBR_CAPABLE 0x01
3479 #define ATI_HBR_ENABLE 0x10
3481 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3482 unsigned char *buf, int *eld_size)
3484 /* call hda_eld.c ATI/AMD-specific function */
3485 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3486 is_amdhdmi_rev3_or_later(codec));
3489 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3490 int active_channels, int conn_type)
3492 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3495 static int atihdmi_paired_swap_fc_lfe(int pos)
3498 * ATI/AMD have automatic FC/LFE swap built-in
3499 * when in pairwise mapping mode.
3503 /* see channel_allocations[].speakers[] */
3512 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3513 int ca, int chs, unsigned char *map)
3515 struct hdac_cea_channel_speaker_allocation *cap;
3518 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3520 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3521 for (i = 0; i < chs; ++i) {
3522 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3524 bool companion_ok = false;
3529 for (j = 0 + i % 2; j < 8; j += 2) {
3530 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3531 if (cap->speakers[chan_idx] == mask) {
3532 /* channel is in a supported position */
3535 if (i % 2 == 0 && i + 1 < chs) {
3536 /* even channel, check the odd companion */
3537 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3538 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3539 int comp_mask_act = cap->speakers[comp_chan_idx];
3541 if (comp_mask_req == comp_mask_act)
3542 companion_ok = true;
3554 i++; /* companion channel already checked */
3560 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3561 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3563 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3565 int ati_channel_setup = 0;
3570 if (!has_amd_full_remap_support(codec)) {
3571 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3573 /* In case this is an odd slot but without stream channel, do not
3574 * disable the slot since the corresponding even slot could have a
3575 * channel. In case neither have a channel, the slot pair will be
3576 * disabled when this function is called for the even slot. */
3577 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3580 hdmi_slot -= hdmi_slot % 2;
3582 if (stream_channel != 0xf)
3583 stream_channel -= stream_channel % 2;
3586 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3588 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3590 if (stream_channel != 0xf)
3591 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3593 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3596 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3597 hda_nid_t pin_nid, int asp_slot)
3599 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3600 bool was_odd = false;
3601 int ati_asp_slot = asp_slot;
3603 int ati_channel_setup;
3608 if (!has_amd_full_remap_support(codec)) {
3609 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3610 if (ati_asp_slot % 2 != 0) {
3616 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3618 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3620 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3623 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3626 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3627 struct hdac_chmap *chmap,
3628 struct hdac_cea_channel_speaker_allocation *cap,
3634 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3635 * we need to take that into account (a single channel may take 2
3636 * channel slots if we need to carry a silent channel next to it).
3637 * On Rev3+ AMD codecs this function is not used.
3641 /* We only produce even-numbered channel count TLVs */
3642 if ((channels % 2) != 0)
3645 for (c = 0; c < 7; c += 2) {
3646 if (cap->speakers[c] || cap->speakers[c+1])
3650 if (chanpairs * 2 != channels)
3653 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3656 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3657 struct hdac_cea_channel_speaker_allocation *cap,
3658 unsigned int *chmap, int channels)
3660 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3664 for (c = 7; c >= 0; c--) {
3665 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3666 int spk = cap->speakers[chan];
3668 /* add N/A channel if the companion channel is occupied */
3669 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3670 chmap[count++] = SNDRV_CHMAP_NA;
3675 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3678 WARN_ON(count != channels);
3681 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3684 int hbr_ctl, hbr_ctl_new;
3686 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3687 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3689 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3691 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3694 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3696 hbr_ctl == hbr_ctl_new ? "" : "new-",
3699 if (hbr_ctl != hbr_ctl_new)
3700 snd_hda_codec_write(codec, pin_nid, 0,
3701 ATI_VERB_SET_HBR_CONTROL,
3710 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3711 hda_nid_t pin_nid, u32 stream_tag, int format)
3714 if (is_amdhdmi_rev3_or_later(codec)) {
3715 int ramp_rate = 180; /* default as per AMD spec */
3716 /* disable ramp-up/down for non-pcm as per AMD spec */
3717 if (format & AC_FMT_TYPE_NON_PCM)
3720 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3723 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3727 static int atihdmi_init(struct hda_codec *codec)
3729 struct hdmi_spec *spec = codec->spec;
3732 err = generic_hdmi_init(codec);
3737 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3738 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3740 /* make sure downmix information in infoframe is zero */
3741 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3743 /* enable channel-wise remap mode if supported */
3744 if (has_amd_full_remap_support(codec))
3745 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3746 ATI_VERB_SET_MULTICHANNEL_MODE,
3747 ATI_MULTICHANNEL_MODE_SINGLE);
3753 static int patch_atihdmi(struct hda_codec *codec)
3755 struct hdmi_spec *spec;
3756 struct hdmi_spec_per_cvt *per_cvt;
3759 err = patch_generic_hdmi(codec);
3764 codec->patch_ops.init = atihdmi_init;
3768 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3769 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3770 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3771 spec->ops.setup_stream = atihdmi_setup_stream;
3773 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3774 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3776 if (!has_amd_full_remap_support(codec)) {
3777 /* override to ATI/AMD-specific versions with pairwise mapping */
3778 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3779 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3780 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3781 atihdmi_paired_cea_alloc_to_tlv_chmap;
3782 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3785 /* ATI/AMD converters do not advertise all of their capabilities */
3786 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3787 per_cvt = get_cvt(spec, cvt_idx);
3788 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3789 per_cvt->rates |= SUPPORTED_RATES;
3790 per_cvt->formats |= SUPPORTED_FORMATS;
3791 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3794 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3799 /* VIA HDMI Implementation */
3800 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3801 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3803 static int patch_via_hdmi(struct hda_codec *codec)
3805 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3811 static const struct hda_device_id snd_hda_id_hdmi[] = {
3812 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3813 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3814 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3815 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3816 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3817 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3818 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3819 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3820 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3821 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3822 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3823 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3824 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3825 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3826 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3827 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3828 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3829 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3830 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3831 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3832 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3833 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3834 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3835 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3836 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3837 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3838 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3839 /* 17 is known to be absent */
3840 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3841 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3842 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3843 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3844 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3845 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3846 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3847 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3848 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3849 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3850 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3851 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3852 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3853 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3854 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3855 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3856 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3857 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3858 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3859 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3860 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3861 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3862 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3863 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3864 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3865 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3866 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3867 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3868 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3869 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3870 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3871 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3872 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3873 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3874 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3875 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3876 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3877 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3878 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3879 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3880 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3881 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3882 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3883 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3884 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3885 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3886 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
3887 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
3888 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
3889 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
3890 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
3891 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3892 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3893 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3894 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3895 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3896 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3897 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3898 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3899 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3900 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3901 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3902 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3903 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3904 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3905 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3906 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3907 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3908 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3909 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
3910 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
3911 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
3912 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3913 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3914 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3915 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3916 /* special ID for generic HDMI */
3917 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3920 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3922 MODULE_LICENSE("GPL");
3923 MODULE_DESCRIPTION("HDMI HD-audio codec");
3924 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3925 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3926 MODULE_ALIAS("snd-hda-codec-atihdmi");
3928 static struct hda_codec_driver hdmi_driver = {
3929 .id = snd_hda_id_hdmi,
3932 module_hda_codec_driver(hdmi_driver);