sound/pci/rme9652/hdsp.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   3  *
   4  *      Copyright (c) 2002  Paul Davis
   5  *                          Marcus Andersson
   6  *                          Thomas Charbonnel
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <linux/math64.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/io.h>
  33 #include <linux/nospec.h>
  34
  35 #include <sound/core.h>
  36 #include <sound/control.h>
  37 #include <sound/pcm.h>
  38 #include <sound/info.h>
  39 #include <sound/asoundef.h>
  40 #include <sound/rawmidi.h>
  41 #include <sound/hwdep.h>
  42 #include <sound/initval.h>
  43 #include <sound/hdsp.h>
  44
  45 #include <asm/byteorder.h>
  46 #include <asm/current.h>
  47
  48 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  49 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  50 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  51
  52 module_param_array(index, int, NULL, 0444);
  53 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  54 module_param_array(id, charp, NULL, 0444);
  55 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  56 module_param_array(enable, bool, NULL, 0444);
  57 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  58 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  59 MODULE_DESCRIPTION("RME Hammerfall DSP");
  60 MODULE_LICENSE("GPL");
  61 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
  62                 "{RME HDSP-9652},"
  63                 "{RME HDSP-9632}}");
  64 /*(DEBLOBBED)*/
  65
  66 #define HDSP_MAX_CHANNELS        26
  67 #define HDSP_MAX_DS_CHANNELS     14
  68 #define HDSP_MAX_QS_CHANNELS     8
  69 #define DIGIFACE_SS_CHANNELS     26
  70 #define DIGIFACE_DS_CHANNELS     14
  71 #define MULTIFACE_SS_CHANNELS    18
  72 #define MULTIFACE_DS_CHANNELS    14
  73 #define H9652_SS_CHANNELS        26
  74 #define H9652_DS_CHANNELS        14
  75 /* This does not include possible Analog Extension Boards
  76    AEBs are detected at card initialization
  77 */
  78 #define H9632_SS_CHANNELS        12
  79 #define H9632_DS_CHANNELS        8
  80 #define H9632_QS_CHANNELS        4
  81 #define RPM_CHANNELS             6
  82
  83 /* Write registers. These are defined as byte-offsets from the iobase value.
  84  */
  85 #define HDSP_resetPointer               0
  86 #define HDSP_freqReg                    0
  87 #define HDSP_outputBufferAddress        32
  88 #define HDSP_inputBufferAddress         36
  89 #define HDSP_controlRegister            64
  90 #define HDSP_interruptConfirmation      96
  91 #define HDSP_outputEnable               128
  92 #define HDSP_control2Reg                256
  93 #define HDSP_midiDataOut0               352
  94 #define HDSP_midiDataOut1               356
  95 #define HDSP_fifoData                   368
  96 #define HDSP_inputEnable                384
  97
  98 /* Read registers. These are defined as byte-offsets from the iobase value
  99  */
 100
 101 #define HDSP_statusRegister    0
 102 #define HDSP_timecode        128
 103 #define HDSP_status2Register 192
 104 #define HDSP_midiDataIn0     360
 105 #define HDSP_midiDataIn1     364
 106 #define HDSP_midiStatusOut0  384
 107 #define HDSP_midiStatusOut1  388
 108 #define HDSP_midiStatusIn0   392
 109 #define HDSP_midiStatusIn1   396
 110 #define HDSP_fifoStatus      400
 111
 112 /* the meters are regular i/o-mapped registers, but offset
 113    considerably from the rest. the peak registers are reset
 114    when read; the least-significant 4 bits are full-scale counters;
 115    the actual peak value is in the most-significant 24 bits.
 116 */
 117
 118 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 119 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 120 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 121 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 122 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 123
 124
 125 /* This is for H9652 cards
 126    Peak values are read downward from the base
 127    Rms values are read upward
 128    There are rms values for the outputs too
 129    26*3 values are read in ss mode
 130    14*3 in ds mode, with no gap between values
 131 */
 132 #define HDSP_9652_peakBase      7164
 133 #define HDSP_9652_rmsBase       4096
 134
 135 /* c.f. the hdsp_9632_meters_t struct */
 136 #define HDSP_9632_metersBase    4096
 137
 138 #define HDSP_IO_EXTENT     7168
 139
 140 /* control2 register bits */
 141
 142 #define HDSP_TMS                0x01
 143 #define HDSP_TCK                0x02
 144 #define HDSP_TDI                0x04
 145 #define HDSP_JTAG               0x08
 146 #define HDSP_PWDN               0x10
 147 #define HDSP_PROGRAM            0x020
 148 #define HDSP_CONFIG_MODE_0      0x040
 149 #define HDSP_CONFIG_MODE_1      0x080
 150 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
 151 #define HDSP_BIGENDIAN_MODE     0x200
 152 #define HDSP_RD_MULTIPLE        0x400
 153 #define HDSP_9652_ENABLE_MIXER  0x800
 154 #define HDSP_S200               0x800
 155 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
 156 #define HDSP_CYCLIC_MODE        0x1000
 157 #define HDSP_TDO                0x10000000
 158
 159 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 160 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 161
 162 /* Control Register bits */
 163
 164 #define HDSP_Start                (1<<0)  /* start engine */
 165 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 166 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 167 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 168 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 169 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 170 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 171 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 172 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 173 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 174 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 175 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 176 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 177 #define HDSP_SyncRef2             (1<<13)
 178 #define HDSP_SPDIFInputSelect0    (1<<14)
 179 #define HDSP_SPDIFInputSelect1    (1<<15)
 180 #define HDSP_SyncRef0             (1<<16)
 181 #define HDSP_SyncRef1             (1<<17)
 182 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 183 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 184 #define HDSP_Midi0InterruptEnable (1<<22)
 185 #define HDSP_Midi1InterruptEnable (1<<23)
 186 #define HDSP_LineOut              (1<<24)
 187 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 188 #define HDSP_ADGain1              (1<<26)
 189 #define HDSP_DAGain0              (1<<27)
 190 #define HDSP_DAGain1              (1<<28)
 191 #define HDSP_PhoneGain0           (1<<29)
 192 #define HDSP_PhoneGain1           (1<<30)
 193 #define HDSP_QuadSpeed            (1<<31)
 194
 195 /* RPM uses some of the registers for special purposes */
 196 #define HDSP_RPM_Inp12            0x04A00
 197 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
 198 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
 199 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
 200 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
 201 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
 202
 203 #define HDSP_RPM_Inp34            0x32000
 204 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
 205 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
 206 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
 207 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
 208 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
 209
 210 #define HDSP_RPM_Bypass           0x01000
 211
 212 #define HDSP_RPM_Disconnect       0x00001
 213
 214 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 215 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 216 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 217 #define HDSP_ADGainLowGain     0
 218
 219 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 220 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 221 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 222 #define HDSP_DAGainMinus10dBV    0
 223
 224 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 225 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 226 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 227 #define HDSP_PhoneGainMinus12dB  0
 228
 229 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 230 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 231
 232 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 233 #define HDSP_SPDIFInputADAT1    0
 234 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 235 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 236 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 237
 238 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 239 #define HDSP_SyncRef_ADAT1       0
 240 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 241 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 242 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 243 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 244 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 245
 246 /* Sample Clock Sources */
 247
 248 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 249 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 250 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 251 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 252 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 253 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 254 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 255 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 256 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 257 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 258
 259 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 260
 261 #define HDSP_SYNC_FROM_WORD      0
 262 #define HDSP_SYNC_FROM_SPDIF     1
 263 #define HDSP_SYNC_FROM_ADAT1     2
 264 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 265 #define HDSP_SYNC_FROM_ADAT2     4
 266 #define HDSP_SYNC_FROM_ADAT3     5
 267
 268 /* SyncCheck status */
 269
 270 #define HDSP_SYNC_CHECK_NO_LOCK 0
 271 #define HDSP_SYNC_CHECK_LOCK    1
 272 #define HDSP_SYNC_CHECK_SYNC    2
 273
 274 /* AutoSync references - used by "autosync_ref" control switch */
 275
 276 #define HDSP_AUTOSYNC_FROM_WORD      0
 277 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 278 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 279 #define HDSP_AUTOSYNC_FROM_NONE      3
 280 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 281 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 282 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 283
 284 /* Possible sources of S/PDIF input */
 285
 286 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 287 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 288 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 289 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 290
 291 #define HDSP_Frequency32KHz    HDSP_Frequency0
 292 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 293 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 294 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 295 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 296 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 297 /* For H9632 cards */
 298 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 299 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 300 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 301 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
 302         return 104857600000000 / rate; // 100 MHz
 303         return 110100480000000 / rate; // 105 MHz
 304 */
 305 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
 306
 307 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 308 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 309
 310 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 311 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 312
 313 /* Status Register bits */
 314
 315 #define HDSP_audioIRQPending    (1<<0)
 316 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 317 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 318 #define HDSP_Lock1              (1<<2)
 319 #define HDSP_Lock0              (1<<3)
 320 #define HDSP_SPDIFSync          (1<<4)
 321 #define HDSP_TimecodeLock       (1<<5)
 322 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 323 #define HDSP_Sync2              (1<<16)
 324 #define HDSP_Sync1              (1<<17)
 325 #define HDSP_Sync0              (1<<18)
 326 #define HDSP_DoubleSpeedStatus  (1<<19)
 327 #define HDSP_ConfigError        (1<<20)
 328 #define HDSP_DllError           (1<<21)
 329 #define HDSP_spdifFrequency0    (1<<22)
 330 #define HDSP_spdifFrequency1    (1<<23)
 331 #define HDSP_spdifFrequency2    (1<<24)
 332 #define HDSP_SPDIFErrorFlag     (1<<25)
 333 #define HDSP_BufferID           (1<<26)
 334 #define HDSP_TimecodeSync       (1<<27)
 335 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 336 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 337 #define HDSP_midi0IRQPending    (1<<30)
 338 #define HDSP_midi1IRQPending    (1<<31)
 339
 340 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 341 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
 342                                       HDSP_spdifFrequency1|\
 343                                       HDSP_spdifFrequency2|\
 344                                       HDSP_spdifFrequency3)
 345
 346 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 347 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 348 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 349
 350 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 351 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 352 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 353
 354 /* This is for H9632 cards */
 355 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
 356                                      HDSP_spdifFrequency1|\
 357                                      HDSP_spdifFrequency2)
 358 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 359 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 360
 361 /* Status2 Register bits */
 362
 363 #define HDSP_version0     (1<<0)
 364 #define HDSP_version1     (1<<1)
 365 #define HDSP_version2     (1<<2)
 366 #define HDSP_wc_lock      (1<<3)
 367 #define HDSP_wc_sync      (1<<4)
 368 #define HDSP_inp_freq0    (1<<5)
 369 #define HDSP_inp_freq1    (1<<6)
 370 #define HDSP_inp_freq2    (1<<7)
 371 #define HDSP_SelSyncRef0  (1<<8)
 372 #define HDSP_SelSyncRef1  (1<<9)
 373 #define HDSP_SelSyncRef2  (1<<10)
 374
 375 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 376
 377 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 378 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 379 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 380 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 381 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 382 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 383 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 384 /* FIXME : more values for 9632 cards ? */
 385
 386 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 387 #define HDSP_SelSyncRef_ADAT1      0
 388 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 389 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 390 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 391 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 392 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 393
 394 /* Card state flags */
 395
 396 #define HDSP_InitializationComplete  (1<<0)
 397 #define HDSP_FirmwareLoaded          (1<<1)
 398 #define HDSP_FirmwareCached          (1<<2)
 399
 400 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 401
 402 #define HDSP_LONG_WAIT   5000
 403 #define HDSP_SHORT_WAIT  30
 404
 405 #define UNITY_GAIN                       32768
 406 #define MINUS_INFINITY_GAIN              0
 407
 408 /* the size of a substream (1 mono data stream) */
 409
 410 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 411 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 412
 413 /* the size of the area we need to allocate for DMA transfers. the
 414    size is the same regardless of the number of channels - the
 415    Multiface still uses the same memory area.
 416
 417    Note that we allocate 1 more channel than is apparently needed
 418    because the h/w seems to write 1 byte beyond the end of the last
 419    page. Sigh.
 420 */
 421
 422 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 423 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 424
 425 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
 426
 427 struct hdsp_9632_meters {
 428     u32 input_peak[16];
 429     u32 playback_peak[16];
 430     u32 output_peak[16];
 431     u32 xxx_peak[16];
 432     u32 padding[64];
 433     u32 input_rms_low[16];
 434     u32 playback_rms_low[16];
 435     u32 output_rms_low[16];
 436     u32 xxx_rms_low[16];
 437     u32 input_rms_high[16];
 438     u32 playback_rms_high[16];
 439     u32 output_rms_high[16];
 440     u32 xxx_rms_high[16];
 441 };
 442
 443 struct hdsp_midi {
 444     struct hdsp             *hdsp;
 445     int                      id;
 446     struct snd_rawmidi           *rmidi;
 447     struct snd_rawmidi_substream *input;
 448     struct snd_rawmidi_substream *output;
 449     char                     istimer; /* timer in use */
 450     struct timer_list        timer;
 451     spinlock_t               lock;
 452     int                      pending;
 453 };
 454
 455 struct hdsp {
 456         spinlock_t            lock;
 457         struct snd_pcm_substream *capture_substream;
 458         struct snd_pcm_substream *playback_substream;
 459         struct hdsp_midi      midi[2];
 460         struct tasklet_struct midi_tasklet;
 461         int                   use_midi_tasklet;
 462         int                   precise_ptr;
 463         u32                   control_register;      /* cached value */
 464         u32                   control2_register;     /* cached value */
 465         u32                   creg_spdif;
 466         u32                   creg_spdif_stream;
 467         int                   clock_source_locked;
 468         char                 *card_name;         /* digiface/multiface/rpm */
 469         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
 470         unsigned short        firmware_rev;
 471         unsigned short        state;                 /* stores state bits */
 472         const struct firmware *firmware;
 473         u32                  *fw_uploaded;
 474         size_t                period_bytes;          /* guess what this is */
 475         unsigned char         max_channels;
 476         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 477         unsigned char         ds_in_channels;
 478         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 479         unsigned char         qs_out_channels;
 480         unsigned char         ds_out_channels;
 481         unsigned char         ss_out_channels;
 482
 483         struct snd_dma_buffer capture_dma_buf;
 484         struct snd_dma_buffer playback_dma_buf;
 485         unsigned char        *capture_buffer;       /* suitably aligned address */
 486         unsigned char        *playback_buffer;      /* suitably aligned address */
 487
 488         pid_t                 capture_pid;
 489         pid_t                 playback_pid;
 490         int                   running;
 491         int                   system_sample_rate;
 492         char                 *channel_map;
 493         int                   dev;
 494         int                   irq;
 495         unsigned long         port;
 496         void __iomem         *iobase;
 497         struct snd_card *card;
 498         struct snd_pcm *pcm;
 499         struct snd_hwdep          *hwdep;
 500         struct pci_dev       *pci;
 501         struct snd_kcontrol *spdif_ctl;
 502         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 503         unsigned int          dds_value; /* last value written to freq register */
 504 };
 505
 506 /* These tables map the ALSA channels 1..N to the channels that we
 507    need to use in order to find the relevant channel buffer. RME
 508    refer to this kind of mapping as between "the ADAT channel and
 509    the DMA channel." We index it using the logical audio channel,
 510    and the value is the DMA channel (i.e. channel buffer number)
 511    where the data for that channel can be read/written from/to.
 512 */
 513
 514 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 515         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 516         18, 19, 20, 21, 22, 23, 24, 25
 517 };
 518
 519 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 520         /* Analog */
 521         0, 1, 2, 3, 4, 5, 6, 7,
 522         /* ADAT 2 */
 523         16, 17, 18, 19, 20, 21, 22, 23,
 524         /* SPDIF */
 525         24, 25,
 526         -1, -1, -1, -1, -1, -1, -1, -1
 527 };
 528
 529 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 530         /* ADAT channels are remapped */
 531         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 532         /* channels 12 and 13 are S/PDIF */
 533         24, 25,
 534         /* others don't exist */
 535         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 536 };
 537
 538 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 539         /* ADAT channels */
 540         0, 1, 2, 3, 4, 5, 6, 7,
 541         /* SPDIF */
 542         8, 9,
 543         /* Analog */
 544         10, 11,
 545         /* AO4S-192 and AI4S-192 extension boards */
 546         12, 13, 14, 15,
 547         /* others don't exist */
 548         -1, -1, -1, -1, -1, -1, -1, -1,
 549         -1, -1
 550 };
 551
 552 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 553         /* ADAT */
 554         1, 3, 5, 7,
 555         /* SPDIF */
 556         8, 9,
 557         /* Analog */
 558         10, 11,
 559         /* AO4S-192 and AI4S-192 extension boards */
 560         12, 13, 14, 15,
 561         /* others don't exist */
 562         -1, -1, -1, -1, -1, -1, -1, -1,
 563         -1, -1, -1, -1, -1, -1
 564 };
 565
 566 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 567         /* ADAT is disabled in this mode */
 568         /* SPDIF */
 569         8, 9,
 570         /* Analog */
 571         10, 11,
 572         /* AO4S-192 and AI4S-192 extension boards */
 573         12, 13, 14, 15,
 574         /* others don't exist */
 575         -1, -1, -1, -1, -1, -1, -1, -1,
 576         -1, -1, -1, -1, -1, -1, -1, -1,
 577         -1, -1
 578 };
 579
 580 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
 581 {
 582         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
 583         dmab->dev.dev = snd_dma_pci_data(pci);
 584         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
 585                                 size, dmab) < 0)
 586                 return -ENOMEM;
 587         return 0;
 588 }
 589
 590 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
 591 {
 592         if (dmab->area)
 593                 snd_dma_free_pages(dmab);
 594 }
 595
 596
 597 static const struct pci_device_id snd_hdsp_ids[] = {
 598         {
 599                 .vendor = PCI_VENDOR_ID_XILINX,
 600                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 601                 .subvendor = PCI_ANY_ID,
 602                 .subdevice = PCI_ANY_ID,
 603         }, /* RME Hammerfall-DSP */
 604         { 0, },
 605 };
 606
 607 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 608
 609 /* prototypes */
 610 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
 611 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
 612 static int snd_hdsp_enable_io (struct hdsp *hdsp);
 613 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
 614 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
 615 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
 616 static int hdsp_autosync_ref(struct hdsp *hdsp);
 617 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
 618 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
 619
 620 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
 621 {
 622         switch (hdsp->io_type) {
 623         case Multiface:
 624         case Digiface:
 625         case RPM:
 626         default:
 627                 if (hdsp->firmware_rev == 0xa)
 628                         return (64 * out) + (32 + (in));
 629                 else
 630                         return (52 * out) + (26 + (in));
 631         case H9632:
 632                 return (32 * out) + (16 + (in));
 633         case H9652:
 634                 return (52 * out) + (26 + (in));
 635         }
 636 }
 637
 638 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
 639 {
 640         switch (hdsp->io_type) {
 641         case Multiface:
 642         case Digiface:
 643         case RPM:
 644         default:
 645                 if (hdsp->firmware_rev == 0xa)
 646                         return (64 * out) + in;
 647                 else
 648                         return (52 * out) + in;
 649         case H9632:
 650                 return (32 * out) + in;
 651         case H9652:
 652                 return (52 * out) + in;
 653         }
 654 }
 655
 656 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
 657 {
 658         writel(val, hdsp->iobase + reg);
 659 }
 660
 661 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
 662 {
 663         return readl (hdsp->iobase + reg);
 664 }
 665
 666 static int hdsp_check_for_iobox (struct hdsp *hdsp)
 667 {
 668         int i;
 669
 670         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 671         for (i = 0; i < 500; i++) {
 672                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
 673                                         HDSP_ConfigError)) {
 674                         if (i) {
 675                                 dev_dbg(hdsp->card->dev,
 676                                         "IO box found after %d ms\n",
 677                                                 (20 * i));
 678                         }
 679                         return 0;
 680                 }
 681                 msleep(20);
 682         }
 683         dev_err(hdsp->card->dev, "no IO box connected!\n");
 684         hdsp->state &= ~HDSP_FirmwareLoaded;
 685         return -EIO;
 686 }
 687
 688 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
 689                                unsigned int delay)
 690 {
 691         unsigned int i;
 692
 693         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 694                 return 0;
 695
 696         for (i = 0; i != loops; ++i) {
 697                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
 698                         msleep(delay);
 699                 else {
 700                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
 701                                    i * delay);
 702                         return 0;
 703                 }
 704         }
 705
 706         dev_info(hdsp->card->dev, "no IO box connected!\n");
 707         hdsp->state &= ~HDSP_FirmwareLoaded;
 708         return -EIO;
 709 }
 710
 711 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
 712
 713         int i;
 714         unsigned long flags;
 715         const u32 *cache;
 716
 717         if (hdsp->fw_uploaded)
 718                 cache = hdsp->fw_uploaded;
 719         else {
 720                 if (!hdsp->firmware)
 721                         return -ENODEV;
 722                 cache = (u32 *)hdsp->firmware->data;
 723                 if (!cache)
 724                         return -ENODEV;
 725         }
 726
 727         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 728
 729                 dev_info(hdsp->card->dev, "loading firmware\n");
 730
 731                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 732                 hdsp_write (hdsp, HDSP_fifoData, 0);
 733
 734                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 735                         dev_info(hdsp->card->dev,
 736                                  "timeout waiting for download preparation\n");
 737                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 738                         return -EIO;
 739                 }
 740
 741                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 742
 743                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
 744                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
 745                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 746                                 dev_info(hdsp->card->dev,
 747                                          "timeout during firmware loading\n");
 748                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 749                                 return -EIO;
 750                         }
 751                 }
 752
 753                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
 754                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 755
 756                 ssleep(3);
 757 #ifdef SNDRV_BIG_ENDIAN
 758                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 759 #else
 760                 hdsp->control2_register = 0;
 761 #endif
 762                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 763                 dev_info(hdsp->card->dev, "finished firmware loading\n");
 764
 765         }
 766         if (hdsp->state & HDSP_InitializationComplete) {
 767                 dev_info(hdsp->card->dev,
 768                          "firmware loaded from cache, restoring defaults\n");
 769                 spin_lock_irqsave(&hdsp->lock, flags);
 770                 snd_hdsp_set_defaults(hdsp);
 771                 spin_unlock_irqrestore(&hdsp->lock, flags);
 772         }
 773
 774         hdsp->state |= HDSP_FirmwareLoaded;
 775
 776         return 0;
 777 }
 778
 779 static int hdsp_get_iobox_version (struct hdsp *hdsp)
 780 {
 781         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 782
 783                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 784                 hdsp_write(hdsp, HDSP_fifoData, 0);
 785
 786                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 787                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 788                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 789                 }
 790
 791                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
 792                 hdsp_write (hdsp, HDSP_fifoData, 0);
 793                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 794                         goto set_multi;
 795
 796                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 797                 hdsp_write(hdsp, HDSP_fifoData, 0);
 798                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 799                         hdsp->io_type = Digiface;
 800                         dev_info(hdsp->card->dev, "Digiface found\n");
 801                         return 0;
 802                 }
 803
 804                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 805                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 806                 hdsp_write(hdsp, HDSP_fifoData, 0);
 807                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
 808                         goto set_multi;
 809
 810                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 811                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 812                 hdsp_write(hdsp, HDSP_fifoData, 0);
 813                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 814                         goto set_multi;
 815
 816                 hdsp->io_type = RPM;
 817                 dev_info(hdsp->card->dev, "RPM found\n");
 818                 return 0;
 819         } else {
 820                 /* firmware was already loaded, get iobox type */
 821                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
 822                         hdsp->io_type = RPM;
 823                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
 824                         hdsp->io_type = Multiface;
 825                 else
 826                         hdsp->io_type = Digiface;
 827         }
 828         return 0;
 829
 830 set_multi:
 831         hdsp->io_type = Multiface;
 832         dev_info(hdsp->card->dev, "Multiface found\n");
 833         return 0;
 834 }
 835
 836
 837 static int hdsp_request_fw_loader(struct hdsp *hdsp);
 838
 839 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
 840 {
 841         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 842                 return 0;
 843         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 844                 hdsp->state &= ~HDSP_FirmwareLoaded;
 845                 if (! load_on_demand)
 846                         return -EIO;
 847                 dev_err(hdsp->card->dev, "firmware not present.\n");
 848                 /* try to load firmware */
 849                 if (! (hdsp->state & HDSP_FirmwareCached)) {
 850                         if (! hdsp_request_fw_loader(hdsp))
 851                                 return 0;
 852                         dev_err(hdsp->card->dev,
 853                                    "No firmware loaded nor cached, please upload firmware.\n");
 854                         return -EIO;
 855                 }
 856                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
 857                         dev_err(hdsp->card->dev,
 858                                    "Firmware loading from cache failed, please upload manually.\n");
 859                         return -EIO;
 860                 }
 861         }
 862         return 0;
 863 }
 864
 865
 866 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
 867 {
 868         int i;
 869
 870         /* the fifoStatus registers reports on how many words
 871            are available in the command FIFO.
 872         */
 873
 874         for (i = 0; i < timeout; i++) {
 875
 876                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 877                         return 0;
 878
 879                 /* not very friendly, but we only do this during a firmware
 880                    load and changing the mixer, so we just put up with it.
 881                 */
 882
 883                 udelay (100);
 884         }
 885
 886         dev_warn(hdsp->card->dev,
 887                  "wait for FIFO status <= %d failed after %d iterations\n",
 888                     count, timeout);
 889         return -1;
 890 }
 891
 892 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
 893 {
 894         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 895                 return 0;
 896
 897         return hdsp->mixer_matrix[addr];
 898 }
 899
 900 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
 901 {
 902         unsigned int ad;
 903
 904         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 905                 return -1;
 906
 907         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 908
 909                 /* from martin bjornsen:
 910
 911                    "You can only write dwords to the
 912                    mixer memory which contain two
 913                    mixer values in the low and high
 914                    word. So if you want to change
 915                    value 0 you have to read value 1
 916                    from the cache and write both to
 917                    the first dword in the mixer
 918                    memory."
 919                 */
 920
 921                 if (hdsp->io_type == H9632 && addr >= 512)
 922                         return 0;
 923
 924                 if (hdsp->io_type == H9652 && addr >= 1352)
 925                         return 0;
 926
 927                 hdsp->mixer_matrix[addr] = data;
 928
 929
 930                 /* `addr' addresses a 16-bit wide address, but
 931                    the address space accessed via hdsp_write
 932                    uses byte offsets. put another way, addr
 933                    varies from 0 to 1351, but to access the
 934                    corresponding memory location, we need
 935                    to access 0 to 2703 ...
 936                 */
 937                 ad = addr/2;
 938
 939                 hdsp_write (hdsp, 4096 + (ad*4),
 940                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 941                             hdsp->mixer_matrix[addr&0x7fe]);
 942
 943                 return 0;
 944
 945         } else {
 946
 947                 ad = (addr << 16) + data;
 948
 949                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
 950                         return -1;
 951
 952                 hdsp_write (hdsp, HDSP_fifoData, ad);
 953                 hdsp->mixer_matrix[addr] = data;
 954
 955         }
 956
 957         return 0;
 958 }
 959
 960 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
 961 {
 962         unsigned long flags;
 963         int ret = 1;
 964
 965         spin_lock_irqsave(&hdsp->lock, flags);
 966         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 967             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
 968                 ret = 0;
 969         spin_unlock_irqrestore(&hdsp->lock, flags);
 970         return ret;
 971 }
 972
 973 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
 974 {
 975         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 976         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 977
 978         /* For the 9632, the mask is different */
 979         if (hdsp->io_type == H9632)
 980                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
 981
 982         if (status & HDSP_SPDIFErrorFlag)
 983                 return 0;
 984
 985         switch (rate_bits) {
 986         case HDSP_spdifFrequency32KHz: return 32000;
 987         case HDSP_spdifFrequency44_1KHz: return 44100;
 988         case HDSP_spdifFrequency48KHz: return 48000;
 989         case HDSP_spdifFrequency64KHz: return 64000;
 990         case HDSP_spdifFrequency88_2KHz: return 88200;
 991         case HDSP_spdifFrequency96KHz: return 96000;
 992         case HDSP_spdifFrequency128KHz:
 993                 if (hdsp->io_type == H9632) return 128000;
 994                 break;
 995         case HDSP_spdifFrequency176_4KHz:
 996                 if (hdsp->io_type == H9632) return 176400;
 997                 break;
 998         case HDSP_spdifFrequency192KHz:
 999                 if (hdsp->io_type == H9632) return 192000;
1000                 break;
1001         default:
1002                 break;
1003         }
1004         dev_warn(hdsp->card->dev,
1005                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1006                  rate_bits, status);
1007         return 0;
1008 }
1009
1010 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1011 {
1012         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1013         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1014
1015         /* For the 9632 card, there seems to be no bit for indicating external
1016          * sample rate greater than 96kHz. The card reports the corresponding
1017          * single speed. So the best means seems to get spdif rate when
1018          * autosync reference is spdif */
1019         if (hdsp->io_type == H9632 &&
1020             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1021                  return hdsp_spdif_sample_rate(hdsp);
1022
1023         switch (rate_bits) {
1024         case HDSP_systemFrequency32:   return 32000;
1025         case HDSP_systemFrequency44_1: return 44100;
1026         case HDSP_systemFrequency48:   return 48000;
1027         case HDSP_systemFrequency64:   return 64000;
1028         case HDSP_systemFrequency88_2: return 88200;
1029         case HDSP_systemFrequency96:   return 96000;
1030         default:
1031                 return 0;
1032         }
1033 }
1034
1035 static void hdsp_compute_period_size(struct hdsp *hdsp)
1036 {
1037         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1038 }
1039
1040 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1041 {
1042         int position;
1043
1044         position = hdsp_read(hdsp, HDSP_statusRegister);
1045
1046         if (!hdsp->precise_ptr)
1047                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1048
1049         position &= HDSP_BufferPositionMask;
1050         position /= 4;
1051         position &= (hdsp->period_bytes/2) - 1;
1052         return position;
1053 }
1054
1055 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1056 {
1057         hdsp_write (hdsp, HDSP_resetPointer, 0);
1058         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1059                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1060                  * requires (?) to write again DDS value after a reset pointer
1061                  * (at least, it works like this) */
1062                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1063 }
1064
1065 static void hdsp_start_audio(struct hdsp *s)
1066 {
1067         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1068         hdsp_write(s, HDSP_controlRegister, s->control_register);
1069 }
1070
1071 static void hdsp_stop_audio(struct hdsp *s)
1072 {
1073         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1074         hdsp_write(s, HDSP_controlRegister, s->control_register);
1075 }
1076
1077 static void hdsp_silence_playback(struct hdsp *hdsp)
1078 {
1079         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1080 }
1081
1082 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1083 {
1084         int n;
1085
1086         spin_lock_irq(&s->lock);
1087
1088         frames >>= 7;
1089         n = 0;
1090         while (frames) {
1091                 n++;
1092                 frames >>= 1;
1093         }
1094
1095         s->control_register &= ~HDSP_LatencyMask;
1096         s->control_register |= hdsp_encode_latency(n);
1097
1098         hdsp_write(s, HDSP_controlRegister, s->control_register);
1099
1100         hdsp_compute_period_size(s);
1101
1102         spin_unlock_irq(&s->lock);
1103
1104         return 0;
1105 }
1106
1107 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1108 {
1109         u64 n;
1110
1111         if (rate >= 112000)
1112                 rate /= 4;
1113         else if (rate >= 56000)
1114                 rate /= 2;
1115
1116         n = DDS_NUMERATOR;
1117         n = div_u64(n, rate);
1118         /* n should be less than 2^32 for being written to FREQ register */
1119         snd_BUG_ON(n >> 32);
1120         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1121            value to write it after a reset */
1122         hdsp->dds_value = n;
1123         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1124 }
1125
1126 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1127 {
1128         int reject_if_open = 0;
1129         int current_rate;
1130         int rate_bits;
1131
1132         /* ASSUMPTION: hdsp->lock is either held, or
1133            there is no need for it (e.g. during module
1134            initialization).
1135         */
1136
1137         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1138                 if (called_internally) {
1139                         /* request from ctl or card initialization */
1140                         dev_err(hdsp->card->dev,
1141                                 "device is not running as a clock master: cannot set sample rate.\n");
1142                         return -1;
1143                 } else {
1144                         /* hw_param request while in AutoSync mode */
1145                         int external_freq = hdsp_external_sample_rate(hdsp);
1146                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1147
1148                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1149                                 dev_info(hdsp->card->dev,
1150                                          "Detected ADAT in double speed mode\n");
1151                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1152                                 dev_info(hdsp->card->dev,
1153                                          "Detected ADAT in quad speed mode\n");
1154                         else if (rate != external_freq) {
1155                                 dev_info(hdsp->card->dev,
1156                                          "No AutoSync source for requested rate\n");
1157                                 return -1;
1158                         }
1159                 }
1160         }
1161
1162         current_rate = hdsp->system_sample_rate;
1163
1164         /* Changing from a "single speed" to a "double speed" rate is
1165            not allowed if any substreams are open. This is because
1166            such a change causes a shift in the location of
1167            the DMA buffers and a reduction in the number of available
1168            buffers.
1169
1170            Note that a similar but essentially insoluble problem
1171            exists for externally-driven rate changes. All we can do
1172            is to flag rate changes in the read/write routines.  */
1173
1174         if (rate > 96000 && hdsp->io_type != H9632)
1175                 return -EINVAL;
1176
1177         switch (rate) {
1178         case 32000:
1179                 if (current_rate > 48000)
1180                         reject_if_open = 1;
1181                 rate_bits = HDSP_Frequency32KHz;
1182                 break;
1183         case 44100:
1184                 if (current_rate > 48000)
1185                         reject_if_open = 1;
1186                 rate_bits = HDSP_Frequency44_1KHz;
1187                 break;
1188         case 48000:
1189                 if (current_rate > 48000)
1190                         reject_if_open = 1;
1191                 rate_bits = HDSP_Frequency48KHz;
1192                 break;
1193         case 64000:
1194                 if (current_rate <= 48000 || current_rate > 96000)
1195                         reject_if_open = 1;
1196                 rate_bits = HDSP_Frequency64KHz;
1197                 break;
1198         case 88200:
1199                 if (current_rate <= 48000 || current_rate > 96000)
1200                         reject_if_open = 1;
1201                 rate_bits = HDSP_Frequency88_2KHz;
1202                 break;
1203         case 96000:
1204                 if (current_rate <= 48000 || current_rate > 96000)
1205                         reject_if_open = 1;
1206                 rate_bits = HDSP_Frequency96KHz;
1207                 break;
1208         case 128000:
1209                 if (current_rate < 128000)
1210                         reject_if_open = 1;
1211                 rate_bits = HDSP_Frequency128KHz;
1212                 break;
1213         case 176400:
1214                 if (current_rate < 128000)
1215                         reject_if_open = 1;
1216                 rate_bits = HDSP_Frequency176_4KHz;
1217                 break;
1218         case 192000:
1219                 if (current_rate < 128000)
1220                         reject_if_open = 1;
1221                 rate_bits = HDSP_Frequency192KHz;
1222                 break;
1223         default:
1224                 return -EINVAL;
1225         }
1226
1227         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1228                 dev_warn(hdsp->card->dev,
1229                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1230                             hdsp->capture_pid,
1231                             hdsp->playback_pid);
1232                 return -EBUSY;
1233         }
1234
1235         hdsp->control_register &= ~HDSP_FrequencyMask;
1236         hdsp->control_register |= rate_bits;
1237         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1238
1239         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1240         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1241                 hdsp_set_dds_value(hdsp, rate);
1242
1243         if (rate >= 128000) {
1244                 hdsp->channel_map = channel_map_H9632_qs;
1245         } else if (rate > 48000) {
1246                 if (hdsp->io_type == H9632)
1247                         hdsp->channel_map = channel_map_H9632_ds;
1248                 else
1249                         hdsp->channel_map = channel_map_ds;
1250         } else {
1251                 switch (hdsp->io_type) {
1252                 case RPM:
1253                 case Multiface:
1254                         hdsp->channel_map = channel_map_mf_ss;
1255                         break;
1256                 case Digiface:
1257                 case H9652:
1258                         hdsp->channel_map = channel_map_df_ss;
1259                         break;
1260                 case H9632:
1261                         hdsp->channel_map = channel_map_H9632_ss;
1262                         break;
1263                 default:
1264                         /* should never happen */
1265                         break;
1266                 }
1267         }
1268
1269         hdsp->system_sample_rate = rate;
1270
1271         return 0;
1272 }
1273
1274 /*----------------------------------------------------------------------------
1275    MIDI
1276   ----------------------------------------------------------------------------*/
1277
1278 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1279 {
1280         /* the hardware already does the relevant bit-mask with 0xff */
1281         if (id)
1282                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1283         else
1284                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1285 }
1286
1287 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1288 {
1289         /* the hardware already does the relevant bit-mask with 0xff */
1290         if (id)
1291                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1292         else
1293                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1294 }
1295
1296 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1297 {
1298         if (id)
1299                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1300         else
1301                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1302 }
1303
1304 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1305 {
1306         int fifo_bytes_used;
1307
1308         if (id)
1309                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1310         else
1311                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1312
1313         if (fifo_bytes_used < 128)
1314                 return  128 - fifo_bytes_used;
1315         else
1316                 return 0;
1317 }
1318
1319 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1320 {
1321         while (snd_hdsp_midi_input_available (hdsp, id))
1322                 snd_hdsp_midi_read_byte (hdsp, id);
1323 }
1324
1325 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1326 {
1327         unsigned long flags;
1328         int n_pending;
1329         int to_write;
1330         int i;
1331         unsigned char buf[128];
1332
1333         /* Output is not interrupt driven */
1334
1335         spin_lock_irqsave (&hmidi->lock, flags);
1336         if (hmidi->output) {
1337                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1338                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1339                                 if (n_pending > (int)sizeof (buf))
1340                                         n_pending = sizeof (buf);
1341
1342                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1343                                         for (i = 0; i < to_write; ++i)
1344                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1345                                 }
1346                         }
1347                 }
1348         }
1349         spin_unlock_irqrestore (&hmidi->lock, flags);
1350         return 0;
1351 }
1352
1353 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1354 {
1355         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1356         unsigned long flags;
1357         int n_pending;
1358         int i;
1359
1360         spin_lock_irqsave (&hmidi->lock, flags);
1361         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1362                 if (hmidi->input) {
1363                         if (n_pending > (int)sizeof (buf))
1364                                 n_pending = sizeof (buf);
1365                         for (i = 0; i < n_pending; ++i)
1366                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1367                         if (n_pending)
1368                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1369                 } else {
1370                         /* flush the MIDI input FIFO */
1371                         while (--n_pending)
1372                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1373                 }
1374         }
1375         hmidi->pending = 0;
1376         if (hmidi->id)
1377                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1378         else
1379                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1380         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1381         spin_unlock_irqrestore (&hmidi->lock, flags);
1382         return snd_hdsp_midi_output_write (hmidi);
1383 }
1384
1385 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1386 {
1387         struct hdsp *hdsp;
1388         struct hdsp_midi *hmidi;
1389         unsigned long flags;
1390         u32 ie;
1391
1392         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1393         hdsp = hmidi->hdsp;
1394         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1395         spin_lock_irqsave (&hdsp->lock, flags);
1396         if (up) {
1397                 if (!(hdsp->control_register & ie)) {
1398                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1399                         hdsp->control_register |= ie;
1400                 }
1401         } else {
1402                 hdsp->control_register &= ~ie;
1403                 tasklet_kill(&hdsp->midi_tasklet);
1404         }
1405
1406         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1407         spin_unlock_irqrestore (&hdsp->lock, flags);
1408 }
1409
1410 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1411 {
1412         struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1413         unsigned long flags;
1414
1415         snd_hdsp_midi_output_write(hmidi);
1416         spin_lock_irqsave (&hmidi->lock, flags);
1417
1418         /* this does not bump hmidi->istimer, because the
1419            kernel automatically removed the timer when it
1420            expired, and we are now adding it back, thus
1421            leaving istimer wherever it was set before.
1422         */
1423
1424         if (hmidi->istimer)
1425                 mod_timer(&hmidi->timer, 1 + jiffies);
1426
1427         spin_unlock_irqrestore (&hmidi->lock, flags);
1428 }
1429
1430 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1431 {
1432         struct hdsp_midi *hmidi;
1433         unsigned long flags;
1434
1435         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1436         spin_lock_irqsave (&hmidi->lock, flags);
1437         if (up) {
1438                 if (!hmidi->istimer) {
1439                         timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1440                                     0);
1441                         mod_timer(&hmidi->timer, 1 + jiffies);
1442                         hmidi->istimer++;
1443                 }
1444         } else {
1445                 if (hmidi->istimer && --hmidi->istimer <= 0)
1446                         del_timer (&hmidi->timer);
1447         }
1448         spin_unlock_irqrestore (&hmidi->lock, flags);
1449         if (up)
1450                 snd_hdsp_midi_output_write(hmidi);
1451 }
1452
1453 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1454 {
1455         struct hdsp_midi *hmidi;
1456
1457         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1458         spin_lock_irq (&hmidi->lock);
1459         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1460         hmidi->input = substream;
1461         spin_unlock_irq (&hmidi->lock);
1462
1463         return 0;
1464 }
1465
1466 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1467 {
1468         struct hdsp_midi *hmidi;
1469
1470         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1471         spin_lock_irq (&hmidi->lock);
1472         hmidi->output = substream;
1473         spin_unlock_irq (&hmidi->lock);
1474
1475         return 0;
1476 }
1477
1478 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1479 {
1480         struct hdsp_midi *hmidi;
1481
1482         snd_hdsp_midi_input_trigger (substream, 0);
1483
1484         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1485         spin_lock_irq (&hmidi->lock);
1486         hmidi->input = NULL;
1487         spin_unlock_irq (&hmidi->lock);
1488
1489         return 0;
1490 }
1491
1492 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1493 {
1494         struct hdsp_midi *hmidi;
1495
1496         snd_hdsp_midi_output_trigger (substream, 0);
1497
1498         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1499         spin_lock_irq (&hmidi->lock);
1500         hmidi->output = NULL;
1501         spin_unlock_irq (&hmidi->lock);
1502
1503         return 0;
1504 }
1505
1506 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1507 {
1508         .open =         snd_hdsp_midi_output_open,
1509         .close =        snd_hdsp_midi_output_close,
1510         .trigger =      snd_hdsp_midi_output_trigger,
1511 };
1512
1513 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1514 {
1515         .open =         snd_hdsp_midi_input_open,
1516         .close =        snd_hdsp_midi_input_close,
1517         .trigger =      snd_hdsp_midi_input_trigger,
1518 };
1519
1520 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1521 {
1522         char buf[40];
1523
1524         hdsp->midi[id].id = id;
1525         hdsp->midi[id].rmidi = NULL;
1526         hdsp->midi[id].input = NULL;
1527         hdsp->midi[id].output = NULL;
1528         hdsp->midi[id].hdsp = hdsp;
1529         hdsp->midi[id].istimer = 0;
1530         hdsp->midi[id].pending = 0;
1531         spin_lock_init (&hdsp->midi[id].lock);
1532
1533         snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1534         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1535                 return -1;
1536
1537         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1538         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1539
1540         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1541         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1542
1543         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1544                 SNDRV_RAWMIDI_INFO_INPUT |
1545                 SNDRV_RAWMIDI_INFO_DUPLEX;
1546
1547         return 0;
1548 }
1549
1550 /*-----------------------------------------------------------------------------
1551   Control Interface
1552   ----------------------------------------------------------------------------*/
1553
1554 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1555 {
1556         u32 val = 0;
1557         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1558         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1559         if (val & HDSP_SPDIFProfessional)
1560                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1561         else
1562                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1563         return val;
1564 }
1565
1566 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1567 {
1568         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1569                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1570         if (val & HDSP_SPDIFProfessional)
1571                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1572         else
1573                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1574 }
1575
1576 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1577 {
1578         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1579         uinfo->count = 1;
1580         return 0;
1581 }
1582
1583 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1584 {
1585         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1586
1587         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1588         return 0;
1589 }
1590
1591 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1592 {
1593         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1594         int change;
1595         u32 val;
1596
1597         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1598         spin_lock_irq(&hdsp->lock);
1599         change = val != hdsp->creg_spdif;
1600         hdsp->creg_spdif = val;
1601         spin_unlock_irq(&hdsp->lock);
1602         return change;
1603 }
1604
1605 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1606 {
1607         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1608         uinfo->count = 1;
1609         return 0;
1610 }
1611
1612 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1613 {
1614         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1615
1616         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1617         return 0;
1618 }
1619
1620 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1621 {
1622         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1623         int change;
1624         u32 val;
1625
1626         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1627         spin_lock_irq(&hdsp->lock);
1628         change = val != hdsp->creg_spdif_stream;
1629         hdsp->creg_spdif_stream = val;
1630         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1631         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1632         spin_unlock_irq(&hdsp->lock);
1633         return change;
1634 }
1635
1636 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1637 {
1638         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1639         uinfo->count = 1;
1640         return 0;
1641 }
1642
1643 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1644 {
1645         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1646         return 0;
1647 }
1648
1649 #define HDSP_SPDIF_IN(xname, xindex) \
1650 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1651   .name = xname, \
1652   .index = xindex, \
1653   .info = snd_hdsp_info_spdif_in, \
1654   .get = snd_hdsp_get_spdif_in, \
1655   .put = snd_hdsp_put_spdif_in }
1656
1657 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1658 {
1659         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1660 }
1661
1662 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1663 {
1664         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1665         hdsp->control_register |= hdsp_encode_spdif_in(in);
1666         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1667         return 0;
1668 }
1669
1670 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1671 {
1672         static const char * const texts[4] = {
1673                 "Optical", "Coaxial", "Internal", "AES"
1674         };
1675         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1676
1677         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1678                                  texts);
1679 }
1680
1681 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1682 {
1683         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1684
1685         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1686         return 0;
1687 }
1688
1689 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1690 {
1691         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1692         int change;
1693         unsigned int val;
1694
1695         if (!snd_hdsp_use_is_exclusive(hdsp))
1696                 return -EBUSY;
1697         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1698         spin_lock_irq(&hdsp->lock);
1699         change = val != hdsp_spdif_in(hdsp);
1700         if (change)
1701                 hdsp_set_spdif_input(hdsp, val);
1702         spin_unlock_irq(&hdsp->lock);
1703         return change;
1704 }
1705
1706 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1707 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1708         .name = xname, \
1709         .private_value = xindex, \
1710         .info = snd_hdsp_info_toggle_setting, \
1711         .get = snd_hdsp_get_toggle_setting, \
1712         .put = snd_hdsp_put_toggle_setting \
1713 }
1714
1715 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1716 {
1717         return (hdsp->control_register & regmask) ? 1 : 0;
1718 }
1719
1720 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1721 {
1722         if (out)
1723                 hdsp->control_register |= regmask;
1724         else
1725                 hdsp->control_register &= ~regmask;
1726         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1727
1728         return 0;
1729 }
1730
1731 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1732
1733 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1734                 struct snd_ctl_elem_value *ucontrol)
1735 {
1736         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1737         u32 regmask = kcontrol->private_value;
1738
1739         spin_lock_irq(&hdsp->lock);
1740         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1741         spin_unlock_irq(&hdsp->lock);
1742         return 0;
1743 }
1744
1745 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1746                 struct snd_ctl_elem_value *ucontrol)
1747 {
1748         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1749         u32 regmask = kcontrol->private_value;
1750         int change;
1751         unsigned int val;
1752
1753         if (!snd_hdsp_use_is_exclusive(hdsp))
1754                 return -EBUSY;
1755         val = ucontrol->value.integer.value[0] & 1;
1756         spin_lock_irq(&hdsp->lock);
1757         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1758         if (change)
1759                 hdsp_set_toggle_setting(hdsp, regmask, val);
1760         spin_unlock_irq(&hdsp->lock);
1761         return change;
1762 }
1763
1764 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1765 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1766   .name = xname, \
1767   .index = xindex, \
1768   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1769   .info = snd_hdsp_info_spdif_sample_rate, \
1770   .get = snd_hdsp_get_spdif_sample_rate \
1771 }
1772
1773 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1774 {
1775         static const char * const texts[] = {
1776                 "32000", "44100", "48000", "64000", "88200", "96000",
1777                 "None", "128000", "176400", "192000"
1778         };
1779         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1780
1781         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1782                                  texts);
1783 }
1784
1785 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1786 {
1787         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1788
1789         switch (hdsp_spdif_sample_rate(hdsp)) {
1790         case 32000:
1791                 ucontrol->value.enumerated.item[0] = 0;
1792                 break;
1793         case 44100:
1794                 ucontrol->value.enumerated.item[0] = 1;
1795                 break;
1796         case 48000:
1797                 ucontrol->value.enumerated.item[0] = 2;
1798                 break;
1799         case 64000:
1800                 ucontrol->value.enumerated.item[0] = 3;
1801                 break;
1802         case 88200:
1803                 ucontrol->value.enumerated.item[0] = 4;
1804                 break;
1805         case 96000:
1806                 ucontrol->value.enumerated.item[0] = 5;
1807                 break;
1808         case 128000:
1809                 ucontrol->value.enumerated.item[0] = 7;
1810                 break;
1811         case 176400:
1812                 ucontrol->value.enumerated.item[0] = 8;
1813                 break;
1814         case 192000:
1815                 ucontrol->value.enumerated.item[0] = 9;
1816                 break;
1817         default:
1818                 ucontrol->value.enumerated.item[0] = 6;
1819         }
1820         return 0;
1821 }
1822
1823 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1824 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1825   .name = xname, \
1826   .index = xindex, \
1827   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1828   .info = snd_hdsp_info_system_sample_rate, \
1829   .get = snd_hdsp_get_system_sample_rate \
1830 }
1831
1832 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1833 {
1834         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1835         uinfo->count = 1;
1836         return 0;
1837 }
1838
1839 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1840 {
1841         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1842
1843         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1844         return 0;
1845 }
1846
1847 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1848 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1849   .name = xname, \
1850   .index = xindex, \
1851   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1852   .info = snd_hdsp_info_autosync_sample_rate, \
1853   .get = snd_hdsp_get_autosync_sample_rate \
1854 }
1855
1856 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1857 {
1858         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1859         static const char * const texts[] = {
1860                 "32000", "44100", "48000", "64000", "88200", "96000",
1861                 "None", "128000", "176400", "192000"
1862         };
1863
1864         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1865                                  texts);
1866 }
1867
1868 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1869 {
1870         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1871
1872         switch (hdsp_external_sample_rate(hdsp)) {
1873         case 32000:
1874                 ucontrol->value.enumerated.item[0] = 0;
1875                 break;
1876         case 44100:
1877                 ucontrol->value.enumerated.item[0] = 1;
1878                 break;
1879         case 48000:
1880                 ucontrol->value.enumerated.item[0] = 2;
1881                 break;
1882         case 64000:
1883                 ucontrol->value.enumerated.item[0] = 3;
1884                 break;
1885         case 88200:
1886                 ucontrol->value.enumerated.item[0] = 4;
1887                 break;
1888         case 96000:
1889                 ucontrol->value.enumerated.item[0] = 5;
1890                 break;
1891         case 128000:
1892                 ucontrol->value.enumerated.item[0] = 7;
1893                 break;
1894         case 176400:
1895                 ucontrol->value.enumerated.item[0] = 8;
1896                 break;
1897         case 192000:
1898                 ucontrol->value.enumerated.item[0] = 9;
1899                 break;
1900         default:
1901                 ucontrol->value.enumerated.item[0] = 6;
1902         }
1903         return 0;
1904 }
1905
1906 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1907 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1908   .name = xname, \
1909   .index = xindex, \
1910   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1911   .info = snd_hdsp_info_system_clock_mode, \
1912   .get = snd_hdsp_get_system_clock_mode \
1913 }
1914
1915 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1916 {
1917         if (hdsp->control_register & HDSP_ClockModeMaster)
1918                 return 0;
1919         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1920                         return 0;
1921         return 1;
1922 }
1923
1924 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1925 {
1926         static const char * const texts[] = {"Master", "Slave" };
1927
1928         return snd_ctl_enum_info(uinfo, 1, 2, texts);
1929 }
1930
1931 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1932 {
1933         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1934
1935         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1936         return 0;
1937 }
1938
1939 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1940 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1941   .name = xname, \
1942   .index = xindex, \
1943   .info = snd_hdsp_info_clock_source, \
1944   .get = snd_hdsp_get_clock_source, \
1945   .put = snd_hdsp_put_clock_source \
1946 }
1947
1948 static int hdsp_clock_source(struct hdsp *hdsp)
1949 {
1950         if (hdsp->control_register & HDSP_ClockModeMaster) {
1951                 switch (hdsp->system_sample_rate) {
1952                 case 32000:
1953                         return 1;
1954                 case 44100:
1955                         return 2;
1956                 case 48000:
1957                         return 3;
1958                 case 64000:
1959                         return 4;
1960                 case 88200:
1961                         return 5;
1962                 case 96000:
1963                         return 6;
1964                 case 128000:
1965                         return 7;
1966                 case 176400:
1967                         return 8;
1968                 case 192000:
1969                         return 9;
1970                 default:
1971                         return 3;
1972                 }
1973         } else {
1974                 return 0;
1975         }
1976 }
1977
1978 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1979 {
1980         int rate;
1981         switch (mode) {
1982         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1983                 if (hdsp_external_sample_rate(hdsp) != 0) {
1984                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1985                         hdsp->control_register &= ~HDSP_ClockModeMaster;
1986                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1987                         return 0;
1988                     }
1989                 }
1990                 return -1;
1991         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1992                 rate = 32000;
1993                 break;
1994         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1995                 rate = 44100;
1996                 break;
1997         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1998                 rate = 48000;
1999                 break;
2000         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2001                 rate = 64000;
2002                 break;
2003         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2004                 rate = 88200;
2005                 break;
2006         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2007                 rate = 96000;
2008                 break;
2009         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2010                 rate = 128000;
2011                 break;
2012         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2013                 rate = 176400;
2014                 break;
2015         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2016                 rate = 192000;
2017                 break;
2018         default:
2019                 rate = 48000;
2020         }
2021         hdsp->control_register |= HDSP_ClockModeMaster;
2022         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2023         hdsp_set_rate(hdsp, rate, 1);
2024         return 0;
2025 }
2026
2027 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2028 {
2029         static const char * const texts[] = {
2030                 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2031                 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2032                 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2033                 "Internal 192.0 KHz"
2034         };
2035         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2036
2037         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2038                                  texts);
2039 }
2040
2041 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2042 {
2043         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2044
2045         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2046         return 0;
2047 }
2048
2049 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2050 {
2051         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2052         int change;
2053         int val;
2054
2055         if (!snd_hdsp_use_is_exclusive(hdsp))
2056                 return -EBUSY;
2057         val = ucontrol->value.enumerated.item[0];
2058         if (val < 0) val = 0;
2059         if (hdsp->io_type == H9632) {
2060                 if (val > 9)
2061                         val = 9;
2062         } else {
2063                 if (val > 6)
2064                         val = 6;
2065         }
2066         spin_lock_irq(&hdsp->lock);
2067         if (val != hdsp_clock_source(hdsp))
2068                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2069         else
2070                 change = 0;
2071         spin_unlock_irq(&hdsp->lock);
2072         return change;
2073 }
2074
2075 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2076
2077 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2078 {
2079         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2080
2081         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2082         return 0;
2083 }
2084
2085 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2086 {
2087         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2088         int change;
2089
2090         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2091         if (change)
2092                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2093         return change;
2094 }
2095
2096 #define HDSP_DA_GAIN(xname, xindex) \
2097 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2098   .name = xname, \
2099   .index = xindex, \
2100   .info = snd_hdsp_info_da_gain, \
2101   .get = snd_hdsp_get_da_gain, \
2102   .put = snd_hdsp_put_da_gain \
2103 }
2104
2105 static int hdsp_da_gain(struct hdsp *hdsp)
2106 {
2107         switch (hdsp->control_register & HDSP_DAGainMask) {
2108         case HDSP_DAGainHighGain:
2109                 return 0;
2110         case HDSP_DAGainPlus4dBu:
2111                 return 1;
2112         case HDSP_DAGainMinus10dBV:
2113                 return 2;
2114         default:
2115                 return 1;
2116         }
2117 }
2118
2119 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2120 {
2121         hdsp->control_register &= ~HDSP_DAGainMask;
2122         switch (mode) {
2123         case 0:
2124                 hdsp->control_register |= HDSP_DAGainHighGain;
2125                 break;
2126         case 1:
2127                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2128                 break;
2129         case 2:
2130                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2131                 break;
2132         default:
2133                 return -1;
2134
2135         }
2136         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2137         return 0;
2138 }
2139
2140 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2141 {
2142         static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2143
2144         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2145 }
2146
2147 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2148 {
2149         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2150
2151         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2152         return 0;
2153 }
2154
2155 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2156 {
2157         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2158         int change;
2159         int val;
2160
2161         if (!snd_hdsp_use_is_exclusive(hdsp))
2162                 return -EBUSY;
2163         val = ucontrol->value.enumerated.item[0];
2164         if (val < 0) val = 0;
2165         if (val > 2) val = 2;
2166         spin_lock_irq(&hdsp->lock);
2167         if (val != hdsp_da_gain(hdsp))
2168                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2169         else
2170                 change = 0;
2171         spin_unlock_irq(&hdsp->lock);
2172         return change;
2173 }
2174
2175 #define HDSP_AD_GAIN(xname, xindex) \
2176 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2177   .name = xname, \
2178   .index = xindex, \
2179   .info = snd_hdsp_info_ad_gain, \
2180   .get = snd_hdsp_get_ad_gain, \
2181   .put = snd_hdsp_put_ad_gain \
2182 }
2183
2184 static int hdsp_ad_gain(struct hdsp *hdsp)
2185 {
2186         switch (hdsp->control_register & HDSP_ADGainMask) {
2187         case HDSP_ADGainMinus10dBV:
2188                 return 0;
2189         case HDSP_ADGainPlus4dBu:
2190                 return 1;
2191         case HDSP_ADGainLowGain:
2192                 return 2;
2193         default:
2194                 return 1;
2195         }
2196 }
2197
2198 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2199 {
2200         hdsp->control_register &= ~HDSP_ADGainMask;
2201         switch (mode) {
2202         case 0:
2203                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2204                 break;
2205         case 1:
2206                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2207                 break;
2208         case 2:
2209                 hdsp->control_register |= HDSP_ADGainLowGain;
2210                 break;
2211         default:
2212                 return -1;
2213
2214         }
2215         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2216         return 0;
2217 }
2218
2219 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2220 {
2221         static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2222
2223         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2224 }
2225
2226 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2227 {
2228         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2229
2230         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2231         return 0;
2232 }
2233
2234 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2235 {
2236         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2237         int change;
2238         int val;
2239
2240         if (!snd_hdsp_use_is_exclusive(hdsp))
2241                 return -EBUSY;
2242         val = ucontrol->value.enumerated.item[0];
2243         if (val < 0) val = 0;
2244         if (val > 2) val = 2;
2245         spin_lock_irq(&hdsp->lock);
2246         if (val != hdsp_ad_gain(hdsp))
2247                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2248         else
2249                 change = 0;
2250         spin_unlock_irq(&hdsp->lock);
2251         return change;
2252 }
2253
2254 #define HDSP_PHONE_GAIN(xname, xindex) \
2255 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2256   .name = xname, \
2257   .index = xindex, \
2258   .info = snd_hdsp_info_phone_gain, \
2259   .get = snd_hdsp_get_phone_gain, \
2260   .put = snd_hdsp_put_phone_gain \
2261 }
2262
2263 static int hdsp_phone_gain(struct hdsp *hdsp)
2264 {
2265         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2266         case HDSP_PhoneGain0dB:
2267                 return 0;
2268         case HDSP_PhoneGainMinus6dB:
2269                 return 1;
2270         case HDSP_PhoneGainMinus12dB:
2271                 return 2;
2272         default:
2273                 return 0;
2274         }
2275 }
2276
2277 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2278 {
2279         hdsp->control_register &= ~HDSP_PhoneGainMask;
2280         switch (mode) {
2281         case 0:
2282                 hdsp->control_register |= HDSP_PhoneGain0dB;
2283                 break;
2284         case 1:
2285                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2286                 break;
2287         case 2:
2288                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2289                 break;
2290         default:
2291                 return -1;
2292
2293         }
2294         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2295         return 0;
2296 }
2297
2298 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2299 {
2300         static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2301
2302         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2303 }
2304
2305 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2306 {
2307         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2308
2309         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2310         return 0;
2311 }
2312
2313 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2314 {
2315         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2316         int change;
2317         int val;
2318
2319         if (!snd_hdsp_use_is_exclusive(hdsp))
2320                 return -EBUSY;
2321         val = ucontrol->value.enumerated.item[0];
2322         if (val < 0) val = 0;
2323         if (val > 2) val = 2;
2324         spin_lock_irq(&hdsp->lock);
2325         if (val != hdsp_phone_gain(hdsp))
2326                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2327         else
2328                 change = 0;
2329         spin_unlock_irq(&hdsp->lock);
2330         return change;
2331 }
2332
2333 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2334 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2335   .name = xname, \
2336   .index = xindex, \
2337   .info = snd_hdsp_info_pref_sync_ref, \
2338   .get = snd_hdsp_get_pref_sync_ref, \
2339   .put = snd_hdsp_put_pref_sync_ref \
2340 }
2341
2342 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2343 {
2344         /* Notice that this looks at the requested sync source,
2345            not the one actually in use.
2346         */
2347
2348         switch (hdsp->control_register & HDSP_SyncRefMask) {
2349         case HDSP_SyncRef_ADAT1:
2350                 return HDSP_SYNC_FROM_ADAT1;
2351         case HDSP_SyncRef_ADAT2:
2352                 return HDSP_SYNC_FROM_ADAT2;
2353         case HDSP_SyncRef_ADAT3:
2354                 return HDSP_SYNC_FROM_ADAT3;
2355         case HDSP_SyncRef_SPDIF:
2356                 return HDSP_SYNC_FROM_SPDIF;
2357         case HDSP_SyncRef_WORD:
2358                 return HDSP_SYNC_FROM_WORD;
2359         case HDSP_SyncRef_ADAT_SYNC:
2360                 return HDSP_SYNC_FROM_ADAT_SYNC;
2361         default:
2362                 return HDSP_SYNC_FROM_WORD;
2363         }
2364         return 0;
2365 }
2366
2367 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2368 {
2369         hdsp->control_register &= ~HDSP_SyncRefMask;
2370         switch (pref) {
2371         case HDSP_SYNC_FROM_ADAT1:
2372                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2373                 break;
2374         case HDSP_SYNC_FROM_ADAT2:
2375                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2376                 break;
2377         case HDSP_SYNC_FROM_ADAT3:
2378                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2379                 break;
2380         case HDSP_SYNC_FROM_SPDIF:
2381                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2382                 break;
2383         case HDSP_SYNC_FROM_WORD:
2384                 hdsp->control_register |= HDSP_SyncRef_WORD;
2385                 break;
2386         case HDSP_SYNC_FROM_ADAT_SYNC:
2387                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2388                 break;
2389         default:
2390                 return -1;
2391         }
2392         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2393         return 0;
2394 }
2395
2396 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2397 {
2398         static const char * const texts[] = {
2399                 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2400         };
2401         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2402         int num_items;
2403
2404         switch (hdsp->io_type) {
2405         case Digiface:
2406         case H9652:
2407                 num_items = 6;
2408                 break;
2409         case Multiface:
2410                 num_items = 4;
2411                 break;
2412         case H9632:
2413                 num_items = 3;
2414                 break;
2415         default:
2416                 return -EINVAL;
2417         }
2418
2419         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2420 }
2421
2422 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2423 {
2424         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2425
2426         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2427         return 0;
2428 }
2429
2430 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2431 {
2432         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2433         int change, max;
2434         unsigned int val;
2435
2436         if (!snd_hdsp_use_is_exclusive(hdsp))
2437                 return -EBUSY;
2438
2439         switch (hdsp->io_type) {
2440         case Digiface:
2441         case H9652:
2442                 max = 6;
2443                 break;
2444         case Multiface:
2445                 max = 4;
2446                 break;
2447         case H9632:
2448                 max = 3;
2449                 break;
2450         default:
2451                 return -EIO;
2452         }
2453
2454         val = ucontrol->value.enumerated.item[0] % max;
2455         spin_lock_irq(&hdsp->lock);
2456         change = (int)val != hdsp_pref_sync_ref(hdsp);
2457         hdsp_set_pref_sync_ref(hdsp, val);
2458         spin_unlock_irq(&hdsp->lock);
2459         return change;
2460 }
2461
2462 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2463 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2464   .name = xname, \
2465   .index = xindex, \
2466   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2467   .info = snd_hdsp_info_autosync_ref, \
2468   .get = snd_hdsp_get_autosync_ref, \
2469 }
2470
2471 static int hdsp_autosync_ref(struct hdsp *hdsp)
2472 {
2473         /* This looks at the autosync selected sync reference */
2474         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2475
2476         switch (status2 & HDSP_SelSyncRefMask) {
2477         case HDSP_SelSyncRef_WORD:
2478                 return HDSP_AUTOSYNC_FROM_WORD;
2479         case HDSP_SelSyncRef_ADAT_SYNC:
2480                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2481         case HDSP_SelSyncRef_SPDIF:
2482                 return HDSP_AUTOSYNC_FROM_SPDIF;
2483         case HDSP_SelSyncRefMask:
2484                 return HDSP_AUTOSYNC_FROM_NONE;
2485         case HDSP_SelSyncRef_ADAT1:
2486                 return HDSP_AUTOSYNC_FROM_ADAT1;
2487         case HDSP_SelSyncRef_ADAT2:
2488                 return HDSP_AUTOSYNC_FROM_ADAT2;
2489         case HDSP_SelSyncRef_ADAT3:
2490                 return HDSP_AUTOSYNC_FROM_ADAT3;
2491         default:
2492                 return HDSP_AUTOSYNC_FROM_WORD;
2493         }
2494         return 0;
2495 }
2496
2497 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2498 {
2499         static const char * const texts[] = {
2500                 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2501         };
2502
2503         return snd_ctl_enum_info(uinfo, 1, 7, texts);
2504 }
2505
2506 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2507 {
2508         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2509
2510         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2511         return 0;
2512 }
2513
2514 #define HDSP_PRECISE_POINTER(xname, xindex) \
2515 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2516   .name = xname, \
2517   .index = xindex, \
2518   .info = snd_hdsp_info_precise_pointer, \
2519   .get = snd_hdsp_get_precise_pointer, \
2520   .put = snd_hdsp_put_precise_pointer \
2521 }
2522
2523 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2524 {
2525         if (precise)
2526                 hdsp->precise_ptr = 1;
2527         else
2528                 hdsp->precise_ptr = 0;
2529         return 0;
2530 }
2531
2532 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2533
2534 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2535 {
2536         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2537
2538         spin_lock_irq(&hdsp->lock);
2539         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2540         spin_unlock_irq(&hdsp->lock);
2541         return 0;
2542 }
2543
2544 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2545 {
2546         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2547         int change;
2548         unsigned int val;
2549
2550         if (!snd_hdsp_use_is_exclusive(hdsp))
2551                 return -EBUSY;
2552         val = ucontrol->value.integer.value[0] & 1;
2553         spin_lock_irq(&hdsp->lock);
2554         change = (int)val != hdsp->precise_ptr;
2555         hdsp_set_precise_pointer(hdsp, val);
2556         spin_unlock_irq(&hdsp->lock);
2557         return change;
2558 }
2559
2560 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2561 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2562   .name = xname, \
2563   .index = xindex, \
2564   .info = snd_hdsp_info_use_midi_tasklet, \
2565   .get = snd_hdsp_get_use_midi_tasklet, \
2566   .put = snd_hdsp_put_use_midi_tasklet \
2567 }
2568
2569 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2570 {
2571         if (use_tasklet)
2572                 hdsp->use_midi_tasklet = 1;
2573         else
2574                 hdsp->use_midi_tasklet = 0;
2575         return 0;
2576 }
2577
2578 #define snd_hdsp_info_use_midi_tasklet          snd_ctl_boolean_mono_info
2579
2580 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2581 {
2582         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2583
2584         spin_lock_irq(&hdsp->lock);
2585         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2586         spin_unlock_irq(&hdsp->lock);
2587         return 0;
2588 }
2589
2590 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2591 {
2592         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2593         int change;
2594         unsigned int val;
2595
2596         if (!snd_hdsp_use_is_exclusive(hdsp))
2597                 return -EBUSY;
2598         val = ucontrol->value.integer.value[0] & 1;
2599         spin_lock_irq(&hdsp->lock);
2600         change = (int)val != hdsp->use_midi_tasklet;
2601         hdsp_set_use_midi_tasklet(hdsp, val);
2602         spin_unlock_irq(&hdsp->lock);
2603         return change;
2604 }
2605
2606 #define HDSP_MIXER(xname, xindex) \
2607 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2608   .name = xname, \
2609   .index = xindex, \
2610   .device = 0, \
2611   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2612                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2613   .info = snd_hdsp_info_mixer, \
2614   .get = snd_hdsp_get_mixer, \
2615   .put = snd_hdsp_put_mixer \
2616 }
2617
2618 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2619 {
2620         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2621         uinfo->count = 3;
2622         uinfo->value.integer.min = 0;
2623         uinfo->value.integer.max = 65536;
2624         uinfo->value.integer.step = 1;
2625         return 0;
2626 }
2627
2628 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2629 {
2630         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2631         int source;
2632         int destination;
2633         int addr;
2634
2635         source = ucontrol->value.integer.value[0];
2636         destination = ucontrol->value.integer.value[1];
2637
2638         if (source >= hdsp->max_channels)
2639                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2640         else
2641                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2642
2643         spin_lock_irq(&hdsp->lock);
2644         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2645         spin_unlock_irq(&hdsp->lock);
2646         return 0;
2647 }
2648
2649 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2650 {
2651         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2652         int change;
2653         int source;
2654         int destination;
2655         int gain;
2656         int addr;
2657
2658         if (!snd_hdsp_use_is_exclusive(hdsp))
2659                 return -EBUSY;
2660
2661         source = ucontrol->value.integer.value[0];
2662         destination = ucontrol->value.integer.value[1];
2663
2664         if (source >= hdsp->max_channels)
2665                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2666         else
2667                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2668
2669         gain = ucontrol->value.integer.value[2];
2670
2671         spin_lock_irq(&hdsp->lock);
2672         change = gain != hdsp_read_gain(hdsp, addr);
2673         if (change)
2674                 hdsp_write_gain(hdsp, addr, gain);
2675         spin_unlock_irq(&hdsp->lock);
2676         return change;
2677 }
2678
2679 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2680 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2681   .name = xname, \
2682   .index = xindex, \
2683   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2684   .info = snd_hdsp_info_sync_check, \
2685   .get = snd_hdsp_get_wc_sync_check \
2686 }
2687
2688 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2689 {
2690         static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2691
2692         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2693 }
2694
2695 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2696 {
2697         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2698         if (status2 & HDSP_wc_lock) {
2699                 if (status2 & HDSP_wc_sync)
2700                         return 2;
2701                 else
2702                          return 1;
2703         } else
2704                 return 0;
2705         return 0;
2706 }
2707
2708 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2709 {
2710         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2711
2712         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2713         return 0;
2714 }
2715
2716 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2717 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2718   .name = xname, \
2719   .index = xindex, \
2720   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2721   .info = snd_hdsp_info_sync_check, \
2722   .get = snd_hdsp_get_spdif_sync_check \
2723 }
2724
2725 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2726 {
2727         int status = hdsp_read(hdsp, HDSP_statusRegister);
2728         if (status & HDSP_SPDIFErrorFlag)
2729                 return 0;
2730         else {
2731                 if (status & HDSP_SPDIFSync)
2732                         return 2;
2733                 else
2734                         return 1;
2735         }
2736         return 0;
2737 }
2738
2739 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2740 {
2741         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2742
2743         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2744         return 0;
2745 }
2746
2747 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2748 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2749   .name = xname, \
2750   .index = xindex, \
2751   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2752   .info = snd_hdsp_info_sync_check, \
2753   .get = snd_hdsp_get_adatsync_sync_check \
2754 }
2755
2756 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2757 {
2758         int status = hdsp_read(hdsp, HDSP_statusRegister);
2759         if (status & HDSP_TimecodeLock) {
2760                 if (status & HDSP_TimecodeSync)
2761                         return 2;
2762                 else
2763                         return 1;
2764         } else
2765                 return 0;
2766 }
2767
2768 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2769 {
2770         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2771
2772         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2773         return 0;
2774 }
2775
2776 #define HDSP_ADAT_SYNC_CHECK \
2777 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2778   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2779   .info = snd_hdsp_info_sync_check, \
2780   .get = snd_hdsp_get_adat_sync_check \
2781 }
2782
2783 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2784 {
2785         int status = hdsp_read(hdsp, HDSP_statusRegister);
2786
2787         if (status & (HDSP_Lock0>>idx)) {
2788                 if (status & (HDSP_Sync0>>idx))
2789                         return 2;
2790                 else
2791                         return 1;
2792         } else
2793                 return 0;
2794 }
2795
2796 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2797 {
2798         int offset;
2799         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2800
2801         offset = ucontrol->id.index - 1;
2802         if (snd_BUG_ON(offset < 0))
2803                 return -EINVAL;
2804
2805         switch (hdsp->io_type) {
2806         case Digiface:
2807         case H9652:
2808                 if (offset >= 3)
2809                         return -EINVAL;
2810                 break;
2811         case Multiface:
2812         case H9632:
2813                 if (offset >= 1)
2814                         return -EINVAL;
2815                 break;
2816         default:
2817                 return -EIO;
2818         }
2819
2820         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2821         return 0;
2822 }
2823
2824 #define HDSP_DDS_OFFSET(xname, xindex) \
2825 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2826   .name = xname, \
2827   .index = xindex, \
2828   .info = snd_hdsp_info_dds_offset, \
2829   .get = snd_hdsp_get_dds_offset, \
2830   .put = snd_hdsp_put_dds_offset \
2831 }
2832
2833 static int hdsp_dds_offset(struct hdsp *hdsp)
2834 {
2835         u64 n;
2836         unsigned int dds_value = hdsp->dds_value;
2837         int system_sample_rate = hdsp->system_sample_rate;
2838
2839         if (!dds_value)
2840                 return 0;
2841
2842         n = DDS_NUMERATOR;
2843         /*
2844          * dds_value = n / rate
2845          * rate = n / dds_value
2846          */
2847         n = div_u64(n, dds_value);
2848         if (system_sample_rate >= 112000)
2849                 n *= 4;
2850         else if (system_sample_rate >= 56000)
2851                 n *= 2;
2852         return ((int)n) - system_sample_rate;
2853 }
2854
2855 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2856 {
2857         int rate = hdsp->system_sample_rate + offset_hz;
2858         hdsp_set_dds_value(hdsp, rate);
2859         return 0;
2860 }
2861
2862 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2863 {
2864         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2865         uinfo->count = 1;
2866         uinfo->value.integer.min = -5000;
2867         uinfo->value.integer.max = 5000;
2868         return 0;
2869 }
2870
2871 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2872 {
2873         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2874
2875         ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2876         return 0;
2877 }
2878
2879 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2880 {
2881         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2882         int change;
2883         int val;
2884
2885         if (!snd_hdsp_use_is_exclusive(hdsp))
2886                 return -EBUSY;
2887         val = ucontrol->value.integer.value[0];
2888         spin_lock_irq(&hdsp->lock);
2889         if (val != hdsp_dds_offset(hdsp))
2890                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2891         else
2892                 change = 0;
2893         spin_unlock_irq(&hdsp->lock);
2894         return change;
2895 }
2896
2897 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2898 HDSP_DA_GAIN("DA Gain", 0),
2899 HDSP_AD_GAIN("AD Gain", 0),
2900 HDSP_PHONE_GAIN("Phones Gain", 0),
2901 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2902 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2903 };
2904
2905 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2906 {
2907         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2908         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2909         .info =         snd_hdsp_control_spdif_info,
2910         .get =          snd_hdsp_control_spdif_get,
2911         .put =          snd_hdsp_control_spdif_put,
2912 },
2913 {
2914         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2915         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2916         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2917         .info =         snd_hdsp_control_spdif_stream_info,
2918         .get =          snd_hdsp_control_spdif_stream_get,
2919         .put =          snd_hdsp_control_spdif_stream_put,
2920 },
2921 {
2922         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2923         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2924         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2925         .info =         snd_hdsp_control_spdif_mask_info,
2926         .get =          snd_hdsp_control_spdif_mask_get,
2927         .private_value = IEC958_AES0_NONAUDIO |
2928                          IEC958_AES0_PROFESSIONAL |
2929                          IEC958_AES0_CON_EMPHASIS,
2930 },
2931 {
2932         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2933         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2934         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2935         .info =         snd_hdsp_control_spdif_mask_info,
2936         .get =          snd_hdsp_control_spdif_mask_get,
2937         .private_value = IEC958_AES0_NONAUDIO |
2938                          IEC958_AES0_PROFESSIONAL |
2939                          IEC958_AES0_PRO_EMPHASIS,
2940 },
2941 HDSP_MIXER("Mixer", 0),
2942 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2943 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2944 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2945 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2946 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2947 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2948 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2949 {
2950         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2951         .name = "Sample Clock Source Locking",
2952         .info = snd_hdsp_info_clock_source_lock,
2953         .get = snd_hdsp_get_clock_source_lock,
2954         .put = snd_hdsp_put_clock_source_lock,
2955 },
2956 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2957 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2958 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2959 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2960 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2961 /* 'External Rate' complies with the alsa control naming scheme */
2962 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2963 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2964 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2965 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2966 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2967 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2968 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2969 };
2970
2971
2972 static int hdsp_rpm_input12(struct hdsp *hdsp)
2973 {
2974         switch (hdsp->control_register & HDSP_RPM_Inp12) {
2975         case HDSP_RPM_Inp12_Phon_6dB:
2976                 return 0;
2977         case HDSP_RPM_Inp12_Phon_n6dB:
2978                 return 2;
2979         case HDSP_RPM_Inp12_Line_0dB:
2980                 return 3;
2981         case HDSP_RPM_Inp12_Line_n6dB:
2982                 return 4;
2983         }
2984         return 1;
2985 }
2986
2987
2988 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2989 {
2990         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2991
2992         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2993         return 0;
2994 }
2995
2996
2997 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2998 {
2999         hdsp->control_register &= ~HDSP_RPM_Inp12;
3000         switch (mode) {
3001         case 0:
3002                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3003                 break;
3004         case 1:
3005                 break;
3006         case 2:
3007                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3008                 break;
3009         case 3:
3010                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3011                 break;
3012         case 4:
3013                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3014                 break;
3015         default:
3016                 return -1;
3017         }
3018
3019         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3020         return 0;
3021 }
3022
3023
3024 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3025 {
3026         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3027         int change;
3028         int val;
3029
3030         if (!snd_hdsp_use_is_exclusive(hdsp))
3031                 return -EBUSY;
3032         val = ucontrol->value.enumerated.item[0];
3033         if (val < 0)
3034                 val = 0;
3035         if (val > 4)
3036                 val = 4;
3037         spin_lock_irq(&hdsp->lock);
3038         if (val != hdsp_rpm_input12(hdsp))
3039                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3040         else
3041                 change = 0;
3042         spin_unlock_irq(&hdsp->lock);
3043         return change;
3044 }
3045
3046
3047 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3048 {
3049         static const char * const texts[] = {
3050                 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3051         };
3052
3053         return snd_ctl_enum_info(uinfo, 1, 5, texts);
3054 }
3055
3056
3057 static int hdsp_rpm_input34(struct hdsp *hdsp)
3058 {
3059         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3060         case HDSP_RPM_Inp34_Phon_6dB:
3061                 return 0;
3062         case HDSP_RPM_Inp34_Phon_n6dB:
3063                 return 2;
3064         case HDSP_RPM_Inp34_Line_0dB:
3065                 return 3;
3066         case HDSP_RPM_Inp34_Line_n6dB:
3067                 return 4;
3068         }
3069         return 1;
3070 }
3071
3072
3073 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3074 {
3075         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3076
3077         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3078         return 0;
3079 }
3080
3081
3082 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3083 {
3084         hdsp->control_register &= ~HDSP_RPM_Inp34;
3085         switch (mode) {
3086         case 0:
3087                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3088                 break;
3089         case 1:
3090                 break;
3091         case 2:
3092                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3093                 break;
3094         case 3:
3095                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3096                 break;
3097         case 4:
3098                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3099                 break;
3100         default:
3101                 return -1;
3102         }
3103
3104         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3105         return 0;
3106 }
3107
3108
3109 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3110 {
3111         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3112         int change;
3113         int val;
3114
3115         if (!snd_hdsp_use_is_exclusive(hdsp))
3116                 return -EBUSY;
3117         val = ucontrol->value.enumerated.item[0];
3118         if (val < 0)
3119                 val = 0;
3120         if (val > 4)
3121                 val = 4;
3122         spin_lock_irq(&hdsp->lock);
3123         if (val != hdsp_rpm_input34(hdsp))
3124                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3125         else
3126                 change = 0;
3127         spin_unlock_irq(&hdsp->lock);
3128         return change;
3129 }
3130
3131
3132 /* RPM Bypass switch */
3133 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3134 {
3135         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3136 }
3137
3138
3139 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3140 {
3141         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3142
3143         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3144         return 0;
3145 }
3146
3147
3148 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3149 {
3150         if (on)
3151                 hdsp->control_register |= HDSP_RPM_Bypass;
3152         else
3153                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3154         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3155         return 0;
3156 }
3157
3158
3159 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3160 {
3161         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3162         int change;
3163         unsigned int val;
3164
3165         if (!snd_hdsp_use_is_exclusive(hdsp))
3166                 return -EBUSY;
3167         val = ucontrol->value.integer.value[0] & 1;
3168         spin_lock_irq(&hdsp->lock);
3169         change = (int)val != hdsp_rpm_bypass(hdsp);
3170         hdsp_set_rpm_bypass(hdsp, val);
3171         spin_unlock_irq(&hdsp->lock);
3172         return change;
3173 }
3174
3175
3176 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3177 {
3178         static const char * const texts[] = {"On", "Off"};
3179
3180         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3181 }
3182
3183
3184 /* RPM Disconnect switch */
3185 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3186 {
3187         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3188 }
3189
3190
3191 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3192 {
3193         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3194
3195         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3196         return 0;
3197 }
3198
3199
3200 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3201 {
3202         if (on)
3203                 hdsp->control_register |= HDSP_RPM_Disconnect;
3204         else
3205                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3206         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3207         return 0;
3208 }
3209
3210
3211 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3212 {
3213         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3214         int change;
3215         unsigned int val;
3216
3217         if (!snd_hdsp_use_is_exclusive(hdsp))
3218                 return -EBUSY;
3219         val = ucontrol->value.integer.value[0] & 1;
3220         spin_lock_irq(&hdsp->lock);
3221         change = (int)val != hdsp_rpm_disconnect(hdsp);
3222         hdsp_set_rpm_disconnect(hdsp, val);
3223         spin_unlock_irq(&hdsp->lock);
3224         return change;
3225 }
3226
3227 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3228 {
3229         static const char * const texts[] = {"On", "Off"};
3230
3231         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3232 }
3233
3234 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3235         {
3236                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3237                 .name = "RPM Bypass",
3238                 .get = snd_hdsp_get_rpm_bypass,
3239                 .put = snd_hdsp_put_rpm_bypass,
3240                 .info = snd_hdsp_info_rpm_bypass
3241         },
3242         {
3243                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3244                 .name = "RPM Disconnect",
3245                 .get = snd_hdsp_get_rpm_disconnect,
3246                 .put = snd_hdsp_put_rpm_disconnect,
3247                 .info = snd_hdsp_info_rpm_disconnect
3248         },
3249         {
3250                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3251                 .name = "Input 1/2",
3252                 .get = snd_hdsp_get_rpm_input12,
3253                 .put = snd_hdsp_put_rpm_input12,
3254                 .info = snd_hdsp_info_rpm_input
3255         },
3256         {
3257                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3258                 .name = "Input 3/4",
3259                 .get = snd_hdsp_get_rpm_input34,
3260                 .put = snd_hdsp_put_rpm_input34,
3261                 .info = snd_hdsp_info_rpm_input
3262         },
3263         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3264         HDSP_MIXER("Mixer", 0)
3265 };
3266
3267 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3268         HDSP_TOGGLE_SETTING("Analog Extension Board",
3269                         HDSP_AnalogExtensionBoard);
3270 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3271
3272 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3273 {
3274         unsigned int idx;
3275         int err;
3276         struct snd_kcontrol *kctl;
3277
3278         if (hdsp->io_type == RPM) {
3279                 /* RPM Bypass, Disconnect and Input switches */
3280                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3281                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3282                         if (err < 0)
3283                                 return err;
3284                 }
3285                 return 0;
3286         }
3287
3288         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3289                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3290                         return err;
3291                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3292                         hdsp->spdif_ctl = kctl;
3293         }
3294
3295         /* ADAT SyncCheck status */
3296         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3297         snd_hdsp_adat_sync_check.index = 1;
3298         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3299                 return err;
3300         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3301                 for (idx = 1; idx < 3; ++idx) {
3302                         snd_hdsp_adat_sync_check.index = idx+1;
3303                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3304                                 return err;
3305                 }
3306         }
3307
3308         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3309         if (hdsp->io_type == H9632) {
3310                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3311                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3312                                 return err;
3313                 }
3314         }
3315
3316         /* AEB control for H96xx card */
3317         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3318                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3319                                 return err;
3320         }
3321
3322         return 0;
3323 }
3324
3325 /*------------------------------------------------------------
3326    /proc interface
3327  ------------------------------------------------------------*/
3328
3329 static void
3330 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3331 {
3332         struct hdsp *hdsp = entry->private_data;
3333         unsigned int status;
3334         unsigned int status2;
3335         char *pref_sync_ref;
3336         char *autosync_ref;
3337         char *system_clock_mode;
3338         char *clock_source;
3339         int x;
3340
3341         status = hdsp_read(hdsp, HDSP_statusRegister);
3342         status2 = hdsp_read(hdsp, HDSP_status2Register);
3343
3344         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3345                     hdsp->card->number + 1);
3346         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3347                     hdsp->capture_buffer, hdsp->playback_buffer);
3348         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3349                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3350         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3351         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3352                     hdsp->control2_register);
3353         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3354         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3355
3356         if (hdsp_check_for_iobox(hdsp)) {
3357                 snd_iprintf(buffer, "No I/O box connected.\n"
3358                             "Please connect one and upload firmware.\n");
3359                 return;
3360         }
3361
3362         if (hdsp_check_for_firmware(hdsp, 0)) {
3363                 if (hdsp->state & HDSP_FirmwareCached) {
3364                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3365                                 snd_iprintf(buffer, "Firmware loading from "
3366                                             "cache failed, "
3367                                             "please upload manually.\n");
3368                                 return;
3369                         }
3370                 } else {
3371                         int err = -EINVAL;
3372                         err = hdsp_request_fw_loader(hdsp);
3373                         if (err < 0) {
3374                                 snd_iprintf(buffer,
3375                                             "No firmware loaded nor cached, "
3376                                             "please upload firmware.\n");
3377                                 return;
3378                         }
3379                 }
3380         }
3381
3382         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3383         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3384         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3385         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3386         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3387         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3388
3389         snd_iprintf(buffer, "\n");
3390
3391         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3392
3393         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3394         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3395         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3396         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3397
3398         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3399
3400         snd_iprintf(buffer, "\n");
3401
3402         switch (hdsp_clock_source(hdsp)) {
3403         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3404                 clock_source = "AutoSync";
3405                 break;
3406         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3407                 clock_source = "Internal 32 kHz";
3408                 break;
3409         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3410                 clock_source = "Internal 44.1 kHz";
3411                 break;
3412         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3413                 clock_source = "Internal 48 kHz";
3414                 break;
3415         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3416                 clock_source = "Internal 64 kHz";
3417                 break;
3418         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3419                 clock_source = "Internal 88.2 kHz";
3420                 break;
3421         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3422                 clock_source = "Internal 96 kHz";
3423                 break;
3424         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3425                 clock_source = "Internal 128 kHz";
3426                 break;
3427         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3428                 clock_source = "Internal 176.4 kHz";
3429                 break;
3430                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3431                 clock_source = "Internal 192 kHz";
3432                 break;
3433         default:
3434                 clock_source = "Error";
3435         }
3436         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3437
3438         if (hdsp_system_clock_mode(hdsp))
3439                 system_clock_mode = "Slave";
3440         else
3441                 system_clock_mode = "Master";
3442
3443         switch (hdsp_pref_sync_ref (hdsp)) {
3444         case HDSP_SYNC_FROM_WORD:
3445                 pref_sync_ref = "Word Clock";
3446                 break;
3447         case HDSP_SYNC_FROM_ADAT_SYNC:
3448                 pref_sync_ref = "ADAT Sync";
3449                 break;
3450         case HDSP_SYNC_FROM_SPDIF:
3451                 pref_sync_ref = "SPDIF";
3452                 break;
3453         case HDSP_SYNC_FROM_ADAT1:
3454                 pref_sync_ref = "ADAT1";
3455                 break;
3456         case HDSP_SYNC_FROM_ADAT2:
3457                 pref_sync_ref = "ADAT2";
3458                 break;
3459         case HDSP_SYNC_FROM_ADAT3:
3460                 pref_sync_ref = "ADAT3";
3461                 break;
3462         default:
3463                 pref_sync_ref = "Word Clock";
3464                 break;
3465         }
3466         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3467
3468         switch (hdsp_autosync_ref (hdsp)) {
3469         case HDSP_AUTOSYNC_FROM_WORD:
3470                 autosync_ref = "Word Clock";
3471                 break;
3472         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3473                 autosync_ref = "ADAT Sync";
3474                 break;
3475         case HDSP_AUTOSYNC_FROM_SPDIF:
3476                 autosync_ref = "SPDIF";
3477                 break;
3478         case HDSP_AUTOSYNC_FROM_NONE:
3479                 autosync_ref = "None";
3480                 break;
3481         case HDSP_AUTOSYNC_FROM_ADAT1:
3482                 autosync_ref = "ADAT1";
3483                 break;
3484         case HDSP_AUTOSYNC_FROM_ADAT2:
3485                 autosync_ref = "ADAT2";
3486                 break;
3487         case HDSP_AUTOSYNC_FROM_ADAT3:
3488                 autosync_ref = "ADAT3";
3489                 break;
3490         default:
3491                 autosync_ref = "---";
3492                 break;
3493         }
3494         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3495
3496         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3497
3498         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3499
3500         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3501         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3502
3503         snd_iprintf(buffer, "\n");
3504
3505         if (hdsp->io_type != RPM) {
3506                 switch (hdsp_spdif_in(hdsp)) {
3507                 case HDSP_SPDIFIN_OPTICAL:
3508                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3509                         break;
3510                 case HDSP_SPDIFIN_COAXIAL:
3511                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3512                         break;
3513                 case HDSP_SPDIFIN_INTERNAL:
3514                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3515                         break;
3516                 case HDSP_SPDIFIN_AES:
3517                         snd_iprintf(buffer, "IEC958 input: AES\n");
3518                         break;
3519                 default:
3520                         snd_iprintf(buffer, "IEC958 input: ???\n");
3521                         break;
3522                 }
3523         }
3524
3525         if (RPM == hdsp->io_type) {
3526                 if (hdsp->control_register & HDSP_RPM_Bypass)
3527                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3528                 else
3529                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3530                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3531                         snd_iprintf(buffer, "RPM disconnected\n");
3532                 else
3533                         snd_iprintf(buffer, "RPM connected\n");
3534
3535                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3536                 case HDSP_RPM_Inp12_Phon_6dB:
3537                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3538                         break;
3539                 case HDSP_RPM_Inp12_Phon_0dB:
3540                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3541                         break;
3542                 case HDSP_RPM_Inp12_Phon_n6dB:
3543                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3544                         break;
3545                 case HDSP_RPM_Inp12_Line_0dB:
3546                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3547                         break;
3548                 case HDSP_RPM_Inp12_Line_n6dB:
3549                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3550                         break;
3551                 default:
3552                         snd_iprintf(buffer, "Input 1/2: ???\n");
3553                 }
3554
3555                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3556                 case HDSP_RPM_Inp34_Phon_6dB:
3557                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3558                         break;
3559                 case HDSP_RPM_Inp34_Phon_0dB:
3560                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3561                         break;
3562                 case HDSP_RPM_Inp34_Phon_n6dB:
3563                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3564                         break;
3565                 case HDSP_RPM_Inp34_Line_0dB:
3566                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3567                         break;
3568                 case HDSP_RPM_Inp34_Line_n6dB:
3569                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3570                         break;
3571                 default:
3572                         snd_iprintf(buffer, "Input 3/4: ???\n");
3573                 }
3574
3575         } else {
3576                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3577                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3578                 else
3579                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3580
3581                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3582                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3583                 else
3584                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3585
3586                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3587                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3588                 else
3589                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3590
3591                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3592                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3593                 else
3594                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3595                 x = hdsp_spdif_sample_rate(hdsp);
3596                 if (x != 0)
3597                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3598                 else
3599                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3600         }
3601         snd_iprintf(buffer, "\n");
3602
3603         /* Sync Check */
3604         x = status & HDSP_Sync0;
3605         if (status & HDSP_Lock0)
3606                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3607         else
3608                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3609
3610         switch (hdsp->io_type) {
3611         case Digiface:
3612         case H9652:
3613                 x = status & HDSP_Sync1;
3614                 if (status & HDSP_Lock1)
3615                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3616                 else
3617                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3618                 x = status & HDSP_Sync2;
3619                 if (status & HDSP_Lock2)
3620                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3621                 else
3622                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3623                 break;
3624         default:
3625                 /* relax */
3626                 break;
3627         }
3628
3629         x = status & HDSP_SPDIFSync;
3630         if (status & HDSP_SPDIFErrorFlag)
3631                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3632         else
3633                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3634
3635         x = status2 & HDSP_wc_sync;
3636         if (status2 & HDSP_wc_lock)
3637                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3638         else
3639                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3640
3641         x = status & HDSP_TimecodeSync;
3642         if (status & HDSP_TimecodeLock)
3643                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3644         else
3645                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3646
3647         snd_iprintf(buffer, "\n");
3648
3649         /* Informations about H9632 specific controls */
3650         if (hdsp->io_type == H9632) {
3651                 char *tmp;
3652
3653                 switch (hdsp_ad_gain(hdsp)) {
3654                 case 0:
3655                         tmp = "-10 dBV";
3656                         break;
3657                 case 1:
3658                         tmp = "+4 dBu";
3659                         break;
3660                 default:
3661                         tmp = "Lo Gain";
3662                         break;
3663                 }
3664                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3665
3666                 switch (hdsp_da_gain(hdsp)) {
3667                 case 0:
3668                         tmp = "Hi Gain";
3669                         break;
3670                 case 1:
3671                         tmp = "+4 dBu";
3672                         break;
3673                 default:
3674                         tmp = "-10 dBV";
3675                         break;
3676                 }
3677                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3678
3679                 switch (hdsp_phone_gain(hdsp)) {
3680                 case 0:
3681                         tmp = "0 dB";
3682                         break;
3683                 case 1:
3684                         tmp = "-6 dB";
3685                         break;
3686                 default:
3687                         tmp = "-12 dB";
3688                         break;
3689                 }
3690                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3691
3692                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3693                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3694                         "yes" : "no");
3695
3696                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3697                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3698                 else
3699                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3700                 snd_iprintf(buffer, "\n");
3701         }
3702
3703 }
3704
3705 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3706 {
3707         struct snd_info_entry *entry;
3708
3709         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3710                 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3711 }
3712
3713 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3714 {
3715         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3716         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3717 }
3718
3719 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3720 {
3721         unsigned long pb_bus, cb_bus;
3722
3723         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3724             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3725                 if (hdsp->capture_dma_buf.area)
3726                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3727                 dev_err(hdsp->card->dev,
3728                         "%s: no buffers available\n", hdsp->card_name);
3729                 return -ENOMEM;
3730         }
3731
3732         /* Align to bus-space 64K boundary */
3733
3734         cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3735         pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3736
3737         /* Tell the card where it is */
3738
3739         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3740         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3741
3742         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3743         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3744
3745         return 0;
3746 }
3747
3748 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3749 {
3750         unsigned int i;
3751
3752         /* ASSUMPTION: hdsp->lock is either held, or
3753            there is no need to hold it (e.g. during module
3754            initialization).
3755          */
3756
3757         /* set defaults:
3758
3759            SPDIF Input via Coax
3760            Master clock mode
3761            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3762                             which implies 2 4096 sample, 32Kbyte periods).
3763            Enable line out.
3764          */
3765
3766         hdsp->control_register = HDSP_ClockModeMaster |
3767                                  HDSP_SPDIFInputCoaxial |
3768                                  hdsp_encode_latency(7) |
3769                                  HDSP_LineOut;
3770
3771
3772         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3773
3774 #ifdef SNDRV_BIG_ENDIAN
3775         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3776 #else
3777         hdsp->control2_register = 0;
3778 #endif
3779         if (hdsp->io_type == H9652)
3780                 snd_hdsp_9652_enable_mixer (hdsp);
3781         else
3782                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3783
3784         hdsp_reset_hw_pointer(hdsp);
3785         hdsp_compute_period_size(hdsp);
3786
3787         /* silence everything */
3788
3789         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3790                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3791
3792         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3793                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3794                         return -EIO;
3795         }
3796
3797         /* H9632 specific defaults */
3798         if (hdsp->io_type == H9632) {
3799                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3800                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3801         }
3802
3803         /* set a default rate so that the channel map is set up.
3804          */
3805
3806         hdsp_set_rate(hdsp, 48000, 1);
3807
3808         return 0;
3809 }
3810
3811 static void hdsp_midi_tasklet(unsigned long arg)
3812 {
3813         struct hdsp *hdsp = (struct hdsp *)arg;
3814
3815         if (hdsp->midi[0].pending)
3816                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3817         if (hdsp->midi[1].pending)
3818                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3819 }
3820
3821 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3822 {
3823         struct hdsp *hdsp = (struct hdsp *) dev_id;
3824         unsigned int status;
3825         int audio;
3826         int midi0;
3827         int midi1;
3828         unsigned int midi0status;
3829         unsigned int midi1status;
3830         int schedule = 0;
3831
3832         status = hdsp_read(hdsp, HDSP_statusRegister);
3833
3834         audio = status & HDSP_audioIRQPending;
3835         midi0 = status & HDSP_midi0IRQPending;
3836         midi1 = status & HDSP_midi1IRQPending;
3837
3838         if (!audio && !midi0 && !midi1)
3839                 return IRQ_NONE;
3840
3841         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3842
3843         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3844         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3845
3846         if (!(hdsp->state & HDSP_InitializationComplete))
3847                 return IRQ_HANDLED;
3848
3849         if (audio) {
3850                 if (hdsp->capture_substream)
3851                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3852
3853                 if (hdsp->playback_substream)
3854                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3855         }
3856
3857         if (midi0 && midi0status) {
3858                 if (hdsp->use_midi_tasklet) {
3859                         /* we disable interrupts for this input until processing is done */
3860                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3861                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3862                         hdsp->midi[0].pending = 1;
3863                         schedule = 1;
3864                 } else {
3865                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3866                 }
3867         }
3868         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3869                 if (hdsp->use_midi_tasklet) {
3870                         /* we disable interrupts for this input until processing is done */
3871                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3872                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3873                         hdsp->midi[1].pending = 1;
3874                         schedule = 1;
3875                 } else {
3876                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3877                 }
3878         }
3879         if (hdsp->use_midi_tasklet && schedule)
3880                 tasklet_schedule(&hdsp->midi_tasklet);
3881         return IRQ_HANDLED;
3882 }
3883
3884 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3885 {
3886         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3887         return hdsp_hw_pointer(hdsp);
3888 }
3889
3890 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3891                                              int stream,
3892                                              int channel)
3893
3894 {
3895         int mapped_channel;
3896
3897         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3898                 return NULL;
3899
3900         if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3901                 return NULL;
3902
3903         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3904                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3905         else
3906                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3907 }
3908
3909 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3910                                   int channel, unsigned long pos,
3911                                   void __user *src, unsigned long count)
3912 {
3913         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3914         char *channel_buf;
3915
3916         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3917                 return -EINVAL;
3918
3919         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3920         if (snd_BUG_ON(!channel_buf))
3921                 return -EIO;
3922         if (copy_from_user(channel_buf + pos, src, count))
3923                 return -EFAULT;
3924         return 0;
3925 }
3926
3927 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3928                                          int channel, unsigned long pos,
3929                                          void *src, unsigned long count)
3930 {
3931         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3932         char *channel_buf;
3933
3934         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3935         if (snd_BUG_ON(!channel_buf))
3936                 return -EIO;
3937         memcpy(channel_buf + pos, src, count);
3938         return 0;
3939 }
3940
3941 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3942                                  int channel, unsigned long pos,
3943                                  void __user *dst, unsigned long count)
3944 {
3945         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3946         char *channel_buf;
3947
3948         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3949                 return -EINVAL;
3950
3951         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3952         if (snd_BUG_ON(!channel_buf))
3953                 return -EIO;
3954         if (copy_to_user(dst, channel_buf + pos, count))
3955                 return -EFAULT;
3956         return 0;
3957 }
3958
3959 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3960                                         int channel, unsigned long pos,
3961                                         void *dst, unsigned long count)
3962 {
3963         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3964         char *channel_buf;
3965
3966         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3967         if (snd_BUG_ON(!channel_buf))
3968                 return -EIO;
3969         memcpy(dst, channel_buf + pos, count);
3970         return 0;
3971 }
3972
3973 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3974                                int channel, unsigned long pos,
3975                                unsigned long count)
3976 {
3977         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3978         char *channel_buf;
3979
3980         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3981         if (snd_BUG_ON(!channel_buf))
3982                 return -EIO;
3983         memset(channel_buf + pos, 0, count);
3984         return 0;
3985 }
3986
3987 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3988 {
3989         struct snd_pcm_runtime *runtime = substream->runtime;
3990         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3991         struct snd_pcm_substream *other;
3992         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3993                 other = hdsp->capture_substream;
3994         else
3995                 other = hdsp->playback_substream;
3996         if (hdsp->running)
3997                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3998         else
3999                 runtime->status->hw_ptr = 0;
4000         if (other) {
4001                 struct snd_pcm_substream *s;
4002                 struct snd_pcm_runtime *oruntime = other->runtime;
4003                 snd_pcm_group_for_each_entry(s, substream) {
4004                         if (s == other) {
4005                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4006                                 break;
4007                         }
4008                 }
4009         }
4010         return 0;
4011 }
4012
4013 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4014                                  struct snd_pcm_hw_params *params)
4015 {
4016         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4017         int err;
4018         pid_t this_pid;
4019         pid_t other_pid;
4020
4021         if (hdsp_check_for_iobox (hdsp))
4022                 return -EIO;
4023
4024         if (hdsp_check_for_firmware(hdsp, 1))
4025                 return -EIO;
4026
4027         spin_lock_irq(&hdsp->lock);
4028
4029         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4030                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4031                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4032                 this_pid = hdsp->playback_pid;
4033                 other_pid = hdsp->capture_pid;
4034         } else {
4035                 this_pid = hdsp->capture_pid;
4036                 other_pid = hdsp->playback_pid;
4037         }
4038
4039         if ((other_pid > 0) && (this_pid != other_pid)) {
4040
4041                 /* The other stream is open, and not by the same
4042                    task as this one. Make sure that the parameters
4043                    that matter are the same.
4044                  */
4045
4046                 if (params_rate(params) != hdsp->system_sample_rate) {
4047                         spin_unlock_irq(&hdsp->lock);
4048                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4049                         return -EBUSY;
4050                 }
4051
4052                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4053                         spin_unlock_irq(&hdsp->lock);
4054                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4055                         return -EBUSY;
4056                 }
4057
4058                 /* We're fine. */
4059
4060                 spin_unlock_irq(&hdsp->lock);
4061                 return 0;
4062
4063         } else {
4064                 spin_unlock_irq(&hdsp->lock);
4065         }
4066
4067         /* how to make sure that the rate matches an externally-set one ?
4068          */
4069
4070         spin_lock_irq(&hdsp->lock);
4071         if (! hdsp->clock_source_locked) {
4072                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4073                         spin_unlock_irq(&hdsp->lock);
4074                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4075                         return err;
4076                 }
4077         }
4078         spin_unlock_irq(&hdsp->lock);
4079
4080         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4081                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4082                 return err;
4083         }
4084
4085         return 0;
4086 }
4087
4088 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4089                                     struct snd_pcm_channel_info *info)
4090 {
4091         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4092         unsigned int channel = info->channel;
4093
4094         if (snd_BUG_ON(channel >= hdsp->max_channels))
4095                 return -EINVAL;
4096         channel = array_index_nospec(channel, hdsp->max_channels);
4097
4098         if (hdsp->channel_map[channel] < 0)
4099                 return -EINVAL;
4100
4101         info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4102         info->first = 0;
4103         info->step = 32;
4104         return 0;
4105 }
4106
4107 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4108                              unsigned int cmd, void *arg)
4109 {
4110         switch (cmd) {
4111         case SNDRV_PCM_IOCTL1_RESET:
4112                 return snd_hdsp_reset(substream);
4113         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4114                 return snd_hdsp_channel_info(substream, arg);
4115         default:
4116                 break;
4117         }
4118
4119         return snd_pcm_lib_ioctl(substream, cmd, arg);
4120 }
4121
4122 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4123 {
4124         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4125         struct snd_pcm_substream *other;
4126         int running;
4127
4128         if (hdsp_check_for_iobox (hdsp))
4129                 return -EIO;
4130
4131         if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4132                 return -EIO;
4133
4134         spin_lock(&hdsp->lock);
4135         running = hdsp->running;
4136         switch (cmd) {
4137         case SNDRV_PCM_TRIGGER_START:
4138                 running |= 1 << substream->stream;
4139                 break;
4140         case SNDRV_PCM_TRIGGER_STOP:
4141                 running &= ~(1 << substream->stream);
4142                 break;
4143         default:
4144                 snd_BUG();
4145                 spin_unlock(&hdsp->lock);
4146                 return -EINVAL;
4147         }
4148         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4149                 other = hdsp->capture_substream;
4150         else
4151                 other = hdsp->playback_substream;
4152
4153         if (other) {
4154                 struct snd_pcm_substream *s;
4155                 snd_pcm_group_for_each_entry(s, substream) {
4156                         if (s == other) {
4157                                 snd_pcm_trigger_done(s, substream);
4158                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4159                                         running |= 1 << s->stream;
4160                                 else
4161                                         running &= ~(1 << s->stream);
4162                                 goto _ok;
4163                         }
4164                 }
4165                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4166                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4167                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4168                                 hdsp_silence_playback(hdsp);
4169                 } else {
4170                         if (running &&
4171                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4172                                 hdsp_silence_playback(hdsp);
4173                 }
4174         } else {
4175                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4176                                 hdsp_silence_playback(hdsp);
4177         }
4178  _ok:
4179         snd_pcm_trigger_done(substream, substream);
4180         if (!hdsp->running && running)
4181                 hdsp_start_audio(hdsp);
4182         else if (hdsp->running && !running)
4183                 hdsp_stop_audio(hdsp);
4184         hdsp->running = running;
4185         spin_unlock(&hdsp->lock);
4186
4187         return 0;
4188 }
4189
4190 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4191 {
4192         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4193         int result = 0;
4194
4195         if (hdsp_check_for_iobox (hdsp))
4196                 return -EIO;
4197
4198         if (hdsp_check_for_firmware(hdsp, 1))
4199                 return -EIO;
4200
4201         spin_lock_irq(&hdsp->lock);
4202         if (!hdsp->running)
4203                 hdsp_reset_hw_pointer(hdsp);
4204         spin_unlock_irq(&hdsp->lock);
4205         return result;
4206 }
4207
4208 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4209 {
4210         .info =                 (SNDRV_PCM_INFO_MMAP |
4211                                  SNDRV_PCM_INFO_MMAP_VALID |
4212                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4213                                  SNDRV_PCM_INFO_SYNC_START |
4214                                  SNDRV_PCM_INFO_DOUBLE),
4215 #ifdef SNDRV_BIG_ENDIAN
4216         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4217 #else
4218         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4219 #endif
4220         .rates =                (SNDRV_PCM_RATE_32000 |
4221                                  SNDRV_PCM_RATE_44100 |
4222                                  SNDRV_PCM_RATE_48000 |
4223                                  SNDRV_PCM_RATE_64000 |
4224                                  SNDRV_PCM_RATE_88200 |
4225                                  SNDRV_PCM_RATE_96000),
4226         .rate_min =             32000,
4227         .rate_max =             96000,
4228         .channels_min =         6,
4229         .channels_max =         HDSP_MAX_CHANNELS,
4230         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4231         .period_bytes_min =     (64 * 4) * 10,
4232         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4233         .periods_min =          2,
4234         .periods_max =          2,
4235         .fifo_size =            0
4236 };
4237
4238 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4239 {
4240         .info =                 (SNDRV_PCM_INFO_MMAP |
4241                                  SNDRV_PCM_INFO_MMAP_VALID |
4242                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4243                                  SNDRV_PCM_INFO_SYNC_START),
4244 #ifdef SNDRV_BIG_ENDIAN
4245         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4246 #else
4247         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4248 #endif
4249         .rates =                (SNDRV_PCM_RATE_32000 |
4250                                  SNDRV_PCM_RATE_44100 |
4251                                  SNDRV_PCM_RATE_48000 |
4252                                  SNDRV_PCM_RATE_64000 |
4253                                  SNDRV_PCM_RATE_88200 |
4254                                  SNDRV_PCM_RATE_96000),
4255         .rate_min =             32000,
4256         .rate_max =             96000,
4257         .channels_min =         5,
4258         .channels_max =         HDSP_MAX_CHANNELS,
4259         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4260         .period_bytes_min =     (64 * 4) * 10,
4261         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4262         .periods_min =          2,
4263         .periods_max =          2,
4264         .fifo_size =            0
4265 };
4266
4267 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4268
4269 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4270         .count = ARRAY_SIZE(hdsp_period_sizes),
4271         .list = hdsp_period_sizes,
4272         .mask = 0
4273 };
4274
4275 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4276
4277 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4278         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4279         .list = hdsp_9632_sample_rates,
4280         .mask = 0
4281 };
4282
4283 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4284                                         struct snd_pcm_hw_rule *rule)
4285 {
4286         struct hdsp *hdsp = rule->private;
4287         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4288         if (hdsp->io_type == H9632) {
4289                 unsigned int list[3];
4290                 list[0] = hdsp->qs_in_channels;
4291                 list[1] = hdsp->ds_in_channels;
4292                 list[2] = hdsp->ss_in_channels;
4293                 return snd_interval_list(c, 3, list, 0);
4294         } else {
4295                 unsigned int list[2];
4296                 list[0] = hdsp->ds_in_channels;
4297                 list[1] = hdsp->ss_in_channels;
4298                 return snd_interval_list(c, 2, list, 0);
4299         }
4300 }
4301
4302 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4303                                         struct snd_pcm_hw_rule *rule)
4304 {
4305         unsigned int list[3];
4306         struct hdsp *hdsp = rule->private;
4307         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4308         if (hdsp->io_type == H9632) {
4309                 list[0] = hdsp->qs_out_channels;
4310                 list[1] = hdsp->ds_out_channels;
4311                 list[2] = hdsp->ss_out_channels;
4312                 return snd_interval_list(c, 3, list, 0);
4313         } else {
4314                 list[0] = hdsp->ds_out_channels;
4315                 list[1] = hdsp->ss_out_channels;
4316         }
4317         return snd_interval_list(c, 2, list, 0);
4318 }
4319
4320 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4321                                              struct snd_pcm_hw_rule *rule)
4322 {
4323         struct hdsp *hdsp = rule->private;
4324         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4325         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4326         if (r->min > 96000 && hdsp->io_type == H9632) {
4327                 struct snd_interval t = {
4328                         .min = hdsp->qs_in_channels,
4329                         .max = hdsp->qs_in_channels,
4330                         .integer = 1,
4331                 };
4332                 return snd_interval_refine(c, &t);
4333         } else if (r->min > 48000 && r->max <= 96000) {
4334                 struct snd_interval t = {
4335                         .min = hdsp->ds_in_channels,
4336                         .max = hdsp->ds_in_channels,
4337                         .integer = 1,
4338                 };
4339                 return snd_interval_refine(c, &t);
4340         } else if (r->max < 64000) {
4341                 struct snd_interval t = {
4342                         .min = hdsp->ss_in_channels,
4343                         .max = hdsp->ss_in_channels,
4344                         .integer = 1,
4345                 };
4346                 return snd_interval_refine(c, &t);
4347         }
4348         return 0;
4349 }
4350
4351 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4352                                              struct snd_pcm_hw_rule *rule)
4353 {
4354         struct hdsp *hdsp = rule->private;
4355         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4356         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4357         if (r->min > 96000 && hdsp->io_type == H9632) {
4358                 struct snd_interval t = {
4359                         .min = hdsp->qs_out_channels,
4360                         .max = hdsp->qs_out_channels,
4361                         .integer = 1,
4362                 };
4363                 return snd_interval_refine(c, &t);
4364         } else if (r->min > 48000 && r->max <= 96000) {
4365                 struct snd_interval t = {
4366                         .min = hdsp->ds_out_channels,
4367                         .max = hdsp->ds_out_channels,
4368                         .integer = 1,
4369                 };
4370                 return snd_interval_refine(c, &t);
4371         } else if (r->max < 64000) {
4372                 struct snd_interval t = {
4373                         .min = hdsp->ss_out_channels,
4374                         .max = hdsp->ss_out_channels,
4375                         .integer = 1,
4376                 };
4377                 return snd_interval_refine(c, &t);
4378         }
4379         return 0;
4380 }
4381
4382 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4383                                              struct snd_pcm_hw_rule *rule)
4384 {
4385         struct hdsp *hdsp = rule->private;
4386         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4387         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4388         if (c->min >= hdsp->ss_out_channels) {
4389                 struct snd_interval t = {
4390                         .min = 32000,
4391                         .max = 48000,
4392                         .integer = 1,
4393                 };
4394                 return snd_interval_refine(r, &t);
4395         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4396                 struct snd_interval t = {
4397                         .min = 128000,
4398                         .max = 192000,
4399                         .integer = 1,
4400                 };
4401                 return snd_interval_refine(r, &t);
4402         } else if (c->max <= hdsp->ds_out_channels) {
4403                 struct snd_interval t = {
4404                         .min = 64000,
4405                         .max = 96000,
4406                         .integer = 1,
4407                 };
4408                 return snd_interval_refine(r, &t);
4409         }
4410         return 0;
4411 }
4412
4413 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4414                                              struct snd_pcm_hw_rule *rule)
4415 {
4416         struct hdsp *hdsp = rule->private;
4417         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4418         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4419         if (c->min >= hdsp->ss_in_channels) {
4420                 struct snd_interval t = {
4421                         .min = 32000,
4422                         .max = 48000,
4423                         .integer = 1,
4424                 };
4425                 return snd_interval_refine(r, &t);
4426         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4427                 struct snd_interval t = {
4428                         .min = 128000,
4429                         .max = 192000,
4430                         .integer = 1,
4431                 };
4432                 return snd_interval_refine(r, &t);
4433         } else if (c->max <= hdsp->ds_in_channels) {
4434                 struct snd_interval t = {
4435                         .min = 64000,
4436                         .max = 96000,
4437                         .integer = 1,
4438                 };
4439                 return snd_interval_refine(r, &t);
4440         }
4441         return 0;
4442 }
4443
4444 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4445 {
4446         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4447         struct snd_pcm_runtime *runtime = substream->runtime;
4448
4449         if (hdsp_check_for_iobox (hdsp))
4450                 return -EIO;
4451
4452         if (hdsp_check_for_firmware(hdsp, 1))
4453                 return -EIO;
4454
4455         spin_lock_irq(&hdsp->lock);
4456
4457         snd_pcm_set_sync(substream);
4458
4459         runtime->hw = snd_hdsp_playback_subinfo;
4460         runtime->dma_area = hdsp->playback_buffer;
4461         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4462
4463         hdsp->playback_pid = current->pid;
4464         hdsp->playback_substream = substream;
4465
4466         spin_unlock_irq(&hdsp->lock);
4467
4468         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4469         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4470         if (hdsp->clock_source_locked) {
4471                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4472         } else if (hdsp->io_type == H9632) {
4473                 runtime->hw.rate_max = 192000;
4474                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4475                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4476         }
4477         if (hdsp->io_type == H9632) {
4478                 runtime->hw.channels_min = hdsp->qs_out_channels;
4479                 runtime->hw.channels_max = hdsp->ss_out_channels;
4480         }
4481
4482         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4483                              snd_hdsp_hw_rule_out_channels, hdsp,
4484                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4485         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4486                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4487                              SNDRV_PCM_HW_PARAM_RATE, -1);
4488         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4489                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4490                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4491
4492         if (RPM != hdsp->io_type) {
4493                 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4494                 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4495                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4496                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4497         }
4498         return 0;
4499 }
4500
4501 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4502 {
4503         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4504
4505         spin_lock_irq(&hdsp->lock);
4506
4507         hdsp->playback_pid = -1;
4508         hdsp->playback_substream = NULL;
4509
4510         spin_unlock_irq(&hdsp->lock);
4511
4512         if (RPM != hdsp->io_type) {
4513                 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4514                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4515                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4516         }
4517         return 0;
4518 }
4519
4520
4521 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4522 {
4523         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4524         struct snd_pcm_runtime *runtime = substream->runtime;
4525
4526         if (hdsp_check_for_iobox (hdsp))
4527                 return -EIO;
4528
4529         if (hdsp_check_for_firmware(hdsp, 1))
4530                 return -EIO;
4531
4532         spin_lock_irq(&hdsp->lock);
4533
4534         snd_pcm_set_sync(substream);
4535
4536         runtime->hw = snd_hdsp_capture_subinfo;
4537         runtime->dma_area = hdsp->capture_buffer;
4538         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4539
4540         hdsp->capture_pid = current->pid;
4541         hdsp->capture_substream = substream;
4542
4543         spin_unlock_irq(&hdsp->lock);
4544
4545         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4546         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4547         if (hdsp->io_type == H9632) {
4548                 runtime->hw.channels_min = hdsp->qs_in_channels;
4549                 runtime->hw.channels_max = hdsp->ss_in_channels;
4550                 runtime->hw.rate_max = 192000;
4551                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4552                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4553         }
4554         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4555                              snd_hdsp_hw_rule_in_channels, hdsp,
4556                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4557         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4558                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4559                              SNDRV_PCM_HW_PARAM_RATE, -1);
4560         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4561                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4562                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4563         return 0;
4564 }
4565
4566 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4567 {
4568         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4569
4570         spin_lock_irq(&hdsp->lock);
4571
4572         hdsp->capture_pid = -1;
4573         hdsp->capture_substream = NULL;
4574
4575         spin_unlock_irq(&hdsp->lock);
4576         return 0;
4577 }
4578
4579 /* helper functions for copying meter values */
4580 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4581 {
4582         u32 val = readl(src);
4583         return copy_to_user(dest, &val, 4);
4584 }
4585
4586 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4587 {
4588         u32 rms_low, rms_high;
4589         u64 rms;
4590         rms_low = readl(src_low);
4591         rms_high = readl(src_high);
4592         rms = ((u64)rms_high << 32) | rms_low;
4593         return copy_to_user(dest, &rms, 8);
4594 }
4595
4596 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4597 {
4598         u32 rms_low, rms_high;
4599         u64 rms;
4600         rms_low = readl(src_low) & 0xffffff00;
4601         rms_high = readl(src_high) & 0xffffff00;
4602         rms = ((u64)rms_high << 32) | rms_low;
4603         return copy_to_user(dest, &rms, 8);
4604 }
4605
4606 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4607 {
4608         int doublespeed = 0;
4609         int i, j, channels, ofs;
4610
4611         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4612                 doublespeed = 1;
4613         channels = doublespeed ? 14 : 26;
4614         for (i = 0, j = 0; i < 26; ++i) {
4615                 if (doublespeed && (i & 4))
4616                         continue;
4617                 ofs = HDSP_9652_peakBase - j * 4;
4618                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4619                         return -EFAULT;
4620                 ofs -= channels * 4;
4621                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4622                         return -EFAULT;
4623                 ofs -= channels * 4;
4624                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4625                         return -EFAULT;
4626                 ofs = HDSP_9652_rmsBase + j * 8;
4627                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4628                                 hdsp->iobase + ofs + 4))
4629                         return -EFAULT;
4630                 ofs += channels * 8;
4631                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4632                                 hdsp->iobase + ofs + 4))
4633                         return -EFAULT;
4634                 ofs += channels * 8;
4635                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4636                                 hdsp->iobase + ofs + 4))
4637                         return -EFAULT;
4638                 j++;
4639         }
4640         return 0;
4641 }
4642
4643 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4644 {
4645         int i, j;
4646         struct hdsp_9632_meters __iomem *m;
4647         int doublespeed = 0;
4648
4649         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4650                 doublespeed = 1;
4651         m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4652         for (i = 0, j = 0; i < 16; ++i, ++j) {
4653                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4654                         return -EFAULT;
4655                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4656                         return -EFAULT;
4657                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4658                         return -EFAULT;
4659                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4660                                 &m->input_rms_high[j]))
4661                         return -EFAULT;
4662                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4663                                 &m->playback_rms_high[j]))
4664                         return -EFAULT;
4665                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4666                                 &m->output_rms_high[j]))
4667                         return -EFAULT;
4668                 if (doublespeed && i == 3) i += 4;
4669         }
4670         return 0;
4671 }
4672
4673 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4674 {
4675         int i;
4676
4677         for (i = 0; i < 26; i++) {
4678                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4679                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4680                         return -EFAULT;
4681                 if (copy_u32_le(&peak_rms->input_peaks[i],
4682                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4683                         return -EFAULT;
4684         }
4685         for (i = 0; i < 28; i++) {
4686                 if (copy_u32_le(&peak_rms->output_peaks[i],
4687                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4688                         return -EFAULT;
4689         }
4690         for (i = 0; i < 26; ++i) {
4691                 if (copy_u64_le(&peak_rms->playback_rms[i],
4692                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4693                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4694                         return -EFAULT;
4695                 if (copy_u64_le(&peak_rms->input_rms[i],
4696                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4697                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4698                         return -EFAULT;
4699         }
4700         return 0;
4701 }
4702
4703 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4704 {
4705         struct hdsp *hdsp = hw->private_data;
4706         void __user *argp = (void __user *)arg;
4707         int err;
4708
4709         switch (cmd) {
4710         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4711                 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4712
4713                 err = hdsp_check_for_iobox(hdsp);
4714                 if (err < 0)
4715                         return err;
4716
4717                 err = hdsp_check_for_firmware(hdsp, 1);
4718                 if (err < 0)
4719                         return err;
4720
4721                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4722                         dev_err(hdsp->card->dev,
4723                                 "firmware needs to be uploaded to the card.\n");
4724                         return -EINVAL;
4725                 }
4726
4727                 switch (hdsp->io_type) {
4728                 case H9652:
4729                         return hdsp_9652_get_peak(hdsp, peak_rms);
4730                 case H9632:
4731                         return hdsp_9632_get_peak(hdsp, peak_rms);
4732                 default:
4733                         return hdsp_get_peak(hdsp, peak_rms);
4734                 }
4735         }
4736         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4737                 struct hdsp_config_info info;
4738                 unsigned long flags;
4739                 int i;
4740
4741                 err = hdsp_check_for_iobox(hdsp);
4742                 if (err < 0)
4743                         return err;
4744
4745                 err = hdsp_check_for_firmware(hdsp, 1);
4746                 if (err < 0)
4747                         return err;
4748
4749                 memset(&info, 0, sizeof(info));
4750                 spin_lock_irqsave(&hdsp->lock, flags);
4751                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4752                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4753                 if (hdsp->io_type != H9632)
4754                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4755                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4756                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4757                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4758                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4759                 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4760                                 HDSP_SPDIFOpticalOut);
4761                 info.spdif_professional = (unsigned char)
4762                         hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4763                 info.spdif_emphasis = (unsigned char)
4764                         hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4765                 info.spdif_nonaudio = (unsigned char)
4766                         hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4767                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4768                 info.system_sample_rate = hdsp->system_sample_rate;
4769                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4770                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4771                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4772                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4773                 info.line_out = (unsigned char)
4774                         hdsp_toggle_setting(hdsp, HDSP_LineOut);
4775                 if (hdsp->io_type == H9632) {
4776                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4777                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4778                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4779                         info.xlr_breakout_cable =
4780                                 (unsigned char)hdsp_toggle_setting(hdsp,
4781                                         HDSP_XLRBreakoutCable);
4782
4783                 } else if (hdsp->io_type == RPM) {
4784                         info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4785                         info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4786                 }
4787                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4788                         info.analog_extension_board =
4789                                 (unsigned char)hdsp_toggle_setting(hdsp,
4790                                             HDSP_AnalogExtensionBoard);
4791                 spin_unlock_irqrestore(&hdsp->lock, flags);
4792                 if (copy_to_user(argp, &info, sizeof(info)))
4793                         return -EFAULT;
4794                 break;
4795         }
4796         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4797                 struct hdsp_9632_aeb h9632_aeb;
4798
4799                 if (hdsp->io_type != H9632) return -EINVAL;
4800                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4801                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4802                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4803                         return -EFAULT;
4804                 break;
4805         }
4806         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4807                 struct hdsp_version hdsp_version;
4808                 int err;
4809
4810                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4811                 if (hdsp->io_type == Undefined) {
4812                         if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4813                                 return err;
4814                 }
4815                 memset(&hdsp_version, 0, sizeof(hdsp_version));
4816                 hdsp_version.io_type = hdsp->io_type;
4817                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4818                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4819                         return -EFAULT;
4820                 break;
4821         }
4822         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4823                 struct hdsp_firmware __user *firmware;
4824                 u32 __user *firmware_data;
4825                 int err;
4826
4827                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4828                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4829                 if (hdsp->io_type == Undefined) return -EINVAL;
4830
4831                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4832                         return -EBUSY;
4833
4834                 dev_info(hdsp->card->dev,
4835                          "initializing firmware upload\n");
4836                 firmware = (struct hdsp_firmware __user *)argp;
4837
4838                 if (get_user(firmware_data, &firmware->firmware_data))
4839                         return -EFAULT;
4840
4841                 if (hdsp_check_for_iobox (hdsp))
4842                         return -EIO;
4843
4844                 if (!hdsp->fw_uploaded) {
4845                         hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4846                         if (!hdsp->fw_uploaded)
4847                                 return -ENOMEM;
4848                 }
4849
4850                 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4851                                    HDSP_FIRMWARE_SIZE)) {
4852                         vfree(hdsp->fw_uploaded);
4853                         hdsp->fw_uploaded = NULL;
4854                         return -EFAULT;
4855                 }
4856
4857                 hdsp->state |= HDSP_FirmwareCached;
4858
4859                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4860                         return err;
4861
4862                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4863                         if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4864                                 return err;
4865
4866                         snd_hdsp_initialize_channels(hdsp);
4867                         snd_hdsp_initialize_midi_flush(hdsp);
4868
4869                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4870                                 dev_err(hdsp->card->dev,
4871                                         "error creating alsa devices\n");
4872                                 return err;
4873                         }
4874                 }
4875                 break;
4876         }
4877         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4878                 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4879                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4880                         return -EFAULT;
4881                 break;
4882         }
4883         default:
4884                 return -EINVAL;
4885         }
4886         return 0;
4887 }
4888
4889 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4890         .open =         snd_hdsp_playback_open,
4891         .close =        snd_hdsp_playback_release,
4892         .ioctl =        snd_hdsp_ioctl,
4893         .hw_params =    snd_hdsp_hw_params,
4894         .prepare =      snd_hdsp_prepare,
4895         .trigger =      snd_hdsp_trigger,
4896         .pointer =      snd_hdsp_hw_pointer,
4897         .copy_user =    snd_hdsp_playback_copy,
4898         .copy_kernel =  snd_hdsp_playback_copy_kernel,
4899         .fill_silence = snd_hdsp_hw_silence,
4900 };
4901
4902 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4903         .open =         snd_hdsp_capture_open,
4904         .close =        snd_hdsp_capture_release,
4905         .ioctl =        snd_hdsp_ioctl,
4906         .hw_params =    snd_hdsp_hw_params,
4907         .prepare =      snd_hdsp_prepare,
4908         .trigger =      snd_hdsp_trigger,
4909         .pointer =      snd_hdsp_hw_pointer,
4910         .copy_user =    snd_hdsp_capture_copy,
4911         .copy_kernel =  snd_hdsp_capture_copy_kernel,
4912 };
4913
4914 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4915 {
4916         struct snd_hwdep *hw;
4917         int err;
4918
4919         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4920                 return err;
4921
4922         hdsp->hwdep = hw;
4923         hw->private_data = hdsp;
4924         strcpy(hw->name, "HDSP hwdep interface");
4925
4926         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4927         hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4928
4929         return 0;
4930 }
4931
4932 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4933 {
4934         struct snd_pcm *pcm;
4935         int err;
4936
4937         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4938                 return err;
4939
4940         hdsp->pcm = pcm;
4941         pcm->private_data = hdsp;
4942         strcpy(pcm->name, hdsp->card_name);
4943
4944         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4945         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4946
4947         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4948
4949         return 0;
4950 }
4951
4952 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4953 {
4954         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4955         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4956 }
4957
4958 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4959 {
4960         int i;
4961
4962         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4963                 dev_err(hdsp->card->dev,
4964                         "enable_io fifo_wait failed\n");
4965                 return -EIO;
4966         }
4967
4968         for (i = 0; i < hdsp->max_channels; ++i) {
4969                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4970                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4971         }
4972
4973         return 0;
4974 }
4975
4976 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4977 {
4978         int status, aebi_channels, aebo_channels;
4979
4980         switch (hdsp->io_type) {
4981         case Digiface:
4982                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4983                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4984                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4985                 break;
4986
4987         case H9652:
4988                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4989                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4990                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4991                 break;
4992
4993         case H9632:
4994                 status = hdsp_read(hdsp, HDSP_statusRegister);
4995                 /* HDSP_AEBx bits are low when AEB are connected */
4996                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4997                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4998                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4999                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5000                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5001                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5002                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5003                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5004                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5005                 break;
5006
5007         case Multiface:
5008                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5009                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5010                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5011                 break;
5012
5013         case RPM:
5014                 hdsp->card_name = "RME Hammerfall DSP + RPM";
5015                 hdsp->ss_in_channels = RPM_CHANNELS-1;
5016                 hdsp->ss_out_channels = RPM_CHANNELS;
5017                 hdsp->ds_in_channels = RPM_CHANNELS-1;
5018                 hdsp->ds_out_channels = RPM_CHANNELS;
5019                 break;
5020
5021         default:
5022                 /* should never get here */
5023                 break;
5024         }
5025 }
5026
5027 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5028 {
5029         snd_hdsp_flush_midi_input (hdsp, 0);
5030         snd_hdsp_flush_midi_input (hdsp, 1);
5031 }
5032
5033 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5034 {
5035         int err;
5036
5037         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5038                 dev_err(card->dev,
5039                         "Error creating pcm interface\n");
5040                 return err;
5041         }
5042
5043
5044         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5045                 dev_err(card->dev,
5046                         "Error creating first midi interface\n");
5047                 return err;
5048         }
5049
5050         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5051                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5052                         dev_err(card->dev,
5053                                 "Error creating second midi interface\n");
5054                         return err;
5055                 }
5056         }
5057
5058         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5059                 dev_err(card->dev,
5060                         "Error creating ctl interface\n");
5061                 return err;
5062         }
5063
5064         snd_hdsp_proc_init(hdsp);
5065
5066         hdsp->system_sample_rate = -1;
5067         hdsp->playback_pid = -1;
5068         hdsp->capture_pid = -1;
5069         hdsp->capture_substream = NULL;
5070         hdsp->playback_substream = NULL;
5071
5072         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5073                 dev_err(card->dev,
5074                         "Error setting default values\n");
5075                 return err;
5076         }
5077
5078         if (!(hdsp->state & HDSP_InitializationComplete)) {
5079                 strcpy(card->shortname, "Hammerfall DSP");
5080                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5081                         hdsp->port, hdsp->irq);
5082
5083                 if ((err = snd_card_register(card)) < 0) {
5084                         dev_err(card->dev,
5085                                 "error registering card\n");
5086                         return err;
5087                 }
5088                 hdsp->state |= HDSP_InitializationComplete;
5089         }
5090
5091         return 0;
5092 }
5093
5094 /* load firmware via hotplug fw loader */
5095 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5096 {
5097         const char *fwfile;
5098         const struct firmware *fw;
5099         int err;
5100
5101         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5102                 return 0;
5103         if (hdsp->io_type == Undefined) {
5104                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5105                         return err;
5106                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5107                         return 0;
5108         }
5109
5110         /* caution: max length of firmware filename is 30! */
5111         switch (hdsp->io_type) {
5112         case RPM:
5113                 fwfile = "/*(DEBLOBBED)*/";
5114                 break;
5115         case Multiface:
5116                 if (hdsp->firmware_rev == 0xa)
5117                         fwfile = "/*(DEBLOBBED)*/";
5118                 else
5119                         fwfile = "/*(DEBLOBBED)*/";
5120                 break;
5121         case Digiface:
5122                 if (hdsp->firmware_rev == 0xa)
5123                         fwfile = "/*(DEBLOBBED)*/";
5124                 else
5125                         fwfile = "/*(DEBLOBBED)*/";
5126                 break;
5127         default:
5128                 dev_err(hdsp->card->dev,
5129                         "invalid io_type %d\n", hdsp->io_type);
5130                 return -EINVAL;
5131         }
5132
5133         if (reject_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5134                 dev_err(hdsp->card->dev,
5135                         "cannot load firmware %s\n", fwfile);
5136                 return -ENOENT;
5137         }
5138         if (fw->size < HDSP_FIRMWARE_SIZE) {
5139                 dev_err(hdsp->card->dev,
5140                         "too short firmware size %d (expected %d)\n",
5141                            (int)fw->size, HDSP_FIRMWARE_SIZE);
5142                 release_firmware(fw);
5143                 return -EINVAL;
5144         }
5145
5146         hdsp->firmware = fw;
5147
5148         hdsp->state |= HDSP_FirmwareCached;
5149
5150         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5151                 return err;
5152
5153         if (!(hdsp->state & HDSP_InitializationComplete)) {
5154                 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5155                         return err;
5156
5157                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5158                         dev_err(hdsp->card->dev,
5159                                 "error creating hwdep device\n");
5160                         return err;
5161                 }
5162                 snd_hdsp_initialize_channels(hdsp);
5163                 snd_hdsp_initialize_midi_flush(hdsp);
5164                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5165                         dev_err(hdsp->card->dev,
5166                                 "error creating alsa devices\n");
5167                         return err;
5168                 }
5169         }
5170         return 0;
5171 }
5172
5173 static int snd_hdsp_create(struct snd_card *card,
5174                            struct hdsp *hdsp)
5175 {
5176         struct pci_dev *pci = hdsp->pci;
5177         int err;
5178         int is_9652 = 0;
5179         int is_9632 = 0;
5180
5181         hdsp->irq = -1;
5182         hdsp->state = 0;
5183         hdsp->midi[0].rmidi = NULL;
5184         hdsp->midi[1].rmidi = NULL;
5185         hdsp->midi[0].input = NULL;
5186         hdsp->midi[1].input = NULL;
5187         hdsp->midi[0].output = NULL;
5188         hdsp->midi[1].output = NULL;
5189         hdsp->midi[0].pending = 0;
5190         hdsp->midi[1].pending = 0;
5191         spin_lock_init(&hdsp->midi[0].lock);
5192         spin_lock_init(&hdsp->midi[1].lock);
5193         hdsp->iobase = NULL;
5194         hdsp->control_register = 0;
5195         hdsp->control2_register = 0;
5196         hdsp->io_type = Undefined;
5197         hdsp->max_channels = 26;
5198
5199         hdsp->card = card;
5200
5201         spin_lock_init(&hdsp->lock);
5202
5203         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5204
5205         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5206         hdsp->firmware_rev &= 0xff;
5207
5208         /* From Martin Bjoernsen :
5209             "It is important that the card's latency timer register in
5210             the PCI configuration space is set to a value much larger
5211             than 0 by the computer's BIOS or the driver.
5212             The windows driver always sets this 8 bit register [...]
5213             to its maximum 255 to avoid problems with some computers."
5214         */
5215         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5216
5217         strcpy(card->driver, "H-DSP");
5218         strcpy(card->mixername, "Xilinx FPGA");
5219
5220         if (hdsp->firmware_rev < 0xa)
5221                 return -ENODEV;
5222         else if (hdsp->firmware_rev < 0x64)
5223                 hdsp->card_name = "RME Hammerfall DSP";
5224         else if (hdsp->firmware_rev < 0x96) {
5225                 hdsp->card_name = "RME HDSP 9652";
5226                 is_9652 = 1;
5227         } else {
5228                 hdsp->card_name = "RME HDSP 9632";
5229                 hdsp->max_channels = 16;
5230                 is_9632 = 1;
5231         }
5232
5233         if ((err = pci_enable_device(pci)) < 0)
5234                 return err;
5235
5236         pci_set_master(hdsp->pci);
5237
5238         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5239                 return err;
5240         hdsp->port = pci_resource_start(pci, 0);
5241         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5242                 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5243                         hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5244                 return -EBUSY;
5245         }
5246
5247         if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5248                         KBUILD_MODNAME, hdsp)) {
5249                 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5250                 return -EBUSY;
5251         }
5252
5253         hdsp->irq = pci->irq;
5254         hdsp->precise_ptr = 0;
5255         hdsp->use_midi_tasklet = 1;
5256         hdsp->dds_value = 0;
5257
5258         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5259                 return err;
5260
5261         if (!is_9652 && !is_9632) {
5262                 /* we wait a maximum of 10 seconds to let freshly
5263                  * inserted cardbus cards do their hardware init */
5264                 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5265
5266                 if (err < 0)
5267                         return err;
5268
5269                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5270                         if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5271                                 /* we don't fail as this can happen
5272                                    if userspace is not ready for
5273                                    firmware upload
5274                                 */
5275                                 dev_err(hdsp->card->dev,
5276                                         "couldn't get firmware from userspace. try using hdsploader\n");
5277                         else
5278                                 /* init is complete, we return */
5279                                 return 0;
5280                         /* we defer initialization */
5281                         dev_info(hdsp->card->dev,
5282                                  "card initialization pending : waiting for firmware\n");
5283                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5284                                 return err;
5285                         return 0;
5286                 } else {
5287                         dev_info(hdsp->card->dev,
5288                                  "Firmware already present, initializing card.\n");
5289                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5290                                 hdsp->io_type = RPM;
5291                         else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5292                                 hdsp->io_type = Multiface;
5293                         else
5294                                 hdsp->io_type = Digiface;
5295                 }
5296         }
5297
5298         if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5299                 return err;
5300
5301         if (is_9652)
5302                 hdsp->io_type = H9652;
5303
5304         if (is_9632)
5305                 hdsp->io_type = H9632;
5306
5307         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5308                 return err;
5309
5310         snd_hdsp_initialize_channels(hdsp);
5311         snd_hdsp_initialize_midi_flush(hdsp);
5312
5313         hdsp->state |= HDSP_FirmwareLoaded;
5314
5315         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5316                 return err;
5317
5318         return 0;
5319 }
5320
5321 static int snd_hdsp_free(struct hdsp *hdsp)
5322 {
5323         if (hdsp->port) {
5324                 /* stop the audio, and cancel all interrupts */
5325                 tasklet_kill(&hdsp->midi_tasklet);
5326                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5327                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5328         }
5329
5330         if (hdsp->irq >= 0)
5331                 free_irq(hdsp->irq, (void *)hdsp);
5332
5333         snd_hdsp_free_buffers(hdsp);
5334
5335         release_firmware(hdsp->firmware);
5336         vfree(hdsp->fw_uploaded);
5337         iounmap(hdsp->iobase);
5338
5339         if (hdsp->port)
5340                 pci_release_regions(hdsp->pci);
5341
5342         if (pci_is_enabled(hdsp->pci))
5343                 pci_disable_device(hdsp->pci);
5344         return 0;
5345 }
5346
5347 static void snd_hdsp_card_free(struct snd_card *card)
5348 {
5349         struct hdsp *hdsp = card->private_data;
5350
5351         if (hdsp)
5352                 snd_hdsp_free(hdsp);
5353 }
5354
5355 static int snd_hdsp_probe(struct pci_dev *pci,
5356                           const struct pci_device_id *pci_id)
5357 {
5358         static int dev;
5359         struct hdsp *hdsp;
5360         struct snd_card *card;
5361         int err;
5362
5363         if (dev >= SNDRV_CARDS)
5364                 return -ENODEV;
5365         if (!enable[dev]) {
5366                 dev++;
5367                 return -ENOENT;
5368         }
5369
5370         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5371                            sizeof(struct hdsp), &card);
5372         if (err < 0)
5373                 return err;
5374
5375         hdsp = card->private_data;
5376         card->private_free = snd_hdsp_card_free;
5377         hdsp->dev = dev;
5378         hdsp->pci = pci;
5379         err = snd_hdsp_create(card, hdsp);
5380         if (err)
5381                 goto free_card;
5382
5383         strcpy(card->shortname, "Hammerfall DSP");
5384         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5385                 hdsp->port, hdsp->irq);
5386         err = snd_card_register(card);
5387         if (err) {
5388 free_card:
5389                 snd_card_free(card);
5390                 return err;
5391         }
5392         pci_set_drvdata(pci, card);
5393         dev++;
5394         return 0;
5395 }
5396
5397 static void snd_hdsp_remove(struct pci_dev *pci)
5398 {
5399         snd_card_free(pci_get_drvdata(pci));
5400 }
5401
5402 static struct pci_driver hdsp_driver = {
5403         .name =     KBUILD_MODNAME,
5404         .id_table = snd_hdsp_ids,
5405         .probe =    snd_hdsp_probe,
5406         .remove = snd_hdsp_remove,
5407 };
5408
5409 module_pci_driver(hdsp_driver);