sound/pci/rme9652/hdsp.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   3  *
   4  *      Copyright (c) 2002  Paul Davis
   5  *                          Marcus Andersson
   6  *                          Thomas Charbonnel
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <linux/math64.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/io.h>
  33 #include <linux/nospec.h>
  34
  35 #include <sound/core.h>
  36 #include <sound/control.h>
  37 #include <sound/pcm.h>
  38 #include <sound/info.h>
  39 #include <sound/asoundef.h>
  40 #include <sound/rawmidi.h>
  41 #include <sound/hwdep.h>
  42 #include <sound/initval.h>
  43 #include <sound/hdsp.h>
  44
  45 #include <asm/byteorder.h>
  46 #include <asm/current.h>
  47
  48 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  49 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  50 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  51
  52 module_param_array(index, int, NULL, 0444);
  53 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  54 module_param_array(id, charp, NULL, 0444);
  55 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  56 module_param_array(enable, bool, NULL, 0444);
  57 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  58 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  59 MODULE_DESCRIPTION("RME Hammerfall DSP");
  60 MODULE_LICENSE("GPL");
  61 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
  62                 "{RME HDSP-9652},"
  63                 "{RME HDSP-9632}}");
  64 /*(DEBLOBBED)*/
  65
  66 #define HDSP_MAX_CHANNELS        26
  67 #define HDSP_MAX_DS_CHANNELS     14
  68 #define HDSP_MAX_QS_CHANNELS     8
  69 #define DIGIFACE_SS_CHANNELS     26
  70 #define DIGIFACE_DS_CHANNELS     14
  71 #define MULTIFACE_SS_CHANNELS    18
  72 #define MULTIFACE_DS_CHANNELS    14
  73 #define H9652_SS_CHANNELS        26
  74 #define H9652_DS_CHANNELS        14
  75 /* This does not include possible Analog Extension Boards
  76    AEBs are detected at card initialization
  77 */
  78 #define H9632_SS_CHANNELS        12
  79 #define H9632_DS_CHANNELS        8
  80 #define H9632_QS_CHANNELS        4
  81 #define RPM_CHANNELS             6
  82
  83 /* Write registers. These are defined as byte-offsets from the iobase value.
  84  */
  85 #define HDSP_resetPointer               0
  86 #define HDSP_freqReg                    0
  87 #define HDSP_outputBufferAddress        32
  88 #define HDSP_inputBufferAddress         36
  89 #define HDSP_controlRegister            64
  90 #define HDSP_interruptConfirmation      96
  91 #define HDSP_outputEnable               128
  92 #define HDSP_control2Reg                256
  93 #define HDSP_midiDataOut0               352
  94 #define HDSP_midiDataOut1               356
  95 #define HDSP_fifoData                   368
  96 #define HDSP_inputEnable                384
  97
  98 /* Read registers. These are defined as byte-offsets from the iobase value
  99  */
 100
 101 #define HDSP_statusRegister    0
 102 #define HDSP_timecode        128
 103 #define HDSP_status2Register 192
 104 #define HDSP_midiDataIn0     360
 105 #define HDSP_midiDataIn1     364
 106 #define HDSP_midiStatusOut0  384
 107 #define HDSP_midiStatusOut1  388
 108 #define HDSP_midiStatusIn0   392
 109 #define HDSP_midiStatusIn1   396
 110 #define HDSP_fifoStatus      400
 111
 112 /* the meters are regular i/o-mapped registers, but offset
 113    considerably from the rest. the peak registers are reset
 114    when read; the least-significant 4 bits are full-scale counters;
 115    the actual peak value is in the most-significant 24 bits.
 116 */
 117
 118 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 119 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 120 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 121 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 122 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 123
 124
 125 /* This is for H9652 cards
 126    Peak values are read downward from the base
 127    Rms values are read upward
 128    There are rms values for the outputs too
 129    26*3 values are read in ss mode
 130    14*3 in ds mode, with no gap between values
 131 */
 132 #define HDSP_9652_peakBase      7164
 133 #define HDSP_9652_rmsBase       4096
 134
 135 /* c.f. the hdsp_9632_meters_t struct */
 136 #define HDSP_9632_metersBase    4096
 137
 138 #define HDSP_IO_EXTENT     7168
 139
 140 /* control2 register bits */
 141
 142 #define HDSP_TMS                0x01
 143 #define HDSP_TCK                0x02
 144 #define HDSP_TDI                0x04
 145 #define HDSP_JTAG               0x08
 146 #define HDSP_PWDN               0x10
 147 #define HDSP_PROGRAM            0x020
 148 #define HDSP_CONFIG_MODE_0      0x040
 149 #define HDSP_CONFIG_MODE_1      0x080
 150 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
 151 #define HDSP_BIGENDIAN_MODE     0x200
 152 #define HDSP_RD_MULTIPLE        0x400
 153 #define HDSP_9652_ENABLE_MIXER  0x800
 154 #define HDSP_S200               0x800
 155 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
 156 #define HDSP_CYCLIC_MODE        0x1000
 157 #define HDSP_TDO                0x10000000
 158
 159 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 160 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 161
 162 /* Control Register bits */
 163
 164 #define HDSP_Start                (1<<0)  /* start engine */
 165 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 166 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 167 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 168 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 169 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 170 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 171 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 172 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 173 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 174 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 175 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 176 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 177 #define HDSP_SyncRef2             (1<<13)
 178 #define HDSP_SPDIFInputSelect0    (1<<14)
 179 #define HDSP_SPDIFInputSelect1    (1<<15)
 180 #define HDSP_SyncRef0             (1<<16)
 181 #define HDSP_SyncRef1             (1<<17)
 182 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 183 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 184 #define HDSP_Midi0InterruptEnable (1<<22)
 185 #define HDSP_Midi1InterruptEnable (1<<23)
 186 #define HDSP_LineOut              (1<<24)
 187 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 188 #define HDSP_ADGain1              (1<<26)
 189 #define HDSP_DAGain0              (1<<27)
 190 #define HDSP_DAGain1              (1<<28)
 191 #define HDSP_PhoneGain0           (1<<29)
 192 #define HDSP_PhoneGain1           (1<<30)
 193 #define HDSP_QuadSpeed            (1<<31)
 194
 195 /* RPM uses some of the registers for special purposes */
 196 #define HDSP_RPM_Inp12            0x04A00
 197 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
 198 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
 199 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
 200 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
 201 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
 202
 203 #define HDSP_RPM_Inp34            0x32000
 204 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
 205 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
 206 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
 207 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
 208 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
 209
 210 #define HDSP_RPM_Bypass           0x01000
 211
 212 #define HDSP_RPM_Disconnect       0x00001
 213
 214 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 215 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 216 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 217 #define HDSP_ADGainLowGain     0
 218
 219 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 220 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 221 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 222 #define HDSP_DAGainMinus10dBV    0
 223
 224 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 225 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 226 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 227 #define HDSP_PhoneGainMinus12dB  0
 228
 229 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 230 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 231
 232 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 233 #define HDSP_SPDIFInputADAT1    0
 234 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 235 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 236 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 237
 238 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 239 #define HDSP_SyncRef_ADAT1       0
 240 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 241 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 242 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 243 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 244 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 245
 246 /* Sample Clock Sources */
 247
 248 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 249 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 250 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 251 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 252 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 253 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 254 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 255 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 256 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 257 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 258
 259 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 260
 261 #define HDSP_SYNC_FROM_WORD      0
 262 #define HDSP_SYNC_FROM_SPDIF     1
 263 #define HDSP_SYNC_FROM_ADAT1     2
 264 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 265 #define HDSP_SYNC_FROM_ADAT2     4
 266 #define HDSP_SYNC_FROM_ADAT3     5
 267
 268 /* SyncCheck status */
 269
 270 #define HDSP_SYNC_CHECK_NO_LOCK 0
 271 #define HDSP_SYNC_CHECK_LOCK    1
 272 #define HDSP_SYNC_CHECK_SYNC    2
 273
 274 /* AutoSync references - used by "autosync_ref" control switch */
 275
 276 #define HDSP_AUTOSYNC_FROM_WORD      0
 277 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 278 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 279 #define HDSP_AUTOSYNC_FROM_NONE      3
 280 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 281 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 282 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 283
 284 /* Possible sources of S/PDIF input */
 285
 286 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 287 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 288 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 289 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 290
 291 #define HDSP_Frequency32KHz    HDSP_Frequency0
 292 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 293 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 294 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 295 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 296 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 297 /* For H9632 cards */
 298 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 299 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 300 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 301 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
 302         return 104857600000000 / rate; // 100 MHz
 303         return 110100480000000 / rate; // 105 MHz
 304 */
 305 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
 306
 307 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 308 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 309
 310 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 311 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 312
 313 /* Status Register bits */
 314
 315 #define HDSP_audioIRQPending    (1<<0)
 316 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 317 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 318 #define HDSP_Lock1              (1<<2)
 319 #define HDSP_Lock0              (1<<3)
 320 #define HDSP_SPDIFSync          (1<<4)
 321 #define HDSP_TimecodeLock       (1<<5)
 322 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 323 #define HDSP_Sync2              (1<<16)
 324 #define HDSP_Sync1              (1<<17)
 325 #define HDSP_Sync0              (1<<18)
 326 #define HDSP_DoubleSpeedStatus  (1<<19)
 327 #define HDSP_ConfigError        (1<<20)
 328 #define HDSP_DllError           (1<<21)
 329 #define HDSP_spdifFrequency0    (1<<22)
 330 #define HDSP_spdifFrequency1    (1<<23)
 331 #define HDSP_spdifFrequency2    (1<<24)
 332 #define HDSP_SPDIFErrorFlag     (1<<25)
 333 #define HDSP_BufferID           (1<<26)
 334 #define HDSP_TimecodeSync       (1<<27)
 335 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 336 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 337 #define HDSP_midi0IRQPending    (1<<30)
 338 #define HDSP_midi1IRQPending    (1<<31)
 339
 340 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 341 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
 342                                       HDSP_spdifFrequency1|\
 343                                       HDSP_spdifFrequency2|\
 344                                       HDSP_spdifFrequency3)
 345
 346 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 347 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 348 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 349
 350 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 351 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 352 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 353
 354 /* This is for H9632 cards */
 355 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
 356                                      HDSP_spdifFrequency1|\
 357                                      HDSP_spdifFrequency2)
 358 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 359 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 360
 361 /* Status2 Register bits */
 362
 363 #define HDSP_version0     (1<<0)
 364 #define HDSP_version1     (1<<1)
 365 #define HDSP_version2     (1<<2)
 366 #define HDSP_wc_lock      (1<<3)
 367 #define HDSP_wc_sync      (1<<4)
 368 #define HDSP_inp_freq0    (1<<5)
 369 #define HDSP_inp_freq1    (1<<6)
 370 #define HDSP_inp_freq2    (1<<7)
 371 #define HDSP_SelSyncRef0  (1<<8)
 372 #define HDSP_SelSyncRef1  (1<<9)
 373 #define HDSP_SelSyncRef2  (1<<10)
 374
 375 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 376
 377 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 378 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 379 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 380 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 381 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 382 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 383 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 384 /* FIXME : more values for 9632 cards ? */
 385
 386 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 387 #define HDSP_SelSyncRef_ADAT1      0
 388 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 389 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 390 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 391 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 392 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 393
 394 /* Card state flags */
 395
 396 #define HDSP_InitializationComplete  (1<<0)
 397 #define HDSP_FirmwareLoaded          (1<<1)
 398 #define HDSP_FirmwareCached          (1<<2)
 399
 400 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 401
 402 #define HDSP_LONG_WAIT   5000
 403 #define HDSP_SHORT_WAIT  30
 404
 405 #define UNITY_GAIN                       32768
 406 #define MINUS_INFINITY_GAIN              0
 407
 408 /* the size of a substream (1 mono data stream) */
 409
 410 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 411 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 412
 413 /* the size of the area we need to allocate for DMA transfers. the
 414    size is the same regardless of the number of channels - the
 415    Multiface still uses the same memory area.
 416
 417    Note that we allocate 1 more channel than is apparently needed
 418    because the h/w seems to write 1 byte beyond the end of the last
 419    page. Sigh.
 420 */
 421
 422 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 423 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 424
 425 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
 426
 427 struct hdsp_9632_meters {
 428     u32 input_peak[16];
 429     u32 playback_peak[16];
 430     u32 output_peak[16];
 431     u32 xxx_peak[16];
 432     u32 padding[64];
 433     u32 input_rms_low[16];
 434     u32 playback_rms_low[16];
 435     u32 output_rms_low[16];
 436     u32 xxx_rms_low[16];
 437     u32 input_rms_high[16];
 438     u32 playback_rms_high[16];
 439     u32 output_rms_high[16];
 440     u32 xxx_rms_high[16];
 441 };
 442
 443 struct hdsp_midi {
 444     struct hdsp             *hdsp;
 445     int                      id;
 446     struct snd_rawmidi           *rmidi;
 447     struct snd_rawmidi_substream *input;
 448     struct snd_rawmidi_substream *output;
 449     char                     istimer; /* timer in use */
 450     struct timer_list        timer;
 451     spinlock_t               lock;
 452     int                      pending;
 453 };
 454
 455 struct hdsp {
 456         spinlock_t            lock;
 457         struct snd_pcm_substream *capture_substream;
 458         struct snd_pcm_substream *playback_substream;
 459         struct hdsp_midi      midi[2];
 460         struct tasklet_struct midi_tasklet;
 461         int                   use_midi_tasklet;
 462         int                   precise_ptr;
 463         u32                   control_register;      /* cached value */
 464         u32                   control2_register;     /* cached value */
 465         u32                   creg_spdif;
 466         u32                   creg_spdif_stream;
 467         int                   clock_source_locked;
 468         char                 *card_name;         /* digiface/multiface/rpm */
 469         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
 470         unsigned short        firmware_rev;
 471         unsigned short        state;                 /* stores state bits */
 472         const struct firmware *firmware;
 473         u32                  *fw_uploaded;
 474         size_t                period_bytes;          /* guess what this is */
 475         unsigned char         max_channels;
 476         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 477         unsigned char         ds_in_channels;
 478         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 479         unsigned char         qs_out_channels;
 480         unsigned char         ds_out_channels;
 481         unsigned char         ss_out_channels;
 482
 483         struct snd_dma_buffer capture_dma_buf;
 484         struct snd_dma_buffer playback_dma_buf;
 485         unsigned char        *capture_buffer;       /* suitably aligned address */
 486         unsigned char        *playback_buffer;      /* suitably aligned address */
 487
 488         pid_t                 capture_pid;
 489         pid_t                 playback_pid;
 490         int                   running;
 491         int                   system_sample_rate;
 492         char                 *channel_map;
 493         int                   dev;
 494         int                   irq;
 495         unsigned long         port;
 496         void __iomem         *iobase;
 497         struct snd_card *card;
 498         struct snd_pcm *pcm;
 499         struct snd_hwdep          *hwdep;
 500         struct pci_dev       *pci;
 501         struct snd_kcontrol *spdif_ctl;
 502         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 503         unsigned int          dds_value; /* last value written to freq register */
 504 };
 505
 506 /* These tables map the ALSA channels 1..N to the channels that we
 507    need to use in order to find the relevant channel buffer. RME
 508    refer to this kind of mapping as between "the ADAT channel and
 509    the DMA channel." We index it using the logical audio channel,
 510    and the value is the DMA channel (i.e. channel buffer number)
 511    where the data for that channel can be read/written from/to.
 512 */
 513
 514 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 515         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 516         18, 19, 20, 21, 22, 23, 24, 25
 517 };
 518
 519 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 520         /* Analog */
 521         0, 1, 2, 3, 4, 5, 6, 7,
 522         /* ADAT 2 */
 523         16, 17, 18, 19, 20, 21, 22, 23,
 524         /* SPDIF */
 525         24, 25,
 526         -1, -1, -1, -1, -1, -1, -1, -1
 527 };
 528
 529 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 530         /* ADAT channels are remapped */
 531         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 532         /* channels 12 and 13 are S/PDIF */
 533         24, 25,
 534         /* others don't exist */
 535         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 536 };
 537
 538 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 539         /* ADAT channels */
 540         0, 1, 2, 3, 4, 5, 6, 7,
 541         /* SPDIF */
 542         8, 9,
 543         /* Analog */
 544         10, 11,
 545         /* AO4S-192 and AI4S-192 extension boards */
 546         12, 13, 14, 15,
 547         /* others don't exist */
 548         -1, -1, -1, -1, -1, -1, -1, -1,
 549         -1, -1
 550 };
 551
 552 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 553         /* ADAT */
 554         1, 3, 5, 7,
 555         /* SPDIF */
 556         8, 9,
 557         /* Analog */
 558         10, 11,
 559         /* AO4S-192 and AI4S-192 extension boards */
 560         12, 13, 14, 15,
 561         /* others don't exist */
 562         -1, -1, -1, -1, -1, -1, -1, -1,
 563         -1, -1, -1, -1, -1, -1
 564 };
 565
 566 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 567         /* ADAT is disabled in this mode */
 568         /* SPDIF */
 569         8, 9,
 570         /* Analog */
 571         10, 11,
 572         /* AO4S-192 and AI4S-192 extension boards */
 573         12, 13, 14, 15,
 574         /* others don't exist */
 575         -1, -1, -1, -1, -1, -1, -1, -1,
 576         -1, -1, -1, -1, -1, -1, -1, -1,
 577         -1, -1
 578 };
 579
 580 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
 581 {
 582         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
 583         dmab->dev.dev = snd_dma_pci_data(pci);
 584         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
 585                                 size, dmab) < 0)
 586                 return -ENOMEM;
 587         return 0;
 588 }
 589
 590 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
 591 {
 592         if (dmab->area)
 593                 snd_dma_free_pages(dmab);
 594 }
 595
 596
 597 static const struct pci_device_id snd_hdsp_ids[] = {
 598         {
 599                 .vendor = PCI_VENDOR_ID_XILINX,
 600                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 601                 .subvendor = PCI_ANY_ID,
 602                 .subdevice = PCI_ANY_ID,
 603         }, /* RME Hammerfall-DSP */
 604         { 0, },
 605 };
 606
 607 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 608
 609 /* prototypes */
 610 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
 611 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
 612 static int snd_hdsp_enable_io (struct hdsp *hdsp);
 613 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
 614 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
 615 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
 616 static int hdsp_autosync_ref(struct hdsp *hdsp);
 617 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
 618 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
 619
 620 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
 621 {
 622         switch (hdsp->io_type) {
 623         case Multiface:
 624         case Digiface:
 625         case RPM:
 626         default:
 627                 if (hdsp->firmware_rev == 0xa)
 628                         return (64 * out) + (32 + (in));
 629                 else
 630                         return (52 * out) + (26 + (in));
 631         case H9632:
 632                 return (32 * out) + (16 + (in));
 633         case H9652:
 634                 return (52 * out) + (26 + (in));
 635         }
 636 }
 637
 638 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
 639 {
 640         switch (hdsp->io_type) {
 641         case Multiface:
 642         case Digiface:
 643         case RPM:
 644         default:
 645                 if (hdsp->firmware_rev == 0xa)
 646                         return (64 * out) + in;
 647                 else
 648                         return (52 * out) + in;
 649         case H9632:
 650                 return (32 * out) + in;
 651         case H9652:
 652                 return (52 * out) + in;
 653         }
 654 }
 655
 656 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
 657 {
 658         writel(val, hdsp->iobase + reg);
 659 }
 660
 661 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
 662 {
 663         return readl (hdsp->iobase + reg);
 664 }
 665
 666 static int hdsp_check_for_iobox (struct hdsp *hdsp)
 667 {
 668         int i;
 669
 670         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 671         for (i = 0; i < 500; i++) {
 672                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
 673                                         HDSP_ConfigError)) {
 674                         if (i) {
 675                                 dev_dbg(hdsp->card->dev,
 676                                         "IO box found after %d ms\n",
 677                                                 (20 * i));
 678                         }
 679                         return 0;
 680                 }
 681                 msleep(20);
 682         }
 683         dev_err(hdsp->card->dev, "no IO box connected!\n");
 684         hdsp->state &= ~HDSP_FirmwareLoaded;
 685         return -EIO;
 686 }
 687
 688 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
 689                                unsigned int delay)
 690 {
 691         unsigned int i;
 692
 693         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 694                 return 0;
 695
 696         for (i = 0; i != loops; ++i) {
 697                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
 698                         msleep(delay);
 699                 else {
 700                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
 701                                    i * delay);
 702                         return 0;
 703                 }
 704         }
 705
 706         dev_info(hdsp->card->dev, "no IO box connected!\n");
 707         hdsp->state &= ~HDSP_FirmwareLoaded;
 708         return -EIO;
 709 }
 710
 711 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
 712
 713         int i;
 714         unsigned long flags;
 715         const u32 *cache;
 716
 717         if (hdsp->fw_uploaded)
 718                 cache = hdsp->fw_uploaded;
 719         else {
 720                 if (!hdsp->firmware)
 721                         return -ENODEV;
 722                 cache = (u32 *)hdsp->firmware->data;
 723                 if (!cache)
 724                         return -ENODEV;
 725         }
 726
 727         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 728
 729                 dev_info(hdsp->card->dev, "loading firmware\n");
 730
 731                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 732                 hdsp_write (hdsp, HDSP_fifoData, 0);
 733
 734                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 735                         dev_info(hdsp->card->dev,
 736                                  "timeout waiting for download preparation\n");
 737                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 738                         return -EIO;
 739                 }
 740
 741                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 742
 743                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
 744                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
 745                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 746                                 dev_info(hdsp->card->dev,
 747                                          "timeout during firmware loading\n");
 748                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 749                                 return -EIO;
 750                         }
 751                 }
 752
 753                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
 754                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 755
 756                 ssleep(3);
 757 #ifdef SNDRV_BIG_ENDIAN
 758                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 759 #else
 760                 hdsp->control2_register = 0;
 761 #endif
 762                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 763                 dev_info(hdsp->card->dev, "finished firmware loading\n");
 764
 765         }
 766         if (hdsp->state & HDSP_InitializationComplete) {
 767                 dev_info(hdsp->card->dev,
 768                          "firmware loaded from cache, restoring defaults\n");
 769                 spin_lock_irqsave(&hdsp->lock, flags);
 770                 snd_hdsp_set_defaults(hdsp);
 771                 spin_unlock_irqrestore(&hdsp->lock, flags);
 772         }
 773
 774         hdsp->state |= HDSP_FirmwareLoaded;
 775
 776         return 0;
 777 }
 778
 779 static int hdsp_get_iobox_version (struct hdsp *hdsp)
 780 {
 781         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 782
 783                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 784                 hdsp_write(hdsp, HDSP_fifoData, 0);
 785
 786                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 787                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 788                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 789                 }
 790
 791                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
 792                 hdsp_write (hdsp, HDSP_fifoData, 0);
 793                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 794                         hdsp->io_type = Multiface;
 795                         dev_info(hdsp->card->dev, "Multiface found\n");
 796                         return 0;
 797                 }
 798
 799                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 800                 hdsp_write(hdsp, HDSP_fifoData, 0);
 801                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 802                         hdsp->io_type = Digiface;
 803                         dev_info(hdsp->card->dev, "Digiface found\n");
 804                         return 0;
 805                 }
 806
 807                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 808                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 809                 hdsp_write(hdsp, HDSP_fifoData, 0);
 810                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 811                         hdsp->io_type = Multiface;
 812                         dev_info(hdsp->card->dev, "Multiface found\n");
 813                         return 0;
 814                 }
 815
 816                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 817                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 818                 hdsp_write(hdsp, HDSP_fifoData, 0);
 819                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 820                         hdsp->io_type = Multiface;
 821                         dev_info(hdsp->card->dev, "Multiface found\n");
 822                         return 0;
 823                 }
 824
 825                 hdsp->io_type = RPM;
 826                 dev_info(hdsp->card->dev, "RPM found\n");
 827                 return 0;
 828         } else {
 829                 /* firmware was already loaded, get iobox type */
 830                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
 831                         hdsp->io_type = RPM;
 832                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
 833                         hdsp->io_type = Multiface;
 834                 else
 835                         hdsp->io_type = Digiface;
 836         }
 837         return 0;
 838 }
 839
 840
 841 static int hdsp_request_fw_loader(struct hdsp *hdsp);
 842
 843 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
 844 {
 845         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 846                 return 0;
 847         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 848                 hdsp->state &= ~HDSP_FirmwareLoaded;
 849                 if (! load_on_demand)
 850                         return -EIO;
 851                 dev_err(hdsp->card->dev, "firmware not present.\n");
 852                 /* try to load firmware */
 853                 if (! (hdsp->state & HDSP_FirmwareCached)) {
 854                         if (! hdsp_request_fw_loader(hdsp))
 855                                 return 0;
 856                         dev_err(hdsp->card->dev,
 857                                    "No firmware loaded nor cached, please upload firmware.\n");
 858                         return -EIO;
 859                 }
 860                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
 861                         dev_err(hdsp->card->dev,
 862                                    "Firmware loading from cache failed, please upload manually.\n");
 863                         return -EIO;
 864                 }
 865         }
 866         return 0;
 867 }
 868
 869
 870 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
 871 {
 872         int i;
 873
 874         /* the fifoStatus registers reports on how many words
 875            are available in the command FIFO.
 876         */
 877
 878         for (i = 0; i < timeout; i++) {
 879
 880                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 881                         return 0;
 882
 883                 /* not very friendly, but we only do this during a firmware
 884                    load and changing the mixer, so we just put up with it.
 885                 */
 886
 887                 udelay (100);
 888         }
 889
 890         dev_warn(hdsp->card->dev,
 891                  "wait for FIFO status <= %d failed after %d iterations\n",
 892                     count, timeout);
 893         return -1;
 894 }
 895
 896 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
 897 {
 898         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 899                 return 0;
 900
 901         return hdsp->mixer_matrix[addr];
 902 }
 903
 904 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
 905 {
 906         unsigned int ad;
 907
 908         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 909                 return -1;
 910
 911         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 912
 913                 /* from martin bjornsen:
 914
 915                    "You can only write dwords to the
 916                    mixer memory which contain two
 917                    mixer values in the low and high
 918                    word. So if you want to change
 919                    value 0 you have to read value 1
 920                    from the cache and write both to
 921                    the first dword in the mixer
 922                    memory."
 923                 */
 924
 925                 if (hdsp->io_type == H9632 && addr >= 512)
 926                         return 0;
 927
 928                 if (hdsp->io_type == H9652 && addr >= 1352)
 929                         return 0;
 930
 931                 hdsp->mixer_matrix[addr] = data;
 932
 933
 934                 /* `addr' addresses a 16-bit wide address, but
 935                    the address space accessed via hdsp_write
 936                    uses byte offsets. put another way, addr
 937                    varies from 0 to 1351, but to access the
 938                    corresponding memory location, we need
 939                    to access 0 to 2703 ...
 940                 */
 941                 ad = addr/2;
 942
 943                 hdsp_write (hdsp, 4096 + (ad*4),
 944                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 945                             hdsp->mixer_matrix[addr&0x7fe]);
 946
 947                 return 0;
 948
 949         } else {
 950
 951                 ad = (addr << 16) + data;
 952
 953                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
 954                         return -1;
 955
 956                 hdsp_write (hdsp, HDSP_fifoData, ad);
 957                 hdsp->mixer_matrix[addr] = data;
 958
 959         }
 960
 961         return 0;
 962 }
 963
 964 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
 965 {
 966         unsigned long flags;
 967         int ret = 1;
 968
 969         spin_lock_irqsave(&hdsp->lock, flags);
 970         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 971             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
 972                 ret = 0;
 973         spin_unlock_irqrestore(&hdsp->lock, flags);
 974         return ret;
 975 }
 976
 977 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
 978 {
 979         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 980         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 981
 982         /* For the 9632, the mask is different */
 983         if (hdsp->io_type == H9632)
 984                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
 985
 986         if (status & HDSP_SPDIFErrorFlag)
 987                 return 0;
 988
 989         switch (rate_bits) {
 990         case HDSP_spdifFrequency32KHz: return 32000;
 991         case HDSP_spdifFrequency44_1KHz: return 44100;
 992         case HDSP_spdifFrequency48KHz: return 48000;
 993         case HDSP_spdifFrequency64KHz: return 64000;
 994         case HDSP_spdifFrequency88_2KHz: return 88200;
 995         case HDSP_spdifFrequency96KHz: return 96000;
 996         case HDSP_spdifFrequency128KHz:
 997                 if (hdsp->io_type == H9632) return 128000;
 998                 break;
 999         case HDSP_spdifFrequency176_4KHz:
1000                 if (hdsp->io_type == H9632) return 176400;
1001                 break;
1002         case HDSP_spdifFrequency192KHz:
1003                 if (hdsp->io_type == H9632) return 192000;
1004                 break;
1005         default:
1006                 break;
1007         }
1008         dev_warn(hdsp->card->dev,
1009                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1010                  rate_bits, status);
1011         return 0;
1012 }
1013
1014 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1015 {
1016         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1017         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1018
1019         /* For the 9632 card, there seems to be no bit for indicating external
1020          * sample rate greater than 96kHz. The card reports the corresponding
1021          * single speed. So the best means seems to get spdif rate when
1022          * autosync reference is spdif */
1023         if (hdsp->io_type == H9632 &&
1024             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1025                  return hdsp_spdif_sample_rate(hdsp);
1026
1027         switch (rate_bits) {
1028         case HDSP_systemFrequency32:   return 32000;
1029         case HDSP_systemFrequency44_1: return 44100;
1030         case HDSP_systemFrequency48:   return 48000;
1031         case HDSP_systemFrequency64:   return 64000;
1032         case HDSP_systemFrequency88_2: return 88200;
1033         case HDSP_systemFrequency96:   return 96000;
1034         default:
1035                 return 0;
1036         }
1037 }
1038
1039 static void hdsp_compute_period_size(struct hdsp *hdsp)
1040 {
1041         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1042 }
1043
1044 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1045 {
1046         int position;
1047
1048         position = hdsp_read(hdsp, HDSP_statusRegister);
1049
1050         if (!hdsp->precise_ptr)
1051                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1052
1053         position &= HDSP_BufferPositionMask;
1054         position /= 4;
1055         position &= (hdsp->period_bytes/2) - 1;
1056         return position;
1057 }
1058
1059 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1060 {
1061         hdsp_write (hdsp, HDSP_resetPointer, 0);
1062         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1063                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1064                  * requires (?) to write again DDS value after a reset pointer
1065                  * (at least, it works like this) */
1066                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1067 }
1068
1069 static void hdsp_start_audio(struct hdsp *s)
1070 {
1071         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1072         hdsp_write(s, HDSP_controlRegister, s->control_register);
1073 }
1074
1075 static void hdsp_stop_audio(struct hdsp *s)
1076 {
1077         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1078         hdsp_write(s, HDSP_controlRegister, s->control_register);
1079 }
1080
1081 static void hdsp_silence_playback(struct hdsp *hdsp)
1082 {
1083         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1084 }
1085
1086 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1087 {
1088         int n;
1089
1090         spin_lock_irq(&s->lock);
1091
1092         frames >>= 7;
1093         n = 0;
1094         while (frames) {
1095                 n++;
1096                 frames >>= 1;
1097         }
1098
1099         s->control_register &= ~HDSP_LatencyMask;
1100         s->control_register |= hdsp_encode_latency(n);
1101
1102         hdsp_write(s, HDSP_controlRegister, s->control_register);
1103
1104         hdsp_compute_period_size(s);
1105
1106         spin_unlock_irq(&s->lock);
1107
1108         return 0;
1109 }
1110
1111 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1112 {
1113         u64 n;
1114
1115         if (rate >= 112000)
1116                 rate /= 4;
1117         else if (rate >= 56000)
1118                 rate /= 2;
1119
1120         n = DDS_NUMERATOR;
1121         n = div_u64(n, rate);
1122         /* n should be less than 2^32 for being written to FREQ register */
1123         snd_BUG_ON(n >> 32);
1124         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1125            value to write it after a reset */
1126         hdsp->dds_value = n;
1127         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1128 }
1129
1130 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1131 {
1132         int reject_if_open = 0;
1133         int current_rate;
1134         int rate_bits;
1135
1136         /* ASSUMPTION: hdsp->lock is either held, or
1137            there is no need for it (e.g. during module
1138            initialization).
1139         */
1140
1141         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1142                 if (called_internally) {
1143                         /* request from ctl or card initialization */
1144                         dev_err(hdsp->card->dev,
1145                                 "device is not running as a clock master: cannot set sample rate.\n");
1146                         return -1;
1147                 } else {
1148                         /* hw_param request while in AutoSync mode */
1149                         int external_freq = hdsp_external_sample_rate(hdsp);
1150                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1151
1152                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1153                                 dev_info(hdsp->card->dev,
1154                                          "Detected ADAT in double speed mode\n");
1155                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1156                                 dev_info(hdsp->card->dev,
1157                                          "Detected ADAT in quad speed mode\n");
1158                         else if (rate != external_freq) {
1159                                 dev_info(hdsp->card->dev,
1160                                          "No AutoSync source for requested rate\n");
1161                                 return -1;
1162                         }
1163                 }
1164         }
1165
1166         current_rate = hdsp->system_sample_rate;
1167
1168         /* Changing from a "single speed" to a "double speed" rate is
1169            not allowed if any substreams are open. This is because
1170            such a change causes a shift in the location of
1171            the DMA buffers and a reduction in the number of available
1172            buffers.
1173
1174            Note that a similar but essentially insoluble problem
1175            exists for externally-driven rate changes. All we can do
1176            is to flag rate changes in the read/write routines.  */
1177
1178         if (rate > 96000 && hdsp->io_type != H9632)
1179                 return -EINVAL;
1180
1181         switch (rate) {
1182         case 32000:
1183                 if (current_rate > 48000)
1184                         reject_if_open = 1;
1185                 rate_bits = HDSP_Frequency32KHz;
1186                 break;
1187         case 44100:
1188                 if (current_rate > 48000)
1189                         reject_if_open = 1;
1190                 rate_bits = HDSP_Frequency44_1KHz;
1191                 break;
1192         case 48000:
1193                 if (current_rate > 48000)
1194                         reject_if_open = 1;
1195                 rate_bits = HDSP_Frequency48KHz;
1196                 break;
1197         case 64000:
1198                 if (current_rate <= 48000 || current_rate > 96000)
1199                         reject_if_open = 1;
1200                 rate_bits = HDSP_Frequency64KHz;
1201                 break;
1202         case 88200:
1203                 if (current_rate <= 48000 || current_rate > 96000)
1204                         reject_if_open = 1;
1205                 rate_bits = HDSP_Frequency88_2KHz;
1206                 break;
1207         case 96000:
1208                 if (current_rate <= 48000 || current_rate > 96000)
1209                         reject_if_open = 1;
1210                 rate_bits = HDSP_Frequency96KHz;
1211                 break;
1212         case 128000:
1213                 if (current_rate < 128000)
1214                         reject_if_open = 1;
1215                 rate_bits = HDSP_Frequency128KHz;
1216                 break;
1217         case 176400:
1218                 if (current_rate < 128000)
1219                         reject_if_open = 1;
1220                 rate_bits = HDSP_Frequency176_4KHz;
1221                 break;
1222         case 192000:
1223                 if (current_rate < 128000)
1224                         reject_if_open = 1;
1225                 rate_bits = HDSP_Frequency192KHz;
1226                 break;
1227         default:
1228                 return -EINVAL;
1229         }
1230
1231         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1232                 dev_warn(hdsp->card->dev,
1233                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1234                             hdsp->capture_pid,
1235                             hdsp->playback_pid);
1236                 return -EBUSY;
1237         }
1238
1239         hdsp->control_register &= ~HDSP_FrequencyMask;
1240         hdsp->control_register |= rate_bits;
1241         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1242
1243         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1244         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1245                 hdsp_set_dds_value(hdsp, rate);
1246
1247         if (rate >= 128000) {
1248                 hdsp->channel_map = channel_map_H9632_qs;
1249         } else if (rate > 48000) {
1250                 if (hdsp->io_type == H9632)
1251                         hdsp->channel_map = channel_map_H9632_ds;
1252                 else
1253                         hdsp->channel_map = channel_map_ds;
1254         } else {
1255                 switch (hdsp->io_type) {
1256                 case RPM:
1257                 case Multiface:
1258                         hdsp->channel_map = channel_map_mf_ss;
1259                         break;
1260                 case Digiface:
1261                 case H9652:
1262                         hdsp->channel_map = channel_map_df_ss;
1263                         break;
1264                 case H9632:
1265                         hdsp->channel_map = channel_map_H9632_ss;
1266                         break;
1267                 default:
1268                         /* should never happen */
1269                         break;
1270                 }
1271         }
1272
1273         hdsp->system_sample_rate = rate;
1274
1275         return 0;
1276 }
1277
1278 /*----------------------------------------------------------------------------
1279    MIDI
1280   ----------------------------------------------------------------------------*/
1281
1282 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1283 {
1284         /* the hardware already does the relevant bit-mask with 0xff */
1285         if (id)
1286                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1287         else
1288                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1289 }
1290
1291 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1292 {
1293         /* the hardware already does the relevant bit-mask with 0xff */
1294         if (id)
1295                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1296         else
1297                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1298 }
1299
1300 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1301 {
1302         if (id)
1303                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1304         else
1305                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1306 }
1307
1308 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1309 {
1310         int fifo_bytes_used;
1311
1312         if (id)
1313                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1314         else
1315                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1316
1317         if (fifo_bytes_used < 128)
1318                 return  128 - fifo_bytes_used;
1319         else
1320                 return 0;
1321 }
1322
1323 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1324 {
1325         while (snd_hdsp_midi_input_available (hdsp, id))
1326                 snd_hdsp_midi_read_byte (hdsp, id);
1327 }
1328
1329 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1330 {
1331         unsigned long flags;
1332         int n_pending;
1333         int to_write;
1334         int i;
1335         unsigned char buf[128];
1336
1337         /* Output is not interrupt driven */
1338
1339         spin_lock_irqsave (&hmidi->lock, flags);
1340         if (hmidi->output) {
1341                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1342                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1343                                 if (n_pending > (int)sizeof (buf))
1344                                         n_pending = sizeof (buf);
1345
1346                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1347                                         for (i = 0; i < to_write; ++i)
1348                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1349                                 }
1350                         }
1351                 }
1352         }
1353         spin_unlock_irqrestore (&hmidi->lock, flags);
1354         return 0;
1355 }
1356
1357 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1358 {
1359         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1360         unsigned long flags;
1361         int n_pending;
1362         int i;
1363
1364         spin_lock_irqsave (&hmidi->lock, flags);
1365         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1366                 if (hmidi->input) {
1367                         if (n_pending > (int)sizeof (buf))
1368                                 n_pending = sizeof (buf);
1369                         for (i = 0; i < n_pending; ++i)
1370                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1371                         if (n_pending)
1372                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1373                 } else {
1374                         /* flush the MIDI input FIFO */
1375                         while (--n_pending)
1376                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1377                 }
1378         }
1379         hmidi->pending = 0;
1380         if (hmidi->id)
1381                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1382         else
1383                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1384         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1385         spin_unlock_irqrestore (&hmidi->lock, flags);
1386         return snd_hdsp_midi_output_write (hmidi);
1387 }
1388
1389 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1390 {
1391         struct hdsp *hdsp;
1392         struct hdsp_midi *hmidi;
1393         unsigned long flags;
1394         u32 ie;
1395
1396         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1397         hdsp = hmidi->hdsp;
1398         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1399         spin_lock_irqsave (&hdsp->lock, flags);
1400         if (up) {
1401                 if (!(hdsp->control_register & ie)) {
1402                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1403                         hdsp->control_register |= ie;
1404                 }
1405         } else {
1406                 hdsp->control_register &= ~ie;
1407                 tasklet_kill(&hdsp->midi_tasklet);
1408         }
1409
1410         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1411         spin_unlock_irqrestore (&hdsp->lock, flags);
1412 }
1413
1414 static void snd_hdsp_midi_output_timer(unsigned long data)
1415 {
1416         struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1417         unsigned long flags;
1418
1419         snd_hdsp_midi_output_write(hmidi);
1420         spin_lock_irqsave (&hmidi->lock, flags);
1421
1422         /* this does not bump hmidi->istimer, because the
1423            kernel automatically removed the timer when it
1424            expired, and we are now adding it back, thus
1425            leaving istimer wherever it was set before.
1426         */
1427
1428         if (hmidi->istimer)
1429                 mod_timer(&hmidi->timer, 1 + jiffies);
1430
1431         spin_unlock_irqrestore (&hmidi->lock, flags);
1432 }
1433
1434 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1435 {
1436         struct hdsp_midi *hmidi;
1437         unsigned long flags;
1438
1439         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1440         spin_lock_irqsave (&hmidi->lock, flags);
1441         if (up) {
1442                 if (!hmidi->istimer) {
1443                         setup_timer(&hmidi->timer, snd_hdsp_midi_output_timer,
1444                                     (unsigned long) hmidi);
1445                         mod_timer(&hmidi->timer, 1 + jiffies);
1446                         hmidi->istimer++;
1447                 }
1448         } else {
1449                 if (hmidi->istimer && --hmidi->istimer <= 0)
1450                         del_timer (&hmidi->timer);
1451         }
1452         spin_unlock_irqrestore (&hmidi->lock, flags);
1453         if (up)
1454                 snd_hdsp_midi_output_write(hmidi);
1455 }
1456
1457 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1458 {
1459         struct hdsp_midi *hmidi;
1460
1461         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1462         spin_lock_irq (&hmidi->lock);
1463         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1464         hmidi->input = substream;
1465         spin_unlock_irq (&hmidi->lock);
1466
1467         return 0;
1468 }
1469
1470 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1471 {
1472         struct hdsp_midi *hmidi;
1473
1474         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1475         spin_lock_irq (&hmidi->lock);
1476         hmidi->output = substream;
1477         spin_unlock_irq (&hmidi->lock);
1478
1479         return 0;
1480 }
1481
1482 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1483 {
1484         struct hdsp_midi *hmidi;
1485
1486         snd_hdsp_midi_input_trigger (substream, 0);
1487
1488         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1489         spin_lock_irq (&hmidi->lock);
1490         hmidi->input = NULL;
1491         spin_unlock_irq (&hmidi->lock);
1492
1493         return 0;
1494 }
1495
1496 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1497 {
1498         struct hdsp_midi *hmidi;
1499
1500         snd_hdsp_midi_output_trigger (substream, 0);
1501
1502         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1503         spin_lock_irq (&hmidi->lock);
1504         hmidi->output = NULL;
1505         spin_unlock_irq (&hmidi->lock);
1506
1507         return 0;
1508 }
1509
1510 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1511 {
1512         .open =         snd_hdsp_midi_output_open,
1513         .close =        snd_hdsp_midi_output_close,
1514         .trigger =      snd_hdsp_midi_output_trigger,
1515 };
1516
1517 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1518 {
1519         .open =         snd_hdsp_midi_input_open,
1520         .close =        snd_hdsp_midi_input_close,
1521         .trigger =      snd_hdsp_midi_input_trigger,
1522 };
1523
1524 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1525 {
1526         char buf[40];
1527
1528         hdsp->midi[id].id = id;
1529         hdsp->midi[id].rmidi = NULL;
1530         hdsp->midi[id].input = NULL;
1531         hdsp->midi[id].output = NULL;
1532         hdsp->midi[id].hdsp = hdsp;
1533         hdsp->midi[id].istimer = 0;
1534         hdsp->midi[id].pending = 0;
1535         spin_lock_init (&hdsp->midi[id].lock);
1536
1537         snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1538         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1539                 return -1;
1540
1541         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1542         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1543
1544         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1545         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1546
1547         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1548                 SNDRV_RAWMIDI_INFO_INPUT |
1549                 SNDRV_RAWMIDI_INFO_DUPLEX;
1550
1551         return 0;
1552 }
1553
1554 /*-----------------------------------------------------------------------------
1555   Control Interface
1556   ----------------------------------------------------------------------------*/
1557
1558 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1559 {
1560         u32 val = 0;
1561         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1562         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1563         if (val & HDSP_SPDIFProfessional)
1564                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1565         else
1566                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1567         return val;
1568 }
1569
1570 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1571 {
1572         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1573                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1574         if (val & HDSP_SPDIFProfessional)
1575                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1576         else
1577                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1578 }
1579
1580 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1581 {
1582         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1583         uinfo->count = 1;
1584         return 0;
1585 }
1586
1587 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1588 {
1589         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1590
1591         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1592         return 0;
1593 }
1594
1595 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1596 {
1597         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1598         int change;
1599         u32 val;
1600
1601         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1602         spin_lock_irq(&hdsp->lock);
1603         change = val != hdsp->creg_spdif;
1604         hdsp->creg_spdif = val;
1605         spin_unlock_irq(&hdsp->lock);
1606         return change;
1607 }
1608
1609 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1610 {
1611         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1612         uinfo->count = 1;
1613         return 0;
1614 }
1615
1616 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1617 {
1618         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1619
1620         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1621         return 0;
1622 }
1623
1624 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1625 {
1626         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1627         int change;
1628         u32 val;
1629
1630         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1631         spin_lock_irq(&hdsp->lock);
1632         change = val != hdsp->creg_spdif_stream;
1633         hdsp->creg_spdif_stream = val;
1634         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1635         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1636         spin_unlock_irq(&hdsp->lock);
1637         return change;
1638 }
1639
1640 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1641 {
1642         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1643         uinfo->count = 1;
1644         return 0;
1645 }
1646
1647 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1648 {
1649         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1650         return 0;
1651 }
1652
1653 #define HDSP_SPDIF_IN(xname, xindex) \
1654 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1655   .name = xname, \
1656   .index = xindex, \
1657   .info = snd_hdsp_info_spdif_in, \
1658   .get = snd_hdsp_get_spdif_in, \
1659   .put = snd_hdsp_put_spdif_in }
1660
1661 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1662 {
1663         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1664 }
1665
1666 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1667 {
1668         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1669         hdsp->control_register |= hdsp_encode_spdif_in(in);
1670         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1671         return 0;
1672 }
1673
1674 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1675 {
1676         static const char * const texts[4] = {
1677                 "Optical", "Coaxial", "Internal", "AES"
1678         };
1679         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1680
1681         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1682                                  texts);
1683 }
1684
1685 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1686 {
1687         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1688
1689         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1690         return 0;
1691 }
1692
1693 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1694 {
1695         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1696         int change;
1697         unsigned int val;
1698
1699         if (!snd_hdsp_use_is_exclusive(hdsp))
1700                 return -EBUSY;
1701         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1702         spin_lock_irq(&hdsp->lock);
1703         change = val != hdsp_spdif_in(hdsp);
1704         if (change)
1705                 hdsp_set_spdif_input(hdsp, val);
1706         spin_unlock_irq(&hdsp->lock);
1707         return change;
1708 }
1709
1710 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1711 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1712         .name = xname, \
1713         .private_value = xindex, \
1714         .info = snd_hdsp_info_toggle_setting, \
1715         .get = snd_hdsp_get_toggle_setting, \
1716         .put = snd_hdsp_put_toggle_setting \
1717 }
1718
1719 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1720 {
1721         return (hdsp->control_register & regmask) ? 1 : 0;
1722 }
1723
1724 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1725 {
1726         if (out)
1727                 hdsp->control_register |= regmask;
1728         else
1729                 hdsp->control_register &= ~regmask;
1730         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1731
1732         return 0;
1733 }
1734
1735 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1736
1737 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1738                 struct snd_ctl_elem_value *ucontrol)
1739 {
1740         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1741         u32 regmask = kcontrol->private_value;
1742
1743         spin_lock_irq(&hdsp->lock);
1744         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1745         spin_unlock_irq(&hdsp->lock);
1746         return 0;
1747 }
1748
1749 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1750                 struct snd_ctl_elem_value *ucontrol)
1751 {
1752         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1753         u32 regmask = kcontrol->private_value;
1754         int change;
1755         unsigned int val;
1756
1757         if (!snd_hdsp_use_is_exclusive(hdsp))
1758                 return -EBUSY;
1759         val = ucontrol->value.integer.value[0] & 1;
1760         spin_lock_irq(&hdsp->lock);
1761         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1762         if (change)
1763                 hdsp_set_toggle_setting(hdsp, regmask, val);
1764         spin_unlock_irq(&hdsp->lock);
1765         return change;
1766 }
1767
1768 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1769 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1770   .name = xname, \
1771   .index = xindex, \
1772   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1773   .info = snd_hdsp_info_spdif_sample_rate, \
1774   .get = snd_hdsp_get_spdif_sample_rate \
1775 }
1776
1777 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1778 {
1779         static const char * const texts[] = {
1780                 "32000", "44100", "48000", "64000", "88200", "96000",
1781                 "None", "128000", "176400", "192000"
1782         };
1783         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1784
1785         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1786                                  texts);
1787 }
1788
1789 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1790 {
1791         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1792
1793         switch (hdsp_spdif_sample_rate(hdsp)) {
1794         case 32000:
1795                 ucontrol->value.enumerated.item[0] = 0;
1796                 break;
1797         case 44100:
1798                 ucontrol->value.enumerated.item[0] = 1;
1799                 break;
1800         case 48000:
1801                 ucontrol->value.enumerated.item[0] = 2;
1802                 break;
1803         case 64000:
1804                 ucontrol->value.enumerated.item[0] = 3;
1805                 break;
1806         case 88200:
1807                 ucontrol->value.enumerated.item[0] = 4;
1808                 break;
1809         case 96000:
1810                 ucontrol->value.enumerated.item[0] = 5;
1811                 break;
1812         case 128000:
1813                 ucontrol->value.enumerated.item[0] = 7;
1814                 break;
1815         case 176400:
1816                 ucontrol->value.enumerated.item[0] = 8;
1817                 break;
1818         case 192000:
1819                 ucontrol->value.enumerated.item[0] = 9;
1820                 break;
1821         default:
1822                 ucontrol->value.enumerated.item[0] = 6;
1823         }
1824         return 0;
1825 }
1826
1827 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1828 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1829   .name = xname, \
1830   .index = xindex, \
1831   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1832   .info = snd_hdsp_info_system_sample_rate, \
1833   .get = snd_hdsp_get_system_sample_rate \
1834 }
1835
1836 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1837 {
1838         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1839         uinfo->count = 1;
1840         return 0;
1841 }
1842
1843 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1844 {
1845         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1846
1847         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1848         return 0;
1849 }
1850
1851 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1852 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1853   .name = xname, \
1854   .index = xindex, \
1855   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1856   .info = snd_hdsp_info_autosync_sample_rate, \
1857   .get = snd_hdsp_get_autosync_sample_rate \
1858 }
1859
1860 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1861 {
1862         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1863         static const char * const texts[] = {
1864                 "32000", "44100", "48000", "64000", "88200", "96000",
1865                 "None", "128000", "176400", "192000"
1866         };
1867
1868         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1869                                  texts);
1870 }
1871
1872 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1873 {
1874         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1875
1876         switch (hdsp_external_sample_rate(hdsp)) {
1877         case 32000:
1878                 ucontrol->value.enumerated.item[0] = 0;
1879                 break;
1880         case 44100:
1881                 ucontrol->value.enumerated.item[0] = 1;
1882                 break;
1883         case 48000:
1884                 ucontrol->value.enumerated.item[0] = 2;
1885                 break;
1886         case 64000:
1887                 ucontrol->value.enumerated.item[0] = 3;
1888                 break;
1889         case 88200:
1890                 ucontrol->value.enumerated.item[0] = 4;
1891                 break;
1892         case 96000:
1893                 ucontrol->value.enumerated.item[0] = 5;
1894                 break;
1895         case 128000:
1896                 ucontrol->value.enumerated.item[0] = 7;
1897                 break;
1898         case 176400:
1899                 ucontrol->value.enumerated.item[0] = 8;
1900                 break;
1901         case 192000:
1902                 ucontrol->value.enumerated.item[0] = 9;
1903                 break;
1904         default:
1905                 ucontrol->value.enumerated.item[0] = 6;
1906         }
1907         return 0;
1908 }
1909
1910 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1911 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1912   .name = xname, \
1913   .index = xindex, \
1914   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1915   .info = snd_hdsp_info_system_clock_mode, \
1916   .get = snd_hdsp_get_system_clock_mode \
1917 }
1918
1919 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1920 {
1921         if (hdsp->control_register & HDSP_ClockModeMaster)
1922                 return 0;
1923         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1924                         return 0;
1925         return 1;
1926 }
1927
1928 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1929 {
1930         static const char * const texts[] = {"Master", "Slave" };
1931
1932         return snd_ctl_enum_info(uinfo, 1, 2, texts);
1933 }
1934
1935 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1936 {
1937         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1938
1939         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1940         return 0;
1941 }
1942
1943 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1944 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1945   .name = xname, \
1946   .index = xindex, \
1947   .info = snd_hdsp_info_clock_source, \
1948   .get = snd_hdsp_get_clock_source, \
1949   .put = snd_hdsp_put_clock_source \
1950 }
1951
1952 static int hdsp_clock_source(struct hdsp *hdsp)
1953 {
1954         if (hdsp->control_register & HDSP_ClockModeMaster) {
1955                 switch (hdsp->system_sample_rate) {
1956                 case 32000:
1957                         return 1;
1958                 case 44100:
1959                         return 2;
1960                 case 48000:
1961                         return 3;
1962                 case 64000:
1963                         return 4;
1964                 case 88200:
1965                         return 5;
1966                 case 96000:
1967                         return 6;
1968                 case 128000:
1969                         return 7;
1970                 case 176400:
1971                         return 8;
1972                 case 192000:
1973                         return 9;
1974                 default:
1975                         return 3;
1976                 }
1977         } else {
1978                 return 0;
1979         }
1980 }
1981
1982 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1983 {
1984         int rate;
1985         switch (mode) {
1986         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1987                 if (hdsp_external_sample_rate(hdsp) != 0) {
1988                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1989                         hdsp->control_register &= ~HDSP_ClockModeMaster;
1990                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1991                         return 0;
1992                     }
1993                 }
1994                 return -1;
1995         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1996                 rate = 32000;
1997                 break;
1998         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1999                 rate = 44100;
2000                 break;
2001         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2002                 rate = 48000;
2003                 break;
2004         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2005                 rate = 64000;
2006                 break;
2007         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2008                 rate = 88200;
2009                 break;
2010         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2011                 rate = 96000;
2012                 break;
2013         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2014                 rate = 128000;
2015                 break;
2016         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2017                 rate = 176400;
2018                 break;
2019         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2020                 rate = 192000;
2021                 break;
2022         default:
2023                 rate = 48000;
2024         }
2025         hdsp->control_register |= HDSP_ClockModeMaster;
2026         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2027         hdsp_set_rate(hdsp, rate, 1);
2028         return 0;
2029 }
2030
2031 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2032 {
2033         static const char * const texts[] = {
2034                 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2035                 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2036                 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2037                 "Internal 192.0 KHz"
2038         };
2039         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2040
2041         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2042                                  texts);
2043 }
2044
2045 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2046 {
2047         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2048
2049         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2050         return 0;
2051 }
2052
2053 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2054 {
2055         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2056         int change;
2057         int val;
2058
2059         if (!snd_hdsp_use_is_exclusive(hdsp))
2060                 return -EBUSY;
2061         val = ucontrol->value.enumerated.item[0];
2062         if (val < 0) val = 0;
2063         if (hdsp->io_type == H9632) {
2064                 if (val > 9)
2065                         val = 9;
2066         } else {
2067                 if (val > 6)
2068                         val = 6;
2069         }
2070         spin_lock_irq(&hdsp->lock);
2071         if (val != hdsp_clock_source(hdsp))
2072                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2073         else
2074                 change = 0;
2075         spin_unlock_irq(&hdsp->lock);
2076         return change;
2077 }
2078
2079 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2080
2081 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2082 {
2083         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2084
2085         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2086         return 0;
2087 }
2088
2089 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2090 {
2091         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2092         int change;
2093
2094         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2095         if (change)
2096                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2097         return change;
2098 }
2099
2100 #define HDSP_DA_GAIN(xname, xindex) \
2101 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2102   .name = xname, \
2103   .index = xindex, \
2104   .info = snd_hdsp_info_da_gain, \
2105   .get = snd_hdsp_get_da_gain, \
2106   .put = snd_hdsp_put_da_gain \
2107 }
2108
2109 static int hdsp_da_gain(struct hdsp *hdsp)
2110 {
2111         switch (hdsp->control_register & HDSP_DAGainMask) {
2112         case HDSP_DAGainHighGain:
2113                 return 0;
2114         case HDSP_DAGainPlus4dBu:
2115                 return 1;
2116         case HDSP_DAGainMinus10dBV:
2117                 return 2;
2118         default:
2119                 return 1;
2120         }
2121 }
2122
2123 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2124 {
2125         hdsp->control_register &= ~HDSP_DAGainMask;
2126         switch (mode) {
2127         case 0:
2128                 hdsp->control_register |= HDSP_DAGainHighGain;
2129                 break;
2130         case 1:
2131                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2132                 break;
2133         case 2:
2134                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2135                 break;
2136         default:
2137                 return -1;
2138
2139         }
2140         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2141         return 0;
2142 }
2143
2144 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2145 {
2146         static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2147
2148         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2149 }
2150
2151 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2152 {
2153         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2154
2155         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2156         return 0;
2157 }
2158
2159 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2160 {
2161         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2162         int change;
2163         int val;
2164
2165         if (!snd_hdsp_use_is_exclusive(hdsp))
2166                 return -EBUSY;
2167         val = ucontrol->value.enumerated.item[0];
2168         if (val < 0) val = 0;
2169         if (val > 2) val = 2;
2170         spin_lock_irq(&hdsp->lock);
2171         if (val != hdsp_da_gain(hdsp))
2172                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2173         else
2174                 change = 0;
2175         spin_unlock_irq(&hdsp->lock);
2176         return change;
2177 }
2178
2179 #define HDSP_AD_GAIN(xname, xindex) \
2180 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2181   .name = xname, \
2182   .index = xindex, \
2183   .info = snd_hdsp_info_ad_gain, \
2184   .get = snd_hdsp_get_ad_gain, \
2185   .put = snd_hdsp_put_ad_gain \
2186 }
2187
2188 static int hdsp_ad_gain(struct hdsp *hdsp)
2189 {
2190         switch (hdsp->control_register & HDSP_ADGainMask) {
2191         case HDSP_ADGainMinus10dBV:
2192                 return 0;
2193         case HDSP_ADGainPlus4dBu:
2194                 return 1;
2195         case HDSP_ADGainLowGain:
2196                 return 2;
2197         default:
2198                 return 1;
2199         }
2200 }
2201
2202 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2203 {
2204         hdsp->control_register &= ~HDSP_ADGainMask;
2205         switch (mode) {
2206         case 0:
2207                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2208                 break;
2209         case 1:
2210                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2211                 break;
2212         case 2:
2213                 hdsp->control_register |= HDSP_ADGainLowGain;
2214                 break;
2215         default:
2216                 return -1;
2217
2218         }
2219         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2220         return 0;
2221 }
2222
2223 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2224 {
2225         static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2226
2227         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2228 }
2229
2230 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2231 {
2232         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2233
2234         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2235         return 0;
2236 }
2237
2238 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2239 {
2240         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2241         int change;
2242         int val;
2243
2244         if (!snd_hdsp_use_is_exclusive(hdsp))
2245                 return -EBUSY;
2246         val = ucontrol->value.enumerated.item[0];
2247         if (val < 0) val = 0;
2248         if (val > 2) val = 2;
2249         spin_lock_irq(&hdsp->lock);
2250         if (val != hdsp_ad_gain(hdsp))
2251                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2252         else
2253                 change = 0;
2254         spin_unlock_irq(&hdsp->lock);
2255         return change;
2256 }
2257
2258 #define HDSP_PHONE_GAIN(xname, xindex) \
2259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2260   .name = xname, \
2261   .index = xindex, \
2262   .info = snd_hdsp_info_phone_gain, \
2263   .get = snd_hdsp_get_phone_gain, \
2264   .put = snd_hdsp_put_phone_gain \
2265 }
2266
2267 static int hdsp_phone_gain(struct hdsp *hdsp)
2268 {
2269         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2270         case HDSP_PhoneGain0dB:
2271                 return 0;
2272         case HDSP_PhoneGainMinus6dB:
2273                 return 1;
2274         case HDSP_PhoneGainMinus12dB:
2275                 return 2;
2276         default:
2277                 return 0;
2278         }
2279 }
2280
2281 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2282 {
2283         hdsp->control_register &= ~HDSP_PhoneGainMask;
2284         switch (mode) {
2285         case 0:
2286                 hdsp->control_register |= HDSP_PhoneGain0dB;
2287                 break;
2288         case 1:
2289                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2290                 break;
2291         case 2:
2292                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2293                 break;
2294         default:
2295                 return -1;
2296
2297         }
2298         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2299         return 0;
2300 }
2301
2302 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2303 {
2304         static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2305
2306         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2307 }
2308
2309 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2310 {
2311         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2312
2313         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2314         return 0;
2315 }
2316
2317 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2318 {
2319         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2320         int change;
2321         int val;
2322
2323         if (!snd_hdsp_use_is_exclusive(hdsp))
2324                 return -EBUSY;
2325         val = ucontrol->value.enumerated.item[0];
2326         if (val < 0) val = 0;
2327         if (val > 2) val = 2;
2328         spin_lock_irq(&hdsp->lock);
2329         if (val != hdsp_phone_gain(hdsp))
2330                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2331         else
2332                 change = 0;
2333         spin_unlock_irq(&hdsp->lock);
2334         return change;
2335 }
2336
2337 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2338 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2339   .name = xname, \
2340   .index = xindex, \
2341   .info = snd_hdsp_info_pref_sync_ref, \
2342   .get = snd_hdsp_get_pref_sync_ref, \
2343   .put = snd_hdsp_put_pref_sync_ref \
2344 }
2345
2346 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2347 {
2348         /* Notice that this looks at the requested sync source,
2349            not the one actually in use.
2350         */
2351
2352         switch (hdsp->control_register & HDSP_SyncRefMask) {
2353         case HDSP_SyncRef_ADAT1:
2354                 return HDSP_SYNC_FROM_ADAT1;
2355         case HDSP_SyncRef_ADAT2:
2356                 return HDSP_SYNC_FROM_ADAT2;
2357         case HDSP_SyncRef_ADAT3:
2358                 return HDSP_SYNC_FROM_ADAT3;
2359         case HDSP_SyncRef_SPDIF:
2360                 return HDSP_SYNC_FROM_SPDIF;
2361         case HDSP_SyncRef_WORD:
2362                 return HDSP_SYNC_FROM_WORD;
2363         case HDSP_SyncRef_ADAT_SYNC:
2364                 return HDSP_SYNC_FROM_ADAT_SYNC;
2365         default:
2366                 return HDSP_SYNC_FROM_WORD;
2367         }
2368         return 0;
2369 }
2370
2371 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2372 {
2373         hdsp->control_register &= ~HDSP_SyncRefMask;
2374         switch (pref) {
2375         case HDSP_SYNC_FROM_ADAT1:
2376                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2377                 break;
2378         case HDSP_SYNC_FROM_ADAT2:
2379                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2380                 break;
2381         case HDSP_SYNC_FROM_ADAT3:
2382                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2383                 break;
2384         case HDSP_SYNC_FROM_SPDIF:
2385                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2386                 break;
2387         case HDSP_SYNC_FROM_WORD:
2388                 hdsp->control_register |= HDSP_SyncRef_WORD;
2389                 break;
2390         case HDSP_SYNC_FROM_ADAT_SYNC:
2391                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2392                 break;
2393         default:
2394                 return -1;
2395         }
2396         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2397         return 0;
2398 }
2399
2400 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2401 {
2402         static const char * const texts[] = {
2403                 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2404         };
2405         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2406         int num_items;
2407
2408         switch (hdsp->io_type) {
2409         case Digiface:
2410         case H9652:
2411                 num_items = 6;
2412                 break;
2413         case Multiface:
2414                 num_items = 4;
2415                 break;
2416         case H9632:
2417                 num_items = 3;
2418                 break;
2419         default:
2420                 return -EINVAL;
2421         }
2422
2423         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2424 }
2425
2426 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2427 {
2428         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2429
2430         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2431         return 0;
2432 }
2433
2434 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2435 {
2436         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2437         int change, max;
2438         unsigned int val;
2439
2440         if (!snd_hdsp_use_is_exclusive(hdsp))
2441                 return -EBUSY;
2442
2443         switch (hdsp->io_type) {
2444         case Digiface:
2445         case H9652:
2446                 max = 6;
2447                 break;
2448         case Multiface:
2449                 max = 4;
2450                 break;
2451         case H9632:
2452                 max = 3;
2453                 break;
2454         default:
2455                 return -EIO;
2456         }
2457
2458         val = ucontrol->value.enumerated.item[0] % max;
2459         spin_lock_irq(&hdsp->lock);
2460         change = (int)val != hdsp_pref_sync_ref(hdsp);
2461         hdsp_set_pref_sync_ref(hdsp, val);
2462         spin_unlock_irq(&hdsp->lock);
2463         return change;
2464 }
2465
2466 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2467 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2468   .name = xname, \
2469   .index = xindex, \
2470   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2471   .info = snd_hdsp_info_autosync_ref, \
2472   .get = snd_hdsp_get_autosync_ref, \
2473 }
2474
2475 static int hdsp_autosync_ref(struct hdsp *hdsp)
2476 {
2477         /* This looks at the autosync selected sync reference */
2478         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2479
2480         switch (status2 & HDSP_SelSyncRefMask) {
2481         case HDSP_SelSyncRef_WORD:
2482                 return HDSP_AUTOSYNC_FROM_WORD;
2483         case HDSP_SelSyncRef_ADAT_SYNC:
2484                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2485         case HDSP_SelSyncRef_SPDIF:
2486                 return HDSP_AUTOSYNC_FROM_SPDIF;
2487         case HDSP_SelSyncRefMask:
2488                 return HDSP_AUTOSYNC_FROM_NONE;
2489         case HDSP_SelSyncRef_ADAT1:
2490                 return HDSP_AUTOSYNC_FROM_ADAT1;
2491         case HDSP_SelSyncRef_ADAT2:
2492                 return HDSP_AUTOSYNC_FROM_ADAT2;
2493         case HDSP_SelSyncRef_ADAT3:
2494                 return HDSP_AUTOSYNC_FROM_ADAT3;
2495         default:
2496                 return HDSP_AUTOSYNC_FROM_WORD;
2497         }
2498         return 0;
2499 }
2500
2501 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2502 {
2503         static const char * const texts[] = {
2504                 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2505         };
2506
2507         return snd_ctl_enum_info(uinfo, 1, 7, texts);
2508 }
2509
2510 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2511 {
2512         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2513
2514         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2515         return 0;
2516 }
2517
2518 #define HDSP_PRECISE_POINTER(xname, xindex) \
2519 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2520   .name = xname, \
2521   .index = xindex, \
2522   .info = snd_hdsp_info_precise_pointer, \
2523   .get = snd_hdsp_get_precise_pointer, \
2524   .put = snd_hdsp_put_precise_pointer \
2525 }
2526
2527 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2528 {
2529         if (precise)
2530                 hdsp->precise_ptr = 1;
2531         else
2532                 hdsp->precise_ptr = 0;
2533         return 0;
2534 }
2535
2536 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2537
2538 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2539 {
2540         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2541
2542         spin_lock_irq(&hdsp->lock);
2543         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2544         spin_unlock_irq(&hdsp->lock);
2545         return 0;
2546 }
2547
2548 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2549 {
2550         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2551         int change;
2552         unsigned int val;
2553
2554         if (!snd_hdsp_use_is_exclusive(hdsp))
2555                 return -EBUSY;
2556         val = ucontrol->value.integer.value[0] & 1;
2557         spin_lock_irq(&hdsp->lock);
2558         change = (int)val != hdsp->precise_ptr;
2559         hdsp_set_precise_pointer(hdsp, val);
2560         spin_unlock_irq(&hdsp->lock);
2561         return change;
2562 }
2563
2564 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2565 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2566   .name = xname, \
2567   .index = xindex, \
2568   .info = snd_hdsp_info_use_midi_tasklet, \
2569   .get = snd_hdsp_get_use_midi_tasklet, \
2570   .put = snd_hdsp_put_use_midi_tasklet \
2571 }
2572
2573 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2574 {
2575         if (use_tasklet)
2576                 hdsp->use_midi_tasklet = 1;
2577         else
2578                 hdsp->use_midi_tasklet = 0;
2579         return 0;
2580 }
2581
2582 #define snd_hdsp_info_use_midi_tasklet          snd_ctl_boolean_mono_info
2583
2584 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2585 {
2586         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2587
2588         spin_lock_irq(&hdsp->lock);
2589         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2590         spin_unlock_irq(&hdsp->lock);
2591         return 0;
2592 }
2593
2594 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2595 {
2596         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2597         int change;
2598         unsigned int val;
2599
2600         if (!snd_hdsp_use_is_exclusive(hdsp))
2601                 return -EBUSY;
2602         val = ucontrol->value.integer.value[0] & 1;
2603         spin_lock_irq(&hdsp->lock);
2604         change = (int)val != hdsp->use_midi_tasklet;
2605         hdsp_set_use_midi_tasklet(hdsp, val);
2606         spin_unlock_irq(&hdsp->lock);
2607         return change;
2608 }
2609
2610 #define HDSP_MIXER(xname, xindex) \
2611 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2612   .name = xname, \
2613   .index = xindex, \
2614   .device = 0, \
2615   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2616                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2617   .info = snd_hdsp_info_mixer, \
2618   .get = snd_hdsp_get_mixer, \
2619   .put = snd_hdsp_put_mixer \
2620 }
2621
2622 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2623 {
2624         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2625         uinfo->count = 3;
2626         uinfo->value.integer.min = 0;
2627         uinfo->value.integer.max = 65536;
2628         uinfo->value.integer.step = 1;
2629         return 0;
2630 }
2631
2632 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2633 {
2634         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2635         int source;
2636         int destination;
2637         int addr;
2638
2639         source = ucontrol->value.integer.value[0];
2640         destination = ucontrol->value.integer.value[1];
2641
2642         if (source >= hdsp->max_channels)
2643                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2644         else
2645                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2646
2647         spin_lock_irq(&hdsp->lock);
2648         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2649         spin_unlock_irq(&hdsp->lock);
2650         return 0;
2651 }
2652
2653 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2654 {
2655         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2656         int change;
2657         int source;
2658         int destination;
2659         int gain;
2660         int addr;
2661
2662         if (!snd_hdsp_use_is_exclusive(hdsp))
2663                 return -EBUSY;
2664
2665         source = ucontrol->value.integer.value[0];
2666         destination = ucontrol->value.integer.value[1];
2667
2668         if (source >= hdsp->max_channels)
2669                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2670         else
2671                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2672
2673         gain = ucontrol->value.integer.value[2];
2674
2675         spin_lock_irq(&hdsp->lock);
2676         change = gain != hdsp_read_gain(hdsp, addr);
2677         if (change)
2678                 hdsp_write_gain(hdsp, addr, gain);
2679         spin_unlock_irq(&hdsp->lock);
2680         return change;
2681 }
2682
2683 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2684 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2685   .name = xname, \
2686   .index = xindex, \
2687   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2688   .info = snd_hdsp_info_sync_check, \
2689   .get = snd_hdsp_get_wc_sync_check \
2690 }
2691
2692 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2693 {
2694         static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2695
2696         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2697 }
2698
2699 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2700 {
2701         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2702         if (status2 & HDSP_wc_lock) {
2703                 if (status2 & HDSP_wc_sync)
2704                         return 2;
2705                 else
2706                          return 1;
2707         } else
2708                 return 0;
2709         return 0;
2710 }
2711
2712 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2713 {
2714         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2715
2716         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2717         return 0;
2718 }
2719
2720 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2721 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2722   .name = xname, \
2723   .index = xindex, \
2724   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2725   .info = snd_hdsp_info_sync_check, \
2726   .get = snd_hdsp_get_spdif_sync_check \
2727 }
2728
2729 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2730 {
2731         int status = hdsp_read(hdsp, HDSP_statusRegister);
2732         if (status & HDSP_SPDIFErrorFlag)
2733                 return 0;
2734         else {
2735                 if (status & HDSP_SPDIFSync)
2736                         return 2;
2737                 else
2738                         return 1;
2739         }
2740         return 0;
2741 }
2742
2743 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2744 {
2745         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2746
2747         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2748         return 0;
2749 }
2750
2751 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2752 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2753   .name = xname, \
2754   .index = xindex, \
2755   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2756   .info = snd_hdsp_info_sync_check, \
2757   .get = snd_hdsp_get_adatsync_sync_check \
2758 }
2759
2760 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2761 {
2762         int status = hdsp_read(hdsp, HDSP_statusRegister);
2763         if (status & HDSP_TimecodeLock) {
2764                 if (status & HDSP_TimecodeSync)
2765                         return 2;
2766                 else
2767                         return 1;
2768         } else
2769                 return 0;
2770 }
2771
2772 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2773 {
2774         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2775
2776         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2777         return 0;
2778 }
2779
2780 #define HDSP_ADAT_SYNC_CHECK \
2781 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2782   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2783   .info = snd_hdsp_info_sync_check, \
2784   .get = snd_hdsp_get_adat_sync_check \
2785 }
2786
2787 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2788 {
2789         int status = hdsp_read(hdsp, HDSP_statusRegister);
2790
2791         if (status & (HDSP_Lock0>>idx)) {
2792                 if (status & (HDSP_Sync0>>idx))
2793                         return 2;
2794                 else
2795                         return 1;
2796         } else
2797                 return 0;
2798 }
2799
2800 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2801 {
2802         int offset;
2803         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2804
2805         offset = ucontrol->id.index - 1;
2806         if (snd_BUG_ON(offset < 0))
2807                 return -EINVAL;
2808
2809         switch (hdsp->io_type) {
2810         case Digiface:
2811         case H9652:
2812                 if (offset >= 3)
2813                         return -EINVAL;
2814                 break;
2815         case Multiface:
2816         case H9632:
2817                 if (offset >= 1)
2818                         return -EINVAL;
2819                 break;
2820         default:
2821                 return -EIO;
2822         }
2823
2824         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2825         return 0;
2826 }
2827
2828 #define HDSP_DDS_OFFSET(xname, xindex) \
2829 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2830   .name = xname, \
2831   .index = xindex, \
2832   .info = snd_hdsp_info_dds_offset, \
2833   .get = snd_hdsp_get_dds_offset, \
2834   .put = snd_hdsp_put_dds_offset \
2835 }
2836
2837 static int hdsp_dds_offset(struct hdsp *hdsp)
2838 {
2839         u64 n;
2840         unsigned int dds_value = hdsp->dds_value;
2841         int system_sample_rate = hdsp->system_sample_rate;
2842
2843         if (!dds_value)
2844                 return 0;
2845
2846         n = DDS_NUMERATOR;
2847         /*
2848          * dds_value = n / rate
2849          * rate = n / dds_value
2850          */
2851         n = div_u64(n, dds_value);
2852         if (system_sample_rate >= 112000)
2853                 n *= 4;
2854         else if (system_sample_rate >= 56000)
2855                 n *= 2;
2856         return ((int)n) - system_sample_rate;
2857 }
2858
2859 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2860 {
2861         int rate = hdsp->system_sample_rate + offset_hz;
2862         hdsp_set_dds_value(hdsp, rate);
2863         return 0;
2864 }
2865
2866 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2867 {
2868         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2869         uinfo->count = 1;
2870         uinfo->value.integer.min = -5000;
2871         uinfo->value.integer.max = 5000;
2872         return 0;
2873 }
2874
2875 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2876 {
2877         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2878
2879         ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2880         return 0;
2881 }
2882
2883 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2884 {
2885         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2886         int change;
2887         int val;
2888
2889         if (!snd_hdsp_use_is_exclusive(hdsp))
2890                 return -EBUSY;
2891         val = ucontrol->value.integer.value[0];
2892         spin_lock_irq(&hdsp->lock);
2893         if (val != hdsp_dds_offset(hdsp))
2894                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2895         else
2896                 change = 0;
2897         spin_unlock_irq(&hdsp->lock);
2898         return change;
2899 }
2900
2901 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2902 HDSP_DA_GAIN("DA Gain", 0),
2903 HDSP_AD_GAIN("AD Gain", 0),
2904 HDSP_PHONE_GAIN("Phones Gain", 0),
2905 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2906 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2907 };
2908
2909 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2910 {
2911         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2912         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2913         .info =         snd_hdsp_control_spdif_info,
2914         .get =          snd_hdsp_control_spdif_get,
2915         .put =          snd_hdsp_control_spdif_put,
2916 },
2917 {
2918         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2919         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2920         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2921         .info =         snd_hdsp_control_spdif_stream_info,
2922         .get =          snd_hdsp_control_spdif_stream_get,
2923         .put =          snd_hdsp_control_spdif_stream_put,
2924 },
2925 {
2926         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2927         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2928         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2929         .info =         snd_hdsp_control_spdif_mask_info,
2930         .get =          snd_hdsp_control_spdif_mask_get,
2931         .private_value = IEC958_AES0_NONAUDIO |
2932                          IEC958_AES0_PROFESSIONAL |
2933                          IEC958_AES0_CON_EMPHASIS,
2934 },
2935 {
2936         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2937         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2938         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2939         .info =         snd_hdsp_control_spdif_mask_info,
2940         .get =          snd_hdsp_control_spdif_mask_get,
2941         .private_value = IEC958_AES0_NONAUDIO |
2942                          IEC958_AES0_PROFESSIONAL |
2943                          IEC958_AES0_PRO_EMPHASIS,
2944 },
2945 HDSP_MIXER("Mixer", 0),
2946 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2947 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2948 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2949 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2950 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2951 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2952 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2953 {
2954         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2955         .name = "Sample Clock Source Locking",
2956         .info = snd_hdsp_info_clock_source_lock,
2957         .get = snd_hdsp_get_clock_source_lock,
2958         .put = snd_hdsp_put_clock_source_lock,
2959 },
2960 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2961 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2962 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2963 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2964 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2965 /* 'External Rate' complies with the alsa control naming scheme */
2966 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2967 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2968 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2969 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2970 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2971 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2972 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2973 };
2974
2975
2976 static int hdsp_rpm_input12(struct hdsp *hdsp)
2977 {
2978         switch (hdsp->control_register & HDSP_RPM_Inp12) {
2979         case HDSP_RPM_Inp12_Phon_6dB:
2980                 return 0;
2981         case HDSP_RPM_Inp12_Phon_n6dB:
2982                 return 2;
2983         case HDSP_RPM_Inp12_Line_0dB:
2984                 return 3;
2985         case HDSP_RPM_Inp12_Line_n6dB:
2986                 return 4;
2987         }
2988         return 1;
2989 }
2990
2991
2992 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2993 {
2994         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2995
2996         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2997         return 0;
2998 }
2999
3000
3001 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3002 {
3003         hdsp->control_register &= ~HDSP_RPM_Inp12;
3004         switch (mode) {
3005         case 0:
3006                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3007                 break;
3008         case 1:
3009                 break;
3010         case 2:
3011                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3012                 break;
3013         case 3:
3014                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3015                 break;
3016         case 4:
3017                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3018                 break;
3019         default:
3020                 return -1;
3021         }
3022
3023         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3024         return 0;
3025 }
3026
3027
3028 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3029 {
3030         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3031         int change;
3032         int val;
3033
3034         if (!snd_hdsp_use_is_exclusive(hdsp))
3035                 return -EBUSY;
3036         val = ucontrol->value.enumerated.item[0];
3037         if (val < 0)
3038                 val = 0;
3039         if (val > 4)
3040                 val = 4;
3041         spin_lock_irq(&hdsp->lock);
3042         if (val != hdsp_rpm_input12(hdsp))
3043                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3044         else
3045                 change = 0;
3046         spin_unlock_irq(&hdsp->lock);
3047         return change;
3048 }
3049
3050
3051 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3052 {
3053         static const char * const texts[] = {
3054                 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3055         };
3056
3057         return snd_ctl_enum_info(uinfo, 1, 5, texts);
3058 }
3059
3060
3061 static int hdsp_rpm_input34(struct hdsp *hdsp)
3062 {
3063         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3064         case HDSP_RPM_Inp34_Phon_6dB:
3065                 return 0;
3066         case HDSP_RPM_Inp34_Phon_n6dB:
3067                 return 2;
3068         case HDSP_RPM_Inp34_Line_0dB:
3069                 return 3;
3070         case HDSP_RPM_Inp34_Line_n6dB:
3071                 return 4;
3072         }
3073         return 1;
3074 }
3075
3076
3077 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3078 {
3079         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3080
3081         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3082         return 0;
3083 }
3084
3085
3086 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3087 {
3088         hdsp->control_register &= ~HDSP_RPM_Inp34;
3089         switch (mode) {
3090         case 0:
3091                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3092                 break;
3093         case 1:
3094                 break;
3095         case 2:
3096                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3097                 break;
3098         case 3:
3099                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3100                 break;
3101         case 4:
3102                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3103                 break;
3104         default:
3105                 return -1;
3106         }
3107
3108         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3109         return 0;
3110 }
3111
3112
3113 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3114 {
3115         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3116         int change;
3117         int val;
3118
3119         if (!snd_hdsp_use_is_exclusive(hdsp))
3120                 return -EBUSY;
3121         val = ucontrol->value.enumerated.item[0];
3122         if (val < 0)
3123                 val = 0;
3124         if (val > 4)
3125                 val = 4;
3126         spin_lock_irq(&hdsp->lock);
3127         if (val != hdsp_rpm_input34(hdsp))
3128                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3129         else
3130                 change = 0;
3131         spin_unlock_irq(&hdsp->lock);
3132         return change;
3133 }
3134
3135
3136 /* RPM Bypass switch */
3137 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3138 {
3139         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3140 }
3141
3142
3143 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3144 {
3145         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3146
3147         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3148         return 0;
3149 }
3150
3151
3152 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3153 {
3154         if (on)
3155                 hdsp->control_register |= HDSP_RPM_Bypass;
3156         else
3157                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3158         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3159         return 0;
3160 }
3161
3162
3163 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3164 {
3165         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3166         int change;
3167         unsigned int val;
3168
3169         if (!snd_hdsp_use_is_exclusive(hdsp))
3170                 return -EBUSY;
3171         val = ucontrol->value.integer.value[0] & 1;
3172         spin_lock_irq(&hdsp->lock);
3173         change = (int)val != hdsp_rpm_bypass(hdsp);
3174         hdsp_set_rpm_bypass(hdsp, val);
3175         spin_unlock_irq(&hdsp->lock);
3176         return change;
3177 }
3178
3179
3180 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3181 {
3182         static const char * const texts[] = {"On", "Off"};
3183
3184         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3185 }
3186
3187
3188 /* RPM Disconnect switch */
3189 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3190 {
3191         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3192 }
3193
3194
3195 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3196 {
3197         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3198
3199         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3200         return 0;
3201 }
3202
3203
3204 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3205 {
3206         if (on)
3207                 hdsp->control_register |= HDSP_RPM_Disconnect;
3208         else
3209                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3210         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3211         return 0;
3212 }
3213
3214
3215 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3216 {
3217         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3218         int change;
3219         unsigned int val;
3220
3221         if (!snd_hdsp_use_is_exclusive(hdsp))
3222                 return -EBUSY;
3223         val = ucontrol->value.integer.value[0] & 1;
3224         spin_lock_irq(&hdsp->lock);
3225         change = (int)val != hdsp_rpm_disconnect(hdsp);
3226         hdsp_set_rpm_disconnect(hdsp, val);
3227         spin_unlock_irq(&hdsp->lock);
3228         return change;
3229 }
3230
3231 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3232 {
3233         static const char * const texts[] = {"On", "Off"};
3234
3235         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3236 }
3237
3238 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3239         {
3240                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3241                 .name = "RPM Bypass",
3242                 .get = snd_hdsp_get_rpm_bypass,
3243                 .put = snd_hdsp_put_rpm_bypass,
3244                 .info = snd_hdsp_info_rpm_bypass
3245         },
3246         {
3247                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3248                 .name = "RPM Disconnect",
3249                 .get = snd_hdsp_get_rpm_disconnect,
3250                 .put = snd_hdsp_put_rpm_disconnect,
3251                 .info = snd_hdsp_info_rpm_disconnect
3252         },
3253         {
3254                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3255                 .name = "Input 1/2",
3256                 .get = snd_hdsp_get_rpm_input12,
3257                 .put = snd_hdsp_put_rpm_input12,
3258                 .info = snd_hdsp_info_rpm_input
3259         },
3260         {
3261                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3262                 .name = "Input 3/4",
3263                 .get = snd_hdsp_get_rpm_input34,
3264                 .put = snd_hdsp_put_rpm_input34,
3265                 .info = snd_hdsp_info_rpm_input
3266         },
3267         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3268         HDSP_MIXER("Mixer", 0)
3269 };
3270
3271 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3272         HDSP_TOGGLE_SETTING("Analog Extension Board",
3273                         HDSP_AnalogExtensionBoard);
3274 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3275
3276 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3277 {
3278         unsigned int idx;
3279         int err;
3280         struct snd_kcontrol *kctl;
3281
3282         if (hdsp->io_type == RPM) {
3283                 /* RPM Bypass, Disconnect and Input switches */
3284                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3285                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3286                         if (err < 0)
3287                                 return err;
3288                 }
3289                 return 0;
3290         }
3291
3292         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3293                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3294                         return err;
3295                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3296                         hdsp->spdif_ctl = kctl;
3297         }
3298
3299         /* ADAT SyncCheck status */
3300         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3301         snd_hdsp_adat_sync_check.index = 1;
3302         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3303                 return err;
3304         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3305                 for (idx = 1; idx < 3; ++idx) {
3306                         snd_hdsp_adat_sync_check.index = idx+1;
3307                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3308                                 return err;
3309                 }
3310         }
3311
3312         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3313         if (hdsp->io_type == H9632) {
3314                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3315                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3316                                 return err;
3317                 }
3318         }
3319
3320         /* AEB control for H96xx card */
3321         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3322                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3323                                 return err;
3324         }
3325
3326         return 0;
3327 }
3328
3329 /*------------------------------------------------------------
3330    /proc interface
3331  ------------------------------------------------------------*/
3332
3333 static void
3334 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3335 {
3336         struct hdsp *hdsp = entry->private_data;
3337         unsigned int status;
3338         unsigned int status2;
3339         char *pref_sync_ref;
3340         char *autosync_ref;
3341         char *system_clock_mode;
3342         char *clock_source;
3343         int x;
3344
3345         status = hdsp_read(hdsp, HDSP_statusRegister);
3346         status2 = hdsp_read(hdsp, HDSP_status2Register);
3347
3348         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3349                     hdsp->card->number + 1);
3350         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3351                     hdsp->capture_buffer, hdsp->playback_buffer);
3352         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3353                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3354         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3355         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3356                     hdsp->control2_register);
3357         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3358         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3359
3360         if (hdsp_check_for_iobox(hdsp)) {
3361                 snd_iprintf(buffer, "No I/O box connected.\n"
3362                             "Please connect one and upload firmware.\n");
3363                 return;
3364         }
3365
3366         if (hdsp_check_for_firmware(hdsp, 0)) {
3367                 if (hdsp->state & HDSP_FirmwareCached) {
3368                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3369                                 snd_iprintf(buffer, "Firmware loading from "
3370                                             "cache failed, "
3371                                             "please upload manually.\n");
3372                                 return;
3373                         }
3374                 } else {
3375                         int err = -EINVAL;
3376                         err = hdsp_request_fw_loader(hdsp);
3377                         if (err < 0) {
3378                                 snd_iprintf(buffer,
3379                                             "No firmware loaded nor cached, "
3380                                             "please upload firmware.\n");
3381                                 return;
3382                         }
3383                 }
3384         }
3385
3386         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3387         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3388         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3389         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3390         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3391         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3392
3393         snd_iprintf(buffer, "\n");
3394
3395         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3396
3397         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3398         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3399         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3400         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3401
3402         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3403
3404         snd_iprintf(buffer, "\n");
3405
3406         switch (hdsp_clock_source(hdsp)) {
3407         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3408                 clock_source = "AutoSync";
3409                 break;
3410         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3411                 clock_source = "Internal 32 kHz";
3412                 break;
3413         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3414                 clock_source = "Internal 44.1 kHz";
3415                 break;
3416         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3417                 clock_source = "Internal 48 kHz";
3418                 break;
3419         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3420                 clock_source = "Internal 64 kHz";
3421                 break;
3422         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3423                 clock_source = "Internal 88.2 kHz";
3424                 break;
3425         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3426                 clock_source = "Internal 96 kHz";
3427                 break;
3428         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3429                 clock_source = "Internal 128 kHz";
3430                 break;
3431         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3432                 clock_source = "Internal 176.4 kHz";
3433                 break;
3434                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3435                 clock_source = "Internal 192 kHz";
3436                 break;
3437         default:
3438                 clock_source = "Error";
3439         }
3440         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3441
3442         if (hdsp_system_clock_mode(hdsp))
3443                 system_clock_mode = "Slave";
3444         else
3445                 system_clock_mode = "Master";
3446
3447         switch (hdsp_pref_sync_ref (hdsp)) {
3448         case HDSP_SYNC_FROM_WORD:
3449                 pref_sync_ref = "Word Clock";
3450                 break;
3451         case HDSP_SYNC_FROM_ADAT_SYNC:
3452                 pref_sync_ref = "ADAT Sync";
3453                 break;
3454         case HDSP_SYNC_FROM_SPDIF:
3455                 pref_sync_ref = "SPDIF";
3456                 break;
3457         case HDSP_SYNC_FROM_ADAT1:
3458                 pref_sync_ref = "ADAT1";
3459                 break;
3460         case HDSP_SYNC_FROM_ADAT2:
3461                 pref_sync_ref = "ADAT2";
3462                 break;
3463         case HDSP_SYNC_FROM_ADAT3:
3464                 pref_sync_ref = "ADAT3";
3465                 break;
3466         default:
3467                 pref_sync_ref = "Word Clock";
3468                 break;
3469         }
3470         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3471
3472         switch (hdsp_autosync_ref (hdsp)) {
3473         case HDSP_AUTOSYNC_FROM_WORD:
3474                 autosync_ref = "Word Clock";
3475                 break;
3476         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3477                 autosync_ref = "ADAT Sync";
3478                 break;
3479         case HDSP_AUTOSYNC_FROM_SPDIF:
3480                 autosync_ref = "SPDIF";
3481                 break;
3482         case HDSP_AUTOSYNC_FROM_NONE:
3483                 autosync_ref = "None";
3484                 break;
3485         case HDSP_AUTOSYNC_FROM_ADAT1:
3486                 autosync_ref = "ADAT1";
3487                 break;
3488         case HDSP_AUTOSYNC_FROM_ADAT2:
3489                 autosync_ref = "ADAT2";
3490                 break;
3491         case HDSP_AUTOSYNC_FROM_ADAT3:
3492                 autosync_ref = "ADAT3";
3493                 break;
3494         default:
3495                 autosync_ref = "---";
3496                 break;
3497         }
3498         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3499
3500         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3501
3502         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3503
3504         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3505         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3506
3507         snd_iprintf(buffer, "\n");
3508
3509         if (hdsp->io_type != RPM) {
3510                 switch (hdsp_spdif_in(hdsp)) {
3511                 case HDSP_SPDIFIN_OPTICAL:
3512                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3513                         break;
3514                 case HDSP_SPDIFIN_COAXIAL:
3515                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3516                         break;
3517                 case HDSP_SPDIFIN_INTERNAL:
3518                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3519                         break;
3520                 case HDSP_SPDIFIN_AES:
3521                         snd_iprintf(buffer, "IEC958 input: AES\n");
3522                         break;
3523                 default:
3524                         snd_iprintf(buffer, "IEC958 input: ???\n");
3525                         break;
3526                 }
3527         }
3528
3529         if (RPM == hdsp->io_type) {
3530                 if (hdsp->control_register & HDSP_RPM_Bypass)
3531                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3532                 else
3533                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3534                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3535                         snd_iprintf(buffer, "RPM disconnected\n");
3536                 else
3537                         snd_iprintf(buffer, "RPM connected\n");
3538
3539                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3540                 case HDSP_RPM_Inp12_Phon_6dB:
3541                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3542                         break;
3543                 case HDSP_RPM_Inp12_Phon_0dB:
3544                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3545                         break;
3546                 case HDSP_RPM_Inp12_Phon_n6dB:
3547                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3548                         break;
3549                 case HDSP_RPM_Inp12_Line_0dB:
3550                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3551                         break;
3552                 case HDSP_RPM_Inp12_Line_n6dB:
3553                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3554                         break;
3555                 default:
3556                         snd_iprintf(buffer, "Input 1/2: ???\n");
3557                 }
3558
3559                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3560                 case HDSP_RPM_Inp34_Phon_6dB:
3561                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3562                         break;
3563                 case HDSP_RPM_Inp34_Phon_0dB:
3564                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3565                         break;
3566                 case HDSP_RPM_Inp34_Phon_n6dB:
3567                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3568                         break;
3569                 case HDSP_RPM_Inp34_Line_0dB:
3570                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3571                         break;
3572                 case HDSP_RPM_Inp34_Line_n6dB:
3573                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3574                         break;
3575                 default:
3576                         snd_iprintf(buffer, "Input 3/4: ???\n");
3577                 }
3578
3579         } else {
3580                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3581                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3582                 else
3583                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3584
3585                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3586                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3587                 else
3588                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3589
3590                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3591                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3592                 else
3593                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3594
3595                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3596                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3597                 else
3598                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3599                 x = hdsp_spdif_sample_rate(hdsp);
3600                 if (x != 0)
3601                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3602                 else
3603                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3604         }
3605         snd_iprintf(buffer, "\n");
3606
3607         /* Sync Check */
3608         x = status & HDSP_Sync0;
3609         if (status & HDSP_Lock0)
3610                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3611         else
3612                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3613
3614         switch (hdsp->io_type) {
3615         case Digiface:
3616         case H9652:
3617                 x = status & HDSP_Sync1;
3618                 if (status & HDSP_Lock1)
3619                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3620                 else
3621                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3622                 x = status & HDSP_Sync2;
3623                 if (status & HDSP_Lock2)
3624                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3625                 else
3626                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3627                 break;
3628         default:
3629                 /* relax */
3630                 break;
3631         }
3632
3633         x = status & HDSP_SPDIFSync;
3634         if (status & HDSP_SPDIFErrorFlag)
3635                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3636         else
3637                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3638
3639         x = status2 & HDSP_wc_sync;
3640         if (status2 & HDSP_wc_lock)
3641                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3642         else
3643                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3644
3645         x = status & HDSP_TimecodeSync;
3646         if (status & HDSP_TimecodeLock)
3647                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3648         else
3649                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3650
3651         snd_iprintf(buffer, "\n");
3652
3653         /* Informations about H9632 specific controls */
3654         if (hdsp->io_type == H9632) {
3655                 char *tmp;
3656
3657                 switch (hdsp_ad_gain(hdsp)) {
3658                 case 0:
3659                         tmp = "-10 dBV";
3660                         break;
3661                 case 1:
3662                         tmp = "+4 dBu";
3663                         break;
3664                 default:
3665                         tmp = "Lo Gain";
3666                         break;
3667                 }
3668                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3669
3670                 switch (hdsp_da_gain(hdsp)) {
3671                 case 0:
3672                         tmp = "Hi Gain";
3673                         break;
3674                 case 1:
3675                         tmp = "+4 dBu";
3676                         break;
3677                 default:
3678                         tmp = "-10 dBV";
3679                         break;
3680                 }
3681                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3682
3683                 switch (hdsp_phone_gain(hdsp)) {
3684                 case 0:
3685                         tmp = "0 dB";
3686                         break;
3687                 case 1:
3688                         tmp = "-6 dB";
3689                         break;
3690                 default:
3691                         tmp = "-12 dB";
3692                         break;
3693                 }
3694                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3695
3696                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3697                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3698                         "yes" : "no");
3699
3700                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3701                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3702                 else
3703                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3704                 snd_iprintf(buffer, "\n");
3705         }
3706
3707 }
3708
3709 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3710 {
3711         struct snd_info_entry *entry;
3712
3713         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3714                 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3715 }
3716
3717 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3718 {
3719         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3720         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3721 }
3722
3723 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3724 {
3725         unsigned long pb_bus, cb_bus;
3726
3727         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3728             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3729                 if (hdsp->capture_dma_buf.area)
3730                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3731                 dev_err(hdsp->card->dev,
3732                         "%s: no buffers available\n", hdsp->card_name);
3733                 return -ENOMEM;
3734         }
3735
3736         /* Align to bus-space 64K boundary */
3737
3738         cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3739         pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3740
3741         /* Tell the card where it is */
3742
3743         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3744         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3745
3746         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3747         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3748
3749         return 0;
3750 }
3751
3752 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3753 {
3754         unsigned int i;
3755
3756         /* ASSUMPTION: hdsp->lock is either held, or
3757            there is no need to hold it (e.g. during module
3758            initialization).
3759          */
3760
3761         /* set defaults:
3762
3763            SPDIF Input via Coax
3764            Master clock mode
3765            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3766                             which implies 2 4096 sample, 32Kbyte periods).
3767            Enable line out.
3768          */
3769
3770         hdsp->control_register = HDSP_ClockModeMaster |
3771                                  HDSP_SPDIFInputCoaxial |
3772                                  hdsp_encode_latency(7) |
3773                                  HDSP_LineOut;
3774
3775
3776         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3777
3778 #ifdef SNDRV_BIG_ENDIAN
3779         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3780 #else
3781         hdsp->control2_register = 0;
3782 #endif
3783         if (hdsp->io_type == H9652)
3784                 snd_hdsp_9652_enable_mixer (hdsp);
3785         else
3786                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3787
3788         hdsp_reset_hw_pointer(hdsp);
3789         hdsp_compute_period_size(hdsp);
3790
3791         /* silence everything */
3792
3793         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3794                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3795
3796         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3797                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3798                         return -EIO;
3799         }
3800
3801         /* H9632 specific defaults */
3802         if (hdsp->io_type == H9632) {
3803                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3804                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3805         }
3806
3807         /* set a default rate so that the channel map is set up.
3808          */
3809
3810         hdsp_set_rate(hdsp, 48000, 1);
3811
3812         return 0;
3813 }
3814
3815 static void hdsp_midi_tasklet(unsigned long arg)
3816 {
3817         struct hdsp *hdsp = (struct hdsp *)arg;
3818
3819         if (hdsp->midi[0].pending)
3820                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3821         if (hdsp->midi[1].pending)
3822                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3823 }
3824
3825 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3826 {
3827         struct hdsp *hdsp = (struct hdsp *) dev_id;
3828         unsigned int status;
3829         int audio;
3830         int midi0;
3831         int midi1;
3832         unsigned int midi0status;
3833         unsigned int midi1status;
3834         int schedule = 0;
3835
3836         status = hdsp_read(hdsp, HDSP_statusRegister);
3837
3838         audio = status & HDSP_audioIRQPending;
3839         midi0 = status & HDSP_midi0IRQPending;
3840         midi1 = status & HDSP_midi1IRQPending;
3841
3842         if (!audio && !midi0 && !midi1)
3843                 return IRQ_NONE;
3844
3845         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3846
3847         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3848         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3849
3850         if (!(hdsp->state & HDSP_InitializationComplete))
3851                 return IRQ_HANDLED;
3852
3853         if (audio) {
3854                 if (hdsp->capture_substream)
3855                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3856
3857                 if (hdsp->playback_substream)
3858                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3859         }
3860
3861         if (midi0 && midi0status) {
3862                 if (hdsp->use_midi_tasklet) {
3863                         /* we disable interrupts for this input until processing is done */
3864                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3865                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3866                         hdsp->midi[0].pending = 1;
3867                         schedule = 1;
3868                 } else {
3869                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3870                 }
3871         }
3872         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3873                 if (hdsp->use_midi_tasklet) {
3874                         /* we disable interrupts for this input until processing is done */
3875                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3876                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3877                         hdsp->midi[1].pending = 1;
3878                         schedule = 1;
3879                 } else {
3880                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3881                 }
3882         }
3883         if (hdsp->use_midi_tasklet && schedule)
3884                 tasklet_schedule(&hdsp->midi_tasklet);
3885         return IRQ_HANDLED;
3886 }
3887
3888 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3889 {
3890         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3891         return hdsp_hw_pointer(hdsp);
3892 }
3893
3894 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3895                                              int stream,
3896                                              int channel)
3897
3898 {
3899         int mapped_channel;
3900
3901         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3902                 return NULL;
3903
3904         if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3905                 return NULL;
3906
3907         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3908                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3909         else
3910                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3911 }
3912
3913 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3914                                   snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3915 {
3916         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3917         char *channel_buf;
3918
3919         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3920                 return -EINVAL;
3921
3922         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3923         if (snd_BUG_ON(!channel_buf))
3924                 return -EIO;
3925         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3926                 return -EFAULT;
3927         return count;
3928 }
3929
3930 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3931                                  snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3932 {
3933         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3934         char *channel_buf;
3935
3936         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3937                 return -EINVAL;
3938
3939         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3940         if (snd_BUG_ON(!channel_buf))
3941                 return -EIO;
3942         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3943                 return -EFAULT;
3944         return count;
3945 }
3946
3947 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
3948                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3949 {
3950         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3951         char *channel_buf;
3952
3953         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3954         if (snd_BUG_ON(!channel_buf))
3955                 return -EIO;
3956         memset(channel_buf + pos * 4, 0, count * 4);
3957         return count;
3958 }
3959
3960 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3961 {
3962         struct snd_pcm_runtime *runtime = substream->runtime;
3963         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3964         struct snd_pcm_substream *other;
3965         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3966                 other = hdsp->capture_substream;
3967         else
3968                 other = hdsp->playback_substream;
3969         if (hdsp->running)
3970                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3971         else
3972                 runtime->status->hw_ptr = 0;
3973         if (other) {
3974                 struct snd_pcm_substream *s;
3975                 struct snd_pcm_runtime *oruntime = other->runtime;
3976                 snd_pcm_group_for_each_entry(s, substream) {
3977                         if (s == other) {
3978                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3979                                 break;
3980                         }
3981                 }
3982         }
3983         return 0;
3984 }
3985
3986 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3987                                  struct snd_pcm_hw_params *params)
3988 {
3989         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3990         int err;
3991         pid_t this_pid;
3992         pid_t other_pid;
3993
3994         if (hdsp_check_for_iobox (hdsp))
3995                 return -EIO;
3996
3997         if (hdsp_check_for_firmware(hdsp, 1))
3998                 return -EIO;
3999
4000         spin_lock_irq(&hdsp->lock);
4001
4002         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4003                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4004                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4005                 this_pid = hdsp->playback_pid;
4006                 other_pid = hdsp->capture_pid;
4007         } else {
4008                 this_pid = hdsp->capture_pid;
4009                 other_pid = hdsp->playback_pid;
4010         }
4011
4012         if ((other_pid > 0) && (this_pid != other_pid)) {
4013
4014                 /* The other stream is open, and not by the same
4015                    task as this one. Make sure that the parameters
4016                    that matter are the same.
4017                  */
4018
4019                 if (params_rate(params) != hdsp->system_sample_rate) {
4020                         spin_unlock_irq(&hdsp->lock);
4021                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4022                         return -EBUSY;
4023                 }
4024
4025                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4026                         spin_unlock_irq(&hdsp->lock);
4027                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4028                         return -EBUSY;
4029                 }
4030
4031                 /* We're fine. */
4032
4033                 spin_unlock_irq(&hdsp->lock);
4034                 return 0;
4035
4036         } else {
4037                 spin_unlock_irq(&hdsp->lock);
4038         }
4039
4040         /* how to make sure that the rate matches an externally-set one ?
4041          */
4042
4043         spin_lock_irq(&hdsp->lock);
4044         if (! hdsp->clock_source_locked) {
4045                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4046                         spin_unlock_irq(&hdsp->lock);
4047                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4048                         return err;
4049                 }
4050         }
4051         spin_unlock_irq(&hdsp->lock);
4052
4053         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4054                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4055                 return err;
4056         }
4057
4058         return 0;
4059 }
4060
4061 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4062                                     struct snd_pcm_channel_info *info)
4063 {
4064         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4065         unsigned int channel = info->channel;
4066
4067         if (snd_BUG_ON(channel >= hdsp->max_channels))
4068                 return -EINVAL;
4069         channel = array_index_nospec(channel, hdsp->max_channels);
4070
4071         if (hdsp->channel_map[channel] < 0)
4072                 return -EINVAL;
4073
4074         info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4075         info->first = 0;
4076         info->step = 32;
4077         return 0;
4078 }
4079
4080 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4081                              unsigned int cmd, void *arg)
4082 {
4083         switch (cmd) {
4084         case SNDRV_PCM_IOCTL1_RESET:
4085                 return snd_hdsp_reset(substream);
4086         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4087                 return snd_hdsp_channel_info(substream, arg);
4088         default:
4089                 break;
4090         }
4091
4092         return snd_pcm_lib_ioctl(substream, cmd, arg);
4093 }
4094
4095 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4096 {
4097         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4098         struct snd_pcm_substream *other;
4099         int running;
4100
4101         if (hdsp_check_for_iobox (hdsp))
4102                 return -EIO;
4103
4104         if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4105                 return -EIO;
4106
4107         spin_lock(&hdsp->lock);
4108         running = hdsp->running;
4109         switch (cmd) {
4110         case SNDRV_PCM_TRIGGER_START:
4111                 running |= 1 << substream->stream;
4112                 break;
4113         case SNDRV_PCM_TRIGGER_STOP:
4114                 running &= ~(1 << substream->stream);
4115                 break;
4116         default:
4117                 snd_BUG();
4118                 spin_unlock(&hdsp->lock);
4119                 return -EINVAL;
4120         }
4121         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4122                 other = hdsp->capture_substream;
4123         else
4124                 other = hdsp->playback_substream;
4125
4126         if (other) {
4127                 struct snd_pcm_substream *s;
4128                 snd_pcm_group_for_each_entry(s, substream) {
4129                         if (s == other) {
4130                                 snd_pcm_trigger_done(s, substream);
4131                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4132                                         running |= 1 << s->stream;
4133                                 else
4134                                         running &= ~(1 << s->stream);
4135                                 goto _ok;
4136                         }
4137                 }
4138                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4139                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4140                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4141                                 hdsp_silence_playback(hdsp);
4142                 } else {
4143                         if (running &&
4144                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4145                                 hdsp_silence_playback(hdsp);
4146                 }
4147         } else {
4148                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4149                                 hdsp_silence_playback(hdsp);
4150         }
4151  _ok:
4152         snd_pcm_trigger_done(substream, substream);
4153         if (!hdsp->running && running)
4154                 hdsp_start_audio(hdsp);
4155         else if (hdsp->running && !running)
4156                 hdsp_stop_audio(hdsp);
4157         hdsp->running = running;
4158         spin_unlock(&hdsp->lock);
4159
4160         return 0;
4161 }
4162
4163 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4164 {
4165         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4166         int result = 0;
4167
4168         if (hdsp_check_for_iobox (hdsp))
4169                 return -EIO;
4170
4171         if (hdsp_check_for_firmware(hdsp, 1))
4172                 return -EIO;
4173
4174         spin_lock_irq(&hdsp->lock);
4175         if (!hdsp->running)
4176                 hdsp_reset_hw_pointer(hdsp);
4177         spin_unlock_irq(&hdsp->lock);
4178         return result;
4179 }
4180
4181 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4182 {
4183         .info =                 (SNDRV_PCM_INFO_MMAP |
4184                                  SNDRV_PCM_INFO_MMAP_VALID |
4185                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4186                                  SNDRV_PCM_INFO_SYNC_START |
4187                                  SNDRV_PCM_INFO_DOUBLE),
4188 #ifdef SNDRV_BIG_ENDIAN
4189         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4190 #else
4191         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4192 #endif
4193         .rates =                (SNDRV_PCM_RATE_32000 |
4194                                  SNDRV_PCM_RATE_44100 |
4195                                  SNDRV_PCM_RATE_48000 |
4196                                  SNDRV_PCM_RATE_64000 |
4197                                  SNDRV_PCM_RATE_88200 |
4198                                  SNDRV_PCM_RATE_96000),
4199         .rate_min =             32000,
4200         .rate_max =             96000,
4201         .channels_min =         6,
4202         .channels_max =         HDSP_MAX_CHANNELS,
4203         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4204         .period_bytes_min =     (64 * 4) * 10,
4205         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4206         .periods_min =          2,
4207         .periods_max =          2,
4208         .fifo_size =            0
4209 };
4210
4211 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4212 {
4213         .info =                 (SNDRV_PCM_INFO_MMAP |
4214                                  SNDRV_PCM_INFO_MMAP_VALID |
4215                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4216                                  SNDRV_PCM_INFO_SYNC_START),
4217 #ifdef SNDRV_BIG_ENDIAN
4218         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4219 #else
4220         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4221 #endif
4222         .rates =                (SNDRV_PCM_RATE_32000 |
4223                                  SNDRV_PCM_RATE_44100 |
4224                                  SNDRV_PCM_RATE_48000 |
4225                                  SNDRV_PCM_RATE_64000 |
4226                                  SNDRV_PCM_RATE_88200 |
4227                                  SNDRV_PCM_RATE_96000),
4228         .rate_min =             32000,
4229         .rate_max =             96000,
4230         .channels_min =         5,
4231         .channels_max =         HDSP_MAX_CHANNELS,
4232         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4233         .period_bytes_min =     (64 * 4) * 10,
4234         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4235         .periods_min =          2,
4236         .periods_max =          2,
4237         .fifo_size =            0
4238 };
4239
4240 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4241
4242 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4243         .count = ARRAY_SIZE(hdsp_period_sizes),
4244         .list = hdsp_period_sizes,
4245         .mask = 0
4246 };
4247
4248 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4249
4250 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4251         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4252         .list = hdsp_9632_sample_rates,
4253         .mask = 0
4254 };
4255
4256 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4257                                         struct snd_pcm_hw_rule *rule)
4258 {
4259         struct hdsp *hdsp = rule->private;
4260         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4261         if (hdsp->io_type == H9632) {
4262                 unsigned int list[3];
4263                 list[0] = hdsp->qs_in_channels;
4264                 list[1] = hdsp->ds_in_channels;
4265                 list[2] = hdsp->ss_in_channels;
4266                 return snd_interval_list(c, 3, list, 0);
4267         } else {
4268                 unsigned int list[2];
4269                 list[0] = hdsp->ds_in_channels;
4270                 list[1] = hdsp->ss_in_channels;
4271                 return snd_interval_list(c, 2, list, 0);
4272         }
4273 }
4274
4275 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4276                                         struct snd_pcm_hw_rule *rule)
4277 {
4278         unsigned int list[3];
4279         struct hdsp *hdsp = rule->private;
4280         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4281         if (hdsp->io_type == H9632) {
4282                 list[0] = hdsp->qs_out_channels;
4283                 list[1] = hdsp->ds_out_channels;
4284                 list[2] = hdsp->ss_out_channels;
4285                 return snd_interval_list(c, 3, list, 0);
4286         } else {
4287                 list[0] = hdsp->ds_out_channels;
4288                 list[1] = hdsp->ss_out_channels;
4289         }
4290         return snd_interval_list(c, 2, list, 0);
4291 }
4292
4293 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4294                                              struct snd_pcm_hw_rule *rule)
4295 {
4296         struct hdsp *hdsp = rule->private;
4297         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4298         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4299         if (r->min > 96000 && hdsp->io_type == H9632) {
4300                 struct snd_interval t = {
4301                         .min = hdsp->qs_in_channels,
4302                         .max = hdsp->qs_in_channels,
4303                         .integer = 1,
4304                 };
4305                 return snd_interval_refine(c, &t);
4306         } else if (r->min > 48000 && r->max <= 96000) {
4307                 struct snd_interval t = {
4308                         .min = hdsp->ds_in_channels,
4309                         .max = hdsp->ds_in_channels,
4310                         .integer = 1,
4311                 };
4312                 return snd_interval_refine(c, &t);
4313         } else if (r->max < 64000) {
4314                 struct snd_interval t = {
4315                         .min = hdsp->ss_in_channels,
4316                         .max = hdsp->ss_in_channels,
4317                         .integer = 1,
4318                 };
4319                 return snd_interval_refine(c, &t);
4320         }
4321         return 0;
4322 }
4323
4324 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4325                                              struct snd_pcm_hw_rule *rule)
4326 {
4327         struct hdsp *hdsp = rule->private;
4328         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4329         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4330         if (r->min > 96000 && hdsp->io_type == H9632) {
4331                 struct snd_interval t = {
4332                         .min = hdsp->qs_out_channels,
4333                         .max = hdsp->qs_out_channels,
4334                         .integer = 1,
4335                 };
4336                 return snd_interval_refine(c, &t);
4337         } else if (r->min > 48000 && r->max <= 96000) {
4338                 struct snd_interval t = {
4339                         .min = hdsp->ds_out_channels,
4340                         .max = hdsp->ds_out_channels,
4341                         .integer = 1,
4342                 };
4343                 return snd_interval_refine(c, &t);
4344         } else if (r->max < 64000) {
4345                 struct snd_interval t = {
4346                         .min = hdsp->ss_out_channels,
4347                         .max = hdsp->ss_out_channels,
4348                         .integer = 1,
4349                 };
4350                 return snd_interval_refine(c, &t);
4351         }
4352         return 0;
4353 }
4354
4355 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4356                                              struct snd_pcm_hw_rule *rule)
4357 {
4358         struct hdsp *hdsp = rule->private;
4359         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4360         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4361         if (c->min >= hdsp->ss_out_channels) {
4362                 struct snd_interval t = {
4363                         .min = 32000,
4364                         .max = 48000,
4365                         .integer = 1,
4366                 };
4367                 return snd_interval_refine(r, &t);
4368         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4369                 struct snd_interval t = {
4370                         .min = 128000,
4371                         .max = 192000,
4372                         .integer = 1,
4373                 };
4374                 return snd_interval_refine(r, &t);
4375         } else if (c->max <= hdsp->ds_out_channels) {
4376                 struct snd_interval t = {
4377                         .min = 64000,
4378                         .max = 96000,
4379                         .integer = 1,
4380                 };
4381                 return snd_interval_refine(r, &t);
4382         }
4383         return 0;
4384 }
4385
4386 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4387                                              struct snd_pcm_hw_rule *rule)
4388 {
4389         struct hdsp *hdsp = rule->private;
4390         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4391         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4392         if (c->min >= hdsp->ss_in_channels) {
4393                 struct snd_interval t = {
4394                         .min = 32000,
4395                         .max = 48000,
4396                         .integer = 1,
4397                 };
4398                 return snd_interval_refine(r, &t);
4399         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4400                 struct snd_interval t = {
4401                         .min = 128000,
4402                         .max = 192000,
4403                         .integer = 1,
4404                 };
4405                 return snd_interval_refine(r, &t);
4406         } else if (c->max <= hdsp->ds_in_channels) {
4407                 struct snd_interval t = {
4408                         .min = 64000,
4409                         .max = 96000,
4410                         .integer = 1,
4411                 };
4412                 return snd_interval_refine(r, &t);
4413         }
4414         return 0;
4415 }
4416
4417 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4418 {
4419         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4420         struct snd_pcm_runtime *runtime = substream->runtime;
4421
4422         if (hdsp_check_for_iobox (hdsp))
4423                 return -EIO;
4424
4425         if (hdsp_check_for_firmware(hdsp, 1))
4426                 return -EIO;
4427
4428         spin_lock_irq(&hdsp->lock);
4429
4430         snd_pcm_set_sync(substream);
4431
4432         runtime->hw = snd_hdsp_playback_subinfo;
4433         runtime->dma_area = hdsp->playback_buffer;
4434         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4435
4436         hdsp->playback_pid = current->pid;
4437         hdsp->playback_substream = substream;
4438
4439         spin_unlock_irq(&hdsp->lock);
4440
4441         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4442         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4443         if (hdsp->clock_source_locked) {
4444                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4445         } else if (hdsp->io_type == H9632) {
4446                 runtime->hw.rate_max = 192000;
4447                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4448                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4449         }
4450         if (hdsp->io_type == H9632) {
4451                 runtime->hw.channels_min = hdsp->qs_out_channels;
4452                 runtime->hw.channels_max = hdsp->ss_out_channels;
4453         }
4454
4455         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4456                              snd_hdsp_hw_rule_out_channels, hdsp,
4457                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4458         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4459                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4460                              SNDRV_PCM_HW_PARAM_RATE, -1);
4461         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4462                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4463                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4464
4465         if (RPM != hdsp->io_type) {
4466                 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4467                 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4468                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4469                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4470         }
4471         return 0;
4472 }
4473
4474 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4475 {
4476         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4477
4478         spin_lock_irq(&hdsp->lock);
4479
4480         hdsp->playback_pid = -1;
4481         hdsp->playback_substream = NULL;
4482
4483         spin_unlock_irq(&hdsp->lock);
4484
4485         if (RPM != hdsp->io_type) {
4486                 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4487                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4488                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4489         }
4490         return 0;
4491 }
4492
4493
4494 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4495 {
4496         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4497         struct snd_pcm_runtime *runtime = substream->runtime;
4498
4499         if (hdsp_check_for_iobox (hdsp))
4500                 return -EIO;
4501
4502         if (hdsp_check_for_firmware(hdsp, 1))
4503                 return -EIO;
4504
4505         spin_lock_irq(&hdsp->lock);
4506
4507         snd_pcm_set_sync(substream);
4508
4509         runtime->hw = snd_hdsp_capture_subinfo;
4510         runtime->dma_area = hdsp->capture_buffer;
4511         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4512
4513         hdsp->capture_pid = current->pid;
4514         hdsp->capture_substream = substream;
4515
4516         spin_unlock_irq(&hdsp->lock);
4517
4518         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4519         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4520         if (hdsp->io_type == H9632) {
4521                 runtime->hw.channels_min = hdsp->qs_in_channels;
4522                 runtime->hw.channels_max = hdsp->ss_in_channels;
4523                 runtime->hw.rate_max = 192000;
4524                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4525                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4526         }
4527         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4528                              snd_hdsp_hw_rule_in_channels, hdsp,
4529                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4530         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4531                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4532                              SNDRV_PCM_HW_PARAM_RATE, -1);
4533         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4534                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4535                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4536         return 0;
4537 }
4538
4539 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4540 {
4541         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4542
4543         spin_lock_irq(&hdsp->lock);
4544
4545         hdsp->capture_pid = -1;
4546         hdsp->capture_substream = NULL;
4547
4548         spin_unlock_irq(&hdsp->lock);
4549         return 0;
4550 }
4551
4552 /* helper functions for copying meter values */
4553 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4554 {
4555         u32 val = readl(src);
4556         return copy_to_user(dest, &val, 4);
4557 }
4558
4559 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4560 {
4561         u32 rms_low, rms_high;
4562         u64 rms;
4563         rms_low = readl(src_low);
4564         rms_high = readl(src_high);
4565         rms = ((u64)rms_high << 32) | rms_low;
4566         return copy_to_user(dest, &rms, 8);
4567 }
4568
4569 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4570 {
4571         u32 rms_low, rms_high;
4572         u64 rms;
4573         rms_low = readl(src_low) & 0xffffff00;
4574         rms_high = readl(src_high) & 0xffffff00;
4575         rms = ((u64)rms_high << 32) | rms_low;
4576         return copy_to_user(dest, &rms, 8);
4577 }
4578
4579 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4580 {
4581         int doublespeed = 0;
4582         int i, j, channels, ofs;
4583
4584         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4585                 doublespeed = 1;
4586         channels = doublespeed ? 14 : 26;
4587         for (i = 0, j = 0; i < 26; ++i) {
4588                 if (doublespeed && (i & 4))
4589                         continue;
4590                 ofs = HDSP_9652_peakBase - j * 4;
4591                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4592                         return -EFAULT;
4593                 ofs -= channels * 4;
4594                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4595                         return -EFAULT;
4596                 ofs -= channels * 4;
4597                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4598                         return -EFAULT;
4599                 ofs = HDSP_9652_rmsBase + j * 8;
4600                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4601                                 hdsp->iobase + ofs + 4))
4602                         return -EFAULT;
4603                 ofs += channels * 8;
4604                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4605                                 hdsp->iobase + ofs + 4))
4606                         return -EFAULT;
4607                 ofs += channels * 8;
4608                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4609                                 hdsp->iobase + ofs + 4))
4610                         return -EFAULT;
4611                 j++;
4612         }
4613         return 0;
4614 }
4615
4616 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4617 {
4618         int i, j;
4619         struct hdsp_9632_meters __iomem *m;
4620         int doublespeed = 0;
4621
4622         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4623                 doublespeed = 1;
4624         m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4625         for (i = 0, j = 0; i < 16; ++i, ++j) {
4626                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4627                         return -EFAULT;
4628                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4629                         return -EFAULT;
4630                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4631                         return -EFAULT;
4632                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4633                                 &m->input_rms_high[j]))
4634                         return -EFAULT;
4635                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4636                                 &m->playback_rms_high[j]))
4637                         return -EFAULT;
4638                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4639                                 &m->output_rms_high[j]))
4640                         return -EFAULT;
4641                 if (doublespeed && i == 3) i += 4;
4642         }
4643         return 0;
4644 }
4645
4646 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4647 {
4648         int i;
4649
4650         for (i = 0; i < 26; i++) {
4651                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4652                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4653                         return -EFAULT;
4654                 if (copy_u32_le(&peak_rms->input_peaks[i],
4655                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4656                         return -EFAULT;
4657         }
4658         for (i = 0; i < 28; i++) {
4659                 if (copy_u32_le(&peak_rms->output_peaks[i],
4660                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4661                         return -EFAULT;
4662         }
4663         for (i = 0; i < 26; ++i) {
4664                 if (copy_u64_le(&peak_rms->playback_rms[i],
4665                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4666                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4667                         return -EFAULT;
4668                 if (copy_u64_le(&peak_rms->input_rms[i],
4669                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4670                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4671                         return -EFAULT;
4672         }
4673         return 0;
4674 }
4675
4676 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4677 {
4678         struct hdsp *hdsp = hw->private_data;
4679         void __user *argp = (void __user *)arg;
4680         int err;
4681
4682         switch (cmd) {
4683         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4684                 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4685
4686                 err = hdsp_check_for_iobox(hdsp);
4687                 if (err < 0)
4688                         return err;
4689
4690                 err = hdsp_check_for_firmware(hdsp, 1);
4691                 if (err < 0)
4692                         return err;
4693
4694                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4695                         dev_err(hdsp->card->dev,
4696                                 "firmware needs to be uploaded to the card.\n");
4697                         return -EINVAL;
4698                 }
4699
4700                 switch (hdsp->io_type) {
4701                 case H9652:
4702                         return hdsp_9652_get_peak(hdsp, peak_rms);
4703                 case H9632:
4704                         return hdsp_9632_get_peak(hdsp, peak_rms);
4705                 default:
4706                         return hdsp_get_peak(hdsp, peak_rms);
4707                 }
4708         }
4709         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4710                 struct hdsp_config_info info;
4711                 unsigned long flags;
4712                 int i;
4713
4714                 err = hdsp_check_for_iobox(hdsp);
4715                 if (err < 0)
4716                         return err;
4717
4718                 err = hdsp_check_for_firmware(hdsp, 1);
4719                 if (err < 0)
4720                         return err;
4721
4722                 memset(&info, 0, sizeof(info));
4723                 spin_lock_irqsave(&hdsp->lock, flags);
4724                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4725                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4726                 if (hdsp->io_type != H9632)
4727                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4728                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4729                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4730                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4731                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4732                 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4733                                 HDSP_SPDIFOpticalOut);
4734                 info.spdif_professional = (unsigned char)
4735                         hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4736                 info.spdif_emphasis = (unsigned char)
4737                         hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4738                 info.spdif_nonaudio = (unsigned char)
4739                         hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4740                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4741                 info.system_sample_rate = hdsp->system_sample_rate;
4742                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4743                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4744                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4745                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4746                 info.line_out = (unsigned char)
4747                         hdsp_toggle_setting(hdsp, HDSP_LineOut);
4748                 if (hdsp->io_type == H9632) {
4749                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4750                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4751                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4752                         info.xlr_breakout_cable =
4753                                 (unsigned char)hdsp_toggle_setting(hdsp,
4754                                         HDSP_XLRBreakoutCable);
4755
4756                 } else if (hdsp->io_type == RPM) {
4757                         info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4758                         info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4759                 }
4760                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4761                         info.analog_extension_board =
4762                                 (unsigned char)hdsp_toggle_setting(hdsp,
4763                                             HDSP_AnalogExtensionBoard);
4764                 spin_unlock_irqrestore(&hdsp->lock, flags);
4765                 if (copy_to_user(argp, &info, sizeof(info)))
4766                         return -EFAULT;
4767                 break;
4768         }
4769         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4770                 struct hdsp_9632_aeb h9632_aeb;
4771
4772                 if (hdsp->io_type != H9632) return -EINVAL;
4773                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4774                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4775                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4776                         return -EFAULT;
4777                 break;
4778         }
4779         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4780                 struct hdsp_version hdsp_version;
4781                 int err;
4782
4783                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4784                 if (hdsp->io_type == Undefined) {
4785                         if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4786                                 return err;
4787                 }
4788                 memset(&hdsp_version, 0, sizeof(hdsp_version));
4789                 hdsp_version.io_type = hdsp->io_type;
4790                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4791                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4792                         return -EFAULT;
4793                 break;
4794         }
4795         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4796                 struct hdsp_firmware __user *firmware;
4797                 u32 __user *firmware_data;
4798                 int err;
4799
4800                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4801                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4802                 if (hdsp->io_type == Undefined) return -EINVAL;
4803
4804                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4805                         return -EBUSY;
4806
4807                 dev_info(hdsp->card->dev,
4808                          "initializing firmware upload\n");
4809                 firmware = (struct hdsp_firmware __user *)argp;
4810
4811                 if (get_user(firmware_data, &firmware->firmware_data))
4812                         return -EFAULT;
4813
4814                 if (hdsp_check_for_iobox (hdsp))
4815                         return -EIO;
4816
4817                 if (!hdsp->fw_uploaded) {
4818                         hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4819                         if (!hdsp->fw_uploaded)
4820                                 return -ENOMEM;
4821                 }
4822
4823                 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4824                                    HDSP_FIRMWARE_SIZE)) {
4825                         vfree(hdsp->fw_uploaded);
4826                         hdsp->fw_uploaded = NULL;
4827                         return -EFAULT;
4828                 }
4829
4830                 hdsp->state |= HDSP_FirmwareCached;
4831
4832                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4833                         return err;
4834
4835                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4836                         if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4837                                 return err;
4838
4839                         snd_hdsp_initialize_channels(hdsp);
4840                         snd_hdsp_initialize_midi_flush(hdsp);
4841
4842                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4843                                 dev_err(hdsp->card->dev,
4844                                         "error creating alsa devices\n");
4845                                 return err;
4846                         }
4847                 }
4848                 break;
4849         }
4850         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4851                 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4852                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4853                         return -EFAULT;
4854                 break;
4855         }
4856         default:
4857                 return -EINVAL;
4858         }
4859         return 0;
4860 }
4861
4862 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4863         .open =         snd_hdsp_playback_open,
4864         .close =        snd_hdsp_playback_release,
4865         .ioctl =        snd_hdsp_ioctl,
4866         .hw_params =    snd_hdsp_hw_params,
4867         .prepare =      snd_hdsp_prepare,
4868         .trigger =      snd_hdsp_trigger,
4869         .pointer =      snd_hdsp_hw_pointer,
4870         .copy =         snd_hdsp_playback_copy,
4871         .silence =      snd_hdsp_hw_silence,
4872 };
4873
4874 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4875         .open =         snd_hdsp_capture_open,
4876         .close =        snd_hdsp_capture_release,
4877         .ioctl =        snd_hdsp_ioctl,
4878         .hw_params =    snd_hdsp_hw_params,
4879         .prepare =      snd_hdsp_prepare,
4880         .trigger =      snd_hdsp_trigger,
4881         .pointer =      snd_hdsp_hw_pointer,
4882         .copy =         snd_hdsp_capture_copy,
4883 };
4884
4885 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4886 {
4887         struct snd_hwdep *hw;
4888         int err;
4889
4890         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4891                 return err;
4892
4893         hdsp->hwdep = hw;
4894         hw->private_data = hdsp;
4895         strcpy(hw->name, "HDSP hwdep interface");
4896
4897         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4898         hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4899
4900         return 0;
4901 }
4902
4903 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4904 {
4905         struct snd_pcm *pcm;
4906         int err;
4907
4908         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4909                 return err;
4910
4911         hdsp->pcm = pcm;
4912         pcm->private_data = hdsp;
4913         strcpy(pcm->name, hdsp->card_name);
4914
4915         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4916         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4917
4918         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4919
4920         return 0;
4921 }
4922
4923 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4924 {
4925         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4926         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4927 }
4928
4929 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4930 {
4931         int i;
4932
4933         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4934                 dev_err(hdsp->card->dev,
4935                         "enable_io fifo_wait failed\n");
4936                 return -EIO;
4937         }
4938
4939         for (i = 0; i < hdsp->max_channels; ++i) {
4940                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4941                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4942         }
4943
4944         return 0;
4945 }
4946
4947 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4948 {
4949         int status, aebi_channels, aebo_channels;
4950
4951         switch (hdsp->io_type) {
4952         case Digiface:
4953                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4954                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4955                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4956                 break;
4957
4958         case H9652:
4959                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4960                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4961                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4962                 break;
4963
4964         case H9632:
4965                 status = hdsp_read(hdsp, HDSP_statusRegister);
4966                 /* HDSP_AEBx bits are low when AEB are connected */
4967                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4968                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4969                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4970                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4971                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4972                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4973                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4974                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4975                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4976                 break;
4977
4978         case Multiface:
4979                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4980                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4981                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4982                 break;
4983
4984         case RPM:
4985                 hdsp->card_name = "RME Hammerfall DSP + RPM";
4986                 hdsp->ss_in_channels = RPM_CHANNELS-1;
4987                 hdsp->ss_out_channels = RPM_CHANNELS;
4988                 hdsp->ds_in_channels = RPM_CHANNELS-1;
4989                 hdsp->ds_out_channels = RPM_CHANNELS;
4990                 break;
4991
4992         default:
4993                 /* should never get here */
4994                 break;
4995         }
4996 }
4997
4998 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
4999 {
5000         snd_hdsp_flush_midi_input (hdsp, 0);
5001         snd_hdsp_flush_midi_input (hdsp, 1);
5002 }
5003
5004 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5005 {
5006         int err;
5007
5008         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5009                 dev_err(card->dev,
5010                         "Error creating pcm interface\n");
5011                 return err;
5012         }
5013
5014
5015         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5016                 dev_err(card->dev,
5017                         "Error creating first midi interface\n");
5018                 return err;
5019         }
5020
5021         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5022                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5023                         dev_err(card->dev,
5024                                 "Error creating second midi interface\n");
5025                         return err;
5026                 }
5027         }
5028
5029         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5030                 dev_err(card->dev,
5031                         "Error creating ctl interface\n");
5032                 return err;
5033         }
5034
5035         snd_hdsp_proc_init(hdsp);
5036
5037         hdsp->system_sample_rate = -1;
5038         hdsp->playback_pid = -1;
5039         hdsp->capture_pid = -1;
5040         hdsp->capture_substream = NULL;
5041         hdsp->playback_substream = NULL;
5042
5043         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5044                 dev_err(card->dev,
5045                         "Error setting default values\n");
5046                 return err;
5047         }
5048
5049         if (!(hdsp->state & HDSP_InitializationComplete)) {
5050                 strcpy(card->shortname, "Hammerfall DSP");
5051                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5052                         hdsp->port, hdsp->irq);
5053
5054                 if ((err = snd_card_register(card)) < 0) {
5055                         dev_err(card->dev,
5056                                 "error registering card\n");
5057                         return err;
5058                 }
5059                 hdsp->state |= HDSP_InitializationComplete;
5060         }
5061
5062         return 0;
5063 }
5064
5065 /* load firmware via hotplug fw loader */
5066 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5067 {
5068         const char *fwfile;
5069         const struct firmware *fw;
5070         int err;
5071
5072         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5073                 return 0;
5074         if (hdsp->io_type == Undefined) {
5075                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5076                         return err;
5077                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5078                         return 0;
5079         }
5080
5081         /* caution: max length of firmware filename is 30! */
5082         switch (hdsp->io_type) {
5083         case RPM:
5084                 fwfile = "/*(DEBLOBBED)*/";
5085                 break;
5086         case Multiface:
5087                 if (hdsp->firmware_rev == 0xa)
5088                         fwfile = "/*(DEBLOBBED)*/";
5089                 else
5090                         fwfile = "/*(DEBLOBBED)*/";
5091                 break;
5092         case Digiface:
5093                 if (hdsp->firmware_rev == 0xa)
5094                         fwfile = "/*(DEBLOBBED)*/";
5095                 else
5096                         fwfile = "/*(DEBLOBBED)*/";
5097                 break;
5098         default:
5099                 dev_err(hdsp->card->dev,
5100                         "invalid io_type %d\n", hdsp->io_type);
5101                 return -EINVAL;
5102         }
5103
5104         if (reject_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5105                 dev_err(hdsp->card->dev,
5106                         "cannot load firmware %s\n", fwfile);
5107                 return -ENOENT;
5108         }
5109         if (fw->size < HDSP_FIRMWARE_SIZE) {
5110                 dev_err(hdsp->card->dev,
5111                         "too short firmware size %d (expected %d)\n",
5112                            (int)fw->size, HDSP_FIRMWARE_SIZE);
5113                 release_firmware(fw);
5114                 return -EINVAL;
5115         }
5116
5117         hdsp->firmware = fw;
5118
5119         hdsp->state |= HDSP_FirmwareCached;
5120
5121         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5122                 return err;
5123
5124         if (!(hdsp->state & HDSP_InitializationComplete)) {
5125                 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5126                         return err;
5127
5128                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5129                         dev_err(hdsp->card->dev,
5130                                 "error creating hwdep device\n");
5131                         return err;
5132                 }
5133                 snd_hdsp_initialize_channels(hdsp);
5134                 snd_hdsp_initialize_midi_flush(hdsp);
5135                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5136                         dev_err(hdsp->card->dev,
5137                                 "error creating alsa devices\n");
5138                         return err;
5139                 }
5140         }
5141         return 0;
5142 }
5143
5144 static int snd_hdsp_create(struct snd_card *card,
5145                            struct hdsp *hdsp)
5146 {
5147         struct pci_dev *pci = hdsp->pci;
5148         int err;
5149         int is_9652 = 0;
5150         int is_9632 = 0;
5151
5152         hdsp->irq = -1;
5153         hdsp->state = 0;
5154         hdsp->midi[0].rmidi = NULL;
5155         hdsp->midi[1].rmidi = NULL;
5156         hdsp->midi[0].input = NULL;
5157         hdsp->midi[1].input = NULL;
5158         hdsp->midi[0].output = NULL;
5159         hdsp->midi[1].output = NULL;
5160         hdsp->midi[0].pending = 0;
5161         hdsp->midi[1].pending = 0;
5162         spin_lock_init(&hdsp->midi[0].lock);
5163         spin_lock_init(&hdsp->midi[1].lock);
5164         hdsp->iobase = NULL;
5165         hdsp->control_register = 0;
5166         hdsp->control2_register = 0;
5167         hdsp->io_type = Undefined;
5168         hdsp->max_channels = 26;
5169
5170         hdsp->card = card;
5171
5172         spin_lock_init(&hdsp->lock);
5173
5174         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5175
5176         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5177         hdsp->firmware_rev &= 0xff;
5178
5179         /* From Martin Bjoernsen :
5180             "It is important that the card's latency timer register in
5181             the PCI configuration space is set to a value much larger
5182             than 0 by the computer's BIOS or the driver.
5183             The windows driver always sets this 8 bit register [...]
5184             to its maximum 255 to avoid problems with some computers."
5185         */
5186         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5187
5188         strcpy(card->driver, "H-DSP");
5189         strcpy(card->mixername, "Xilinx FPGA");
5190
5191         if (hdsp->firmware_rev < 0xa)
5192                 return -ENODEV;
5193         else if (hdsp->firmware_rev < 0x64)
5194                 hdsp->card_name = "RME Hammerfall DSP";
5195         else if (hdsp->firmware_rev < 0x96) {
5196                 hdsp->card_name = "RME HDSP 9652";
5197                 is_9652 = 1;
5198         } else {
5199                 hdsp->card_name = "RME HDSP 9632";
5200                 hdsp->max_channels = 16;
5201                 is_9632 = 1;
5202         }
5203
5204         if ((err = pci_enable_device(pci)) < 0)
5205                 return err;
5206
5207         pci_set_master(hdsp->pci);
5208
5209         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5210                 return err;
5211         hdsp->port = pci_resource_start(pci, 0);
5212         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5213                 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5214                         hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5215                 return -EBUSY;
5216         }
5217
5218         if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5219                         KBUILD_MODNAME, hdsp)) {
5220                 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5221                 return -EBUSY;
5222         }
5223
5224         hdsp->irq = pci->irq;
5225         hdsp->precise_ptr = 0;
5226         hdsp->use_midi_tasklet = 1;
5227         hdsp->dds_value = 0;
5228
5229         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5230                 return err;
5231
5232         if (!is_9652 && !is_9632) {
5233                 /* we wait a maximum of 10 seconds to let freshly
5234                  * inserted cardbus cards do their hardware init */
5235                 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5236
5237                 if (err < 0)
5238                         return err;
5239
5240                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5241                         if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5242                                 /* we don't fail as this can happen
5243                                    if userspace is not ready for
5244                                    firmware upload
5245                                 */
5246                                 dev_err(hdsp->card->dev,
5247                                         "couldn't get firmware from userspace. try using hdsploader\n");
5248                         else
5249                                 /* init is complete, we return */
5250                                 return 0;
5251                         /* we defer initialization */
5252                         dev_info(hdsp->card->dev,
5253                                  "card initialization pending : waiting for firmware\n");
5254                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5255                                 return err;
5256                         return 0;
5257                 } else {
5258                         dev_info(hdsp->card->dev,
5259                                  "Firmware already present, initializing card.\n");
5260                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5261                                 hdsp->io_type = RPM;
5262                         else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5263                                 hdsp->io_type = Multiface;
5264                         else
5265                                 hdsp->io_type = Digiface;
5266                 }
5267         }
5268
5269         if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5270                 return err;
5271
5272         if (is_9652)
5273                 hdsp->io_type = H9652;
5274
5275         if (is_9632)
5276                 hdsp->io_type = H9632;
5277
5278         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5279                 return err;
5280
5281         snd_hdsp_initialize_channels(hdsp);
5282         snd_hdsp_initialize_midi_flush(hdsp);
5283
5284         hdsp->state |= HDSP_FirmwareLoaded;
5285
5286         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5287                 return err;
5288
5289         return 0;
5290 }
5291
5292 static int snd_hdsp_free(struct hdsp *hdsp)
5293 {
5294         if (hdsp->port) {
5295                 /* stop the audio, and cancel all interrupts */
5296                 tasklet_kill(&hdsp->midi_tasklet);
5297                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5298                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5299         }
5300
5301         if (hdsp->irq >= 0)
5302                 free_irq(hdsp->irq, (void *)hdsp);
5303
5304         snd_hdsp_free_buffers(hdsp);
5305
5306         release_firmware(hdsp->firmware);
5307         vfree(hdsp->fw_uploaded);
5308         iounmap(hdsp->iobase);
5309
5310         if (hdsp->port)
5311                 pci_release_regions(hdsp->pci);
5312
5313         if (pci_is_enabled(hdsp->pci))
5314                 pci_disable_device(hdsp->pci);
5315         return 0;
5316 }
5317
5318 static void snd_hdsp_card_free(struct snd_card *card)
5319 {
5320         struct hdsp *hdsp = card->private_data;
5321
5322         if (hdsp)
5323                 snd_hdsp_free(hdsp);
5324 }
5325
5326 static int snd_hdsp_probe(struct pci_dev *pci,
5327                           const struct pci_device_id *pci_id)
5328 {
5329         static int dev;
5330         struct hdsp *hdsp;
5331         struct snd_card *card;
5332         int err;
5333
5334         if (dev >= SNDRV_CARDS)
5335                 return -ENODEV;
5336         if (!enable[dev]) {
5337                 dev++;
5338                 return -ENOENT;
5339         }
5340
5341         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5342                            sizeof(struct hdsp), &card);
5343         if (err < 0)
5344                 return err;
5345
5346         hdsp = card->private_data;
5347         card->private_free = snd_hdsp_card_free;
5348         hdsp->dev = dev;
5349         hdsp->pci = pci;
5350
5351         if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5352                 snd_card_free(card);
5353                 return err;
5354         }
5355
5356         strcpy(card->shortname, "Hammerfall DSP");
5357         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5358                 hdsp->port, hdsp->irq);
5359
5360         if ((err = snd_card_register(card)) < 0) {
5361                 snd_card_free(card);
5362                 return err;
5363         }
5364         pci_set_drvdata(pci, card);
5365         dev++;
5366         return 0;
5367 }
5368
5369 static void snd_hdsp_remove(struct pci_dev *pci)
5370 {
5371         snd_card_free(pci_get_drvdata(pci));
5372 }
5373
5374 static struct pci_driver hdsp_driver = {
5375         .name =     KBUILD_MODNAME,
5376         .id_table = snd_hdsp_ids,
5377         .probe =    snd_hdsp_probe,
5378         .remove = snd_hdsp_remove,
5379 };
5380
5381 module_pci_driver(hdsp_driver);