2 * max98090.c -- MAX98090 ALSA SoC Audio driver
4 * Copyright 2011-2012 Maxim Integrated Products
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <linux/acpi.h>
20 #include <linux/clk.h>
21 #include <sound/jack.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/tlv.h>
26 #include <sound/max98090.h>
29 /* Allows for sparsely populated register maps */
30 static const struct reg_default max98090_reg[] = {
31 { 0x00, 0x00 }, /* 00 Software Reset */
32 { 0x03, 0x04 }, /* 03 Interrupt Masks */
33 { 0x04, 0x00 }, /* 04 System Clock Quick */
34 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
35 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
36 { 0x07, 0x00 }, /* 07 DAC Path Quick */
37 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
38 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
39 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
40 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
41 { 0x0C, 0x00 }, /* 0C Reserved */
42 { 0x0D, 0x00 }, /* 0D Input Config */
43 { 0x0E, 0x1B }, /* 0E Line Input Level */
44 { 0x0F, 0x00 }, /* 0F Line Config */
46 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
47 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
48 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
49 { 0x13, 0x00 }, /* 13 Digital Mic Config */
50 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
51 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
52 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
53 { 0x17, 0x03 }, /* 17 Left ADC Level */
54 { 0x18, 0x03 }, /* 18 Right ADC Level */
55 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
56 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
57 { 0x1B, 0x00 }, /* 1B System Clock */
58 { 0x1C, 0x00 }, /* 1C Clock Mode */
59 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
60 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
61 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
63 { 0x20, 0x00 }, /* 20 Any Clock 4 */
64 { 0x21, 0x00 }, /* 21 Master Mode */
65 { 0x22, 0x00 }, /* 22 Interface Format */
66 { 0x23, 0x00 }, /* 23 TDM Format 1*/
67 { 0x24, 0x00 }, /* 24 TDM Format 2*/
68 { 0x25, 0x00 }, /* 25 I/O Configuration */
69 { 0x26, 0x80 }, /* 26 Filter Config */
70 { 0x27, 0x00 }, /* 27 DAI Playback Level */
71 { 0x28, 0x00 }, /* 28 EQ Playback Level */
72 { 0x29, 0x00 }, /* 29 Left HP Mixer */
73 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
74 { 0x2B, 0x00 }, /* 2B HP Control */
75 { 0x2C, 0x1A }, /* 2C Left HP Volume */
76 { 0x2D, 0x1A }, /* 2D Right HP Volume */
77 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
78 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
80 { 0x30, 0x00 }, /* 30 Spk Control */
81 { 0x31, 0x2C }, /* 31 Left Spk Volume */
82 { 0x32, 0x2C }, /* 32 Right Spk Volume */
83 { 0x33, 0x00 }, /* 33 ALC Timing */
84 { 0x34, 0x00 }, /* 34 ALC Compressor */
85 { 0x35, 0x00 }, /* 35 ALC Expander */
86 { 0x36, 0x00 }, /* 36 ALC Gain */
87 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
88 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
89 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
90 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
91 { 0x3B, 0x00 }, /* 3B Line OutR Control */
92 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
93 { 0x3D, 0x00 }, /* 3D Jack Detect */
94 { 0x3E, 0x00 }, /* 3E Input Enable */
95 { 0x3F, 0x00 }, /* 3F Output Enable */
97 { 0x40, 0x00 }, /* 40 Level Control */
98 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
99 { 0x42, 0x00 }, /* 42 Bias Control */
100 { 0x43, 0x00 }, /* 43 DAC Control */
101 { 0x44, 0x06 }, /* 44 ADC Control */
102 { 0x45, 0x00 }, /* 45 Device Shutdown */
103 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
104 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
105 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
106 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
107 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
108 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
109 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
110 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
111 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
112 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
114 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
115 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
116 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
117 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
118 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
119 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
120 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
121 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
122 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
123 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
124 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
125 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
126 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
127 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
128 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
129 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
131 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
132 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
133 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
134 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
135 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
136 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
137 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
138 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
139 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
140 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
141 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
142 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
143 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
144 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
145 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
146 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
148 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
149 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
150 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
151 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
152 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
153 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
154 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
155 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
156 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
157 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
158 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
159 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
160 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
161 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
162 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
163 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
165 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
166 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
167 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
168 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
169 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
170 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
171 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
172 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
173 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
174 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
175 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
176 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
177 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
178 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
179 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
180 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
182 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
183 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
184 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
185 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
186 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
187 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
188 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
189 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
190 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
191 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
192 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
193 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
194 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
195 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
196 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
197 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
199 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
200 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
201 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
202 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
203 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
204 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
205 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
206 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
207 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
208 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
209 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
210 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
211 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
212 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
213 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
214 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
216 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
217 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
218 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
219 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
220 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
221 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
222 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
223 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
224 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
225 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
226 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
227 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
228 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
229 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
230 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
231 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
233 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
234 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
235 { 0xC2, 0x00 }, /* C2 Sample Rate */
236 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
237 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
238 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
239 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
240 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
241 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
242 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
243 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
244 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
245 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
246 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
247 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
248 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
250 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
251 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
254 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
257 case M98090_REG_SOFTWARE_RESET:
258 case M98090_REG_DEVICE_STATUS:
259 case M98090_REG_JACK_STATUS:
260 case M98090_REG_REVISION_ID:
267 static bool max98090_readable_register(struct device *dev, unsigned int reg)
270 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
271 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
272 case M98090_REG_REVISION_ID:
279 static int max98090_reset(struct max98090_priv *max98090)
283 /* Reset the codec by writing to this write-only reset register */
284 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
285 M98090_SWRESET_MASK);
287 dev_err(max98090->codec->dev,
288 "Failed to reset codec: %d\n", ret);
296 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
297 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
298 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
301 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
303 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
306 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
307 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
308 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
311 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
312 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
314 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
317 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
319 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
320 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
321 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
322 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
323 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
325 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
326 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
327 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
330 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
331 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
332 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
333 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
334 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
335 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
338 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
339 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
340 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
341 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
342 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
343 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
346 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
347 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
348 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
349 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
350 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
351 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
354 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
357 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
358 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
359 struct soc_mixer_control *mc =
360 (struct soc_mixer_control *)kcontrol->private_value;
361 unsigned int mask = (1 << fls(mc->max)) - 1;
362 unsigned int val = snd_soc_read(codec, mc->reg);
363 unsigned int *select;
366 case M98090_REG_MIC1_INPUT_LEVEL:
367 select = &(max98090->pa1en);
369 case M98090_REG_MIC2_INPUT_LEVEL:
370 select = &(max98090->pa2en);
372 case M98090_REG_ADC_SIDETONE:
373 select = &(max98090->sidetone);
379 val = (val >> mc->shift) & mask;
382 /* If on, return the volume */
386 /* If off, return last stored value */
390 ucontrol->value.integer.value[0] = val;
394 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
395 struct snd_ctl_elem_value *ucontrol)
397 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
398 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
399 struct soc_mixer_control *mc =
400 (struct soc_mixer_control *)kcontrol->private_value;
401 unsigned int mask = (1 << fls(mc->max)) - 1;
402 unsigned int sel = ucontrol->value.integer.value[0];
403 unsigned int val = snd_soc_read(codec, mc->reg);
404 unsigned int *select;
407 case M98090_REG_MIC1_INPUT_LEVEL:
408 select = &(max98090->pa1en);
410 case M98090_REG_MIC2_INPUT_LEVEL:
411 select = &(max98090->pa2en);
413 case M98090_REG_ADC_SIDETONE:
414 select = &(max98090->sidetone);
420 val = (val >> mc->shift) & mask;
422 if (sel < 0 || sel > mc->max)
427 /* Setting a volume is only valid if it is already On */
431 /* Write what was already there */
435 snd_soc_update_bits(codec, mc->reg,
439 return *select != val;
442 static const char *max98090_perf_pwr_text[] =
443 { "High Performance", "Low Power" };
444 static const char *max98090_pwr_perf_text[] =
445 { "Low Power", "High Performance" };
447 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
448 M98090_REG_BIAS_CONTROL,
449 M98090_VCM_MODE_SHIFT,
450 max98090_pwr_perf_text);
452 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
454 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
455 M98090_REG_ADC_CONTROL,
457 max98090_osr128_text);
459 static const char *max98090_mode_text[] = { "Voice", "Music" };
461 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
462 M98090_REG_FILTER_CONFIG,
466 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
467 M98090_REG_FILTER_CONFIG,
468 M98090_FLT_DMIC34MODE_SHIFT,
471 static const char *max98090_drcatk_text[] =
472 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
474 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
475 M98090_REG_DRC_TIMING,
477 max98090_drcatk_text);
479 static const char *max98090_drcrls_text[] =
480 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
482 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
483 M98090_REG_DRC_TIMING,
485 max98090_drcrls_text);
487 static const char *max98090_alccmp_text[] =
488 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
490 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
491 M98090_REG_DRC_COMPRESSOR,
493 max98090_alccmp_text);
495 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
497 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
498 M98090_REG_DRC_EXPANDER,
500 max98090_drcexp_text);
502 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
503 M98090_REG_DAC_CONTROL,
504 M98090_PERFMODE_SHIFT,
505 max98090_perf_pwr_text);
507 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
508 M98090_REG_DAC_CONTROL,
510 max98090_pwr_perf_text);
512 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
513 M98090_REG_ADC_CONTROL,
515 max98090_pwr_perf_text);
517 static const struct snd_kcontrol_new max98090_snd_controls[] = {
518 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
520 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
521 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
523 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
524 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
525 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
526 max98090_put_enab_tlv, max98090_micboost_tlv),
528 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
529 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
530 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
531 max98090_put_enab_tlv, max98090_micboost_tlv),
533 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
534 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
537 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
538 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
541 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
542 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
543 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
545 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
546 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
547 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
549 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
550 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
553 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
554 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
557 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
558 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
559 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
560 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
562 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
563 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
565 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
566 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
569 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
570 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
572 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
573 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
576 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
577 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
578 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
579 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
581 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
582 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
583 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
584 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
585 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
586 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
587 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
588 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
589 SOC_ENUM("Filter Mode", max98090_mode_enum),
590 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
591 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
592 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
593 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
594 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
595 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
596 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
597 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
598 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
599 max98090_put_enab_tlv, max98090_sdg_tlv),
600 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
601 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
603 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
604 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
606 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
607 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
608 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
609 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
610 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
611 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
612 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
613 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
614 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
616 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
617 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
620 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
621 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
622 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
623 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
624 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
625 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
626 max98090_alcmakeup_tlv),
627 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
628 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
629 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
630 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
631 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
632 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
633 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
634 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
636 SOC_ENUM("DAC HP Playback Performance Mode",
637 max98090_dac_perfmode_enum),
638 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
640 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
641 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
642 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
643 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
644 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
645 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
647 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
648 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
649 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
650 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
651 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
652 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
654 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
655 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
656 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
657 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
658 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
659 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
661 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
662 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
663 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
665 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
666 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
667 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
668 0, max98090_spk_tlv),
670 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
671 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
672 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
674 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
675 M98090_HPLM_SHIFT, 1, 1),
676 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
677 M98090_HPRM_SHIFT, 1, 1),
679 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
680 M98090_SPLM_SHIFT, 1, 1),
681 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
682 M98090_SPRM_SHIFT, 1, 1),
684 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
685 M98090_RCVLM_SHIFT, 1, 1),
686 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
687 M98090_RCVRM_SHIFT, 1, 1),
689 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
690 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
691 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
692 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
693 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
694 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
696 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
697 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
698 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
701 static const struct snd_kcontrol_new max98091_snd_controls[] = {
703 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
704 M98090_DMIC34_ZEROPAD_SHIFT,
705 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
707 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
708 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
709 M98090_FLT_DMIC34HPF_SHIFT,
710 M98090_FLT_DMIC34HPF_NUM - 1, 0),
712 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
713 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
715 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
716 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
719 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
720 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
722 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
723 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
726 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
727 M98090_REG_DMIC34_BIQUAD_BASE, 15),
728 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
729 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
731 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
732 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
733 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
736 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
737 struct snd_kcontrol *kcontrol, int event)
739 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
740 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
742 unsigned int val = snd_soc_read(codec, w->reg);
744 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
745 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
747 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
750 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
751 max98090->pa1en = val - 1; /* Update for volatile */
753 max98090->pa2en = val - 1; /* Update for volatile */
758 case SND_SOC_DAPM_POST_PMU:
759 /* If turning on, set to most recently selected volume */
760 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
761 val = max98090->pa1en + 1;
763 val = max98090->pa2en + 1;
765 case SND_SOC_DAPM_POST_PMD:
766 /* If turning off, turn off */
773 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
774 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
775 val << M98090_MIC_PA1EN_SHIFT);
777 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
778 val << M98090_MIC_PA2EN_SHIFT);
783 static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
784 struct snd_kcontrol *kcontrol, int event)
786 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
787 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
789 if (event & SND_SOC_DAPM_POST_PMU)
790 max98090->shdn_pending = true;
796 static const char *mic1_mux_text[] = { "IN12", "IN56" };
798 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
799 M98090_REG_INPUT_MODE,
800 M98090_EXTMIC1_SHIFT,
803 static const struct snd_kcontrol_new max98090_mic1_mux =
804 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
806 static const char *mic2_mux_text[] = { "IN34", "IN56" };
808 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
809 M98090_REG_INPUT_MODE,
810 M98090_EXTMIC2_SHIFT,
813 static const struct snd_kcontrol_new max98090_mic2_mux =
814 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
816 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
818 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
820 static const struct snd_kcontrol_new max98090_dmic_mux =
821 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
823 static const char *max98090_micpre_text[] = { "Off", "On" };
825 static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum,
826 M98090_REG_MIC1_INPUT_LEVEL,
827 M98090_MIC_PA1EN_SHIFT,
828 max98090_micpre_text);
830 static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum,
831 M98090_REG_MIC2_INPUT_LEVEL,
832 M98090_MIC_PA2EN_SHIFT,
833 max98090_micpre_text);
835 /* LINEA mixer switch */
836 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
837 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
838 M98090_IN1SEEN_SHIFT, 1, 0),
839 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
840 M98090_IN3SEEN_SHIFT, 1, 0),
841 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
842 M98090_IN5SEEN_SHIFT, 1, 0),
843 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
844 M98090_IN34DIFF_SHIFT, 1, 0),
847 /* LINEB mixer switch */
848 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
849 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
850 M98090_IN2SEEN_SHIFT, 1, 0),
851 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
852 M98090_IN4SEEN_SHIFT, 1, 0),
853 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
854 M98090_IN6SEEN_SHIFT, 1, 0),
855 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
856 M98090_IN56DIFF_SHIFT, 1, 0),
859 /* Left ADC mixer switch */
860 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
861 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
862 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
863 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
864 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
865 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
866 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
867 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
868 M98090_MIXADL_LINEA_SHIFT, 1, 0),
869 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
870 M98090_MIXADL_LINEB_SHIFT, 1, 0),
871 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
872 M98090_MIXADL_MIC1_SHIFT, 1, 0),
873 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
874 M98090_MIXADL_MIC2_SHIFT, 1, 0),
877 /* Right ADC mixer switch */
878 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
879 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
880 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
881 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
882 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
883 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
884 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
885 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
886 M98090_MIXADR_LINEA_SHIFT, 1, 0),
887 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
888 M98090_MIXADR_LINEB_SHIFT, 1, 0),
889 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
890 M98090_MIXADR_MIC1_SHIFT, 1, 0),
891 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
892 M98090_MIXADR_MIC2_SHIFT, 1, 0),
895 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
897 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
898 M98090_REG_IO_CONFIGURATION,
902 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
903 M98090_REG_IO_CONFIGURATION,
907 static const struct snd_kcontrol_new max98090_ltenl_mux =
908 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
910 static const struct snd_kcontrol_new max98090_ltenr_mux =
911 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
913 static const char *lben_mux_text[] = { "Normal", "Loopback" };
915 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
916 M98090_REG_IO_CONFIGURATION,
920 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
921 M98090_REG_IO_CONFIGURATION,
925 static const struct snd_kcontrol_new max98090_lbenl_mux =
926 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
928 static const struct snd_kcontrol_new max98090_lbenr_mux =
929 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
931 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
933 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
935 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
936 M98090_REG_ADC_SIDETONE,
940 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
941 M98090_REG_ADC_SIDETONE,
945 static const struct snd_kcontrol_new max98090_stenl_mux =
946 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
948 static const struct snd_kcontrol_new max98090_stenr_mux =
949 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
951 /* Left speaker mixer switch */
953 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
954 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
955 M98090_MIXSPL_DACL_SHIFT, 1, 0),
956 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
957 M98090_MIXSPL_DACR_SHIFT, 1, 0),
958 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
959 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
960 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
961 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
962 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
963 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
964 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
965 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
968 /* Right speaker mixer switch */
970 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
971 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
972 M98090_MIXSPR_DACL_SHIFT, 1, 0),
973 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
974 M98090_MIXSPR_DACR_SHIFT, 1, 0),
975 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
976 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
977 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
978 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
979 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
980 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
981 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
982 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
985 /* Left headphone mixer switch */
986 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
987 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
988 M98090_MIXHPL_DACL_SHIFT, 1, 0),
989 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
990 M98090_MIXHPL_DACR_SHIFT, 1, 0),
991 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
992 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
993 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
994 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
995 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
996 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
997 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
998 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1001 /* Right headphone mixer switch */
1002 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1003 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1004 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1005 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1006 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1007 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1008 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1009 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1010 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1011 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1012 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1013 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1014 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1017 /* Left receiver mixer switch */
1018 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1019 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1020 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1021 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1022 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1023 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1024 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1025 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1026 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1027 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1028 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1029 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1030 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1033 /* Right receiver mixer switch */
1034 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1035 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1036 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1037 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1038 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1039 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1040 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1041 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1042 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1043 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1044 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1045 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1046 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1049 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1051 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1052 M98090_REG_LOUTR_MIXER,
1053 M98090_LINMOD_SHIFT,
1056 static const struct snd_kcontrol_new max98090_linmod_mux =
1057 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1059 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1062 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1064 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1065 M98090_REG_HP_CONTROL,
1066 M98090_MIXHPLSEL_SHIFT,
1069 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1070 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1072 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1073 M98090_REG_HP_CONTROL,
1074 M98090_MIXHPRSEL_SHIFT,
1077 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1078 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1080 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1081 SND_SOC_DAPM_INPUT("MIC1"),
1082 SND_SOC_DAPM_INPUT("MIC2"),
1083 SND_SOC_DAPM_INPUT("DMICL"),
1084 SND_SOC_DAPM_INPUT("DMICR"),
1085 SND_SOC_DAPM_INPUT("IN1"),
1086 SND_SOC_DAPM_INPUT("IN2"),
1087 SND_SOC_DAPM_INPUT("IN3"),
1088 SND_SOC_DAPM_INPUT("IN4"),
1089 SND_SOC_DAPM_INPUT("IN5"),
1090 SND_SOC_DAPM_INPUT("IN6"),
1091 SND_SOC_DAPM_INPUT("IN12"),
1092 SND_SOC_DAPM_INPUT("IN34"),
1093 SND_SOC_DAPM_INPUT("IN56"),
1095 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1096 M98090_MBEN_SHIFT, 0, NULL, 0),
1097 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1098 M98090_SHDNN_SHIFT, 0, NULL, 0),
1099 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1100 M98090_SDIEN_SHIFT, 0, NULL, 0),
1101 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1102 M98090_SDOEN_SHIFT, 0, NULL, 0),
1103 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1104 M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
1105 SND_SOC_DAPM_POST_PMU),
1106 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1107 M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
1108 SND_SOC_DAPM_POST_PMU),
1109 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1110 M98090_AHPF_SHIFT, 0, NULL, 0),
1113 * Note: Sysclk and misc power supplies are taken care of by SHDN
1116 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1117 0, 0, &max98090_mic1_mux),
1119 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1120 0, 0, &max98090_mic2_mux),
1122 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1124 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1125 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1126 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1128 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1129 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1130 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1132 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1133 &max98090_linea_mixer_controls[0],
1134 ARRAY_SIZE(max98090_linea_mixer_controls)),
1136 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1137 &max98090_lineb_mixer_controls[0],
1138 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1140 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1141 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1142 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1143 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1145 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1146 &max98090_left_adc_mixer_controls[0],
1147 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1149 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1150 &max98090_right_adc_mixer_controls[0],
1151 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1153 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1154 M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
1155 SND_SOC_DAPM_POST_PMU),
1156 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1157 M98090_ADREN_SHIFT, 0, max98090_shdn_event,
1158 SND_SOC_DAPM_POST_PMU),
1160 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1161 SND_SOC_NOPM, 0, 0),
1162 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1163 SND_SOC_NOPM, 0, 0),
1165 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1166 0, 0, &max98090_lbenl_mux),
1168 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1169 0, 0, &max98090_lbenr_mux),
1171 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1172 0, 0, &max98090_ltenl_mux),
1174 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1175 0, 0, &max98090_ltenr_mux),
1177 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1178 0, 0, &max98090_stenl_mux),
1180 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1181 0, 0, &max98090_stenr_mux),
1183 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1184 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1186 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1187 M98090_DALEN_SHIFT, 0),
1188 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1189 M98090_DAREN_SHIFT, 0),
1191 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1192 &max98090_left_hp_mixer_controls[0],
1193 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1195 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1196 &max98090_right_hp_mixer_controls[0],
1197 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1199 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1200 &max98090_left_speaker_mixer_controls[0],
1201 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1203 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1204 &max98090_right_speaker_mixer_controls[0],
1205 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1207 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1208 &max98090_left_rcv_mixer_controls[0],
1209 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1211 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1212 &max98090_right_rcv_mixer_controls[0],
1213 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1215 SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0,
1216 &max98090_linmod_mux),
1218 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
1219 &max98090_mixhplsel_mux),
1221 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
1222 &max98090_mixhprsel_mux),
1224 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1225 M98090_HPLEN_SHIFT, 0, NULL, 0),
1226 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1227 M98090_HPREN_SHIFT, 0, NULL, 0),
1229 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1230 M98090_SPLEN_SHIFT, 0, NULL, 0),
1231 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1232 M98090_SPREN_SHIFT, 0, NULL, 0),
1234 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1235 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1236 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1237 M98090_RCVREN_SHIFT, 0, NULL, 0),
1239 SND_SOC_DAPM_OUTPUT("HPL"),
1240 SND_SOC_DAPM_OUTPUT("HPR"),
1241 SND_SOC_DAPM_OUTPUT("SPKL"),
1242 SND_SOC_DAPM_OUTPUT("SPKR"),
1243 SND_SOC_DAPM_OUTPUT("RCVL"),
1244 SND_SOC_DAPM_OUTPUT("RCVR"),
1247 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1248 SND_SOC_DAPM_INPUT("DMIC3"),
1249 SND_SOC_DAPM_INPUT("DMIC4"),
1251 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1252 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1253 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1254 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1257 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1258 {"MIC1 Input", NULL, "MIC1"},
1259 {"MIC2 Input", NULL, "MIC2"},
1261 {"DMICL", NULL, "DMICL_ENA"},
1262 {"DMICL", NULL, "DMICR_ENA"},
1263 {"DMICR", NULL, "DMICL_ENA"},
1264 {"DMICR", NULL, "DMICR_ENA"},
1265 {"DMICL", NULL, "AHPF"},
1266 {"DMICR", NULL, "AHPF"},
1268 /* MIC1 input mux */
1269 {"MIC1 Mux", "IN12", "IN12"},
1270 {"MIC1 Mux", "IN56", "IN56"},
1272 /* MIC2 input mux */
1273 {"MIC2 Mux", "IN34", "IN34"},
1274 {"MIC2 Mux", "IN56", "IN56"},
1276 {"MIC1 Input", NULL, "MIC1 Mux"},
1277 {"MIC2 Input", NULL, "MIC2 Mux"},
1279 /* Left ADC input mixer */
1280 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1281 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1282 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1283 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1284 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1285 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1286 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1288 /* Right ADC input mixer */
1289 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1290 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1291 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1292 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1293 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1294 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1295 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1297 /* Line A input mixer */
1298 {"LINEA Mixer", "IN1 Switch", "IN1"},
1299 {"LINEA Mixer", "IN3 Switch", "IN3"},
1300 {"LINEA Mixer", "IN5 Switch", "IN5"},
1301 {"LINEA Mixer", "IN34 Switch", "IN34"},
1303 /* Line B input mixer */
1304 {"LINEB Mixer", "IN2 Switch", "IN2"},
1305 {"LINEB Mixer", "IN4 Switch", "IN4"},
1306 {"LINEB Mixer", "IN6 Switch", "IN6"},
1307 {"LINEB Mixer", "IN56 Switch", "IN56"},
1309 {"LINEA Input", NULL, "LINEA Mixer"},
1310 {"LINEB Input", NULL, "LINEB Mixer"},
1313 {"ADCL", NULL, "Left ADC Mixer"},
1314 {"ADCR", NULL, "Right ADC Mixer"},
1315 {"ADCL", NULL, "SHDN"},
1316 {"ADCR", NULL, "SHDN"},
1318 {"DMIC Mux", "ADC", "ADCL"},
1319 {"DMIC Mux", "ADC", "ADCR"},
1320 {"DMIC Mux", "DMIC", "DMICL"},
1321 {"DMIC Mux", "DMIC", "DMICR"},
1323 {"LBENL Mux", "Normal", "DMIC Mux"},
1324 {"LBENL Mux", "Loopback", "LTENL Mux"},
1325 {"LBENR Mux", "Normal", "DMIC Mux"},
1326 {"LBENR Mux", "Loopback", "LTENR Mux"},
1328 {"AIFOUTL", NULL, "LBENL Mux"},
1329 {"AIFOUTR", NULL, "LBENR Mux"},
1330 {"AIFOUTL", NULL, "SHDN"},
1331 {"AIFOUTR", NULL, "SHDN"},
1332 {"AIFOUTL", NULL, "SDOEN"},
1333 {"AIFOUTR", NULL, "SDOEN"},
1335 {"LTENL Mux", "Normal", "AIFINL"},
1336 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1337 {"LTENR Mux", "Normal", "AIFINR"},
1338 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1340 {"DACL", NULL, "LTENL Mux"},
1341 {"DACR", NULL, "LTENR Mux"},
1343 {"STENL Mux", "Sidetone Left", "ADCL"},
1344 {"STENL Mux", "Sidetone Left", "DMICL"},
1345 {"STENR Mux", "Sidetone Right", "ADCR"},
1346 {"STENR Mux", "Sidetone Right", "DMICR"},
1347 {"DACL", NULL, "STENL Mux"},
1348 {"DACR", NULL, "STENR Mux"},
1350 {"AIFINL", NULL, "SHDN"},
1351 {"AIFINR", NULL, "SHDN"},
1352 {"AIFINL", NULL, "SDIEN"},
1353 {"AIFINR", NULL, "SDIEN"},
1354 {"DACL", NULL, "SHDN"},
1355 {"DACR", NULL, "SHDN"},
1357 /* Left headphone output mixer */
1358 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1359 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1360 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1361 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1362 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1363 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1365 /* Right headphone output mixer */
1366 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1367 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1368 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1369 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1370 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1371 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1373 /* Left speaker output mixer */
1374 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1375 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1376 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1377 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1378 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1379 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1381 /* Right speaker output mixer */
1382 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1383 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1384 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1385 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1386 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1387 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1389 /* Left Receiver output mixer */
1390 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1391 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1392 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1393 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1394 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1395 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1397 /* Right Receiver output mixer */
1398 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1399 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1400 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1401 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1402 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1403 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1405 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1408 * Disable this for lowest power if bypassing
1409 * the DAC with an analog signal
1411 {"HP Left Out", NULL, "DACL"},
1412 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1414 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1417 * Disable this for lowest power if bypassing
1418 * the DAC with an analog signal
1420 {"HP Right Out", NULL, "DACR"},
1421 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1423 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1424 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1425 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1427 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1428 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1429 {"RCV Right Out", NULL, "LINMOD Mux"},
1431 {"HPL", NULL, "HP Left Out"},
1432 {"HPR", NULL, "HP Right Out"},
1433 {"SPKL", NULL, "SPK Left Out"},
1434 {"SPKR", NULL, "SPK Right Out"},
1435 {"RCVL", NULL, "RCV Left Out"},
1436 {"RCVR", NULL, "RCV Right Out"},
1439 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1441 {"DMIC3", NULL, "DMIC3_ENA"},
1442 {"DMIC4", NULL, "DMIC4_ENA"},
1443 {"DMIC3", NULL, "AHPF"},
1444 {"DMIC4", NULL, "AHPF"},
1447 static int max98090_add_widgets(struct snd_soc_codec *codec)
1449 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1450 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1452 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1453 ARRAY_SIZE(max98090_snd_controls));
1455 if (max98090->devtype == MAX98091) {
1456 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1457 ARRAY_SIZE(max98091_snd_controls));
1460 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1461 ARRAY_SIZE(max98090_dapm_widgets));
1463 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1464 ARRAY_SIZE(max98090_dapm_routes));
1466 if (max98090->devtype == MAX98091) {
1467 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1468 ARRAY_SIZE(max98091_dapm_widgets));
1470 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1471 ARRAY_SIZE(max98091_dapm_routes));
1477 static const int pclk_rates[] = {
1478 12000000, 12000000, 13000000, 13000000,
1479 16000000, 16000000, 19200000, 19200000
1482 static const int lrclk_rates[] = {
1483 8000, 16000, 8000, 16000,
1484 8000, 16000, 8000, 16000
1487 static const int user_pclk_rates[] = {
1488 13000000, 13000000, 19200000, 19200000,
1491 static const int user_lrclk_rates[] = {
1492 44100, 48000, 44100, 48000,
1495 static const unsigned long long ni_value[] = {
1499 static const unsigned long long mi_value[] = {
1500 8125, 1625, 1500, 25
1503 static void max98090_configure_bclk(struct snd_soc_codec *codec)
1505 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1506 unsigned long long ni;
1509 if (!max98090->sysclk) {
1510 dev_err(codec->dev, "No SYSCLK configured\n");
1514 if (!max98090->bclk || !max98090->lrclk) {
1515 dev_err(codec->dev, "No audio clocks configured\n");
1519 /* Skip configuration when operating as slave */
1520 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1525 /* Check for supported PCLK to LRCLK ratios */
1526 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1527 if ((pclk_rates[i] == max98090->sysclk) &&
1528 (lrclk_rates[i] == max98090->lrclk)) {
1530 "Found supported PCLK to LRCLK rates 0x%x\n",
1533 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1535 (i + 0x8) << M98090_FREQ_SHIFT);
1536 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1537 M98090_USE_M1_MASK, 0);
1542 /* Check for user calculated MI and NI ratios */
1543 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1544 if ((user_pclk_rates[i] == max98090->sysclk) &&
1545 (user_lrclk_rates[i] == max98090->lrclk)) {
1547 "Found user supported PCLK to LRCLK rates\n");
1548 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1549 i, ni_value[i], mi_value[i]);
1551 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1552 M98090_FREQ_MASK, 0);
1553 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1555 1 << M98090_USE_M1_SHIFT);
1557 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1558 (ni_value[i] >> 8) & 0x7F);
1559 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1560 ni_value[i] & 0xFF);
1561 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1562 (mi_value[i] >> 8) & 0x7F);
1563 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1564 mi_value[i] & 0xFF);
1571 * Calculate based on MI = 65536 (not as good as either method above)
1573 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1574 M98090_FREQ_MASK, 0);
1575 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1576 M98090_USE_M1_MASK, 0);
1579 * Configure NI when operating as master
1580 * Note: There is a small, but significant audio quality improvement
1581 * by calculating ni and mi.
1583 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1584 * (unsigned long long int)max98090->lrclk;
1585 do_div(ni, (unsigned long long int)max98090->sysclk);
1586 dev_info(codec->dev, "No better method found\n");
1587 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1588 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1590 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1593 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1596 struct snd_soc_codec *codec = codec_dai->codec;
1597 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1598 struct max98090_cdata *cdata;
1601 max98090->dai_fmt = fmt;
1602 cdata = &max98090->dai[0];
1604 if (fmt != cdata->fmt) {
1608 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1609 case SND_SOC_DAIFMT_CBS_CFS:
1610 /* Set to slave mode PLL - MAS mode off */
1611 snd_soc_write(codec,
1612 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1613 snd_soc_write(codec,
1614 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1615 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1616 M98090_USE_M1_MASK, 0);
1617 max98090->master = false;
1619 case SND_SOC_DAIFMT_CBM_CFM:
1620 /* Set to master mode */
1621 if (max98090->tdm_slots == 4) {
1623 regval |= M98090_MAS_MASK |
1625 } else if (max98090->tdm_slots == 3) {
1627 regval |= M98090_MAS_MASK |
1630 /* Few TDM slots, or No TDM */
1631 regval |= M98090_MAS_MASK |
1634 max98090->master = true;
1636 case SND_SOC_DAIFMT_CBS_CFM:
1637 case SND_SOC_DAIFMT_CBM_CFS:
1639 dev_err(codec->dev, "DAI clock mode unsupported");
1642 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1645 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1646 case SND_SOC_DAIFMT_I2S:
1647 regval |= M98090_DLY_MASK;
1649 case SND_SOC_DAIFMT_LEFT_J:
1651 case SND_SOC_DAIFMT_RIGHT_J:
1652 regval |= M98090_RJ_MASK;
1654 case SND_SOC_DAIFMT_DSP_A:
1655 /* Not supported mode */
1657 dev_err(codec->dev, "DAI format unsupported");
1661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1662 case SND_SOC_DAIFMT_NB_NF:
1664 case SND_SOC_DAIFMT_NB_IF:
1665 regval |= M98090_WCI_MASK;
1667 case SND_SOC_DAIFMT_IB_NF:
1668 regval |= M98090_BCI_MASK;
1670 case SND_SOC_DAIFMT_IB_IF:
1671 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1674 dev_err(codec->dev, "DAI invert mode unsupported");
1679 * This accommodates an inverted logic in the MAX98090 chip
1680 * for Bit Clock Invert (BCI). The inverted logic is only
1681 * seen for the case of TDM mode. The remaining cases have
1684 if (max98090->tdm_slots > 1)
1685 regval ^= M98090_BCI_MASK;
1687 snd_soc_write(codec,
1688 M98090_REG_INTERFACE_FORMAT, regval);
1694 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1695 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1697 struct snd_soc_codec *codec = codec_dai->codec;
1698 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1699 struct max98090_cdata *cdata;
1700 cdata = &max98090->dai[0];
1702 if (slots < 0 || slots > 4)
1705 max98090->tdm_slots = slots;
1706 max98090->tdm_width = slot_width;
1708 if (max98090->tdm_slots > 1) {
1709 /* SLOTL SLOTR SLOTDLY */
1710 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1711 0 << M98090_TDM_SLOTL_SHIFT |
1712 1 << M98090_TDM_SLOTR_SHIFT |
1713 0 << M98090_TDM_SLOTDLY_SHIFT);
1716 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1722 * Normally advisable to set TDM first, but this permits either order
1725 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1730 static int max98090_set_bias_level(struct snd_soc_codec *codec,
1731 enum snd_soc_bias_level level)
1733 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1737 case SND_SOC_BIAS_ON:
1740 case SND_SOC_BIAS_PREPARE:
1742 * SND_SOC_BIAS_PREPARE is called while preparing for a
1743 * transition to ON or away from ON. If current bias_level
1744 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1745 * away from ON. Disable the clock in that case, otherwise
1748 if (IS_ERR(max98090->mclk))
1751 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
1752 clk_disable_unprepare(max98090->mclk);
1754 ret = clk_prepare_enable(max98090->mclk);
1760 case SND_SOC_BIAS_STANDBY:
1761 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1762 ret = regcache_sync(max98090->regmap);
1765 "Failed to sync cache: %d\n", ret);
1771 case SND_SOC_BIAS_OFF:
1772 /* Set internal pull-up to lowest power mode */
1773 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1774 M98090_JDWK_MASK, M98090_JDWK_MASK);
1775 regcache_mark_dirty(max98090->regmap);
1781 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
1783 static const int comp_lrclk_rates[] = {
1784 8000, 16000, 32000, 44100, 48000, 96000
1791 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1792 } settings[6]; /* One for each dmic divisor. */
1795 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1799 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1800 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1801 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1802 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1803 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1804 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1810 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1811 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1812 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1813 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1814 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1815 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1821 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1822 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1823 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1824 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1825 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1826 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1832 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1833 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1834 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1835 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1836 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1837 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1843 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1844 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1845 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1846 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1847 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1848 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1853 static int max98090_find_divisor(int target_freq, int pclk)
1855 int current_diff = INT_MAX;
1856 int test_diff = INT_MAX;
1857 int divisor_index = 0;
1860 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
1861 test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1862 if (test_diff < current_diff) {
1863 current_diff = test_diff;
1868 return divisor_index;
1871 static int max98090_find_closest_pclk(int pclk)
1877 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
1878 if (pclk == dmic_table[i].pclk)
1880 if (pclk < dmic_table[i].pclk) {
1883 m1 = pclk - dmic_table[i-1].pclk;
1884 m2 = dmic_table[i].pclk - pclk;
1895 static int max98090_configure_dmic(struct max98090_priv *max98090,
1896 int target_dmic_clk, int pclk, int fs)
1904 pclk_index = max98090_find_closest_pclk(pclk);
1908 micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
1910 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1911 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1915 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1916 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1918 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1920 micclk_index << M98090_MICCLK_SHIFT);
1922 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1923 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1924 dmic_comp << M98090_DMIC_COMP_SHIFT |
1925 dmic_freq << M98090_DMIC_FREQ_SHIFT);
1930 static int max98090_dai_startup(struct snd_pcm_substream *substream,
1931 struct snd_soc_dai *dai)
1933 struct snd_soc_component *component = dai->component;
1934 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1935 unsigned int fmt = max98090->dai_fmt;
1937 /* Remove 24-bit format support if it is not in right justified mode. */
1938 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) {
1939 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
1940 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16);
1945 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1946 struct snd_pcm_hw_params *params,
1947 struct snd_soc_dai *dai)
1949 struct snd_soc_codec *codec = dai->codec;
1950 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1951 struct max98090_cdata *cdata;
1953 cdata = &max98090->dai[0];
1954 max98090->bclk = snd_soc_params_to_bclk(params);
1955 if (params_channels(params) == 1)
1956 max98090->bclk *= 2;
1958 max98090->lrclk = params_rate(params);
1960 switch (params_width(params)) {
1962 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1969 if (max98090->master)
1970 max98090_configure_bclk(codec);
1972 cdata->rate = max98090->lrclk;
1974 /* Update filter mode */
1975 if (max98090->lrclk < 24000)
1976 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1977 M98090_MODE_MASK, 0);
1979 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1980 M98090_MODE_MASK, M98090_MODE_MASK);
1982 /* Update sample rate mode */
1983 if (max98090->lrclk < 50000)
1984 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1985 M98090_DHF_MASK, 0);
1987 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1988 M98090_DHF_MASK, M98090_DHF_MASK);
1990 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
1999 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
2000 int clk_id, unsigned int freq, int dir)
2002 struct snd_soc_codec *codec = dai->codec;
2003 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2005 /* Requested clock frequency is already setup */
2006 if (freq == max98090->sysclk)
2009 if (!IS_ERR(max98090->mclk)) {
2010 freq = clk_round_rate(max98090->mclk, freq);
2011 clk_set_rate(max98090->mclk, freq);
2014 /* Setup clocks for slave mode, and using the PLL
2015 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
2016 * 0x02 (when master clk is 20MHz to 40MHz)..
2017 * 0x03 (when master clk is 40MHz to 60MHz)..
2019 if ((freq >= 10000000) && (freq <= 20000000)) {
2020 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2022 max98090->pclk = freq;
2023 } else if ((freq > 20000000) && (freq <= 40000000)) {
2024 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2026 max98090->pclk = freq >> 1;
2027 } else if ((freq > 40000000) && (freq <= 60000000)) {
2028 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2030 max98090->pclk = freq >> 2;
2032 dev_err(codec->dev, "Invalid master clock frequency\n");
2036 max98090->sysclk = freq;
2041 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2043 struct snd_soc_codec *codec = codec_dai->codec;
2046 regval = mute ? M98090_DVM_MASK : 0;
2047 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
2048 M98090_DVM_MASK, regval);
2053 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2054 struct snd_soc_dai *dai)
2056 struct snd_soc_codec *codec = dai->codec;
2057 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2060 case SNDRV_PCM_TRIGGER_START:
2061 case SNDRV_PCM_TRIGGER_RESUME:
2062 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2063 if (!max98090->master && dai->active == 1)
2064 queue_delayed_work(system_power_efficient_wq,
2065 &max98090->pll_det_enable_work,
2066 msecs_to_jiffies(10));
2068 case SNDRV_PCM_TRIGGER_STOP:
2069 case SNDRV_PCM_TRIGGER_SUSPEND:
2070 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2071 if (!max98090->master && dai->active == 1)
2072 schedule_work(&max98090->pll_det_disable_work);
2081 static void max98090_pll_det_enable_work(struct work_struct *work)
2083 struct max98090_priv *max98090 =
2084 container_of(work, struct max98090_priv,
2085 pll_det_enable_work.work);
2086 struct snd_soc_codec *codec = max98090->codec;
2087 unsigned int status, mask;
2090 * Clear status register in order to clear possibly already occurred
2091 * PLL unlock. If PLL hasn't still locked, the status will be set
2092 * again and PLL unlock interrupt will occur.
2093 * Note this will clear all status bits
2095 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2098 * Queue jack work in case jack state has just changed but handler
2101 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2103 if (status & M98090_JDET_MASK)
2104 queue_delayed_work(system_power_efficient_wq,
2105 &max98090->jack_work,
2106 msecs_to_jiffies(100));
2108 /* Enable PLL unlock interrupt */
2109 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2111 1 << M98090_IULK_SHIFT);
2114 static void max98090_pll_det_disable_work(struct work_struct *work)
2116 struct max98090_priv *max98090 =
2117 container_of(work, struct max98090_priv, pll_det_disable_work);
2118 struct snd_soc_codec *codec = max98090->codec;
2120 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2122 /* Disable PLL unlock interrupt */
2123 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2124 M98090_IULK_MASK, 0);
2127 static void max98090_pll_work(struct work_struct *work)
2129 struct max98090_priv *max98090 =
2130 container_of(work, struct max98090_priv, pll_work);
2131 struct snd_soc_codec *codec = max98090->codec;
2133 if (!snd_soc_codec_is_active(codec))
2136 dev_info(codec->dev, "PLL unlocked\n");
2138 /* Toggle shutdown OFF then ON */
2139 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2140 M98090_SHDNN_MASK, 0);
2142 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2143 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2145 /* Give PLL time to lock */
2149 static void max98090_jack_work(struct work_struct *work)
2151 struct max98090_priv *max98090 = container_of(work,
2152 struct max98090_priv,
2154 struct snd_soc_codec *codec = max98090->codec;
2158 /* Read a second time */
2159 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2161 /* Strong pull up allows mic detection */
2162 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2163 M98090_JDWK_MASK, 0);
2167 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2169 /* Weak pull up allows only insertion detection */
2170 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2171 M98090_JDWK_MASK, M98090_JDWK_MASK);
2173 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2176 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2178 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2179 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2180 dev_dbg(codec->dev, "No Headset Detected\n");
2182 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2189 if (max98090->jack_state ==
2190 M98090_JACK_STATE_HEADSET) {
2193 "Headset Button Down Detected\n");
2196 * max98090_headset_button_event(codec)
2197 * could be defined, then called here.
2200 status |= SND_JACK_HEADSET;
2201 status |= SND_JACK_BTN_0;
2206 /* Line is reported as Headphone */
2207 /* Nokia Headset is reported as Headphone */
2208 /* Mono Headphone is reported as Headphone */
2209 dev_dbg(codec->dev, "Headphone Detected\n");
2211 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2213 status |= SND_JACK_HEADPHONE;
2217 case M98090_JKSNS_MASK:
2218 dev_dbg(codec->dev, "Headset Detected\n");
2220 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2222 status |= SND_JACK_HEADSET;
2227 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2231 snd_soc_jack_report(max98090->jack, status,
2232 SND_JACK_HEADSET | SND_JACK_BTN_0);
2235 static irqreturn_t max98090_interrupt(int irq, void *data)
2237 struct max98090_priv *max98090 = data;
2238 struct snd_soc_codec *codec = max98090->codec;
2241 unsigned int active;
2243 /* Treat interrupt before codec is initialized as spurious */
2247 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2249 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2253 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2258 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2262 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2267 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2268 active, mask, active & mask);
2275 if (active & M98090_CLD_MASK)
2276 dev_err(codec->dev, "M98090_CLD_MASK\n");
2278 if (active & M98090_SLD_MASK)
2279 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
2281 if (active & M98090_ULK_MASK) {
2282 dev_dbg(codec->dev, "M98090_ULK_MASK\n");
2283 schedule_work(&max98090->pll_work);
2286 if (active & M98090_JDET_MASK) {
2287 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2289 pm_wakeup_event(codec->dev, 100);
2291 queue_delayed_work(system_power_efficient_wq,
2292 &max98090->jack_work,
2293 msecs_to_jiffies(100));
2296 if (active & M98090_DRCACT_MASK)
2297 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2299 if (active & M98090_DRCCLP_MASK)
2300 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2306 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2308 * @codec: MAX98090 codec
2309 * @jack: jack to report detection events on
2311 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2312 * being used to bring out signals to the processor then only platform
2313 * data configuration is needed for MAX98090 and processor GPIOs should
2314 * be configured using snd_soc_jack_add_gpios() instead.
2316 * If no jack is supplied detection will be disabled.
2318 int max98090_mic_detect(struct snd_soc_codec *codec,
2319 struct snd_soc_jack *jack)
2321 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2323 dev_dbg(codec->dev, "max98090_mic_detect\n");
2325 max98090->jack = jack;
2327 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2329 1 << M98090_IJDET_SHIFT);
2331 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2336 /* Send an initial empty report */
2337 snd_soc_jack_report(max98090->jack, 0,
2338 SND_JACK_HEADSET | SND_JACK_BTN_0);
2340 queue_delayed_work(system_power_efficient_wq,
2341 &max98090->jack_work,
2342 msecs_to_jiffies(100));
2346 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2348 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2349 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2351 static const struct snd_soc_dai_ops max98090_dai_ops = {
2352 .startup = max98090_dai_startup,
2353 .set_sysclk = max98090_dai_set_sysclk,
2354 .set_fmt = max98090_dai_set_fmt,
2355 .set_tdm_slot = max98090_set_tdm_slot,
2356 .hw_params = max98090_dai_hw_params,
2357 .digital_mute = max98090_dai_digital_mute,
2358 .trigger = max98090_dai_trigger,
2361 static struct snd_soc_dai_driver max98090_dai[] = {
2365 .stream_name = "HiFi Playback",
2368 .rates = MAX98090_RATES,
2369 .formats = MAX98090_FORMATS,
2372 .stream_name = "HiFi Capture",
2375 .rates = MAX98090_RATES,
2376 .formats = MAX98090_FORMATS,
2378 .ops = &max98090_dai_ops,
2382 static int max98090_probe(struct snd_soc_codec *codec)
2384 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2385 struct max98090_cdata *cdata;
2386 enum max98090_type devtype;
2389 unsigned int micbias;
2391 dev_dbg(codec->dev, "max98090_probe\n");
2393 max98090->mclk = devm_clk_get(codec->dev, "mclk");
2394 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2395 return -EPROBE_DEFER;
2397 max98090->codec = codec;
2399 /* Reset the codec, the DSP core, and disable all interrupts */
2400 max98090_reset(max98090);
2402 /* Initialize private data */
2404 max98090->sysclk = (unsigned)-1;
2405 max98090->pclk = (unsigned)-1;
2406 max98090->master = false;
2408 cdata = &max98090->dai[0];
2409 cdata->rate = (unsigned)-1;
2410 cdata->fmt = (unsigned)-1;
2412 max98090->lin_state = 0;
2413 max98090->pa1en = 0;
2414 max98090->pa2en = 0;
2416 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2418 dev_err(codec->dev, "Failed to read device revision: %d\n",
2423 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2425 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2426 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2428 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2431 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2434 if (max98090->devtype != devtype) {
2435 dev_warn(codec->dev, "Mismatch in DT specified CODEC type.\n");
2436 max98090->devtype = devtype;
2439 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2441 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2442 INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2443 max98090_pll_det_enable_work);
2444 INIT_WORK(&max98090->pll_det_disable_work,
2445 max98090_pll_det_disable_work);
2446 INIT_WORK(&max98090->pll_work, max98090_pll_work);
2448 /* Enable jack detection */
2449 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2450 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2453 * Clear any old interrupts.
2454 * An old interrupt ocurring prior to installing the ISR
2455 * can keep a new interrupt from generating a trigger.
2457 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2459 /* High Performance is default */
2460 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2462 1 << M98090_DACHP_SHIFT);
2463 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2464 M98090_PERFMODE_MASK,
2465 0 << M98090_PERFMODE_SHIFT);
2466 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2468 1 << M98090_ADCHP_SHIFT);
2470 /* Turn on VCM bandgap reference */
2471 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2472 M98090_VCM_MODE_MASK);
2474 err = device_property_read_u32(codec->dev, "maxim,micbias", &micbias);
2476 micbias = M98090_MBVSEL_2V8;
2477 dev_info(codec->dev, "use default 2.8v micbias\n");
2478 } else if (micbias > M98090_MBVSEL_2V8) {
2479 dev_err(codec->dev, "micbias out of range 0x%x\n", micbias);
2480 micbias = M98090_MBVSEL_2V8;
2483 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
2484 M98090_MBVSEL_MASK, micbias);
2486 max98090_add_widgets(codec);
2492 static int max98090_remove(struct snd_soc_codec *codec)
2494 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2496 cancel_delayed_work_sync(&max98090->jack_work);
2497 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2498 cancel_work_sync(&max98090->pll_det_disable_work);
2499 cancel_work_sync(&max98090->pll_work);
2500 max98090->codec = NULL;
2505 static void max98090_seq_notifier(struct snd_soc_dapm_context *dapm,
2506 enum snd_soc_dapm_type event, int subseq)
2508 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
2509 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2511 if (max98090->shdn_pending) {
2512 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2513 M98090_SHDNN_MASK, 0);
2515 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2516 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2517 max98090->shdn_pending = false;
2521 static const struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2522 .probe = max98090_probe,
2523 .remove = max98090_remove,
2524 .seq_notifier = max98090_seq_notifier,
2525 .set_bias_level = max98090_set_bias_level,
2528 static const struct regmap_config max98090_regmap = {
2532 .max_register = MAX98090_MAX_REGISTER,
2533 .reg_defaults = max98090_reg,
2534 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2535 .volatile_reg = max98090_volatile_register,
2536 .readable_reg = max98090_readable_register,
2537 .cache_type = REGCACHE_RBTREE,
2540 static int max98090_i2c_probe(struct i2c_client *i2c,
2541 const struct i2c_device_id *i2c_id)
2543 struct max98090_priv *max98090;
2544 const struct acpi_device_id *acpi_id;
2545 kernel_ulong_t driver_data = 0;
2548 pr_debug("max98090_i2c_probe\n");
2550 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2552 if (max98090 == NULL)
2555 if (ACPI_HANDLE(&i2c->dev)) {
2556 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2559 dev_err(&i2c->dev, "No driver data\n");
2562 driver_data = acpi_id->driver_data;
2563 } else if (i2c_id) {
2564 driver_data = i2c_id->driver_data;
2567 max98090->devtype = driver_data;
2568 i2c_set_clientdata(i2c, max98090);
2569 max98090->pdata = i2c->dev.platform_data;
2571 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2572 &max98090->dmic_freq);
2574 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2576 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2577 if (IS_ERR(max98090->regmap)) {
2578 ret = PTR_ERR(max98090->regmap);
2579 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2583 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2584 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2585 "max98090_interrupt", max98090);
2587 dev_err(&i2c->dev, "request_irq failed: %d\n",
2592 ret = snd_soc_register_codec(&i2c->dev,
2593 &soc_codec_dev_max98090, max98090_dai,
2594 ARRAY_SIZE(max98090_dai));
2599 static void max98090_i2c_shutdown(struct i2c_client *i2c)
2601 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
2604 * Enable volume smoothing, disable zero cross. This will cause
2605 * a quick 40ms ramp to mute on shutdown.
2607 regmap_write(max98090->regmap,
2608 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
2609 regmap_write(max98090->regmap,
2610 M98090_REG_DEVICE_SHUTDOWN, 0x00);
2614 static int max98090_i2c_remove(struct i2c_client *client)
2616 max98090_i2c_shutdown(client);
2617 snd_soc_unregister_codec(&client->dev);
2622 static int max98090_runtime_resume(struct device *dev)
2624 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2626 regcache_cache_only(max98090->regmap, false);
2628 max98090_reset(max98090);
2630 regcache_sync(max98090->regmap);
2635 static int max98090_runtime_suspend(struct device *dev)
2637 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2639 regcache_cache_only(max98090->regmap, true);
2645 #ifdef CONFIG_PM_SLEEP
2646 static int max98090_resume(struct device *dev)
2648 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2649 unsigned int status;
2651 regcache_mark_dirty(max98090->regmap);
2653 max98090_reset(max98090);
2655 /* clear IRQ status */
2656 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2658 regcache_sync(max98090->regmap);
2663 static int max98090_suspend(struct device *dev)
2669 static const struct dev_pm_ops max98090_pm = {
2670 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2671 max98090_runtime_resume, NULL)
2672 SET_SYSTEM_SLEEP_PM_OPS(max98090_suspend, max98090_resume)
2675 static const struct i2c_device_id max98090_i2c_id[] = {
2676 { "max98090", MAX98090 },
2677 { "max98091", MAX98091 },
2680 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2682 static const struct of_device_id max98090_of_match[] = {
2683 { .compatible = "maxim,max98090", },
2684 { .compatible = "maxim,max98091", },
2687 MODULE_DEVICE_TABLE(of, max98090_of_match);
2690 static const struct acpi_device_id max98090_acpi_match[] = {
2691 { "193C9890", MAX98090 },
2694 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2697 static struct i2c_driver max98090_i2c_driver = {
2701 .of_match_table = of_match_ptr(max98090_of_match),
2702 .acpi_match_table = ACPI_PTR(max98090_acpi_match),
2704 .probe = max98090_i2c_probe,
2705 .shutdown = max98090_i2c_shutdown,
2706 .remove = max98090_i2c_remove,
2707 .id_table = max98090_i2c_id,
2710 module_i2c_driver(max98090_i2c_driver);
2712 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2713 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2714 MODULE_LICENSE("GPL");