1 /* Copyright (c) 2016, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/module.h>
14 #include <linux/err.h>
15 #include <linux/kernel.h>
16 #include <linux/delay.h>
17 #include <linux/types.h>
18 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/mfd/syscon.h>
23 #include <sound/soc.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/tlv.h>
28 #define LPASS_CDC_CLK_RX_RESET_CTL (0x000)
29 #define LPASS_CDC_CLK_TX_RESET_B1_CTL (0x004)
30 #define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK BIT(0)
31 #define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK BIT(1)
32 #define LPASS_CDC_CLK_DMIC_B1_CTL (0x008)
33 #define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK GENMASK(3, 1)
34 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2 (0x0 << 1)
35 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3 (0x1 << 1)
36 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4 (0x2 << 1)
37 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6 (0x3 << 1)
38 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16 (0x4 << 1)
39 #define DMIC_B1_CTL_DMIC0_CLK_EN_MASK BIT(0)
40 #define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE BIT(0)
42 #define LPASS_CDC_CLK_RX_I2S_CTL (0x00C)
43 #define RX_I2S_CTL_RX_I2S_MODE_MASK BIT(5)
44 #define RX_I2S_CTL_RX_I2S_MODE_16 BIT(5)
45 #define RX_I2S_CTL_RX_I2S_MODE_32 0
46 #define RX_I2S_CTL_RX_I2S_FS_RATE_MASK GENMASK(2, 0)
47 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ 0x0
48 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ 0x1
49 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ 0x2
50 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ 0x3
51 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ 0x4
52 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ 0x5
53 #define LPASS_CDC_CLK_TX_I2S_CTL (0x010)
54 #define TX_I2S_CTL_TX_I2S_MODE_MASK BIT(5)
55 #define TX_I2S_CTL_TX_I2S_MODE_16 BIT(5)
56 #define TX_I2S_CTL_TX_I2S_MODE_32 0
57 #define TX_I2S_CTL_TX_I2S_FS_RATE_MASK GENMASK(2, 0)
58 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ 0x0
59 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ 0x1
60 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ 0x2
61 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ 0x3
62 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ 0x4
63 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ 0x5
65 #define LPASS_CDC_CLK_OTHR_RESET_B1_CTL (0x014)
66 #define LPASS_CDC_CLK_TX_CLK_EN_B1_CTL (0x018)
67 #define LPASS_CDC_CLK_OTHR_CTL (0x01C)
68 #define LPASS_CDC_CLK_RX_B1_CTL (0x020)
69 #define LPASS_CDC_CLK_MCLK_CTL (0x024)
70 #define MCLK_CTL_MCLK_EN_MASK BIT(0)
71 #define MCLK_CTL_MCLK_EN_ENABLE BIT(0)
72 #define MCLK_CTL_MCLK_EN_DISABLE 0
73 #define LPASS_CDC_CLK_PDM_CTL (0x028)
74 #define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK BIT(0)
75 #define LPASS_CDC_CLK_PDM_CTL_PDM_EN BIT(0)
76 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK BIT(1)
77 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB BIT(1)
78 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_PDM_CLK 0
80 #define LPASS_CDC_CLK_SD_CTL (0x02C)
81 #define LPASS_CDC_RX1_B1_CTL (0x040)
82 #define LPASS_CDC_RX2_B1_CTL (0x060)
83 #define LPASS_CDC_RX3_B1_CTL (0x080)
84 #define LPASS_CDC_RX1_B2_CTL (0x044)
85 #define LPASS_CDC_RX2_B2_CTL (0x064)
86 #define LPASS_CDC_RX3_B2_CTL (0x084)
87 #define LPASS_CDC_RX1_B3_CTL (0x048)
88 #define LPASS_CDC_RX2_B3_CTL (0x068)
89 #define LPASS_CDC_RX3_B3_CTL (0x088)
90 #define LPASS_CDC_RX1_B4_CTL (0x04C)
91 #define LPASS_CDC_RX2_B4_CTL (0x06C)
92 #define LPASS_CDC_RX3_B4_CTL (0x08C)
93 #define LPASS_CDC_RX1_B5_CTL (0x050)
94 #define LPASS_CDC_RX2_B5_CTL (0x070)
95 #define LPASS_CDC_RX3_B5_CTL (0x090)
96 #define LPASS_CDC_RX1_B6_CTL (0x054)
97 #define RXn_B6_CTL_MUTE_MASK BIT(0)
98 #define RXn_B6_CTL_MUTE_ENABLE BIT(0)
99 #define RXn_B6_CTL_MUTE_DISABLE 0
100 #define LPASS_CDC_RX2_B6_CTL (0x074)
101 #define LPASS_CDC_RX3_B6_CTL (0x094)
102 #define LPASS_CDC_RX1_VOL_CTL_B1_CTL (0x058)
103 #define LPASS_CDC_RX2_VOL_CTL_B1_CTL (0x078)
104 #define LPASS_CDC_RX3_VOL_CTL_B1_CTL (0x098)
105 #define LPASS_CDC_RX1_VOL_CTL_B2_CTL (0x05C)
106 #define LPASS_CDC_RX2_VOL_CTL_B2_CTL (0x07C)
107 #define LPASS_CDC_RX3_VOL_CTL_B2_CTL (0x09C)
108 #define LPASS_CDC_TOP_GAIN_UPDATE (0x0A0)
109 #define LPASS_CDC_TOP_CTL (0x0A4)
110 #define TOP_CTL_DIG_MCLK_FREQ_MASK BIT(0)
111 #define TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ 0
112 #define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ BIT(0)
114 #define LPASS_CDC_DEBUG_DESER1_CTL (0x0E0)
115 #define LPASS_CDC_DEBUG_DESER2_CTL (0x0E4)
116 #define LPASS_CDC_DEBUG_B1_CTL_CFG (0x0E8)
117 #define LPASS_CDC_DEBUG_B2_CTL_CFG (0x0EC)
118 #define LPASS_CDC_DEBUG_B3_CTL_CFG (0x0F0)
119 #define LPASS_CDC_IIR1_GAIN_B1_CTL (0x100)
120 #define LPASS_CDC_IIR2_GAIN_B1_CTL (0x140)
121 #define LPASS_CDC_IIR1_GAIN_B2_CTL (0x104)
122 #define LPASS_CDC_IIR2_GAIN_B2_CTL (0x144)
123 #define LPASS_CDC_IIR1_GAIN_B3_CTL (0x108)
124 #define LPASS_CDC_IIR2_GAIN_B3_CTL (0x148)
125 #define LPASS_CDC_IIR1_GAIN_B4_CTL (0x10C)
126 #define LPASS_CDC_IIR2_GAIN_B4_CTL (0x14C)
127 #define LPASS_CDC_IIR1_GAIN_B5_CTL (0x110)
128 #define LPASS_CDC_IIR2_GAIN_B5_CTL (0x150)
129 #define LPASS_CDC_IIR1_GAIN_B6_CTL (0x114)
130 #define LPASS_CDC_IIR2_GAIN_B6_CTL (0x154)
131 #define LPASS_CDC_IIR1_GAIN_B7_CTL (0x118)
132 #define LPASS_CDC_IIR2_GAIN_B7_CTL (0x158)
133 #define LPASS_CDC_IIR1_GAIN_B8_CTL (0x11C)
134 #define LPASS_CDC_IIR2_GAIN_B8_CTL (0x15C)
135 #define LPASS_CDC_IIR1_CTL (0x120)
136 #define LPASS_CDC_IIR2_CTL (0x160)
137 #define LPASS_CDC_IIR1_GAIN_TIMER_CTL (0x124)
138 #define LPASS_CDC_IIR2_GAIN_TIMER_CTL (0x164)
139 #define LPASS_CDC_IIR1_COEF_B1_CTL (0x128)
140 #define LPASS_CDC_IIR2_COEF_B1_CTL (0x168)
141 #define LPASS_CDC_IIR1_COEF_B2_CTL (0x12C)
142 #define LPASS_CDC_IIR2_COEF_B2_CTL (0x16C)
143 #define LPASS_CDC_CONN_RX1_B1_CTL (0x180)
144 #define LPASS_CDC_CONN_RX1_B2_CTL (0x184)
145 #define LPASS_CDC_CONN_RX1_B3_CTL (0x188)
146 #define LPASS_CDC_CONN_RX2_B1_CTL (0x18C)
147 #define LPASS_CDC_CONN_RX2_B2_CTL (0x190)
148 #define LPASS_CDC_CONN_RX2_B3_CTL (0x194)
149 #define LPASS_CDC_CONN_RX3_B1_CTL (0x198)
150 #define LPASS_CDC_CONN_RX3_B2_CTL (0x19C)
151 #define LPASS_CDC_CONN_TX_B1_CTL (0x1A0)
152 #define LPASS_CDC_CONN_EQ1_B1_CTL (0x1A8)
153 #define LPASS_CDC_CONN_EQ1_B2_CTL (0x1AC)
154 #define LPASS_CDC_CONN_EQ1_B3_CTL (0x1B0)
155 #define LPASS_CDC_CONN_EQ1_B4_CTL (0x1B4)
156 #define LPASS_CDC_CONN_EQ2_B1_CTL (0x1B8)
157 #define LPASS_CDC_CONN_EQ2_B2_CTL (0x1BC)
158 #define LPASS_CDC_CONN_EQ2_B3_CTL (0x1C0)
159 #define LPASS_CDC_CONN_EQ2_B4_CTL (0x1C4)
160 #define LPASS_CDC_CONN_TX_I2S_SD1_CTL (0x1C8)
161 #define LPASS_CDC_TX1_VOL_CTL_TIMER (0x280)
162 #define LPASS_CDC_TX2_VOL_CTL_TIMER (0x2A0)
163 #define LPASS_CDC_TX1_VOL_CTL_GAIN (0x284)
164 #define LPASS_CDC_TX2_VOL_CTL_GAIN (0x2A4)
165 #define LPASS_CDC_TX1_VOL_CTL_CFG (0x288)
166 #define TX_VOL_CTL_CFG_MUTE_EN_MASK BIT(0)
167 #define TX_VOL_CTL_CFG_MUTE_EN_ENABLE BIT(0)
169 #define LPASS_CDC_TX2_VOL_CTL_CFG (0x2A8)
170 #define LPASS_CDC_TX1_MUX_CTL (0x28C)
171 #define TX_MUX_CTL_CUT_OFF_FREQ_MASK GENMASK(5, 4)
172 #define TX_MUX_CTL_CUT_OFF_FREQ_SHIFT 4
173 #define TX_MUX_CTL_CF_NEG_3DB_4HZ (0x0 << 4)
174 #define TX_MUX_CTL_CF_NEG_3DB_75HZ (0x1 << 4)
175 #define TX_MUX_CTL_CF_NEG_3DB_150HZ (0x2 << 4)
176 #define TX_MUX_CTL_HPF_BP_SEL_MASK BIT(3)
177 #define TX_MUX_CTL_HPF_BP_SEL_BYPASS BIT(3)
178 #define TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS 0
180 #define LPASS_CDC_TX2_MUX_CTL (0x2AC)
181 #define LPASS_CDC_TX1_CLK_FS_CTL (0x290)
182 #define LPASS_CDC_TX2_CLK_FS_CTL (0x2B0)
183 #define LPASS_CDC_TX1_DMIC_CTL (0x294)
184 #define LPASS_CDC_TX2_DMIC_CTL (0x2B4)
185 #define TXN_DMIC_CTL_CLK_SEL_MASK GENMASK(2, 0)
186 #define TXN_DMIC_CTL_CLK_SEL_DIV2 0x0
187 #define TXN_DMIC_CTL_CLK_SEL_DIV3 0x1
188 #define TXN_DMIC_CTL_CLK_SEL_DIV4 0x2
189 #define TXN_DMIC_CTL_CLK_SEL_DIV6 0x3
190 #define TXN_DMIC_CTL_CLK_SEL_DIV16 0x4
192 #define MSM8916_WCD_DIGITAL_RATES (SNDRV_PCM_RATE_8000 | \
193 SNDRV_PCM_RATE_16000 | \
194 SNDRV_PCM_RATE_32000 | \
195 SNDRV_PCM_RATE_48000)
196 #define MSM8916_WCD_DIGITAL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
197 SNDRV_PCM_FMTBIT_S32_LE)
199 struct msm8916_wcd_digital_priv {
200 struct clk *ahbclk, *mclk;
203 static const unsigned long rx_gain_reg[] = {
204 LPASS_CDC_RX1_VOL_CTL_B2_CTL,
205 LPASS_CDC_RX2_VOL_CTL_B2_CTL,
206 LPASS_CDC_RX3_VOL_CTL_B2_CTL,
209 static const unsigned long tx_gain_reg[] = {
210 LPASS_CDC_TX1_VOL_CTL_GAIN,
211 LPASS_CDC_TX2_VOL_CTL_GAIN,
214 static const char *const rx_mix1_text[] = {
215 "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
218 static const char *const dec_mux_text[] = {
219 "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
222 static const char *const cic_mux_text[] = { "AMIC", "DMIC" };
223 static const char *const rx_mix2_text[] = { "ZERO", "IIR1", "IIR2" };
224 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
227 static const struct soc_enum rx_mix1_inp_enum[] = {
228 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 0, 6, rx_mix1_text),
229 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 3, 6, rx_mix1_text),
230 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B2_CTL, 0, 6, rx_mix1_text),
234 static const struct soc_enum rx_mix2_inp1_chain_enum = SOC_ENUM_SINGLE(
235 LPASS_CDC_CONN_RX1_B3_CTL, 0, 3, rx_mix2_text);
238 static const struct soc_enum rx2_mix1_inp_enum[] = {
239 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text),
240 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text),
241 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B2_CTL, 0, 6, rx_mix1_text),
245 static const struct soc_enum rx2_mix2_inp1_chain_enum = SOC_ENUM_SINGLE(
246 LPASS_CDC_CONN_RX2_B3_CTL, 0, 3, rx_mix2_text);
249 static const struct soc_enum rx3_mix1_inp_enum[] = {
250 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text),
251 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text),
252 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B2_CTL, 0, 6, rx_mix1_text),
256 static const struct soc_enum dec1_mux_enum = SOC_ENUM_SINGLE(
257 LPASS_CDC_CONN_TX_B1_CTL, 0, 6, dec_mux_text);
258 static const struct soc_enum dec2_mux_enum = SOC_ENUM_SINGLE(
259 LPASS_CDC_CONN_TX_B1_CTL, 3, 6, dec_mux_text);
262 static const struct soc_enum cic1_mux_enum = SOC_ENUM_SINGLE(
263 LPASS_CDC_TX1_MUX_CTL, 0, 2, cic_mux_text);
264 static const struct soc_enum cic2_mux_enum = SOC_ENUM_SINGLE(
265 LPASS_CDC_TX2_MUX_CTL, 0, 2, cic_mux_text);
268 static const struct snd_kcontrol_new dec1_mux = SOC_DAPM_ENUM(
269 "DEC1 MUX Mux", dec1_mux_enum);
270 static const struct snd_kcontrol_new dec2_mux = SOC_DAPM_ENUM(
271 "DEC2 MUX Mux", dec2_mux_enum);
272 static const struct snd_kcontrol_new cic1_mux = SOC_DAPM_ENUM(
273 "CIC1 MUX Mux", cic1_mux_enum);
274 static const struct snd_kcontrol_new cic2_mux = SOC_DAPM_ENUM(
275 "CIC2 MUX Mux", cic2_mux_enum);
276 static const struct snd_kcontrol_new rx_mix1_inp1_mux = SOC_DAPM_ENUM(
277 "RX1 MIX1 INP1 Mux", rx_mix1_inp_enum[0]);
278 static const struct snd_kcontrol_new rx_mix1_inp2_mux = SOC_DAPM_ENUM(
279 "RX1 MIX1 INP2 Mux", rx_mix1_inp_enum[1]);
280 static const struct snd_kcontrol_new rx_mix1_inp3_mux = SOC_DAPM_ENUM(
281 "RX1 MIX1 INP3 Mux", rx_mix1_inp_enum[2]);
282 static const struct snd_kcontrol_new rx2_mix1_inp1_mux = SOC_DAPM_ENUM(
283 "RX2 MIX1 INP1 Mux", rx2_mix1_inp_enum[0]);
284 static const struct snd_kcontrol_new rx2_mix1_inp2_mux = SOC_DAPM_ENUM(
285 "RX2 MIX1 INP2 Mux", rx2_mix1_inp_enum[1]);
286 static const struct snd_kcontrol_new rx2_mix1_inp3_mux = SOC_DAPM_ENUM(
287 "RX2 MIX1 INP3 Mux", rx2_mix1_inp_enum[2]);
288 static const struct snd_kcontrol_new rx3_mix1_inp1_mux = SOC_DAPM_ENUM(
289 "RX3 MIX1 INP1 Mux", rx3_mix1_inp_enum[0]);
290 static const struct snd_kcontrol_new rx3_mix1_inp2_mux = SOC_DAPM_ENUM(
291 "RX3 MIX1 INP2 Mux", rx3_mix1_inp_enum[1]);
292 static const struct snd_kcontrol_new rx3_mix1_inp3_mux = SOC_DAPM_ENUM(
293 "RX3 MIX1 INP3 Mux", rx3_mix1_inp_enum[2]);
295 /* Digital Gain control -38.4 dB to +38.4 dB in 0.3 dB steps */
296 static const DECLARE_TLV_DB_SCALE(digital_gain, -3840, 30, 0);
298 /* Cutoff Freq for High Pass Filter at -3dB */
299 static const char * const hpf_cutoff_text[] = {
300 "4Hz", "75Hz", "150Hz",
303 static SOC_ENUM_SINGLE_DECL(tx1_hpf_cutoff_enum, LPASS_CDC_TX1_MUX_CTL, 4,
305 static SOC_ENUM_SINGLE_DECL(tx2_hpf_cutoff_enum, LPASS_CDC_TX2_MUX_CTL, 4,
308 /* cut off for dc blocker inside rx chain */
309 static const char * const dc_blocker_cutoff_text[] = {
310 "4Hz", "75Hz", "150Hz",
313 static SOC_ENUM_SINGLE_DECL(rx1_dcb_cutoff_enum, LPASS_CDC_RX1_B4_CTL, 0,
314 dc_blocker_cutoff_text);
315 static SOC_ENUM_SINGLE_DECL(rx2_dcb_cutoff_enum, LPASS_CDC_RX2_B4_CTL, 0,
316 dc_blocker_cutoff_text);
317 static SOC_ENUM_SINGLE_DECL(rx3_dcb_cutoff_enum, LPASS_CDC_RX3_B4_CTL, 0,
318 dc_blocker_cutoff_text);
320 static const struct snd_kcontrol_new msm8916_wcd_digital_snd_controls[] = {
321 SOC_SINGLE_S8_TLV("RX1 Digital Volume", LPASS_CDC_RX1_VOL_CTL_B2_CTL,
322 -128, 127, digital_gain),
323 SOC_SINGLE_S8_TLV("RX2 Digital Volume", LPASS_CDC_RX2_VOL_CTL_B2_CTL,
324 -128, 127, digital_gain),
325 SOC_SINGLE_S8_TLV("RX3 Digital Volume", LPASS_CDC_RX3_VOL_CTL_B2_CTL,
326 -128, 127, digital_gain),
327 SOC_SINGLE_S8_TLV("TX1 Digital Volume", LPASS_CDC_TX1_VOL_CTL_GAIN,
328 -128, 127, digital_gain),
329 SOC_SINGLE_S8_TLV("TX2 Digital Volume", LPASS_CDC_TX2_VOL_CTL_GAIN,
330 -128, 127, digital_gain),
331 SOC_ENUM("TX1 HPF Cutoff", tx1_hpf_cutoff_enum),
332 SOC_ENUM("TX2 HPF Cutoff", tx2_hpf_cutoff_enum),
333 SOC_SINGLE("TX1 HPF Switch", LPASS_CDC_TX1_MUX_CTL, 3, 1, 0),
334 SOC_SINGLE("TX2 HPF Switch", LPASS_CDC_TX2_MUX_CTL, 3, 1, 0),
335 SOC_ENUM("RX1 DCB Cutoff", rx1_dcb_cutoff_enum),
336 SOC_ENUM("RX2 DCB Cutoff", rx2_dcb_cutoff_enum),
337 SOC_ENUM("RX3 DCB Cutoff", rx3_dcb_cutoff_enum),
338 SOC_SINGLE("RX1 DCB Switch", LPASS_CDC_RX1_B5_CTL, 2, 1, 0),
339 SOC_SINGLE("RX2 DCB Switch", LPASS_CDC_RX2_B5_CTL, 2, 1, 0),
340 SOC_SINGLE("RX3 DCB Switch", LPASS_CDC_RX3_B5_CTL, 2, 1, 0),
341 SOC_SINGLE("RX1 Mute Switch", LPASS_CDC_RX1_B6_CTL, 0, 1, 0),
342 SOC_SINGLE("RX2 Mute Switch", LPASS_CDC_RX2_B6_CTL, 0, 1, 0),
343 SOC_SINGLE("RX3 Mute Switch", LPASS_CDC_RX3_B6_CTL, 0, 1, 0),
346 static int msm8916_wcd_digital_enable_interpolator(
347 struct snd_soc_dapm_widget *w,
348 struct snd_kcontrol *kcontrol,
351 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
354 case SND_SOC_DAPM_POST_PMU:
355 /* apply the digital gain after the interpolator is enabled */
356 usleep_range(10000, 10100);
357 snd_soc_component_write(component, rx_gain_reg[w->shift],
358 snd_soc_component_read32(component, rx_gain_reg[w->shift]));
360 case SND_SOC_DAPM_POST_PMD:
361 snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
362 1 << w->shift, 1 << w->shift);
363 snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
370 static int msm8916_wcd_digital_enable_dec(struct snd_soc_dapm_widget *w,
371 struct snd_kcontrol *kcontrol,
374 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
375 unsigned int decimator = w->shift + 1;
376 u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
377 u8 dec_hpf_cut_of_freq;
379 dec_reset_reg = LPASS_CDC_CLK_TX_RESET_B1_CTL;
380 tx_vol_ctl_reg = LPASS_CDC_TX1_VOL_CTL_CFG + 32 * (decimator - 1);
381 tx_mux_ctl_reg = LPASS_CDC_TX1_MUX_CTL + 32 * (decimator - 1);
384 case SND_SOC_DAPM_PRE_PMU:
385 /* Enable TX digital mute */
386 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
387 TX_VOL_CTL_CFG_MUTE_EN_MASK,
388 TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
389 dec_hpf_cut_of_freq = snd_soc_component_read32(component, tx_mux_ctl_reg) &
390 TX_MUX_CTL_CUT_OFF_FREQ_MASK;
391 dec_hpf_cut_of_freq >>= TX_MUX_CTL_CUT_OFF_FREQ_SHIFT;
392 if (dec_hpf_cut_of_freq != TX_MUX_CTL_CF_NEG_3DB_150HZ) {
393 /* set cut of freq to CF_MIN_3DB_150HZ (0x1) */
394 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
395 TX_MUX_CTL_CUT_OFF_FREQ_MASK,
396 TX_MUX_CTL_CF_NEG_3DB_150HZ);
399 case SND_SOC_DAPM_POST_PMU:
401 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
402 TX_MUX_CTL_HPF_BP_SEL_MASK,
403 TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS);
404 /* apply the digital gain after the decimator is enabled */
405 snd_soc_component_write(component, tx_gain_reg[w->shift],
406 snd_soc_component_read32(component, tx_gain_reg[w->shift]));
407 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
408 TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
410 case SND_SOC_DAPM_PRE_PMD:
411 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
412 TX_VOL_CTL_CFG_MUTE_EN_MASK,
413 TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
414 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
415 TX_MUX_CTL_HPF_BP_SEL_MASK,
416 TX_MUX_CTL_HPF_BP_SEL_BYPASS);
418 case SND_SOC_DAPM_POST_PMD:
419 snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift,
421 snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift, 0x0);
422 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
423 TX_MUX_CTL_HPF_BP_SEL_MASK,
424 TX_MUX_CTL_HPF_BP_SEL_BYPASS);
425 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
426 TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
433 static int msm8916_wcd_digital_enable_dmic(struct snd_soc_dapm_widget *w,
434 struct snd_kcontrol *kcontrol,
437 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
440 /* get dmic number out of widget name */
441 char *dmic_num = strpbrk(w->name, "12");
443 if (dmic_num == NULL) {
444 dev_err(component->dev, "Invalid DMIC\n");
447 ret = kstrtouint(dmic_num, 10, &dmic);
448 if (ret < 0 || dmic > 2) {
449 dev_err(component->dev, "Invalid DMIC line on the component\n");
454 case SND_SOC_DAPM_PRE_PMU:
455 snd_soc_component_update_bits(component, LPASS_CDC_CLK_DMIC_B1_CTL,
456 DMIC_B1_CTL_DMIC0_CLK_SEL_MASK,
457 DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3);
460 snd_soc_component_update_bits(component, LPASS_CDC_TX1_DMIC_CTL,
461 TXN_DMIC_CTL_CLK_SEL_MASK,
462 TXN_DMIC_CTL_CLK_SEL_DIV3);
465 snd_soc_component_update_bits(component, LPASS_CDC_TX2_DMIC_CTL,
466 TXN_DMIC_CTL_CLK_SEL_MASK,
467 TXN_DMIC_CTL_CLK_SEL_DIV3);
476 static const struct snd_soc_dapm_widget msm8916_wcd_digital_dapm_widgets[] = {
478 SND_SOC_DAPM_AIF_IN("I2S RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
479 SND_SOC_DAPM_AIF_IN("I2S RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
480 SND_SOC_DAPM_AIF_IN("I2S RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
482 SND_SOC_DAPM_OUTPUT("PDM_RX1"),
483 SND_SOC_DAPM_OUTPUT("PDM_RX2"),
484 SND_SOC_DAPM_OUTPUT("PDM_RX3"),
486 SND_SOC_DAPM_INPUT("LPASS_PDM_TX"),
488 SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
489 SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
490 SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
493 SND_SOC_DAPM_MIXER_E("RX1 INT", LPASS_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
494 0, msm8916_wcd_digital_enable_interpolator,
495 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
496 SND_SOC_DAPM_MIXER_E("RX2 INT", LPASS_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
497 0, msm8916_wcd_digital_enable_interpolator,
498 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
499 SND_SOC_DAPM_MIXER_E("RX3 INT", LPASS_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
500 0, msm8916_wcd_digital_enable_interpolator,
501 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
502 SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
504 SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
506 SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
508 SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
510 SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
512 SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
514 SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
516 SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
518 SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
521 SND_SOC_DAPM_MUX("CIC1 MUX", SND_SOC_NOPM, 0, 0, &cic1_mux),
522 SND_SOC_DAPM_MUX("CIC2 MUX", SND_SOC_NOPM, 0, 0, &cic2_mux),
524 SND_SOC_DAPM_MIXER("ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
525 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
526 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
528 SND_SOC_DAPM_MUX_E("DEC1 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
529 &dec1_mux, msm8916_wcd_digital_enable_dec,
530 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
531 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
532 SND_SOC_DAPM_MUX_E("DEC2 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
533 &dec2_mux, msm8916_wcd_digital_enable_dec,
534 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
535 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
536 SND_SOC_DAPM_AIF_OUT("I2S TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
537 SND_SOC_DAPM_AIF_OUT("I2S TX2", NULL, 0, SND_SOC_NOPM, 0, 0),
538 SND_SOC_DAPM_AIF_OUT("I2S TX3", NULL, 0, SND_SOC_NOPM, 0, 0),
540 /* Digital Mic Inputs */
541 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
542 msm8916_wcd_digital_enable_dmic,
543 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
544 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
545 msm8916_wcd_digital_enable_dmic,
546 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
547 SND_SOC_DAPM_SUPPLY("DMIC_CLK", LPASS_CDC_CLK_DMIC_B1_CTL, 0, 0,
549 SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", LPASS_CDC_CLK_RX_I2S_CTL,
551 SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", LPASS_CDC_CLK_TX_I2S_CTL, 4, 0,
554 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
555 SND_SOC_DAPM_SUPPLY("PDM_CLK", LPASS_CDC_CLK_PDM_CTL, 0, 0, NULL, 0),
556 /* Connectivity Clock */
557 SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, LPASS_CDC_CLK_OTHR_CTL, 2, 0,
559 SND_SOC_DAPM_MIC("Digital Mic1", NULL),
560 SND_SOC_DAPM_MIC("Digital Mic2", NULL),
564 static int msm8916_wcd_digital_get_clks(struct platform_device *pdev,
565 struct msm8916_wcd_digital_priv *priv)
567 struct device *dev = &pdev->dev;
569 priv->ahbclk = devm_clk_get(dev, "ahbix-clk");
570 if (IS_ERR(priv->ahbclk)) {
571 dev_err(dev, "failed to get ahbix clk\n");
572 return PTR_ERR(priv->ahbclk);
575 priv->mclk = devm_clk_get(dev, "mclk");
576 if (IS_ERR(priv->mclk)) {
577 dev_err(dev, "failed to get mclk\n");
578 return PTR_ERR(priv->mclk);
584 static int msm8916_wcd_digital_component_probe(struct snd_soc_component *component)
586 struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(component->dev);
588 snd_soc_component_set_drvdata(component, priv);
593 static int msm8916_wcd_digital_component_set_sysclk(struct snd_soc_component *component,
594 int clk_id, int source,
595 unsigned int freq, int dir)
597 struct msm8916_wcd_digital_priv *p = dev_get_drvdata(component->dev);
599 return clk_set_rate(p->mclk, freq);
602 static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream,
603 struct snd_pcm_hw_params *params,
604 struct snd_soc_dai *dai)
609 switch (params_rate(params)) {
611 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ;
612 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ;
615 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ;
616 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ;
619 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ;
620 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ;
623 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ;
624 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ;
627 dev_err(dai->component->dev, "Invalid sampling rate %d\n",
628 params_rate(params));
632 switch (substream->stream) {
633 case SNDRV_PCM_STREAM_CAPTURE:
634 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
635 TX_I2S_CTL_TX_I2S_FS_RATE_MASK, tx_fs_rate);
637 case SNDRV_PCM_STREAM_PLAYBACK:
638 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
639 RX_I2S_CTL_RX_I2S_FS_RATE_MASK, rx_fs_rate);
645 switch (params_format(params)) {
646 case SNDRV_PCM_FORMAT_S16_LE:
647 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
648 TX_I2S_CTL_TX_I2S_MODE_MASK,
649 TX_I2S_CTL_TX_I2S_MODE_16);
650 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
651 RX_I2S_CTL_RX_I2S_MODE_MASK,
652 RX_I2S_CTL_RX_I2S_MODE_16);
655 case SNDRV_PCM_FORMAT_S32_LE:
656 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
657 TX_I2S_CTL_TX_I2S_MODE_MASK,
658 TX_I2S_CTL_TX_I2S_MODE_32);
659 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
660 RX_I2S_CTL_RX_I2S_MODE_MASK,
661 RX_I2S_CTL_RX_I2S_MODE_32);
664 dev_err(dai->dev, "%s: wrong format selected\n", __func__);
671 static const struct snd_soc_dapm_route msm8916_wcd_digital_audio_map[] = {
673 {"I2S RX1", NULL, "AIF1 Playback"},
674 {"I2S RX2", NULL, "AIF1 Playback"},
675 {"I2S RX3", NULL, "AIF1 Playback"},
677 {"AIF1 Capture", NULL, "I2S TX1"},
678 {"AIF1 Capture", NULL, "I2S TX2"},
679 {"AIF1 Capture", NULL, "I2S TX3"},
681 {"CIC1 MUX", "DMIC", "DEC1 MUX"},
682 {"CIC1 MUX", "AMIC", "DEC1 MUX"},
683 {"CIC2 MUX", "DMIC", "DEC2 MUX"},
684 {"CIC2 MUX", "AMIC", "DEC2 MUX"},
686 /* Decimator Inputs */
687 {"DEC1 MUX", "DMIC1", "DMIC1"},
688 {"DEC1 MUX", "DMIC2", "DMIC2"},
689 {"DEC1 MUX", "ADC1", "ADC1"},
690 {"DEC1 MUX", "ADC2", "ADC2"},
691 {"DEC1 MUX", "ADC3", "ADC3"},
692 {"DEC1 MUX", NULL, "CDC_CONN"},
694 {"DEC2 MUX", "DMIC1", "DMIC1"},
695 {"DEC2 MUX", "DMIC2", "DMIC2"},
696 {"DEC2 MUX", "ADC1", "ADC1"},
697 {"DEC2 MUX", "ADC2", "ADC2"},
698 {"DEC2 MUX", "ADC3", "ADC3"},
699 {"DEC2 MUX", NULL, "CDC_CONN"},
701 {"DMIC1", NULL, "DMIC_CLK"},
702 {"DMIC2", NULL, "DMIC_CLK"},
704 {"I2S TX1", NULL, "CIC1 MUX"},
705 {"I2S TX2", NULL, "CIC2 MUX"},
707 {"I2S TX1", NULL, "TX_I2S_CLK"},
708 {"I2S TX2", NULL, "TX_I2S_CLK"},
710 {"TX_I2S_CLK", NULL, "MCLK"},
711 {"TX_I2S_CLK", NULL, "PDM_CLK"},
713 {"ADC1", NULL, "LPASS_PDM_TX"},
714 {"ADC2", NULL, "LPASS_PDM_TX"},
715 {"ADC3", NULL, "LPASS_PDM_TX"},
717 {"I2S RX1", NULL, "RX_I2S_CLK"},
718 {"I2S RX2", NULL, "RX_I2S_CLK"},
719 {"I2S RX3", NULL, "RX_I2S_CLK"},
721 {"RX_I2S_CLK", NULL, "PDM_CLK"},
722 {"RX_I2S_CLK", NULL, "MCLK"},
723 {"RX_I2S_CLK", NULL, "CDC_CONN"},
726 {"PDM_RX1", NULL, "RX1 INT"},
727 {"RX1 INT", NULL, "RX1 MIX1"},
729 {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
730 {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
731 {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
733 {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
734 {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
735 {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
737 {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
738 {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
739 {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
741 {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
742 {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
743 {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
746 {"PDM_RX2", NULL, "RX2 INT"},
747 {"RX2 INT", NULL, "RX2 MIX1"},
749 {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
750 {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
751 {"RX2 MIX1", NULL, "RX2 MIX1 INP3"},
753 {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
754 {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
755 {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
757 {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
758 {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
759 {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
761 {"RX2 MIX1 INP3", "RX1", "I2S RX1"},
762 {"RX2 MIX1 INP3", "RX2", "I2S RX2"},
763 {"RX2 MIX1 INP3", "RX3", "I2S RX3"},
766 {"PDM_RX3", NULL, "RX3 INT"},
767 {"RX3 INT", NULL, "RX3 MIX1"},
769 {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
770 {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
771 {"RX3 MIX1", NULL, "RX3 MIX1 INP3"},
773 {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
774 {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
775 {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
777 {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
778 {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
779 {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
781 {"RX3 MIX1 INP3", "RX1", "I2S RX1"},
782 {"RX3 MIX1 INP3", "RX2", "I2S RX2"},
783 {"RX3 MIX1 INP3", "RX3", "I2S RX3"},
787 static int msm8916_wcd_digital_startup(struct snd_pcm_substream *substream,
788 struct snd_soc_dai *dai)
790 struct snd_soc_component *component = dai->component;
791 struct msm8916_wcd_digital_priv *msm8916_wcd;
792 unsigned long mclk_rate;
794 msm8916_wcd = snd_soc_component_get_drvdata(component);
795 snd_soc_component_update_bits(component, LPASS_CDC_CLK_MCLK_CTL,
796 MCLK_CTL_MCLK_EN_MASK,
797 MCLK_CTL_MCLK_EN_ENABLE);
798 snd_soc_component_update_bits(component, LPASS_CDC_CLK_PDM_CTL,
799 LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK,
800 LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB);
802 mclk_rate = clk_get_rate(msm8916_wcd->mclk);
805 snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
806 TOP_CTL_DIG_MCLK_FREQ_MASK,
807 TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ);
810 snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
811 TOP_CTL_DIG_MCLK_FREQ_MASK,
812 TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ);
815 dev_err(component->dev, "Invalid mclk rate %ld\n", mclk_rate);
821 static void msm8916_wcd_digital_shutdown(struct snd_pcm_substream *substream,
822 struct snd_soc_dai *dai)
824 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_PDM_CTL,
825 LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK, 0);
828 static const struct snd_soc_dai_ops msm8916_wcd_digital_dai_ops = {
829 .startup = msm8916_wcd_digital_startup,
830 .shutdown = msm8916_wcd_digital_shutdown,
831 .hw_params = msm8916_wcd_digital_hw_params,
834 static struct snd_soc_dai_driver msm8916_wcd_digital_dai[] = {
836 .name = "msm8916_wcd_digital_i2s_rx1",
839 .stream_name = "AIF1 Playback",
840 .rates = MSM8916_WCD_DIGITAL_RATES,
841 .formats = MSM8916_WCD_DIGITAL_FORMATS,
845 .ops = &msm8916_wcd_digital_dai_ops,
848 .name = "msm8916_wcd_digital_i2s_tx1",
851 .stream_name = "AIF1 Capture",
852 .rates = MSM8916_WCD_DIGITAL_RATES,
853 .formats = MSM8916_WCD_DIGITAL_FORMATS,
857 .ops = &msm8916_wcd_digital_dai_ops,
861 static const struct snd_soc_component_driver msm8916_wcd_digital = {
862 .probe = msm8916_wcd_digital_component_probe,
863 .set_sysclk = msm8916_wcd_digital_component_set_sysclk,
864 .controls = msm8916_wcd_digital_snd_controls,
865 .num_controls = ARRAY_SIZE(msm8916_wcd_digital_snd_controls),
866 .dapm_widgets = msm8916_wcd_digital_dapm_widgets,
867 .num_dapm_widgets = ARRAY_SIZE(msm8916_wcd_digital_dapm_widgets),
868 .dapm_routes = msm8916_wcd_digital_audio_map,
869 .num_dapm_routes = ARRAY_SIZE(msm8916_wcd_digital_audio_map),
871 .use_pmdown_time = 1,
873 .non_legacy_dai_naming = 1,
876 static const struct regmap_config msm8916_codec_regmap_config = {
880 .max_register = LPASS_CDC_TX2_DMIC_CTL,
881 .cache_type = REGCACHE_FLAT,
884 static int msm8916_wcd_digital_probe(struct platform_device *pdev)
886 struct msm8916_wcd_digital_priv *priv;
887 struct device *dev = &pdev->dev;
889 struct resource *mem_res;
890 struct regmap *digital_map;
893 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
897 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
898 base = devm_ioremap_resource(&pdev->dev, mem_res);
900 return PTR_ERR(base);
903 devm_regmap_init_mmio(&pdev->dev, base,
904 &msm8916_codec_regmap_config);
905 if (IS_ERR(digital_map))
906 return PTR_ERR(digital_map);
908 ret = msm8916_wcd_digital_get_clks(pdev, priv);
912 ret = clk_prepare_enable(priv->ahbclk);
914 dev_err(dev, "failed to enable ahbclk %d\n", ret);
918 ret = clk_prepare_enable(priv->mclk);
920 dev_err(dev, "failed to enable mclk %d\n", ret);
924 dev_set_drvdata(dev, priv);
926 ret = devm_snd_soc_register_component(dev, &msm8916_wcd_digital,
927 msm8916_wcd_digital_dai,
928 ARRAY_SIZE(msm8916_wcd_digital_dai));
935 clk_disable_unprepare(priv->mclk);
937 clk_disable_unprepare(priv->ahbclk);
941 static int msm8916_wcd_digital_remove(struct platform_device *pdev)
943 struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(&pdev->dev);
945 clk_disable_unprepare(priv->mclk);
946 clk_disable_unprepare(priv->ahbclk);
951 static const struct of_device_id msm8916_wcd_digital_match_table[] = {
952 { .compatible = "qcom,msm8916-wcd-digital-codec" },
956 MODULE_DEVICE_TABLE(of, msm8916_wcd_digital_match_table);
958 static struct platform_driver msm8916_wcd_digital_driver = {
960 .name = "msm8916-wcd-digital-codec",
961 .of_match_table = msm8916_wcd_digital_match_table,
963 .probe = msm8916_wcd_digital_probe,
964 .remove = msm8916_wcd_digital_remove,
967 module_platform_driver(msm8916_wcd_digital_driver);
969 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
970 MODULE_DESCRIPTION("MSM8916 WCD Digital Codec driver");
971 MODULE_LICENSE("GPL v2");