sound/soc/codecs/tscs454.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
   3 // Copyright 2018 Tempo Semiconductor, Inc.
   4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
   5
   6 #include <linux/kernel.h>
   7 #include <linux/clk.h>
   8 #include <linux/device.h>
   9 #include <linux/regmap.h>
  10 #include <linux/i2c.h>
  11 #include <linux/err.h>
  12 #include <linux/string.h>
  13 #include <linux/module.h>
  14 #include <linux/delay.h>
  15 #include <linux/mutex.h>
  16
  17 #include <sound/tlv.h>
  18 #include <sound/pcm_params.h>
  19 #include <sound/pcm.h>
  20 #include <sound/soc.h>
  21 #include <sound/soc-dapm.h>
  22
  23 #include "tscs454.h"
  24
  25 static const unsigned int PLL_48K_RATE = (48000 * 256);
  26 static const unsigned int PLL_44_1K_RATE = (44100 * 256);
  27
  28 #define COEFF_SIZE 3
  29 #define BIQUAD_COEFF_COUNT 5
  30 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
  31
  32 #define COEFF_RAM_MAX_ADDR 0xcd
  33 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
  34 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
  35
  36 enum {
  37         TSCS454_DAI1_ID,
  38         TSCS454_DAI2_ID,
  39         TSCS454_DAI3_ID,
  40         TSCS454_DAI_COUNT,
  41 };
  42
  43 struct pll {
  44         int id;
  45         unsigned int users;
  46         struct mutex lock;
  47 };
  48
  49 static inline void pll_init(struct pll *pll, int id)
  50 {
  51         pll->id = id;
  52         mutex_init(&pll->lock);
  53 }
  54
  55 struct internal_rate {
  56         struct pll *pll;
  57 };
  58
  59 struct aif {
  60         unsigned int id;
  61         bool master;
  62         struct pll *pll;
  63 };
  64
  65 static inline void aif_init(struct aif *aif, unsigned int id)
  66 {
  67         aif->id = id;
  68 }
  69
  70 struct coeff_ram {
  71         u8 cache[COEFF_RAM_SIZE];
  72         bool synced;
  73         struct mutex lock;
  74 };
  75
  76 static inline void init_coeff_ram_cache(u8 *cache)
  77 {
  78         static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19,
  79                 0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45,
  80                 0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74,
  81                 0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3,
  82                 0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9};
  83         int i;
  84
  85         for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
  86                 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
  87 }
  88
  89 static inline void coeff_ram_init(struct coeff_ram *ram)
  90 {
  91         init_coeff_ram_cache(ram->cache);
  92         mutex_init(&ram->lock);
  93 }
  94
  95 struct aifs_status {
  96         u8 streams;
  97 };
  98
  99 static inline void set_aif_status_active(struct aifs_status *status,
 100                 int aif_id, bool playback)
 101 {
 102         u8 mask = 0x01 << (aif_id * 2 + !playback);
 103
 104         status->streams |= mask;
 105 }
 106
 107 static inline void set_aif_status_inactive(struct aifs_status *status,
 108                 int aif_id, bool playback)
 109 {
 110         u8 mask = ~(0x01 << (aif_id * 2 + !playback));
 111
 112         status->streams &= mask;
 113 }
 114
 115 static bool aifs_active(struct aifs_status *status)
 116 {
 117         return status->streams;
 118 }
 119
 120 static bool aif_active(struct aifs_status *status, int aif_id)
 121 {
 122         return (0x03 << aif_id * 2) & status->streams;
 123 }
 124
 125 struct tscs454 {
 126         struct regmap *regmap;
 127         struct aif aifs[TSCS454_DAI_COUNT];
 128
 129         struct aifs_status aifs_status;
 130         struct mutex aifs_status_lock;
 131
 132         struct pll pll1;
 133         struct pll pll2;
 134         struct internal_rate internal_rate;
 135
 136         struct coeff_ram dac_ram;
 137         struct coeff_ram spk_ram;
 138         struct coeff_ram sub_ram;
 139
 140         struct clk *sysclk;
 141         int sysclk_src_id;
 142         unsigned int bclk_freq;
 143 };
 144
 145 struct coeff_ram_ctl {
 146         unsigned int addr;
 147         struct soc_bytes_ext bytes_ext;
 148 };
 149
 150 static const struct reg_sequence tscs454_patch[] = {
 151         /* Assign ASRC out of the box so DAI 1 just works */
 152         { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 },
 153         { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 },
 154         { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR },
 155         { R_TDMCTL0, FV_TDMMD_256 },
 156         { VIRT_ADDR(0x0A, 0x13), 1 << 3 },
 157 };
 158
 159 static bool tscs454_volatile(struct device *dev, unsigned int reg)
 160 {
 161         switch (reg) {
 162         case R_PLLSTAT:
 163
 164         case R_SPKCRRDL:
 165         case R_SPKCRRDM:
 166         case R_SPKCRRDH:
 167         case R_SPKCRS:
 168
 169         case R_DACCRRDL:
 170         case R_DACCRRDM:
 171         case R_DACCRRDH:
 172         case R_DACCRS:
 173
 174         case R_SUBCRRDL:
 175         case R_SUBCRRDM:
 176         case R_SUBCRRDH:
 177         case R_SUBCRS:
 178                 return true;
 179         default:
 180                 return false;
 181         };
 182 }
 183
 184 static bool tscs454_writable(struct device *dev, unsigned int reg)
 185 {
 186         switch (reg) {
 187         case R_SPKCRRDL:
 188         case R_SPKCRRDM:
 189         case R_SPKCRRDH:
 190
 191         case R_DACCRRDL:
 192         case R_DACCRRDM:
 193         case R_DACCRRDH:
 194
 195         case R_SUBCRRDL:
 196         case R_SUBCRRDM:
 197         case R_SUBCRRDH:
 198                 return false;
 199         default:
 200                 return true;
 201         };
 202 }
 203
 204 static bool tscs454_readable(struct device *dev, unsigned int reg)
 205 {
 206         switch (reg) {
 207         case R_SPKCRWDL:
 208         case R_SPKCRWDM:
 209         case R_SPKCRWDH:
 210
 211         case R_DACCRWDL:
 212         case R_DACCRWDM:
 213         case R_DACCRWDH:
 214
 215         case R_SUBCRWDL:
 216         case R_SUBCRWDM:
 217         case R_SUBCRWDH:
 218                 return false;
 219         default:
 220                 return true;
 221         };
 222 }
 223
 224 static bool tscs454_precious(struct device *dev, unsigned int reg)
 225 {
 226         switch (reg) {
 227         case R_SPKCRWDL:
 228         case R_SPKCRWDM:
 229         case R_SPKCRWDH:
 230         case R_SPKCRRDL:
 231         case R_SPKCRRDM:
 232         case R_SPKCRRDH:
 233
 234         case R_DACCRWDL:
 235         case R_DACCRWDM:
 236         case R_DACCRWDH:
 237         case R_DACCRRDL:
 238         case R_DACCRRDM:
 239         case R_DACCRRDH:
 240
 241         case R_SUBCRWDL:
 242         case R_SUBCRWDM:
 243         case R_SUBCRWDH:
 244         case R_SUBCRRDL:
 245         case R_SUBCRRDM:
 246         case R_SUBCRRDH:
 247                 return true;
 248         default:
 249                 return false;
 250         };
 251 }
 252
 253 static const struct regmap_range_cfg tscs454_regmap_range_cfg = {
 254         .name = "Pages",
 255         .range_min = VIRT_BASE,
 256         .range_max = VIRT_ADDR(0xFE, 0x02),
 257         .selector_reg = R_PAGESEL,
 258         .selector_mask = 0xff,
 259         .selector_shift = 0,
 260         .window_start = 0,
 261         .window_len = 0x100,
 262 };
 263
 264 static struct regmap_config const tscs454_regmap_cfg = {
 265         .reg_bits = 8,
 266         .val_bits = 8,
 267         .writeable_reg = tscs454_writable,
 268         .readable_reg = tscs454_readable,
 269         .volatile_reg = tscs454_volatile,
 270         .precious_reg = tscs454_precious,
 271         .ranges = &tscs454_regmap_range_cfg,
 272         .num_ranges = 1,
 273         .max_register = VIRT_ADDR(0xFE, 0x02),
 274         .cache_type = REGCACHE_RBTREE,
 275 };
 276
 277 static inline int tscs454_data_init(struct tscs454 *tscs454,
 278                 struct i2c_client *i2c)
 279 {
 280         int i;
 281         int ret;
 282
 283         tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg);
 284         if (IS_ERR(tscs454->regmap)) {
 285                 ret = PTR_ERR(tscs454->regmap);
 286                 return ret;
 287         }
 288
 289         for (i = 0; i < TSCS454_DAI_COUNT; i++)
 290                 aif_init(&tscs454->aifs[i], i);
 291
 292         mutex_init(&tscs454->aifs_status_lock);
 293         pll_init(&tscs454->pll1, 1);
 294         pll_init(&tscs454->pll2, 2);
 295
 296         coeff_ram_init(&tscs454->dac_ram);
 297         coeff_ram_init(&tscs454->spk_ram);
 298         coeff_ram_init(&tscs454->sub_ram);
 299
 300         return 0;
 301 }
 302
 303 struct reg_setting {
 304         unsigned int addr;
 305         unsigned int val;
 306 };
 307
 308 static int coeff_ram_get(struct snd_kcontrol *kcontrol,
 309         struct snd_ctl_elem_value *ucontrol)
 310 {
 311         struct snd_soc_component *component =
 312                 snd_soc_kcontrol_component(kcontrol);
 313         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 314         struct coeff_ram_ctl *ctl =
 315                 (struct coeff_ram_ctl *)kcontrol->private_value;
 316         struct soc_bytes_ext *params = &ctl->bytes_ext;
 317         u8 *coeff_ram;
 318         struct mutex *coeff_ram_lock;
 319
 320         if (strstr(kcontrol->id.name, "DAC")) {
 321                 coeff_ram = tscs454->dac_ram.cache;
 322                 coeff_ram_lock = &tscs454->dac_ram.lock;
 323         } else if (strstr(kcontrol->id.name, "Speaker")) {
 324                 coeff_ram = tscs454->spk_ram.cache;
 325                 coeff_ram_lock = &tscs454->spk_ram.lock;
 326         } else if (strstr(kcontrol->id.name, "Sub")) {
 327                 coeff_ram = tscs454->sub_ram.cache;
 328                 coeff_ram_lock = &tscs454->sub_ram.lock;
 329         } else {
 330                 return -EINVAL;
 331         }
 332
 333         mutex_lock(coeff_ram_lock);
 334
 335         memcpy(ucontrol->value.bytes.data,
 336                 &coeff_ram[ctl->addr * COEFF_SIZE], params->max);
 337
 338         mutex_unlock(coeff_ram_lock);
 339
 340         return 0;
 341 }
 342
 343 #define DACCRSTAT_MAX_TRYS 10
 344 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
 345                 unsigned int r_stat, unsigned int r_addr, unsigned int r_wr,
 346                 unsigned int coeff_addr, unsigned int coeff_cnt)
 347 {
 348         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 349         unsigned int val;
 350         int cnt;
 351         int trys;
 352         int ret;
 353
 354         for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) {
 355
 356                 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
 357                         ret = snd_soc_component_read(component, r_stat, &val);
 358                         if (ret < 0) {
 359                                 dev_err(component->dev,
 360                                         "Failed to read stat (%d)\n", ret);
 361                                 return ret;
 362                         }
 363                         if (!val)
 364                                 break;
 365                 }
 366
 367                 if (trys == DACCRSTAT_MAX_TRYS) {
 368                         ret = -EIO;
 369                         dev_err(component->dev,
 370                                 "Coefficient write error (%d)\n", ret);
 371                         return ret;
 372                 }
 373
 374                 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr);
 375                 if (ret < 0) {
 376                         dev_err(component->dev,
 377                                 "Failed to write dac ram address (%d)\n", ret);
 378                         return ret;
 379                 }
 380
 381                 ret = regmap_bulk_write(tscs454->regmap, r_wr,
 382                         &coeff_ram[coeff_addr * COEFF_SIZE],
 383                         COEFF_SIZE);
 384                 if (ret < 0) {
 385                         dev_err(component->dev,
 386                                 "Failed to write dac ram (%d)\n", ret);
 387                         return ret;
 388                 }
 389         }
 390
 391         return 0;
 392 }
 393
 394 static int coeff_ram_put(struct snd_kcontrol *kcontrol,
 395         struct snd_ctl_elem_value *ucontrol)
 396 {
 397         struct snd_soc_component *component =
 398                 snd_soc_kcontrol_component(kcontrol);
 399         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 400         struct coeff_ram_ctl *ctl =
 401                 (struct coeff_ram_ctl *)kcontrol->private_value;
 402         struct soc_bytes_ext *params = &ctl->bytes_ext;
 403         unsigned int coeff_cnt = params->max / COEFF_SIZE;
 404         u8 *coeff_ram;
 405         struct mutex *coeff_ram_lock;
 406         bool *coeff_ram_synced;
 407         unsigned int r_stat;
 408         unsigned int r_addr;
 409         unsigned int r_wr;
 410         unsigned int val;
 411         int ret;
 412
 413         if (strstr(kcontrol->id.name, "DAC")) {
 414                 coeff_ram = tscs454->dac_ram.cache;
 415                 coeff_ram_lock = &tscs454->dac_ram.lock;
 416                 coeff_ram_synced = &tscs454->dac_ram.synced;
 417                 r_stat = R_DACCRS;
 418                 r_addr = R_DACCRADD;
 419                 r_wr = R_DACCRWDL;
 420         } else if (strstr(kcontrol->id.name, "Speaker")) {
 421                 coeff_ram = tscs454->spk_ram.cache;
 422                 coeff_ram_lock = &tscs454->spk_ram.lock;
 423                 coeff_ram_synced = &tscs454->spk_ram.synced;
 424                 r_stat = R_SPKCRS;
 425                 r_addr = R_SPKCRADD;
 426                 r_wr = R_SPKCRWDL;
 427         } else if (strstr(kcontrol->id.name, "Sub")) {
 428                 coeff_ram = tscs454->sub_ram.cache;
 429                 coeff_ram_lock = &tscs454->sub_ram.lock;
 430                 coeff_ram_synced = &tscs454->sub_ram.synced;
 431                 r_stat = R_SUBCRS;
 432                 r_addr = R_SUBCRADD;
 433                 r_wr = R_SUBCRWDL;
 434         } else {
 435                 return -EINVAL;
 436         }
 437
 438         mutex_lock(coeff_ram_lock);
 439
 440         *coeff_ram_synced = false;
 441
 442         memcpy(&coeff_ram[ctl->addr * COEFF_SIZE],
 443                 ucontrol->value.bytes.data, params->max);
 444
 445         mutex_lock(&tscs454->pll1.lock);
 446         mutex_lock(&tscs454->pll2.lock);
 447
 448         ret = snd_soc_component_read(component, R_PLLSTAT, &val);
 449         if (ret < 0) {
 450                 dev_err(component->dev, "Failed to read PLL status (%d)\n",
 451                                 ret);
 452                 goto exit;
 453         }
 454         if (val) { /* PLLs locked */
 455                 ret = write_coeff_ram(component, coeff_ram,
 456                         r_stat, r_addr, r_wr,
 457                         ctl->addr, coeff_cnt);
 458                 if (ret < 0) {
 459                         dev_err(component->dev,
 460                                 "Failed to flush coeff ram cache (%d)\n", ret);
 461                         goto exit;
 462                 }
 463                 *coeff_ram_synced = true;
 464         }
 465
 466         ret = 0;
 467 exit:
 468         mutex_unlock(&tscs454->pll2.lock);
 469         mutex_unlock(&tscs454->pll1.lock);
 470         mutex_unlock(coeff_ram_lock);
 471
 472         return ret;
 473 }
 474
 475 static inline int coeff_ram_sync(struct snd_soc_component *component,
 476                 struct tscs454 *tscs454)
 477 {
 478         int ret;
 479
 480         mutex_lock(&tscs454->dac_ram.lock);
 481         if (!tscs454->dac_ram.synced) {
 482                 ret = write_coeff_ram(component, tscs454->dac_ram.cache,
 483                                 R_DACCRS, R_DACCRADD, R_DACCRWDL,
 484                                 0x00, COEFF_RAM_COEFF_COUNT);
 485                 if (ret < 0) {
 486                         mutex_unlock(&tscs454->dac_ram.lock);
 487                         return ret;
 488                 }
 489         }
 490         mutex_unlock(&tscs454->dac_ram.lock);
 491
 492         mutex_lock(&tscs454->spk_ram.lock);
 493         if (!tscs454->spk_ram.synced) {
 494                 ret = write_coeff_ram(component, tscs454->spk_ram.cache,
 495                                 R_SPKCRS, R_SPKCRADD, R_SPKCRWDL,
 496                                 0x00, COEFF_RAM_COEFF_COUNT);
 497                 if (ret < 0) {
 498                         mutex_unlock(&tscs454->spk_ram.lock);
 499                         return ret;
 500                 }
 501         }
 502         mutex_unlock(&tscs454->spk_ram.lock);
 503
 504         mutex_lock(&tscs454->sub_ram.lock);
 505         if (!tscs454->sub_ram.synced) {
 506                 ret = write_coeff_ram(component, tscs454->sub_ram.cache,
 507                                 R_SUBCRS, R_SUBCRADD, R_SUBCRWDL,
 508                                 0x00, COEFF_RAM_COEFF_COUNT);
 509                 if (ret < 0) {
 510                         mutex_unlock(&tscs454->sub_ram.lock);
 511                         return ret;
 512                 }
 513         }
 514         mutex_unlock(&tscs454->sub_ram.lock);
 515
 516         return 0;
 517 }
 518
 519 #define PLL_REG_SETTINGS_COUNT 11
 520 struct pll_ctl {
 521         int freq_in;
 522         struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
 523 };
 524
 525 #define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h)       \
 526         {                                                               \
 527                 .freq_in = f,                                           \
 528                 .settings = {                                           \
 529                         {R_PLL1CTL,     c1},                            \
 530                         {R_PLL1RDIV,    r1},                            \
 531                         {R_PLL1ODIV,    o1},                            \
 532                         {R_PLL1FDIVL,   f1l},                           \
 533                         {R_PLL1FDIVH,   f1h},                           \
 534                         {R_PLL2CTL,     c2},                            \
 535                         {R_PLL2RDIV,    r2},                            \
 536                         {R_PLL2ODIV,    o2},                            \
 537                         {R_PLL2FDIVL,   f2l},                           \
 538                         {R_PLL2FDIVH,   f2h},                           \
 539                         {R_TIMEBASE,    t},                             \
 540                 },                                                      \
 541         }
 542
 543 static const struct pll_ctl pll_ctls[] = {
 544         PLL_CTL(1411200, 0x05,
 545                 0xB9, 0x07, 0x02, 0xC3, 0x04,
 546                 0x5A, 0x02, 0x03, 0xE0, 0x01),
 547         PLL_CTL(1536000, 0x05,
 548                 0x5A, 0x02, 0x03, 0xE0, 0x01,
 549                 0x5A, 0x02, 0x03, 0xB9, 0x01),
 550         PLL_CTL(2822400, 0x0A,
 551                 0x63, 0x07, 0x04, 0xC3, 0x04,
 552                 0x62, 0x07, 0x03, 0x48, 0x03),
 553         PLL_CTL(3072000, 0x0B,
 554                 0x62, 0x07, 0x03, 0x48, 0x03,
 555                 0x5A, 0x04, 0x03, 0xB9, 0x01),
 556         PLL_CTL(5644800, 0x15,
 557                 0x63, 0x0E, 0x04, 0xC3, 0x04,
 558                 0x5A, 0x08, 0x03, 0xE0, 0x01),
 559         PLL_CTL(6144000, 0x17,
 560                 0x5A, 0x08, 0x03, 0xE0, 0x01,
 561                 0x5A, 0x08, 0x03, 0xB9, 0x01),
 562         PLL_CTL(12000000, 0x2E,
 563                 0x5B, 0x19, 0x03, 0x00, 0x03,
 564                 0x6A, 0x19, 0x05, 0x98, 0x04),
 565         PLL_CTL(19200000, 0x4A,
 566                 0x53, 0x14, 0x03, 0x80, 0x01,
 567                 0x5A, 0x19, 0x03, 0xB9, 0x01),
 568         PLL_CTL(22000000, 0x55,
 569                 0x6A, 0x37, 0x05, 0x00, 0x06,
 570                 0x62, 0x26, 0x03, 0x49, 0x02),
 571         PLL_CTL(22579200, 0x57,
 572                 0x62, 0x31, 0x03, 0x20, 0x03,
 573                 0x53, 0x1D, 0x03, 0xB3, 0x01),
 574         PLL_CTL(24000000, 0x5D,
 575                 0x53, 0x19, 0x03, 0x80, 0x01,
 576                 0x5B, 0x19, 0x05, 0x4C, 0x02),
 577         PLL_CTL(24576000, 0x5F,
 578                 0x53, 0x1D, 0x03, 0xB3, 0x01,
 579                 0x62, 0x40, 0x03, 0x72, 0x03),
 580         PLL_CTL(27000000, 0x68,
 581                 0x62, 0x4B, 0x03, 0x00, 0x04,
 582                 0x6A, 0x7D, 0x03, 0x20, 0x06),
 583         PLL_CTL(36000000, 0x8C,
 584                 0x5B, 0x4B, 0x03, 0x00, 0x03,
 585                 0x6A, 0x7D, 0x03, 0x98, 0x04),
 586         PLL_CTL(11289600, 0x2B,
 587                 0x6A, 0x31, 0x03, 0x40, 0x06,
 588                 0x5A, 0x12, 0x03, 0x1C, 0x02),
 589         PLL_CTL(26000000, 0x65,
 590                 0x63, 0x41, 0x05, 0x00, 0x06,
 591                 0x5A, 0x26, 0x03, 0xEF, 0x01),
 592         PLL_CTL(12288000, 0x2F,
 593                 0x5A, 0x12, 0x03, 0x1C, 0x02,
 594                 0x62, 0x20, 0x03, 0x72, 0x03),
 595         PLL_CTL(40000000, 0x9B,
 596                 0xA2, 0x7D, 0x03, 0x80, 0x04,
 597                 0x63, 0x7D, 0x05, 0xE4, 0x06),
 598         PLL_CTL(512000, 0x01,
 599                 0x62, 0x01, 0x03, 0xD0, 0x02,
 600                 0x5B, 0x01, 0x04, 0x72, 0x03),
 601         PLL_CTL(705600, 0x02,
 602                 0x62, 0x02, 0x03, 0x15, 0x04,
 603                 0x62, 0x01, 0x04, 0x80, 0x02),
 604         PLL_CTL(1024000, 0x03,
 605                 0x62, 0x02, 0x03, 0xD0, 0x02,
 606                 0x5B, 0x02, 0x04, 0x72, 0x03),
 607         PLL_CTL(2048000, 0x07,
 608                 0x62, 0x04, 0x03, 0xD0, 0x02,
 609                 0x5B, 0x04, 0x04, 0x72, 0x03),
 610         PLL_CTL(2400000, 0x08,
 611                 0x62, 0x05, 0x03, 0x00, 0x03,
 612                 0x63, 0x05, 0x05, 0x98, 0x04),
 613 };
 614
 615 static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in)
 616 {
 617         int i;
 618         struct pll_ctl const *pll_ctl = NULL;
 619
 620         for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
 621                 if (pll_ctls[i].freq_in == freq_in) {
 622                         pll_ctl = &pll_ctls[i];
 623                         break;
 624                 }
 625
 626         return pll_ctl;
 627 }
 628
 629 enum {
 630         PLL_INPUT_XTAL = 0,
 631         PLL_INPUT_MCLK1,
 632         PLL_INPUT_MCLK2,
 633         PLL_INPUT_BCLK,
 634 };
 635
 636 static int set_sysclk(struct snd_soc_component *component)
 637 {
 638         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 639         struct pll_ctl const *pll_ctl;
 640         unsigned long freq;
 641         int i;
 642         int ret;
 643
 644         if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
 645                 freq = clk_get_rate(tscs454->sysclk);
 646         else
 647                 freq = tscs454->bclk_freq;
 648         pll_ctl = get_pll_ctl(freq);
 649         if (!pll_ctl) {
 650                 ret = -EINVAL;
 651                 dev_err(component->dev,
 652                                 "Invalid PLL input %lu (%d)\n", freq, ret);
 653                 return ret;
 654         }
 655
 656         for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
 657                 ret = snd_soc_component_write(component,
 658                                 pll_ctl->settings[i].addr,
 659                                 pll_ctl->settings[i].val);
 660                 if (ret < 0) {
 661                         dev_err(component->dev,
 662                                         "Failed to set pll setting (%d)\n",
 663                                         ret);
 664                         return ret;
 665                 }
 666         }
 667
 668         return 0;
 669 }
 670
 671 static inline void reserve_pll(struct pll *pll)
 672 {
 673         mutex_lock(&pll->lock);
 674         pll->users++;
 675         mutex_unlock(&pll->lock);
 676 }
 677
 678 static inline void free_pll(struct pll *pll)
 679 {
 680         mutex_lock(&pll->lock);
 681         pll->users--;
 682         mutex_unlock(&pll->lock);
 683 }
 684
 685 static int pll_connected(struct snd_soc_dapm_widget *source,
 686                 struct snd_soc_dapm_widget *sink)
 687 {
 688         struct snd_soc_component *component =
 689                 snd_soc_dapm_to_component(source->dapm);
 690         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 691         int users;
 692
 693         if (strstr(source->name, "PLL 1")) {
 694                 mutex_lock(&tscs454->pll1.lock);
 695                 users = tscs454->pll1.users;
 696                 mutex_unlock(&tscs454->pll1.lock);
 697                 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__,
 698                                 users);
 699         } else {
 700                 mutex_lock(&tscs454->pll2.lock);
 701                 users = tscs454->pll2.users;
 702                 mutex_unlock(&tscs454->pll2.lock);
 703                 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__,
 704                                 users);
 705         }
 706
 707         return users;
 708 }
 709
 710 /*
 711  * PLL must be enabled after power up and must be disabled before power down
 712  * for proper clock switching.
 713  */
 714 static int pll_power_event(struct snd_soc_dapm_widget *w,
 715                 struct snd_kcontrol *kcontrol, int event)
 716 {
 717         struct snd_soc_component *component =
 718                 snd_soc_dapm_to_component(w->dapm);
 719         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 720         bool enable;
 721         bool pll1;
 722         unsigned int msk;
 723         unsigned int val;
 724         int ret;
 725
 726         if (strstr(w->name, "PLL 1"))
 727                 pll1 = true;
 728         else
 729                 pll1 = false;
 730
 731         msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN;
 732
 733         if (event == SND_SOC_DAPM_POST_PMU)
 734                 enable = true;
 735         else
 736                 enable = false;
 737
 738         if (enable)
 739                 val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE;
 740         else
 741                 val = pll1 ? FV_PLL1CLKEN_DISABLE : FV_PLL2CLKEN_DISABLE;
 742
 743         ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val);
 744         if (ret < 0) {
 745                 dev_err(component->dev, "Failed to %s PLL %d  (%d)\n",
 746                                 enable ? "enable" : "disable",
 747                                 pll1 ? 1 : 2,
 748                                 ret);
 749                 return ret;
 750         }
 751
 752         if (enable) {
 753                 msleep(20); // Wait for lock
 754                 ret = coeff_ram_sync(component, tscs454);
 755                 if (ret < 0) {
 756                         dev_err(component->dev,
 757                                         "Failed to sync coeff ram (%d)\n", ret);
 758                         return ret;
 759                 }
 760         }
 761
 762         return 0;
 763 }
 764
 765 static inline int aif_set_master(struct snd_soc_component *component,
 766                 unsigned int aif_id, bool master)
 767 {
 768         unsigned int reg;
 769         unsigned int mask;
 770         unsigned int val;
 771         int ret;
 772
 773         switch (aif_id) {
 774         case TSCS454_DAI1_ID:
 775                 reg = R_I2SP1CTL;
 776                 break;
 777         case TSCS454_DAI2_ID:
 778                 reg = R_I2SP2CTL;
 779                 break;
 780         case TSCS454_DAI3_ID:
 781                 reg = R_I2SP3CTL;
 782                 break;
 783         default:
 784                 ret = -ENODEV;
 785                 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret);
 786                 return ret;
 787         }
 788         mask = FM_I2SPCTL_PORTMS;
 789         val = master ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE;
 790
 791         ret = snd_soc_component_update_bits(component, reg, mask, val);
 792         if (ret < 0) {
 793                 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n",
 794                         aif_id, master ? "master" : "slave", ret);
 795                 return ret;
 796         }
 797
 798         return 0;
 799 }
 800
 801 static inline
 802 int aif_prepare(struct snd_soc_component *component, struct aif *aif)
 803 {
 804         int ret;
 805
 806         ret = aif_set_master(component, aif->id, aif->master);
 807         if (ret < 0)
 808                 return ret;
 809
 810         return 0;
 811 }
 812
 813 static inline int aif_free(struct snd_soc_component *component,
 814                 struct aif *aif, bool playback)
 815 {
 816         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 817
 818         mutex_lock(&tscs454->aifs_status_lock);
 819
 820         dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id);
 821
 822         set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback);
 823
 824         dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n",
 825                 aif->id, tscs454->aifs_status.streams);
 826
 827         if (!aif_active(&tscs454->aifs_status, aif->id)) {
 828                 /* Do config in slave mode */
 829                 aif_set_master(component, aif->id, false);
 830                 dev_dbg(component->dev, "Freeing pll %d from aif %d\n",
 831                                 aif->pll->id, aif->id);
 832                 free_pll(aif->pll);
 833         }
 834
 835         if (!aifs_active(&tscs454->aifs_status)) {
 836                 dev_dbg(component->dev, "Freeing pll %d from ir\n",
 837                                 tscs454->internal_rate.pll->id);
 838                 free_pll(tscs454->internal_rate.pll);
 839         }
 840
 841         mutex_unlock(&tscs454->aifs_status_lock);
 842
 843         return 0;
 844 }
 845
 846 /* R_PLLCTL PG 0 ADDR 0x15 */
 847 static char const * const bclk_sel_txt[] = {
 848                 "BCLK 1", "BCLK 2", "BCLK 3"};
 849
 850 static struct soc_enum const bclk_sel_enum =
 851                 SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL,
 852                                 ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt);
 853
 854 /* R_ISRC PG 0 ADDR 0x16 */
 855 static char const * const isrc_br_txt[] = {
 856                 "44.1kHz", "48kHz"};
 857
 858 static struct soc_enum const isrc_br_enum =
 859                 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR,
 860                                 ARRAY_SIZE(isrc_br_txt), isrc_br_txt);
 861
 862 static char const * const isrc_bm_txt[] = {
 863                 "0.25x", "0.5x", "1.0x", "2.0x"};
 864
 865 static struct soc_enum const isrc_bm_enum =
 866                 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM,
 867                                 ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt);
 868
 869 /* R_SCLKCTL PG 0 ADDR 0x18 */
 870 static char const * const modular_rate_txt[] = {
 871         "Reserved", "Half", "Full", "Auto",};
 872
 873 static struct soc_enum const adc_modular_rate_enum =
 874         SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM,
 875                         ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
 876
 877 static struct soc_enum const dac_modular_rate_enum =
 878         SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM,
 879                         ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
 880
 881 /* R_I2SIDCTL PG 0 ADDR 0x38 */
 882 static char const * const data_ctrl_txt[] = {
 883         "L/R", "L/L", "R/R", "R/L"};
 884
 885 static struct soc_enum const data_in_ctrl_enums[] = {
 886         SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL,
 887                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 888         SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL,
 889                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 890         SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL,
 891                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 892 };
 893
 894 /* R_I2SODCTL PG 0 ADDR 0x39 */
 895 static struct soc_enum const data_out_ctrl_enums[] = {
 896         SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL,
 897                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 898         SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL,
 899                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 900         SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL,
 901                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 902 };
 903
 904 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
 905 static char const * const asrc_mux_txt[] = {
 906                 "None", "DAI 1", "DAI 2", "DAI 3"};
 907
 908 static struct soc_enum const asrc_in_mux_enum =
 909                 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX,
 910                                 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
 911
 912 static char const * const dai_mux_txt[] = {
 913                 "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1",
 914                 "DMic 2", "ClassD", "DAC", "Sub"};
 915
 916 static struct soc_enum const dai2_mux_enum =
 917                 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX,
 918                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 919
 920 static struct snd_kcontrol_new const dai2_mux_dapm_enum =
 921                 SOC_DAPM_ENUM("DAI 2 Mux",  dai2_mux_enum);
 922
 923 static struct soc_enum const dai1_mux_enum =
 924                 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX,
 925                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 926
 927 static struct snd_kcontrol_new const dai1_mux_dapm_enum =
 928                 SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum);
 929
 930 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
 931 static struct soc_enum const asrc_out_mux_enum =
 932                 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX,
 933                                 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
 934
 935 static struct soc_enum const dac_mux_enum =
 936                 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX,
 937                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 938
 939 static struct snd_kcontrol_new const dac_mux_dapm_enum =
 940                 SOC_DAPM_ENUM("DAC Mux", dac_mux_enum);
 941
 942 static struct soc_enum const dai3_mux_enum =
 943                 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX,
 944                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 945
 946 static struct snd_kcontrol_new const dai3_mux_dapm_enum =
 947                 SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum);
 948
 949 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
 950 static char const * const sub_mux_txt[] = {
 951                 "CH 0", "CH 1", "CH 0 + 1",
 952                 "CH 2", "CH 3", "CH 2 + 3",
 953                 "CH 4", "CH 5", "CH 4 + 5",
 954                 "ADC/DMic 1 Left", "ADC/DMic 1 Right",
 955                 "ADC/DMic 1 Left Plus Right",
 956                 "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right",
 957                 "ClassD Left", "ClassD Right", "ClassD Left Plus Right"};
 958
 959 static struct soc_enum const sub_mux_enum =
 960                 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX,
 961                                 ARRAY_SIZE(sub_mux_txt), sub_mux_txt);
 962
 963 static struct snd_kcontrol_new const sub_mux_dapm_enum =
 964                 SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
 965
 966 static struct soc_enum const classd_mux_enum =
 967                 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX,
 968                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 969
 970 static struct snd_kcontrol_new const classd_mux_dapm_enum =
 971                 SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum);
 972
 973 /* R_HSDCTL1 PG 1 ADDR 0x01 */
 974 static char const * const jack_type_txt[] = {
 975                 "3 Terminal", "4 Terminal"};
 976
 977 static struct soc_enum const hp_jack_type_enum =
 978                 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE,
 979                                 ARRAY_SIZE(jack_type_txt), jack_type_txt);
 980
 981 static char const * const hs_det_pol_txt[] = {
 982                 "Rising", "Falling"};
 983
 984 static struct soc_enum const hs_det_pol_enum =
 985                 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL,
 986                                 ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt);
 987
 988 /* R_HSDCTL1 PG 1 ADDR 0x02 */
 989 static char const * const hs_mic_bias_force_txt[] = {
 990                 "Off", "Ring", "Sleeve"};
 991
 992 static struct soc_enum const hs_mic_bias_force_enum =
 993                 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1,
 994                                 ARRAY_SIZE(hs_mic_bias_force_txt),
 995                                 hs_mic_bias_force_txt);
 996
 997 static char const * const plug_type_txt[] = {
 998                 "OMTP", "CTIA", "Reserved", "Headphone"};
 999
1000 static struct soc_enum const plug_type_force_enum =
1001                 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE,
1002                 ARRAY_SIZE(plug_type_txt), plug_type_txt);
1003
1004
1005 /* R_CH0AIC PG 1 ADDR 0x06 */
1006 static char const * const in_bst_mux_txt[] = {
1007                 "Input 1", "Input 2", "Input 3", "D2S"};
1008
1009 static struct soc_enum const in_bst_mux_ch0_enum =
1010                 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL,
1011                                 ARRAY_SIZE(in_bst_mux_txt),
1012                                 in_bst_mux_txt);
1013 static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum =
1014                 SOC_DAPM_ENUM("Input Boost Channel 0 Enum",
1015                                 in_bst_mux_ch0_enum);
1016
1017 static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0);
1018
1019 static char const * const adc_mux_txt[] = {
1020                 "Input 1 Boost Bypass", "Input 2 Boost Bypass",
1021                 "Input 3 Boost Bypass", "Input Boost"};
1022
1023 static struct soc_enum const adc_mux_ch0_enum =
1024                 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN,
1025                                 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1026 static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum =
1027                 SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum);
1028
1029 static char const * const in_proc_mux_txt[] = {
1030                 "ADC", "DMic"};
1031
1032 static struct soc_enum const in_proc_ch0_enum =
1033                 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S,
1034                                 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1035 static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum =
1036                 SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
1037                                 in_proc_ch0_enum);
1038
1039 /* R_CH1AIC PG 1 ADDR 0x07 */
1040 static struct soc_enum const in_bst_mux_ch1_enum =
1041                 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR,
1042                                 ARRAY_SIZE(in_bst_mux_txt),
1043                                 in_bst_mux_txt);
1044 static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum =
1045                 SOC_DAPM_ENUM("Input Boost Channel 1 Enum",
1046                                 in_bst_mux_ch1_enum);
1047
1048 static struct soc_enum const adc_mux_ch1_enum =
1049                 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN,
1050                                 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1051 static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum =
1052                 SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum);
1053
1054 static struct soc_enum const in_proc_ch1_enum =
1055                 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S,
1056                                 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1057 static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum =
1058                 SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
1059                                 in_proc_ch1_enum);
1060
1061 /* R_ICTL0 PG 1 ADDR 0x0A */
1062 static char const * const pol_txt[] = {
1063                 "Normal", "Invert"};
1064
1065 static struct soc_enum const in_pol_ch1_enum =
1066                 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL,
1067                                 ARRAY_SIZE(pol_txt), pol_txt);
1068
1069 static struct soc_enum const in_pol_ch0_enum =
1070                 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL,
1071                                 ARRAY_SIZE(pol_txt), pol_txt);
1072
1073 static char const * const in_proc_ch_sel_txt[] = {
1074                 "Normal", "Mono Mix to Channel 0",
1075                 "Mono Mix to Channel 1", "Add"};
1076
1077 static struct soc_enum const in_proc_ch01_sel_enum =
1078                 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL,
1079                                 ARRAY_SIZE(in_proc_ch_sel_txt),
1080                                 in_proc_ch_sel_txt);
1081
1082 /* R_ICTL1 PG 1 ADDR 0x0B */
1083 static struct soc_enum const in_pol_ch3_enum =
1084                 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL,
1085                                 ARRAY_SIZE(pol_txt), pol_txt);
1086
1087 static struct soc_enum const in_pol_ch2_enum =
1088                 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL,
1089                                 ARRAY_SIZE(pol_txt), pol_txt);
1090
1091 static struct soc_enum const in_proc_ch23_sel_enum =
1092                 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL,
1093                                 ARRAY_SIZE(in_proc_ch_sel_txt),
1094                                 in_proc_ch_sel_txt);
1095
1096 /* R_MICBIAS PG 1 ADDR 0x0C */
1097 static char const * const mic_bias_txt[] = {
1098                 "2.5V", "2.1V", "1.8V", "Vdd"};
1099
1100 static struct soc_enum const mic_bias_2_enum =
1101                 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2,
1102                                 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1103
1104 static struct soc_enum const mic_bias_1_enum =
1105                 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1,
1106                                 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1107
1108 /* R_PGACTL0 PG 1 ADDR 0x0D */
1109 /* R_PGACTL1 PG 1 ADDR 0x0E */
1110 /* R_PGACTL2 PG 1 ADDR 0x0F */
1111 /* R_PGACTL3 PG 1 ADDR 0x10 */
1112 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1113
1114 /* R_ICH0VOL PG1 ADDR 0x12 */
1115 /* R_ICH1VOL PG1 ADDR 0x13 */
1116 /* R_ICH2VOL PG1 ADDR 0x14 */
1117 /* R_ICH3VOL PG1 ADDR 0x15 */
1118 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1119
1120 /* R_ASRCILVOL PG1 ADDR 0x16 */
1121 /* R_ASRCIRVOL PG1 ADDR 0x17 */
1122 /* R_ASRCOLVOL PG1 ADDR 0x18 */
1123 /* R_ASRCORVOL PG1 ADDR 0x19 */
1124 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1125
1126 /* R_ALCCTL0 PG1 ADDR 0x1D */
1127 static char const * const alc_mode_txt[] = {
1128                 "ALC", "Limiter"};
1129
1130 static struct soc_enum const alc_mode_enum =
1131                 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE,
1132                                 ARRAY_SIZE(alc_mode_txt), alc_mode_txt);
1133
1134 static char const * const alc_ref_text[] = {
1135                 "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"};
1136
1137 static struct soc_enum const alc_ref_enum =
1138                 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF,
1139                                 ARRAY_SIZE(alc_ref_text), alc_ref_text);
1140
1141 /* R_ALCCTL1 PG 1 ADDR 0x1E */
1142 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1143 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1144
1145 /* R_ALCCTL2 PG 1 ADDR 0x1F */
1146 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1147
1148 /* R_NGATE PG 1 ADDR 0x21 */
1149 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1150
1151 static char const * const ngate_type_txt[] = {
1152                 "PGA Constant", "ADC Mute"};
1153
1154 static struct soc_enum const ngate_type_enum =
1155                 SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG,
1156                                 ARRAY_SIZE(ngate_type_txt), ngate_type_txt);
1157
1158 /* R_DMICCTL PG 1 ADDR 0x22 */
1159 static char const * const dmic_mono_sel_txt[] = {
1160                 "Stereo", "Mono"};
1161
1162 static struct soc_enum const dmic_mono_sel_enum =
1163                 SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO,
1164                         ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt);
1165
1166 /* R_DACCTL PG 2 ADDR 0x01 */
1167 static struct soc_enum const dac_pol_r_enum =
1168                 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR,
1169                         ARRAY_SIZE(pol_txt), pol_txt);
1170
1171 static struct soc_enum const dac_pol_l_enum =
1172                 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL,
1173                         ARRAY_SIZE(pol_txt), pol_txt);
1174
1175 static char const * const dac_dith_txt[] = {
1176                 "Half", "Full", "Disabled", "Static"};
1177
1178 static struct soc_enum const dac_dith_enum =
1179                 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH,
1180                         ARRAY_SIZE(dac_dith_txt), dac_dith_txt);
1181
1182 /* R_SPKCTL PG 2 ADDR 0x02 */
1183 static struct soc_enum const spk_pol_r_enum =
1184                 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR,
1185                                 ARRAY_SIZE(pol_txt), pol_txt);
1186
1187 static struct soc_enum const spk_pol_l_enum =
1188                 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL,
1189                                 ARRAY_SIZE(pol_txt), pol_txt);
1190
1191 /* R_SUBCTL PG 2 ADDR 0x03 */
1192 static struct soc_enum const sub_pol_enum =
1193                 SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL,
1194                                 ARRAY_SIZE(pol_txt), pol_txt);
1195
1196 /* R_MVOLL PG 2 ADDR 0x08 */
1197 /* R_MVOLR PG 2 ADDR 0x09 */
1198 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1199
1200 /* R_HPVOLL PG 2 ADDR 0x0A */
1201 /* R_HPVOLR PG 2 ADDR 0x0B */
1202 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1203
1204 /* R_SPKVOLL PG 2 ADDR 0x0C */
1205 /* R_SPKVOLR PG 2 ADDR 0x0D */
1206 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1207
1208 /* R_SPKEQFILT PG 3 ADDR 0x01 */
1209 static char const * const eq_txt[] = {
1210         "Pre Scale",
1211         "Pre Scale + EQ Band 0",
1212         "Pre Scale + EQ Band 0 - 1",
1213         "Pre Scale + EQ Band 0 - 2",
1214         "Pre Scale + EQ Band 0 - 3",
1215         "Pre Scale + EQ Band 0 - 4",
1216         "Pre Scale + EQ Band 0 - 5",
1217 };
1218
1219 static struct soc_enum const spk_eq_enums[] = {
1220         SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE,
1221                 ARRAY_SIZE(eq_txt), eq_txt),
1222         SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE,
1223                 ARRAY_SIZE(eq_txt), eq_txt),
1224 };
1225
1226 /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1227 static char const * const lvl_mode_txt[] = {
1228                 "Average", "Peak"};
1229
1230 static struct soc_enum const spk_mbc3_lvl_det_mode_enum =
1231                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3,
1232                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1233
1234 static char const * const win_sel_txt[] = {
1235                 "512", "64"};
1236
1237 static struct soc_enum const spk_mbc3_win_sel_enum =
1238                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3,
1239                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1240
1241 static struct soc_enum const spk_mbc2_lvl_det_mode_enum =
1242                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2,
1243                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1244
1245 static struct soc_enum const spk_mbc2_win_sel_enum =
1246                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2,
1247                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1248
1249 static struct soc_enum const spk_mbc1_lvl_det_mode_enum =
1250                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1,
1251                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1252
1253 static struct soc_enum const spk_mbc1_win_sel_enum =
1254                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1,
1255                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1256
1257 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1258 static struct soc_enum const spk_mbc1_phase_pol_enum =
1259                 SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE,
1260                                 ARRAY_SIZE(pol_txt), pol_txt);
1261
1262 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1263
1264 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1265 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1266
1267 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1268 static char const * const comp_rat_txt[] = {
1269                 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
1270                 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
1271                 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"};
1272
1273 static struct soc_enum const spk_mbc1_comp_rat_enum =
1274                 SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO,
1275                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1276
1277 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1278 static struct soc_enum const spk_mbc2_phase_pol_enum =
1279                 SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE,
1280                                 ARRAY_SIZE(pol_txt), pol_txt);
1281
1282 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1283 static struct soc_enum const spk_mbc2_comp_rat_enum =
1284                 SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO,
1285                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1286
1287 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1288 static struct soc_enum const spk_mbc3_phase_pol_enum =
1289                 SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE,
1290                                 ARRAY_SIZE(pol_txt), pol_txt);
1291
1292 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1293 static struct soc_enum const spk_mbc3_comp_rat_enum =
1294                 SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO,
1295                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1296
1297 /* R_SPKCLECTL PG 3 ADDR 0x21 */
1298 static struct soc_enum const spk_cle_lvl_mode_enum =
1299                 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE,
1300                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1301
1302 static struct soc_enum const spk_cle_win_sel_enum =
1303                 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL,
1304                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1305
1306 /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1307 static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650);
1308
1309 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1310 static struct soc_enum const spk_comp_rat_enum =
1311                 SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO,
1312                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1313
1314 /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1315 static char const * const exp_rat_txt[] = {
1316                 "Reserved", "Reserved", "1:2", "1:3",
1317                 "1:4", "1:5", "1:6", "1:7"};
1318
1319 static struct soc_enum const spk_exp_rat_enum =
1320                 SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO,
1321                                 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1322
1323 /* R_DACEQFILT PG 4 ADDR 0x01 */
1324 static struct soc_enum const dac_eq_enums[] = {
1325         SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE,
1326                 ARRAY_SIZE(eq_txt), eq_txt),
1327         SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE,
1328                 ARRAY_SIZE(eq_txt), eq_txt),
1329 };
1330
1331 /* R_DACMBCCTL PG 4 ADDR 0x0B */
1332 static struct soc_enum const dac_mbc3_lvl_det_mode_enum =
1333                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
1334                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1335
1336 static struct soc_enum const dac_mbc3_win_sel_enum =
1337                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
1338                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1339
1340 static struct soc_enum const dac_mbc2_lvl_det_mode_enum =
1341                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
1342                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1343
1344 static struct soc_enum const dac_mbc2_win_sel_enum =
1345                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
1346                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1347
1348 static struct soc_enum const dac_mbc1_lvl_det_mode_enum =
1349                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
1350                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1351
1352 static struct soc_enum const dac_mbc1_win_sel_enum =
1353                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
1354                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1355
1356 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1357 static struct soc_enum const dac_mbc1_phase_pol_enum =
1358                 SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE,
1359                                 ARRAY_SIZE(pol_txt), pol_txt);
1360
1361 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1362 static struct soc_enum const dac_mbc1_comp_rat_enum =
1363                 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO,
1364                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1365
1366 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1367 static struct soc_enum const dac_mbc2_phase_pol_enum =
1368                 SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE,
1369                                 ARRAY_SIZE(pol_txt), pol_txt);
1370
1371 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1372 static struct soc_enum const dac_mbc2_comp_rat_enum =
1373                 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO,
1374                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1375
1376 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1377 static struct soc_enum const dac_mbc3_phase_pol_enum =
1378                 SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE,
1379                                 ARRAY_SIZE(pol_txt), pol_txt);
1380
1381 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1382 static struct soc_enum const dac_mbc3_comp_rat_enum =
1383                 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO,
1384                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1385
1386 /* R_DACCLECTL PG 4 ADDR 0x21 */
1387 static struct soc_enum const dac_cle_lvl_mode_enum =
1388                 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE,
1389                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1390
1391 static struct soc_enum const dac_cle_win_sel_enum =
1392                 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL,
1393                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1394
1395 /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1396 static struct soc_enum const dac_comp_rat_enum =
1397                 SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO,
1398                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1399
1400 /* R_DACEXPRAT PG 4 ADDR 0x30 */
1401 static struct soc_enum const dac_exp_rat_enum =
1402                 SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO,
1403                                 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1404
1405 /* R_SUBEQFILT PG 5 ADDR 0x01 */
1406 static struct soc_enum const sub_eq_enums[] = {
1407         SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE,
1408                 ARRAY_SIZE(eq_txt), eq_txt),
1409         SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE,
1410                 ARRAY_SIZE(eq_txt), eq_txt),
1411 };
1412
1413 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
1414 static struct soc_enum const sub_mbc3_lvl_det_mode_enum =
1415                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3,
1416                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1417
1418 static struct soc_enum const sub_mbc3_win_sel_enum =
1419                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3,
1420                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1421
1422 static struct soc_enum const sub_mbc2_lvl_det_mode_enum =
1423                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2,
1424                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1425
1426 static struct soc_enum const sub_mbc2_win_sel_enum =
1427                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2,
1428                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1429
1430 static struct soc_enum const sub_mbc1_lvl_det_mode_enum =
1431                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1,
1432                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1433
1434 static struct soc_enum const sub_mbc1_win_sel_enum =
1435                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1,
1436                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1437
1438 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
1439 static struct soc_enum const sub_mbc1_phase_pol_enum =
1440                 SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE,
1441                                 ARRAY_SIZE(pol_txt), pol_txt);
1442
1443 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
1444 static struct soc_enum const sub_mbc1_comp_rat_enum =
1445                 SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO,
1446                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1447
1448 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
1449 static struct soc_enum const sub_mbc2_phase_pol_enum =
1450                 SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE,
1451                                 ARRAY_SIZE(pol_txt), pol_txt);
1452
1453 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
1454 static struct soc_enum const sub_mbc2_comp_rat_enum =
1455                 SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO,
1456                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1457
1458 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
1459 static struct soc_enum const sub_mbc3_phase_pol_enum =
1460                 SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE,
1461                                 ARRAY_SIZE(pol_txt), pol_txt);
1462
1463 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
1464 static struct soc_enum const sub_mbc3_comp_rat_enum =
1465                 SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO,
1466                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1467
1468 /* R_SUBCLECTL PG 5 ADDR 0x21 */
1469 static struct soc_enum const sub_cle_lvl_mode_enum =
1470                 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE,
1471                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1472 static struct soc_enum const sub_cle_win_sel_enum =
1473                 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL,
1474                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1475
1476 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
1477 static struct soc_enum const sub_comp_rat_enum =
1478                 SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO,
1479                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1480
1481 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
1482 static struct soc_enum const sub_exp_rat_enum =
1483                 SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO,
1484                                 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1485
1486 static int bytes_info_ext(struct snd_kcontrol *kcontrol,
1487         struct snd_ctl_elem_info *ucontrol)
1488 {
1489         struct coeff_ram_ctl *ctl =
1490                 (struct coeff_ram_ctl *)kcontrol->private_value;
1491         struct soc_bytes_ext *params = &ctl->bytes_ext;
1492
1493         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1494         ucontrol->count = params->max;
1495
1496         return 0;
1497 }
1498
1499 /* CH 0_1 Input Mux */
1500 static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"};
1501
1502 static struct soc_enum const ch_0_1_mux_enum =
1503                 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1504                                 ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt);
1505
1506 static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum =
1507                 SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum);
1508
1509 /* CH 2_3 Input Mux */
1510 static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"};
1511
1512 static struct soc_enum const ch_2_3_mux_enum =
1513                 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1514                                 ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt);
1515
1516 static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum =
1517                 SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum);
1518
1519 /* CH 4_5 Input Mux */
1520 static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"};
1521
1522 static struct soc_enum const ch_4_5_mux_enum =
1523                 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1524                                 ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt);
1525
1526 static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum =
1527                 SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum);
1528
1529 #define COEFF_RAM_CTL(xname, xcount, xaddr) \
1530 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1531         .info = bytes_info_ext, \
1532         .get = coeff_ram_get, .put = coeff_ram_put, \
1533         .private_value = (unsigned long)&(struct coeff_ram_ctl) { \
1534                 .addr = xaddr, \
1535                 .bytes_ext = {.max = xcount, }, \
1536         } \
1537 }
1538
1539 static struct snd_kcontrol_new const tscs454_snd_controls[] = {
1540         /* R_PLLCTL PG 0 ADDR 0x15 */
1541         SOC_ENUM("PLL BCLK Input", bclk_sel_enum),
1542         /* R_ISRC PG 0 ADDR 0x16 */
1543         SOC_ENUM("Internal Rate", isrc_br_enum),
1544         SOC_ENUM("Internal Rate Multiple", isrc_bm_enum),
1545         /* R_SCLKCTL PG 0 ADDR 0x18 */
1546         SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum),
1547         SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum),
1548         /* R_ASRC PG 0 ADDR 0x28 */
1549         SOC_SINGLE("ASRC Out High Bandwidth Switch",
1550                         R_ASRC, FB_ASRC_ASRCOBW, 1, 0),
1551         SOC_SINGLE("ASRC In High Bandwidth Switch",
1552                         R_ASRC, FB_ASRC_ASRCIBW, 1, 0),
1553         /* R_I2SIDCTL PG 0 ADDR 0x38 */
1554         SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]),
1555         SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]),
1556         SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]),
1557         /* R_I2SODCTL PG 0 ADDR 0x39 */
1558         SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]),
1559         SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]),
1560         SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]),
1561         /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
1562         SOC_ENUM("ASRC In", asrc_in_mux_enum),
1563         /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
1564         SOC_ENUM("ASRC Out", asrc_out_mux_enum),
1565         /* R_HSDCTL1 PG 1 ADDR 0x01 */
1566         SOC_ENUM("Headphone Jack Type", hp_jack_type_enum),
1567         SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum),
1568         SOC_SINGLE("Headphone Detection Switch",
1569                         R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0),
1570         SOC_SINGLE("Headset OMTP/CTIA Switch",
1571                         R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0),
1572         /* R_HSDCTL1 PG 1 ADDR 0x02 */
1573         SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum),
1574         SOC_SINGLE("Manual Mic Bias Switch",
1575                         R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0),
1576         SOC_SINGLE("Ring/Sleeve Auto Switch",
1577                         R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0),
1578         SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum),
1579         /* R_CH0AIC PG 1 ADDR 0x06 */
1580         SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC,
1581                         FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1582         /* R_CH1AIC PG 1 ADDR 0x07 */
1583         SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC,
1584                         FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1585         /* R_CH2AIC PG 1 ADDR 0x08 */
1586         SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC,
1587                         FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1588         /* R_CH3AIC PG 1 ADDR 0x09 */
1589         SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC,
1590                         FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1591         /* R_ICTL0 PG 1 ADDR 0x0A */
1592         SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum),
1593         SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum),
1594         SOC_ENUM("Input Processor Channel 0/1 Operation",
1595                         in_proc_ch01_sel_enum),
1596         SOC_SINGLE("Input Channel 1 Mute Switch",
1597                         R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0),
1598         SOC_SINGLE("Input Channel 0 Mute Switch",
1599                         R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0),
1600         SOC_SINGLE("Input Channel 1 HPF Disable Switch",
1601                         R_ICTL0, FB_ICTL0_IN1HP, 1, 0),
1602         SOC_SINGLE("Input Channel 0 HPF Disable Switch",
1603                         R_ICTL0, FB_ICTL0_IN0HP, 1, 0),
1604         /* R_ICTL1 PG 1 ADDR 0x0B */
1605         SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum),
1606         SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum),
1607         SOC_ENUM("Input Processor Channel 2/3 Operation",
1608                         in_proc_ch23_sel_enum),
1609         SOC_SINGLE("Input Channel 3 Mute Switch",
1610                         R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0),
1611         SOC_SINGLE("Input Channel 2 Mute Switch",
1612                         R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0),
1613         SOC_SINGLE("Input Channel 3 HPF Disable Switch",
1614                         R_ICTL1, FB_ICTL1_IN3HP, 1, 0),
1615         SOC_SINGLE("Input Channel 2 HPF Disable Switch",
1616                         R_ICTL1, FB_ICTL1_IN2HP, 1, 0),
1617         /* R_MICBIAS PG 1 ADDR 0x0C */
1618         SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum),
1619         SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum),
1620         /* R_PGACTL0 PG 1 ADDR 0x0D */
1621         SOC_SINGLE("Input Channel 0 PGA Mute Switch",
1622                         R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0),
1623         SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0,
1624                         FB_PGACTL_PGAVOL,
1625                         FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1626         /* R_PGACTL1 PG 1 ADDR 0x0E */
1627         SOC_SINGLE("Input Channel 1 PGA Mute Switch",
1628                         R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0),
1629         SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1,
1630                         FB_PGACTL_PGAVOL,
1631                         FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1632         /* R_PGACTL2 PG 1 ADDR 0x0F */
1633         SOC_SINGLE("Input Channel 2 PGA Mute Switch",
1634                         R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0),
1635         SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2,
1636                         FB_PGACTL_PGAVOL,
1637                         FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1638         /* R_PGACTL3 PG 1 ADDR 0x10 */
1639         SOC_SINGLE("Input Channel 3 PGA Mute Switch",
1640                         R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0),
1641         SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3,
1642                         FB_PGACTL_PGAVOL,
1643                         FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1644         /* R_ICH0VOL PG 1 ADDR 0x12 */
1645         SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL,
1646                         FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1647         /* R_ICH1VOL PG 1 ADDR 0x13 */
1648         SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL,
1649                         FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1650         /* R_ICH2VOL PG 1 ADDR 0x14 */
1651         SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL,
1652                         FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1653         /* R_ICH3VOL PG 1 ADDR 0x15 */
1654         SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL,
1655                         FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1656         /* R_ASRCILVOL PG 1 ADDR 0x16 */
1657         SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL,
1658                         FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL,
1659                         0, asrc_vol_tlv_arr),
1660         /* R_ASRCIRVOL PG 1 ADDR 0x17 */
1661         SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL,
1662                         FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL,
1663                         0, asrc_vol_tlv_arr),
1664         /* R_ASRCOLVOL PG 1 ADDR 0x18 */
1665         SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL,
1666                         FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL,
1667                         0, asrc_vol_tlv_arr),
1668         /* R_ASRCORVOL PG 1 ADDR 0x19 */
1669         SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL,
1670                         FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL,
1671                         0, asrc_vol_tlv_arr),
1672         /* R_IVOLCTLU PG 1 ADDR 0x1C */
1673         /* R_ALCCTL0 PG 1 ADDR 0x1D */
1674         SOC_ENUM("ALC Mode", alc_mode_enum),
1675         SOC_ENUM("ALC Reference", alc_ref_enum),
1676         SOC_SINGLE("Input Channel 3 ALC Switch",
1677                         R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0),
1678         SOC_SINGLE("Input Channel 2 ALC Switch",
1679                         R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0),
1680         SOC_SINGLE("Input Channel 1 ALC Switch",
1681                         R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0),
1682         SOC_SINGLE("Input Channel 0 ALC Switch",
1683                         R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0),
1684         /* R_ALCCTL1 PG 1 ADDR 0x1E */
1685         SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1,
1686                         FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN,
1687                         0, alc_max_gain_tlv_arr),
1688         SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1,
1689                         FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL,
1690                         0, alc_target_tlv_arr),
1691         /* R_ALCCTL2 PG 1 ADDR 0x1F */
1692         SOC_SINGLE("ALC Zero Cross Switch",
1693                         R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0),
1694         SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2,
1695                         FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN,
1696                         0, alc_min_gain_tlv_arr),
1697         SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2,
1698                         FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0),
1699         /* R_ALCCTL3 PG 1 ADDR 0x20 */
1700         SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3,
1701                         FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0),
1702         SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3,
1703                         FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0),
1704         /* R_NGATE PG 1 ADDR 0x21 */
1705         SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE,
1706                         FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr),
1707         SOC_ENUM("Noise Gate Type", ngate_type_enum),
1708         SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0),
1709         /* R_DMICCTL PG 1 ADDR 0x22 */
1710         SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0),
1711         SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0),
1712         SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum),
1713         /* R_DACCTL PG 2 ADDR 0x01 */
1714         SOC_ENUM("DAC Polarity Left", dac_pol_r_enum),
1715         SOC_ENUM("DAC Polarity Right", dac_pol_l_enum),
1716         SOC_ENUM("DAC Dither", dac_dith_enum),
1717         SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0),
1718         SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1719         /* R_SPKCTL PG 2 ADDR 0x02 */
1720         SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum),
1721         SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum),
1722         SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0),
1723         SOC_SINGLE("Speaker De-Emphasis Switch",
1724                         R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0),
1725         /* R_SUBCTL PG 2 ADDR 0x03 */
1726         SOC_ENUM("Sub Polarity", sub_pol_enum),
1727         SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
1728         SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1729         /* R_DCCTL PG 2 ADDR 0x04 */
1730         SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
1731         SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1),
1732         SOC_SINGLE("Speaker DC Removal Switch",
1733                         R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1),
1734         SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL,
1735                         FM_DCCTL_DCCOEFSEL, 0),
1736         /* R_OVOLCTLU PG 2 ADDR 0x06 */
1737         SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0),
1738         /* R_MVOLL PG 2 ADDR 0x08 */
1739         /* R_MVOLR PG 2 ADDR 0x09 */
1740         SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR,
1741                         FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr),
1742         /* R_HPVOLL PG 2 ADDR 0x0A */
1743         /* R_HPVOLR PG 2 ADDR 0x0B */
1744         SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
1745                         FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0,
1746                         hp_vol_tlv_arr),
1747         /* R_SPKVOLL PG 2 ADDR 0x0C */
1748         /* R_SPKVOLR PG 2 ADDR 0x0D */
1749         SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
1750                         FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0,
1751                         spk_vol_tlv_arr),
1752         /* R_SUBVOL PG 2 ADDR 0x10 */
1753         SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
1754                         FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr),
1755         /* R_SPKEQFILT PG 3 ADDR 0x01 */
1756         SOC_SINGLE("Speaker EQ 2 Switch",
1757                         R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0),
1758         SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]),
1759         SOC_SINGLE("Speaker EQ 1 Switch",
1760                         R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0),
1761         SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]),
1762         /* R_SPKMBCEN PG 3 ADDR 0x0A */
1763         SOC_SINGLE("Speaker MBC 3 Switch",
1764                         R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0),
1765         SOC_SINGLE("Speaker MBC 2 Switch",
1766                         R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0),
1767         SOC_SINGLE("Speaker MBC 1 Switch",
1768                         R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0),
1769         /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1770         SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum),
1771         SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum),
1772         SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum),
1773         SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum),
1774         SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum),
1775         SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum),
1776         /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1777         SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum),
1778         SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1779                         FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1780                         0, mbc_mug_tlv_arr),
1781         /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1782         SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume",
1783                         R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1784                         0, thr_tlv_arr),
1785         /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1786         SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum),
1787         /* R_SPKMBCATK1L PG 3 ADDR 0x0F */
1788         /* R_SPKMBCATK1H PG 3 ADDR 0x10 */
1789         SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2),
1790         /* R_SPKMBCREL1L PG 3 ADDR 0x11 */
1791         /* R_SPKMBCREL1H PG 3 ADDR 0x12 */
1792         SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2),
1793         /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1794         SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum),
1795         SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1796                         FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1797                         0, mbc_mug_tlv_arr),
1798         /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */
1799         SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume",
1800                         R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1801                         0, thr_tlv_arr),
1802         /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1803         SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum),
1804         /* R_SPKMBCATK2L PG 3 ADDR 0x16 */
1805         /* R_SPKMBCATK2H PG 3 ADDR 0x17 */
1806         SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2),
1807         /* R_SPKMBCREL2L PG 3 ADDR 0x18 */
1808         /* R_SPKMBCREL2H PG 3 ADDR 0x19 */
1809         SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2),
1810         /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1811         SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum),
1812         SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1813                         FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1814                         0, mbc_mug_tlv_arr),
1815         /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */
1816         SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3,
1817                         FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1818                         0, thr_tlv_arr),
1819         /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1820         SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum),
1821         /* R_SPKMBCATK3L PG 3 ADDR 0x1D */
1822         /* R_SPKMBCATK3H PG 3 ADDR 0x1E */
1823         SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3),
1824         /* R_SPKMBCREL3L PG 3 ADDR 0x1F */
1825         /* R_SPKMBCREL3H PG 3 ADDR 0x20 */
1826         SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3),
1827         /* R_SPKCLECTL PG 3 ADDR 0x21 */
1828         SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum),
1829         SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum),
1830         SOC_SINGLE("Speaker CLE Expander Switch",
1831                         R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0),
1832         SOC_SINGLE("Speaker CLE Limiter Switch",
1833                         R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0),
1834         SOC_SINGLE("Speaker CLE Compressor Switch",
1835                         R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0),
1836         /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1837         SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1838                         FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN,
1839                         0, cle_mug_tlv_arr),
1840         /* R_SPKCOMPTHR PG 3 ADDR 0x23 */
1841         SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR,
1842                         FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH,
1843                         0, thr_tlv_arr),
1844         /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1845         SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum),
1846         /* R_SPKCOMPATKL PG 3 ADDR 0x25 */
1847         /* R_SPKCOMPATKH PG 3 ADDR 0x26 */
1848         SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2),
1849         /* R_SPKCOMPRELL PG 3 ADDR 0x27 */
1850         /* R_SPKCOMPRELH PG 3 ADDR 0x28 */
1851         SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2),
1852         /* R_SPKLIMTHR PG 3 ADDR 0x29 */
1853         SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR,
1854                         FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH,
1855                         0, thr_tlv_arr),
1856         /* R_SPKLIMTGT PG 3 ADDR 0x2A */
1857         SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT,
1858                         FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET,
1859                         0, thr_tlv_arr),
1860         /* R_SPKLIMATKL PG 3 ADDR 0x2B */
1861         /* R_SPKLIMATKH PG 3 ADDR 0x2C */
1862         SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2),
1863         /* R_SPKLIMRELL PG 3 ADDR 0x2D */
1864         /* R_SPKLIMRELR PG 3 ADDR 0x2E */
1865         SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2),
1866         /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1867         SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR,
1868                         FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH,
1869                         0, thr_tlv_arr),
1870         /* R_SPKEXPRAT PG 3 ADDR 0x30 */
1871         SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum),
1872         /* R_SPKEXPATKL PG 3 ADDR 0x31 */
1873         /* R_SPKEXPATKR PG 3 ADDR 0x32 */
1874         SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2),
1875         /* R_SPKEXPRELL PG 3 ADDR 0x33 */
1876         /* R_SPKEXPRELR PG 3 ADDR 0x34 */
1877         SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2),
1878         /* R_SPKFXCTL PG 3 ADDR 0x35 */
1879         SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0),
1880         SOC_SINGLE("Speaker Treble Enhancement Switch",
1881                         R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0),
1882         SOC_SINGLE("Speaker Treble NLF Switch",
1883                         R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1),
1884         SOC_SINGLE("Speaker Bass Enhancement Switch",
1885                         R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0),
1886         SOC_SINGLE("Speaker Bass NLF Switch",
1887                         R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1),
1888         /* R_DACEQFILT PG 4 ADDR 0x01 */
1889         SOC_SINGLE("DAC EQ 2 Switch",
1890                         R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0),
1891         SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]),
1892         SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0),
1893         SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]),
1894         /* R_DACMBCEN PG 4 ADDR 0x0A */
1895         SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
1896         SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
1897         SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
1898         /* R_DACMBCCTL PG 4 ADDR 0x0B */
1899         SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum),
1900         SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum),
1901         SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum),
1902         SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum),
1903         SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum),
1904         SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum),
1905         /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1906         SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum),
1907         SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1908                         FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1909                         0, mbc_mug_tlv_arr),
1910         /* R_DACMBCTHR1 PG 4 ADDR 0x0D */
1911         SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1,
1912                         FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1913                         0, thr_tlv_arr),
1914         /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1915         SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum),
1916         /* R_DACMBCATK1L PG 4 ADDR 0x0F */
1917         /* R_DACMBCATK1H PG 4 ADDR 0x10 */
1918         SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2),
1919         /* R_DACMBCREL1L PG 4 ADDR 0x11 */
1920         /* R_DACMBCREL1H PG 4 ADDR 0x12 */
1921         SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2),
1922         /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1923         SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum),
1924         SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1925                         FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1926                         0, mbc_mug_tlv_arr),
1927         /* R_DACMBCTHR2 PG 4 ADDR 0x14 */
1928         SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2,
1929                         FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1930                         0, thr_tlv_arr),
1931         /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1932         SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum),
1933         /* R_DACMBCATK2L PG 4 ADDR 0x16 */
1934         /* R_DACMBCATK2H PG 4 ADDR 0x17 */
1935         SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2),
1936         /* R_DACMBCREL2L PG 4 ADDR 0x18 */
1937         /* R_DACMBCREL2H PG 4 ADDR 0x19 */
1938         SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2),
1939         /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1940         SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum),
1941         SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1942                         FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1943                         0, mbc_mug_tlv_arr),
1944         /* R_DACMBCTHR3 PG 4 ADDR 0x1B */
1945         SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3,
1946                         FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1947                         0, thr_tlv_arr),
1948         /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1949         SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum),
1950         /* R_DACMBCATK3L PG 4 ADDR 0x1D */
1951         /* R_DACMBCATK3H PG 4 ADDR 0x1E */
1952         SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3),
1953         /* R_DACMBCREL3L PG 4 ADDR 0x1F */
1954         /* R_DACMBCREL3H PG 4 ADDR 0x20 */
1955         SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3),
1956         /* R_DACCLECTL PG 4 ADDR 0x21 */
1957         SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum),
1958         SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum),
1959         SOC_SINGLE("DAC CLE Expander Switch",
1960                         R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0),
1961         SOC_SINGLE("DAC CLE Limiter Switch",
1962                         R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0),
1963         SOC_SINGLE("DAC CLE Compressor Switch",
1964                         R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0),
1965         /* R_DACCLEMUG PG 4 ADDR 0x22 */
1966         SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
1967                         FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN,
1968                         0, cle_mug_tlv_arr),
1969         /* R_DACCOMPTHR PG 4 ADDR 0x23 */
1970         SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR,
1971                         FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH,
1972                         0, thr_tlv_arr),
1973         /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1974         SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum),
1975         /* R_DACCOMPATKL PG 4 ADDR 0x25 */
1976         /* R_DACCOMPATKH PG 4 ADDR 0x26 */
1977         SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2),
1978         /* R_DACCOMPRELL PG 4 ADDR 0x27 */
1979         /* R_DACCOMPRELH PG 4 ADDR 0x28 */
1980         SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2),
1981         /* R_DACLIMTHR PG 4 ADDR 0x29 */
1982         SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR,
1983                         FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH,
1984                         0, thr_tlv_arr),
1985         /* R_DACLIMTGT PG 4 ADDR 0x2A */
1986         SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT,
1987                         FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET,
1988                         0, thr_tlv_arr),
1989         /* R_DACLIMATKL PG 4 ADDR 0x2B */
1990         /* R_DACLIMATKH PG 4 ADDR 0x2C */
1991         SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2),
1992         /* R_DACLIMRELL PG 4 ADDR 0x2D */
1993         /* R_DACLIMRELR PG 4 ADDR 0x2E */
1994         SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2),
1995         /* R_DACEXPTHR PG 4 ADDR 0x2F */
1996         SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR,
1997                         FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH,
1998                         0, thr_tlv_arr),
1999         /* R_DACEXPRAT PG 4 ADDR 0x30 */
2000         SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum),
2001         /* R_DACEXPATKL PG 4 ADDR 0x31 */
2002         /* R_DACEXPATKR PG 4 ADDR 0x32 */
2003         SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2),
2004         /* R_DACEXPRELL PG 4 ADDR 0x33 */
2005         /* R_DACEXPRELR PG 4 ADDR 0x34 */
2006         SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2),
2007         /* R_DACFXCTL PG 4 ADDR 0x35 */
2008         SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0),
2009         SOC_SINGLE("DAC Treble Enhancement Switch",
2010                         R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0),
2011         SOC_SINGLE("DAC Treble NLF Switch",
2012                         R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1),
2013         SOC_SINGLE("DAC Bass Enhancement Switch",
2014                         R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0),
2015         SOC_SINGLE("DAC Bass NLF Switch",
2016                         R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1),
2017         /* R_SUBEQFILT PG 5 ADDR 0x01 */
2018         SOC_SINGLE("Sub EQ 2 Switch",
2019                         R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0),
2020         SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
2021         SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
2022         SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
2023         /* R_SUBMBCEN PG 5 ADDR 0x0A */
2024         SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
2025         SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
2026         SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
2027         /* R_SUBMBCCTL PG 5 ADDR 0x0B */
2028         SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
2029         SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
2030         SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
2031         SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
2032         SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
2033         SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
2034         /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
2035         SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
2036         SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2037                         FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2038                         0, mbc_mug_tlv_arr),
2039         /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */
2040         SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
2041                         FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2042                         0, thr_tlv_arr),
2043         /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
2044         SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
2045         /* R_SUBMBCATK1L PG 5 ADDR 0x0F */
2046         /* R_SUBMBCATK1H PG 5 ADDR 0x10 */
2047         SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
2048         /* R_SUBMBCREL1L PG 5 ADDR 0x11 */
2049         /* R_SUBMBCREL1H PG 5 ADDR 0x12 */
2050         SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
2051         /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
2052         SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
2053         SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2054                         FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2055                         0, mbc_mug_tlv_arr),
2056         /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */
2057         SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
2058                         FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2059                         0, thr_tlv_arr),
2060         /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
2061         SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
2062         /* R_SUBMBCATK2L PG 5 ADDR 0x16 */
2063         /* R_SUBMBCATK2H PG 5 ADDR 0x17 */
2064         SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
2065         /* R_SUBMBCREL2L PG 5 ADDR 0x18 */
2066         /* R_SUBMBCREL2H PG 5 ADDR 0x19 */
2067         SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
2068         /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
2069         SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
2070         SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2071                         FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2072                         0, mbc_mug_tlv_arr),
2073         /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */
2074         SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
2075                         FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2076                         0, thr_tlv_arr),
2077         /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
2078         SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
2079         /* R_SUBMBCATK3L PG 5 ADDR 0x1D */
2080         /* R_SUBMBCATK3H PG 5 ADDR 0x1E */
2081         SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
2082         /* R_SUBMBCREL3L PG 5 ADDR 0x1F */
2083         /* R_SUBMBCREL3H PG 5 ADDR 0x20 */
2084         SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
2085         /* R_SUBCLECTL PG 5 ADDR 0x21 */
2086         SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
2087         SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
2088         SOC_SINGLE("Sub CLE Expander Switch",
2089                         R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0),
2090         SOC_SINGLE("Sub CLE Limiter Switch",
2091                         R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0),
2092         SOC_SINGLE("Sub CLE Compressor Switch",
2093                         R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0),
2094         /* R_SUBCLEMUG PG 5 ADDR 0x22 */
2095         SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2096                         FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN,
2097                         0, cle_mug_tlv_arr),
2098         /* R_SUBCOMPTHR PG 5 ADDR 0x23 */
2099         SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
2100                         FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH,
2101                         0, thr_tlv_arr),
2102         /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
2103         SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
2104         /* R_SUBCOMPATKL PG 5 ADDR 0x25 */
2105         /* R_SUBCOMPATKH PG 5 ADDR 0x26 */
2106         SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
2107         /* R_SUBCOMPRELL PG 5 ADDR 0x27 */
2108         /* R_SUBCOMPRELH PG 5 ADDR 0x28 */
2109         SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
2110         /* R_SUBLIMTHR PG 5 ADDR 0x29 */
2111         SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
2112                         FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH,
2113                         0, thr_tlv_arr),
2114         /* R_SUBLIMTGT PG 5 ADDR 0x2A */
2115         SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
2116                         FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET,
2117                         0, thr_tlv_arr),
2118         /* R_SUBLIMATKL PG 5 ADDR 0x2B */
2119         /* R_SUBLIMATKH PG 5 ADDR 0x2C */
2120         SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
2121         /* R_SUBLIMRELL PG 5 ADDR 0x2D */
2122         /* R_SUBLIMRELR PG 5 ADDR 0x2E */
2123         SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
2124         /* R_SUBEXPTHR PG 5 ADDR 0x2F */
2125         SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
2126                         FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH,
2127                         0, thr_tlv_arr),
2128         /* R_SUBEXPRAT PG 5 ADDR 0x30 */
2129         SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
2130         /* R_SUBEXPATKL PG 5 ADDR 0x31 */
2131         /* R_SUBEXPATKR PG 5 ADDR 0x32 */
2132         SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
2133         /* R_SUBEXPRELL PG 5 ADDR 0x33 */
2134         /* R_SUBEXPRELR PG 5 ADDR 0x34 */
2135         SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
2136         /* R_SUBFXCTL PG 5 ADDR 0x35 */
2137         SOC_SINGLE("Sub Treble Enhancement Switch",
2138                         R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0),
2139         SOC_SINGLE("Sub Treble NLF Switch",
2140                         R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1),
2141         SOC_SINGLE("Sub Bass Enhancement Switch",
2142                         R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0),
2143         SOC_SINGLE("Sub Bass NLF Switch",
2144                         R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1),
2145         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2146         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2147         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2148         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2149         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2150         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2151
2152         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2153         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2154         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2155         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2156         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2157         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2158
2159         COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2160         COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2161
2162         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2163         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2164         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2165         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2166         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2167         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2168
2169         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2170         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2171         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2172         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2173         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2174         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2175
2176         COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2177         COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2178
2179         COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2180         COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2181
2182         COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2183         COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2184
2185         COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2186
2187         COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2188
2189         COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96),
2190
2191         COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2192         COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2193
2194         COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2195         COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2196
2197         COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2198
2199         COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2200
2201         COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad),
2202
2203         COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae),
2204
2205         COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf),
2206
2207         COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2208         COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2209
2210         COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2211         COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2212
2213         COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2214         COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2215
2216         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2217         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2218         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2219         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2220         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2221         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2222
2223         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2224         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2225         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2226         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2227         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2228         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2229
2230         COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2231         COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2232
2233         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2234         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2235         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2236         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2237         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2238         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2239
2240         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2241         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2242         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2243         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2244         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2245         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2246
2247         COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2248         COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2249
2250         COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2251         COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2252
2253         COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2254         COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2255
2256         COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2257
2258         COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2259
2260         COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96),
2261
2262         COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2263         COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2264
2265         COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2266         COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2267
2268         COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2269
2270         COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2271
2272         COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad),
2273
2274         COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae),
2275
2276         COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf),
2277
2278         COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2279         COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2280
2281         COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2282         COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2283
2284         COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2285         COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2286
2287         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2288         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2289         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2290         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2291         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2292         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2293
2294         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2295         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2296         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2297         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2298         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2299         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2300
2301         COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2302         COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2303
2304         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2305         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2306         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2307         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2308         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2309         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2310
2311         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2312         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2313         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2314         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2315         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2316         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2317
2318         COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2319         COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2320
2321         COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2322         COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2323
2324         COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2325         COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2326
2327         COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2328
2329         COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2330
2331         COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
2332
2333         COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2334         COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2335
2336         COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2337         COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2338
2339         COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2340
2341         COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2342
2343         COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
2344
2345         COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
2346
2347         COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
2348
2349         COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2350         COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2351
2352         COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2353         COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2354
2355         COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2356         COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2357 };
2358
2359 static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = {
2360         /* R_PLLCTL PG 0 ADDR 0x15 */
2361         SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0,
2362                         pll_power_event,
2363                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2364         SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0,
2365                         pll_power_event,
2366                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2367         /* R_I2SPINC0 PG 0 ADDR 0x22 */
2368         SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0,
2369                         R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1),
2370         SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0,
2371                         R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1),
2372         SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0,
2373                         R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1),
2374         /* R_PWRM0 PG 0 ADDR 0x33 */
2375         SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
2376                         R_PWRM0, FB_PWRM0_INPROC3PU, 0),
2377         SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
2378                         R_PWRM0, FB_PWRM0_INPROC2PU, 0),
2379         SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
2380                         R_PWRM0, FB_PWRM0_INPROC1PU, 0),
2381         SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
2382                         R_PWRM0, FB_PWRM0_INPROC0PU, 0),
2383         SND_SOC_DAPM_SUPPLY("Mic Bias 2",
2384                         R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0),
2385         SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0,
2386                         FB_PWRM0_MICB1PU, 0, NULL, 0),
2387         /* R_PWRM1 PG 0 ADDR 0x34 */
2388         SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
2389         SND_SOC_DAPM_SUPPLY("Headphone Left Power",
2390                         R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0),
2391         SND_SOC_DAPM_SUPPLY("Headphone Right Power",
2392                         R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0),
2393         SND_SOC_DAPM_SUPPLY("Speaker Left Power",
2394                         R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0),
2395         SND_SOC_DAPM_SUPPLY("Speaker Right Power",
2396                         R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0),
2397         SND_SOC_DAPM_SUPPLY("Differential Input 2 Power",
2398                         R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0),
2399         SND_SOC_DAPM_SUPPLY("Differential Input 1 Power",
2400                         R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0),
2401         /* R_PWRM2 PG 0 ADDR 0x35 */
2402         SND_SOC_DAPM_SUPPLY("DAI 3 Out Power",
2403                         R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0),
2404         SND_SOC_DAPM_SUPPLY("DAI 2 Out Power",
2405                         R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0),
2406         SND_SOC_DAPM_SUPPLY("DAI 1 Out Power",
2407                         R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0),
2408         SND_SOC_DAPM_SUPPLY("DAI 3 In Power",
2409                         R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0),
2410         SND_SOC_DAPM_SUPPLY("DAI 2 In Power",
2411                         R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0),
2412         SND_SOC_DAPM_SUPPLY("DAI 1 In Power",
2413                         R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0),
2414         /* R_PWRM3 PG 0 ADDR 0x36 */
2415         SND_SOC_DAPM_SUPPLY("Line Out Left Power",
2416                         R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0),
2417         SND_SOC_DAPM_SUPPLY("Line Out Right Power",
2418                         R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0),
2419         /* R_PWRM4 PG 0 ADDR 0x37 */
2420         SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
2421         SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0),
2422         SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0),
2423         SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0),
2424         SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0),
2425         /* R_AUDIOMUX1  PG 0 ADDR 0x3A */
2426         SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0,
2427                         &dai2_mux_dapm_enum),
2428         SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0,
2429                         &dai1_mux_dapm_enum),
2430         /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
2431         SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
2432                         &dac_mux_dapm_enum),
2433         SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0,
2434                         &dai3_mux_dapm_enum),
2435         /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
2436         SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
2437                         &sub_mux_dapm_enum),
2438         SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
2439                         &classd_mux_dapm_enum),
2440         /* R_HSDCTL1 PG 1 ADDR 0x01 */
2441         SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1,
2442                         FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0),
2443         /* R_CH0AIC PG 1 ADDR 0x06 */
2444         SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2445                         &in_bst_mux_ch0_dapm_enum),
2446         SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2447                         &adc_mux_ch0_dapm_enum),
2448         SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2449                         &in_proc_mux_ch0_dapm_enum),
2450         /* R_CH1AIC PG 1 ADDR 0x07 */
2451         SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2452                         &in_bst_mux_ch1_dapm_enum),
2453         SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2454                         &adc_mux_ch1_dapm_enum),
2455         SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2456                         &in_proc_mux_ch1_dapm_enum),
2457         /* Virtual */
2458         SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0,
2459                         SND_SOC_NOPM, 0, 0),
2460         SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0,
2461                         SND_SOC_NOPM, 0, 0),
2462         SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0,
2463                         SND_SOC_NOPM, 0, 0),
2464         SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0),
2465         SND_SOC_DAPM_OUTPUT("Sub Out"),
2466         SND_SOC_DAPM_OUTPUT("Headphone Left"),
2467         SND_SOC_DAPM_OUTPUT("Headphone Right"),
2468         SND_SOC_DAPM_OUTPUT("Speaker Left"),
2469         SND_SOC_DAPM_OUTPUT("Speaker Right"),
2470         SND_SOC_DAPM_OUTPUT("Line Out Left"),
2471         SND_SOC_DAPM_OUTPUT("Line Out Right"),
2472         SND_SOC_DAPM_INPUT("D2S 2"),
2473         SND_SOC_DAPM_INPUT("D2S 1"),
2474         SND_SOC_DAPM_INPUT("Line In 1 Left"),
2475         SND_SOC_DAPM_INPUT("Line In 1 Right"),
2476         SND_SOC_DAPM_INPUT("Line In 2 Left"),
2477         SND_SOC_DAPM_INPUT("Line In 2 Right"),
2478         SND_SOC_DAPM_INPUT("Line In 3 Left"),
2479         SND_SOC_DAPM_INPUT("Line In 3 Right"),
2480         SND_SOC_DAPM_INPUT("DMic 1"),
2481         SND_SOC_DAPM_INPUT("DMic 2"),
2482
2483         SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0,
2484                         &ch_0_1_mux_dapm_enum),
2485         SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0,
2486                         &ch_2_3_mux_dapm_enum),
2487         SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0,
2488                         &ch_4_5_mux_dapm_enum),
2489 };
2490
2491 static struct snd_soc_dapm_route const tscs454_intercon[] = {
2492         /* PLLs */
2493         {"PLLs", NULL, "PLL 1 Power", pll_connected},
2494         {"PLLs", NULL, "PLL 2 Power", pll_connected},
2495         /* Inputs */
2496         {"DAI 3 In", NULL, "DAI 3 In Power"},
2497         {"DAI 2 In", NULL, "DAI 2 In Power"},
2498         {"DAI 1 In", NULL, "DAI 1 In Power"},
2499         /* Outputs */
2500         {"DAI 3 Out", NULL, "DAI 3 Out Power"},
2501         {"DAI 2 Out", NULL, "DAI 2 Out Power"},
2502         {"DAI 1 Out", NULL, "DAI 1 Out Power"},
2503         /* Ch Muxing */
2504         {"CH 0_1 Mux", "DAI 1", "DAI 1 In"},
2505         {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"},
2506         {"CH 2_3 Mux", "DAI 2", "DAI 2 In"},
2507         {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"},
2508         {"CH 4_5 Mux", "DAI 3", "DAI 2 In"},
2509         {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"},
2510         /* In/Out Muxing */
2511         {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2512         {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2513         {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2514         {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2515         {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2516         {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2517         {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2518         {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2519         {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2520         /******************
2521          * Playback Paths *
2522          ******************/
2523         /* DAC Path */
2524         {"DAC Mux", "CH 4_5", "CH 4_5 Mux"},
2525         {"DAC Mux", "CH 2_3", "CH 2_3 Mux"},
2526         {"DAC Mux", "CH 0_1", "CH 0_1 Mux"},
2527         {"DAC Left", NULL, "DAC Mux"},
2528         {"DAC Right", NULL, "DAC Mux"},
2529         {"DAC Left", NULL, "PLLs"},
2530         {"DAC Right", NULL, "PLLs"},
2531         {"Headphone Left", NULL, "Headphone Left Power"},
2532         {"Headphone Right", NULL, "Headphone Right Power"},
2533         {"Headphone Left", NULL, "DAC Left"},
2534         {"Headphone Right", NULL, "DAC Right"},
2535         /* Line Out */
2536         {"Line Out Left", NULL, "Line Out Left Power"},
2537         {"Line Out Right", NULL, "Line Out Right Power"},
2538         {"Line Out Left", NULL, "DAC Left"},
2539         {"Line Out Right", NULL, "DAC Right"},
2540         /* ClassD Path */
2541         {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"},
2542         {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"},
2543         {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"},
2544         {"ClassD Left", NULL, "Speaker Mux"},
2545         {"ClassD Right", NULL, "Speaker Mux"},
2546         {"ClassD Left", NULL, "PLLs"},
2547         {"ClassD Right", NULL, "PLLs"},
2548         {"Speaker Left", NULL, "Speaker Left Power"},
2549         {"Speaker Right", NULL, "Speaker Right Power"},
2550         {"Speaker Left", NULL, "ClassD Left"},
2551         {"Speaker Right", NULL, "ClassD Right"},
2552         /* Sub Path */
2553         {"Sub Mux", "CH 4", "CH 4_5 Mux"},
2554         {"Sub Mux", "CH 5", "CH 4_5 Mux"},
2555         {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
2556         {"Sub Mux", "CH 2", "CH 2_3 Mux"},
2557         {"Sub Mux", "CH 3", "CH 2_3 Mux"},
2558         {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
2559         {"Sub Mux", "CH 0", "CH 0_1 Mux"},
2560         {"Sub Mux", "CH 1", "CH 0_1 Mux"},
2561         {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
2562         {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
2563         {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
2564         {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
2565         {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
2566         {"Sub Mux", "DMic 2 Left", "DMic 2"},
2567         {"Sub Mux", "DMic 2 Right", "DMic 2"},
2568         {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
2569         {"Sub Mux", "ClassD Left", "ClassD Left"},
2570         {"Sub Mux", "ClassD Right", "ClassD Right"},
2571         {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
2572         {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
2573         {"Sub", NULL, "Sub Mux"},
2574         {"Sub", NULL, "PLLs"},
2575         {"Sub Out", NULL, "Sub Power"},
2576         {"Sub Out", NULL, "Sub"},
2577         /*****************
2578          * Capture Paths *
2579          *****************/
2580         {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"},
2581         {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"},
2582         {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"},
2583         {"Input Boost Channel 0 Mux", "D2S", "D2S 1"},
2584
2585         {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"},
2586         {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"},
2587         {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"},
2588         {"Input Boost Channel 1 Mux", "D2S", "D2S 2"},
2589
2590         {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"},
2591         {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"},
2592         {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"},
2593         {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"},
2594
2595         {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"},
2596         {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"},
2597         {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"},
2598         {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"},
2599
2600         {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
2601         {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
2602
2603         {"Input Processor Channel 0", NULL, "PLLs"},
2604         {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
2605
2606         {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
2607         {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
2608
2609         {"Input Processor Channel 1", NULL, "PLLs"},
2610         {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
2611
2612         {"Input Processor Channel 2", NULL, "PLLs"},
2613         {"Input Processor Channel 2", NULL, "DMic 2"},
2614
2615         {"Input Processor Channel 3", NULL, "PLLs"},
2616         {"Input Processor Channel 3", NULL, "DMic 2"},
2617
2618         {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2619         {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2620         {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
2621         {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
2622
2623         {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2624         {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2625         {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
2626         {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
2627
2628         {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2629         {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2630         {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
2631         {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
2632
2633         {"DAI 1 Out", NULL, "DAI 1 Out Mux"},
2634         {"DAI 2 Out", NULL, "DAI 2 Out Mux"},
2635         {"DAI 3 Out", NULL, "DAI 3 Out Mux"},
2636 };
2637
2638 /* This is used when BCLK is sourcing the PLLs */
2639 static int tscs454_set_sysclk(struct snd_soc_dai *dai,
2640                 int clk_id, unsigned int freq, int dir)
2641 {
2642         struct snd_soc_component *component = dai->component;
2643         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2644         unsigned int val;
2645         int bclk_dai;
2646         int ret;
2647
2648         dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq);
2649
2650         ret = snd_soc_component_read(component, R_PLLCTL, &val);
2651         if (ret < 0)
2652                 return ret;
2653
2654         bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL;
2655         if (bclk_dai != dai->id)
2656                 return 0;
2657
2658         tscs454->bclk_freq = freq;
2659         return set_sysclk(component);
2660 }
2661
2662 static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai,
2663                 unsigned int ratio)
2664 {
2665         unsigned int mask;
2666         int ret;
2667         struct snd_soc_component *component = dai->component;
2668         unsigned int val;
2669         int shift;
2670
2671         dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n",
2672                         dai->id, ratio);
2673
2674         switch (dai->id) {
2675         case TSCS454_DAI1_ID:
2676                 mask = FM_I2SCMC_BCMP1;
2677                 shift = FB_I2SCMC_BCMP1;
2678                 break;
2679         case TSCS454_DAI2_ID:
2680                 mask = FM_I2SCMC_BCMP2;
2681                 shift = FB_I2SCMC_BCMP2;
2682                 break;
2683         case TSCS454_DAI3_ID:
2684                 mask = FM_I2SCMC_BCMP3;
2685                 shift = FB_I2SCMC_BCMP3;
2686                 break;
2687         default:
2688                 ret = -EINVAL;
2689                 dev_err(component->dev, "Unknown audio interface (%d)\n", ret);
2690                 return ret;
2691         }
2692
2693         switch (ratio) {
2694         case 32:
2695                 val = I2SCMC_BCMP_32X;
2696                 break;
2697         case 40:
2698                 val = I2SCMC_BCMP_40X;
2699                 break;
2700         case 64:
2701                 val = I2SCMC_BCMP_64X;
2702                 break;
2703         default:
2704                 ret = -EINVAL;
2705                 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
2706                 return ret;
2707         }
2708
2709         ret = snd_soc_component_update_bits(component,
2710                         R_I2SCMC, mask, val << shift);
2711         if (ret < 0) {
2712                 dev_err(component->dev,
2713                                 "Failed to set DAI BCLK ratio (%d)\n", ret);
2714                 return ret;
2715         }
2716
2717         return 0;
2718 }
2719
2720 static inline int set_aif_master_from_fmt(struct snd_soc_component *component,
2721                 struct aif *aif, unsigned int fmt)
2722 {
2723         int ret;
2724
2725         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2726         case SND_SOC_DAIFMT_CBM_CFM:
2727                 aif->master = true;
2728                 break;
2729         case SND_SOC_DAIFMT_CBS_CFS:
2730                 aif->master = false;
2731                 break;
2732         default:
2733                 ret = -EINVAL;
2734                 dev_err(component->dev, "Unsupported format (%d)\n", ret);
2735                 return ret;
2736         }
2737
2738         return 0;
2739 }
2740
2741 static inline int set_aif_tdm_delay(struct snd_soc_component *component,
2742                 unsigned int dai_id, bool delay)
2743 {
2744         unsigned int reg;
2745         int ret;
2746
2747         switch (dai_id) {
2748         case TSCS454_DAI1_ID:
2749                 reg = R_TDMCTL0;
2750                 break;
2751         case TSCS454_DAI2_ID:
2752                 reg = R_PCMP2CTL0;
2753                 break;
2754         case TSCS454_DAI3_ID:
2755                 reg = R_PCMP3CTL0;
2756                 break;
2757         default:
2758                 ret = -EINVAL;
2759                 dev_err(component->dev,
2760                                 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2761                 return ret;
2762         }
2763         ret = snd_soc_component_update_bits(component,
2764                         reg, FM_TDMCTL0_BDELAY, delay);
2765         if (ret < 0) {
2766                 dev_err(component->dev, "Failed to setup tdm format (%d)\n",
2767                                 ret);
2768                 return ret;
2769         }
2770
2771         return 0;
2772 }
2773
2774 static inline int set_aif_format_from_fmt(struct snd_soc_component *component,
2775                 unsigned int dai_id, unsigned int fmt)
2776 {
2777         unsigned int reg;
2778         unsigned int val;
2779         int ret;
2780
2781         switch (dai_id) {
2782         case TSCS454_DAI1_ID:
2783                 reg = R_I2SP1CTL;
2784                 break;
2785         case TSCS454_DAI2_ID:
2786                 reg = R_I2SP2CTL;
2787                 break;
2788         case TSCS454_DAI3_ID:
2789                 reg = R_I2SP3CTL;
2790                 break;
2791         default:
2792                 ret = -EINVAL;
2793                 dev_err(component->dev,
2794                                 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2795                 return ret;
2796         }
2797
2798         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2799         case SND_SOC_DAIFMT_RIGHT_J:
2800                 val = FV_FORMAT_RIGHT;
2801                 break;
2802         case SND_SOC_DAIFMT_LEFT_J:
2803                 val = FV_FORMAT_LEFT;
2804                 break;
2805         case SND_SOC_DAIFMT_I2S:
2806                 val = FV_FORMAT_I2S;
2807                 break;
2808         case SND_SOC_DAIFMT_DSP_A:
2809                 ret = set_aif_tdm_delay(component, dai_id, true);
2810                 if (ret < 0)
2811                         return ret;
2812                 val = FV_FORMAT_TDM;
2813                 break;
2814         case SND_SOC_DAIFMT_DSP_B:
2815                 ret = set_aif_tdm_delay(component, dai_id, false);
2816                 if (ret < 0)
2817                         return ret;
2818                 val = FV_FORMAT_TDM;
2819                 break;
2820         default:
2821                 ret = -EINVAL;
2822                 dev_err(component->dev, "Format unsupported (%d)\n", ret);
2823                 return ret;
2824         }
2825
2826         ret = snd_soc_component_update_bits(component,
2827                         reg, FM_I2SPCTL_FORMAT, val);
2828         if (ret < 0) {
2829                 dev_err(component->dev, "Failed to set DAI %d format (%d)\n",
2830                                 dai_id + 1, ret);
2831                 return ret;
2832         }
2833
2834         return 0;
2835 }
2836
2837 static inline int
2838 set_aif_clock_format_from_fmt(struct snd_soc_component *component,
2839                 unsigned int dai_id, unsigned int fmt)
2840 {
2841         unsigned int reg;
2842         unsigned int val;
2843         int ret;
2844
2845         switch (dai_id) {
2846         case TSCS454_DAI1_ID:
2847                 reg = R_I2SP1CTL;
2848                 break;
2849         case TSCS454_DAI2_ID:
2850                 reg = R_I2SP2CTL;
2851                 break;
2852         case TSCS454_DAI3_ID:
2853                 reg = R_I2SP3CTL;
2854                 break;
2855         default:
2856                 ret = -EINVAL;
2857                 dev_err(component->dev,
2858                                 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2859                 return ret;
2860         }
2861
2862         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2863         case SND_SOC_DAIFMT_NB_NF:
2864                 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED;
2865                 break;
2866         case SND_SOC_DAIFMT_NB_IF:
2867                 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED;
2868                 break;
2869         case SND_SOC_DAIFMT_IB_NF:
2870                 val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED;
2871                 break;
2872         case SND_SOC_DAIFMT_IB_IF:
2873                 val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED;
2874                 break;
2875         default:
2876                 ret = -EINVAL;
2877                 dev_err(component->dev, "Format unknown (%d)\n", ret);
2878                 return ret;
2879         }
2880
2881         ret = snd_soc_component_update_bits(component, reg,
2882                         FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val);
2883         if (ret < 0) {
2884                 dev_err(component->dev,
2885                                 "Failed to set clock polarity for DAI%d (%d)\n",
2886                                 dai_id + 1, ret);
2887                 return ret;
2888         }
2889
2890         return 0;
2891 }
2892
2893 static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2894 {
2895         struct snd_soc_component *component = dai->component;
2896         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2897         struct aif *aif = &tscs454->aifs[dai->id];
2898         int ret;
2899
2900         ret = set_aif_master_from_fmt(component, aif, fmt);
2901         if (ret < 0)
2902                 return ret;
2903
2904         ret = set_aif_format_from_fmt(component, dai->id, fmt);
2905         if (ret < 0)
2906                 return ret;
2907
2908         ret = set_aif_clock_format_from_fmt(component, dai->id, fmt);
2909         if (ret < 0)
2910                 return ret;
2911
2912         return 0;
2913 }
2914
2915 static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai,
2916                 unsigned int tx_mask, unsigned int rx_mask, int slots,
2917                 int slot_width)
2918 {
2919         struct snd_soc_component *component = dai->component;
2920         unsigned int val;
2921         int ret;
2922
2923         if (!slots)
2924                 return 0;
2925
2926         if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2927                 ret = -EINVAL;
2928                 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2929                 return ret;
2930         }
2931
2932         switch (slots) {
2933         case 2:
2934                 val = FV_TDMSO_2 | FV_TDMSI_2;
2935                 break;
2936         case 4:
2937                 val = FV_TDMSO_4 | FV_TDMSI_4;
2938                 break;
2939         case 6:
2940                 val = FV_TDMSO_6 | FV_TDMSI_6;
2941                 break;
2942         default:
2943                 ret = -EINVAL;
2944                 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
2945                 return ret;
2946         }
2947
2948         switch (slot_width) {
2949         case 16:
2950                 val = val | FV_TDMDSS_16;
2951                 break;
2952         case 24:
2953                 val = val | FV_TDMDSS_24;
2954                 break;
2955         case 32:
2956                 val = val | FV_TDMDSS_32;
2957                 break;
2958         default:
2959                 ret = -EINVAL;
2960                 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
2961                 return ret;
2962         }
2963         ret = snd_soc_component_write(component, R_TDMCTL1, val);
2964         if (ret < 0) {
2965                 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
2966                 return ret;
2967         }
2968
2969         return 0;
2970 }
2971
2972 static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai,
2973                 unsigned int tx_mask, unsigned int rx_mask, int slots,
2974                 int slot_width)
2975 {
2976         struct snd_soc_component *component = dai->component;
2977         unsigned int reg;
2978         unsigned int val;
2979         int ret;
2980
2981         if (!slots)
2982                 return 0;
2983
2984         if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2985                 ret = -EINVAL;
2986                 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2987                 return ret;
2988         }
2989
2990         switch (dai->id) {
2991         case TSCS454_DAI2_ID:
2992                 reg = R_PCMP2CTL1;
2993                 break;
2994         case TSCS454_DAI3_ID:
2995                 reg = R_PCMP3CTL1;
2996                 break;
2997         default:
2998                 ret = -EINVAL;
2999                 dev_err(component->dev, "Unrecognized interface %d (%d)\n",
3000                                 dai->id, ret);
3001                 return ret;
3002         }
3003
3004         switch (slots) {
3005         case 1:
3006                 val = FV_PCMSOP_1 | FV_PCMSIP_1;
3007                 break;
3008         case 2:
3009                 val = FV_PCMSOP_2 | FV_PCMSIP_2;
3010                 break;
3011         default:
3012                 ret = -EINVAL;
3013                 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
3014                 return ret;
3015         }
3016
3017         switch (slot_width) {
3018         case 16:
3019                 val = val | FV_PCMDSSP_16;
3020                 break;
3021         case 24:
3022                 val = val | FV_PCMDSSP_24;
3023                 break;
3024         case 32:
3025                 val = val | FV_PCMDSSP_32;
3026                 break;
3027         default:
3028                 ret = -EINVAL;
3029                 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
3030                 return ret;
3031         }
3032         ret = snd_soc_component_write(component, reg, val);
3033         if (ret < 0) {
3034                 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
3035                 return ret;
3036         }
3037
3038         return 0;
3039 }
3040
3041 static int set_aif_fs(struct snd_soc_component *component,
3042                 unsigned int id,
3043                 unsigned int rate)
3044 {
3045         unsigned int reg;
3046         unsigned int br;
3047         unsigned int bm;
3048         int ret;
3049
3050         switch (rate) {
3051         case 8000:
3052                 br = FV_I2SMBR_32;
3053                 bm = FV_I2SMBM_0PT25;
3054                 break;
3055         case 16000:
3056                 br = FV_I2SMBR_32;
3057                 bm = FV_I2SMBM_0PT5;
3058                 break;
3059         case 24000:
3060                 br = FV_I2SMBR_48;
3061                 bm = FV_I2SMBM_0PT5;
3062                 break;
3063         case 32000:
3064                 br = FV_I2SMBR_32;
3065                 bm = FV_I2SMBM_1;
3066                 break;
3067         case 48000:
3068                 br = FV_I2SMBR_48;
3069                 bm = FV_I2SMBM_1;
3070                 break;
3071         case 96000:
3072                 br = FV_I2SMBR_48;
3073                 bm = FV_I2SMBM_2;
3074                 break;
3075         case 11025:
3076                 br = FV_I2SMBR_44PT1;
3077                 bm = FV_I2SMBM_0PT25;
3078                 break;
3079         case 22050:
3080                 br = FV_I2SMBR_44PT1;
3081                 bm = FV_I2SMBM_0PT5;
3082                 break;
3083         case 44100:
3084                 br = FV_I2SMBR_44PT1;
3085                 bm = FV_I2SMBM_1;
3086                 break;
3087         case 88200:
3088                 br = FV_I2SMBR_44PT1;
3089                 bm = FV_I2SMBM_2;
3090                 break;
3091         default:
3092                 ret = -EINVAL;
3093                 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret);
3094                 return ret;
3095         }
3096
3097         switch (id) {
3098         case TSCS454_DAI1_ID:
3099                 reg = R_I2S1MRATE;
3100                 break;
3101         case TSCS454_DAI2_ID:
3102                 reg = R_I2S2MRATE;
3103                 break;
3104         case TSCS454_DAI3_ID:
3105                 reg = R_I2S3MRATE;
3106                 break;
3107         default:
3108                 ret = -EINVAL;
3109                 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret);
3110                 return ret;
3111         }
3112
3113         ret = snd_soc_component_update_bits(component, reg,
3114                         FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm);
3115         if (ret < 0) {
3116                 dev_err(component->dev,
3117                                 "Failed to update register (%d)\n", ret);
3118                 return ret;
3119         }
3120
3121         return 0;
3122 }
3123
3124 static int set_aif_sample_format(struct snd_soc_component *component,
3125                 snd_pcm_format_t format,
3126                 int aif_id)
3127 {
3128         unsigned int reg;
3129         unsigned int width;
3130         int ret;
3131
3132         switch (snd_pcm_format_width(format)) {
3133         case 16:
3134                 width = FV_WL_16;
3135                 break;
3136         case 20:
3137                 width = FV_WL_20;
3138                 break;
3139         case 24:
3140                 width = FV_WL_24;
3141                 break;
3142         case 32:
3143                 width = FV_WL_32;
3144                 break;
3145         default:
3146                 ret = -EINVAL;
3147                 dev_err(component->dev, "Unsupported format width (%d)\n", ret);
3148                 return ret;
3149         }
3150
3151         switch (aif_id) {
3152         case TSCS454_DAI1_ID:
3153                 reg = R_I2SP1CTL;
3154                 break;
3155         case TSCS454_DAI2_ID:
3156                 reg = R_I2SP2CTL;
3157                 break;
3158         case TSCS454_DAI3_ID:
3159                 reg = R_I2SP3CTL;
3160                 break;
3161         default:
3162                 ret = -EINVAL;
3163                 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret);
3164                 return ret;
3165         }
3166
3167         ret = snd_soc_component_update_bits(component,
3168                         reg, FM_I2SPCTL_WL, width);
3169         if (ret < 0) {
3170                 dev_err(component->dev,
3171                                 "Failed to set sample width (%d)\n", ret);
3172                 return ret;
3173         }
3174
3175         return 0;
3176 }
3177
3178 static int tscs454_hw_params(struct snd_pcm_substream *substream,
3179                 struct snd_pcm_hw_params *params,
3180                 struct snd_soc_dai *dai)
3181 {
3182         struct snd_soc_component *component = dai->component;
3183         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3184         unsigned int fs = params_rate(params);
3185         struct aif *aif = &tscs454->aifs[dai->id];
3186         unsigned int val;
3187         int ret;
3188
3189         mutex_lock(&tscs454->aifs_status_lock);
3190
3191         dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__,
3192                         aif->id, fs);
3193
3194         if (!aif_active(&tscs454->aifs_status, aif->id)) {
3195                 if (PLL_44_1K_RATE % fs)
3196                         aif->pll = &tscs454->pll1;
3197                 else
3198                         aif->pll = &tscs454->pll2;
3199
3200                 dev_dbg(component->dev, "Reserving pll %d for aif %d\n",
3201                                 aif->pll->id, aif->id);
3202
3203                 reserve_pll(aif->pll);
3204         }
3205
3206         if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */
3207                 ret = snd_soc_component_read(component, R_ISRC, &val);
3208                 if (ret < 0)
3209                         goto exit;
3210
3211                 if ((val & FM_ISRC_IBR) == FV_IBR_48)
3212                         tscs454->internal_rate.pll = &tscs454->pll1;
3213                 else
3214                         tscs454->internal_rate.pll = &tscs454->pll2;
3215
3216                 dev_dbg(component->dev, "Reserving pll %d for ir\n",
3217                                 tscs454->internal_rate.pll->id);
3218
3219                 reserve_pll(tscs454->internal_rate.pll);
3220         }
3221
3222         ret = set_aif_fs(component, aif->id, fs);
3223         if (ret < 0) {
3224                 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret);
3225                 goto exit;
3226         }
3227
3228         ret = set_aif_sample_format(component, params_format(params), aif->id);
3229         if (ret < 0) {
3230                 dev_err(component->dev,
3231                                 "Failed to set aif sample format (%d)\n", ret);
3232                 goto exit;
3233         }
3234
3235         set_aif_status_active(&tscs454->aifs_status, aif->id,
3236                         substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3237
3238         dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n",
3239                 aif->id, tscs454->aifs_status.streams);
3240
3241         ret = 0;
3242 exit:
3243         mutex_unlock(&tscs454->aifs_status_lock);
3244
3245         return ret;
3246 }
3247
3248 static int tscs454_hw_free(struct snd_pcm_substream *substream,
3249                 struct snd_soc_dai *dai)
3250 {
3251         struct snd_soc_component *component = dai->component;
3252         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3253         struct aif *aif = &tscs454->aifs[dai->id];
3254
3255         return aif_free(component, aif,
3256                         substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3257 }
3258
3259 static int tscs454_prepare(struct snd_pcm_substream *substream,
3260                 struct snd_soc_dai *dai)
3261 {
3262         int ret;
3263         struct snd_soc_component *component = dai->component;
3264         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3265         struct aif *aif = &tscs454->aifs[dai->id];
3266
3267         ret = aif_prepare(component, aif);
3268         if (ret < 0)
3269                 return ret;
3270
3271         return 0;
3272 }
3273
3274 static struct snd_soc_dai_ops const tscs454_dai1_ops = {
3275         .set_sysclk     = tscs454_set_sysclk,
3276         .set_bclk_ratio = tscs454_set_bclk_ratio,
3277         .set_fmt        = tscs454_set_dai_fmt,
3278         .set_tdm_slot   = tscs454_dai1_set_tdm_slot,
3279         .hw_params      = tscs454_hw_params,
3280         .hw_free        = tscs454_hw_free,
3281         .prepare        = tscs454_prepare,
3282 };
3283
3284 static struct snd_soc_dai_ops const tscs454_dai23_ops = {
3285         .set_sysclk     = tscs454_set_sysclk,
3286         .set_bclk_ratio = tscs454_set_bclk_ratio,
3287         .set_fmt        = tscs454_set_dai_fmt,
3288         .set_tdm_slot   = tscs454_dai23_set_tdm_slot,
3289         .hw_params      = tscs454_hw_params,
3290         .hw_free        = tscs454_hw_free,
3291         .prepare        = tscs454_prepare,
3292 };
3293
3294 static int tscs454_probe(struct snd_soc_component *component)
3295 {
3296         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3297         unsigned int val;
3298         int ret = 0;
3299
3300         switch (tscs454->sysclk_src_id) {
3301         case PLL_INPUT_XTAL:
3302                 val = FV_PLLISEL_XTAL;
3303                 break;
3304         case PLL_INPUT_MCLK1:
3305                 val = FV_PLLISEL_MCLK1;
3306                 break;
3307         case PLL_INPUT_MCLK2:
3308                 val = FV_PLLISEL_MCLK2;
3309                 break;
3310         case PLL_INPUT_BCLK:
3311                 val = FV_PLLISEL_BCLK;
3312                 break;
3313         default:
3314                 ret = -EINVAL;
3315                 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret);
3316                 return ret;
3317         }
3318
3319         ret = snd_soc_component_update_bits(component, R_PLLCTL,
3320                         FM_PLLCTL_PLLISEL, val);
3321         if (ret < 0) {
3322                 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret);
3323                 return ret;
3324         }
3325
3326         if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
3327                 ret = set_sysclk(component);
3328
3329         return ret;
3330 }
3331
3332 static const struct snd_soc_component_driver soc_component_dev_tscs454 = {
3333         .probe =        tscs454_probe,
3334         .dapm_widgets = tscs454_dapm_widgets,
3335         .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets),
3336         .dapm_routes = tscs454_intercon,
3337         .num_dapm_routes = ARRAY_SIZE(tscs454_intercon),
3338         .controls =     tscs454_snd_controls,
3339         .num_controls = ARRAY_SIZE(tscs454_snd_controls),
3340         .endianness = 1,
3341 };
3342
3343 #define TSCS454_RATES SNDRV_PCM_RATE_8000_96000
3344
3345 #define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
3346         | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
3347         | SNDRV_PCM_FMTBIT_S32_LE)
3348
3349 static struct snd_soc_dai_driver tscs454_dais[] = {
3350         {
3351                 .name = "tscs454-dai1",
3352                 .id = TSCS454_DAI1_ID,
3353                 .playback = {
3354                         .stream_name = "DAI 1 Playback",
3355                         .channels_min = 1,
3356                         .channels_max = 6,
3357                         .rates = TSCS454_RATES,
3358                         .formats = TSCS454_FORMATS,},
3359                 .capture = {
3360                         .stream_name = "DAI 1 Capture",
3361                         .channels_min = 1,
3362                         .channels_max = 6,
3363                         .rates = TSCS454_RATES,
3364                         .formats = TSCS454_FORMATS,},
3365                 .ops = &tscs454_dai1_ops,
3366                 .symmetric_rates = 1,
3367                 .symmetric_channels = 1,
3368                 .symmetric_samplebits = 1,
3369         },
3370         {
3371                 .name = "tscs454-dai2",
3372                 .id = TSCS454_DAI2_ID,
3373                 .playback = {
3374                         .stream_name = "DAI 2 Playback",
3375                         .channels_min = 1,
3376                         .channels_max = 2,
3377                         .rates = TSCS454_RATES,
3378                         .formats = TSCS454_FORMATS,},
3379                 .capture = {
3380                         .stream_name = "DAI 2 Capture",
3381                         .channels_min = 1,
3382                         .channels_max = 2,
3383                         .rates = TSCS454_RATES,
3384                         .formats = TSCS454_FORMATS,},
3385                 .ops = &tscs454_dai23_ops,
3386                 .symmetric_rates = 1,
3387                 .symmetric_channels = 1,
3388                 .symmetric_samplebits = 1,
3389         },
3390         {
3391                 .name = "tscs454-dai3",
3392                 .id = TSCS454_DAI3_ID,
3393                 .playback = {
3394                         .stream_name = "DAI 3 Playback",
3395                         .channels_min = 1,
3396                         .channels_max = 2,
3397                         .rates = TSCS454_RATES,
3398                         .formats = TSCS454_FORMATS,},
3399                 .capture = {
3400                         .stream_name = "DAI 3 Capture",
3401                         .channels_min = 1,
3402                         .channels_max = 2,
3403                         .rates = TSCS454_RATES,
3404                         .formats = TSCS454_FORMATS,},
3405                 .ops = &tscs454_dai23_ops,
3406                 .symmetric_rates = 1,
3407                 .symmetric_channels = 1,
3408                 .symmetric_samplebits = 1,
3409         },
3410 };
3411
3412 static char const * const src_names[] = {
3413         "xtal", "mclk1", "mclk2", "bclk"};
3414
3415 static int tscs454_i2c_probe(struct i2c_client *i2c,
3416                 const struct i2c_device_id *id)
3417 {
3418         struct tscs454 *tscs454;
3419         int src;
3420         int ret;
3421
3422         tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL);
3423         if (!tscs454)
3424                 return -ENOMEM;
3425
3426         ret = tscs454_data_init(tscs454, i2c);
3427         if (ret < 0)
3428                 return ret;
3429
3430         i2c_set_clientdata(i2c, tscs454);
3431
3432         for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) {
3433                 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
3434                 if (!IS_ERR(tscs454->sysclk)) {
3435                         break;
3436                 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) {
3437                         ret = PTR_ERR(tscs454->sysclk);
3438                         dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
3439                         return ret;
3440                 }
3441         }
3442         dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]);
3443         tscs454->sysclk_src_id = src;
3444
3445         ret = regmap_write(tscs454->regmap,
3446                         R_RESET, FV_RESET_PWR_ON_DEFAULTS);
3447         if (ret < 0) {
3448                 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret);
3449                 return ret;
3450         }
3451         regcache_mark_dirty(tscs454->regmap);
3452
3453         ret = regmap_register_patch(tscs454->regmap, tscs454_patch,
3454                         ARRAY_SIZE(tscs454_patch));
3455         if (ret < 0) {
3456                 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
3457                 return ret;
3458         }
3459         /* Sync pg sel reg with cache */
3460         regmap_write(tscs454->regmap, R_PAGESEL, 0x00);
3461
3462         ret = snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
3463                         tscs454_dais, ARRAY_SIZE(tscs454_dais));
3464         if (ret) {
3465                 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret);
3466                 return ret;
3467         }
3468
3469         return 0;
3470 }
3471
3472 static const struct i2c_device_id tscs454_i2c_id[] = {
3473         { "tscs454", 0 },
3474         { }
3475 };
3476 MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id);
3477
3478 static const struct of_device_id tscs454_of_match[] = {
3479         { .compatible = "tempo,tscs454", },
3480         { }
3481 };
3482 MODULE_DEVICE_TABLE(of, tscs454_of_match);
3483
3484 static struct i2c_driver tscs454_i2c_driver = {
3485         .driver = {
3486                 .name = "tscs454",
3487                 .of_match_table = tscs454_of_match,
3488         },
3489         .probe =    tscs454_i2c_probe,
3490         .id_table = tscs454_i2c_id,
3491 };
3492
3493 module_i2c_driver(tscs454_i2c_driver);
3494
3495 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com");
3496 MODULE_DESCRIPTION("ASoC TSCS454 driver");
3497 MODULE_LICENSE("GPL v2");