2 * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
22 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
23 SNDRV_PCM_FMTBIT_S16_LE | \
24 SNDRV_PCM_FMTBIT_S20_3LE | \
25 SNDRV_PCM_FMTBIT_S24_LE)
28 * fsl_esai: ESAI private data
30 * @dma_params_rx: DMA parameters for receive channel
31 * @dma_params_tx: DMA parameters for transmit channel
32 * @pdev: platform device pointer
33 * @regmap: regmap handler
34 * @coreclk: clock source to access register
35 * @extalclk: esai clock source to derive HCK, SCK and FS
36 * @fsysclk: system clock source to derive HCK, SCK and FS
37 * @spbaclk: SPBA clock (optional, depending on SoC design)
38 * @fifo_depth: depth of tx/rx FIFO
39 * @slot_width: width of each DAI slot
40 * @slots: number of slots
41 * @hck_rate: clock rate of desired HCKx clock
42 * @sck_rate: clock rate of desired SCKx clock
43 * @hck_dir: the direction of HCKx pads
44 * @sck_div: if using PSR/PM dividers for SCKx clock
45 * @slave_mode: if fully using DAI slave mode
46 * @synchronous: if using tx/rx synchronous mode
50 struct snd_dmaengine_dai_dma_data dma_params_rx;
51 struct snd_dmaengine_dai_dma_data dma_params_tx;
52 struct platform_device *pdev;
53 struct regmap *regmap;
72 static irqreturn_t esai_isr(int irq, void *devid)
74 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
75 struct platform_device *pdev = esai_priv->pdev;
78 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
80 if (esr & ESAI_ESR_TINIT_MASK)
81 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
83 if (esr & ESAI_ESR_RFF_MASK)
84 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
86 if (esr & ESAI_ESR_TFE_MASK)
87 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
89 if (esr & ESAI_ESR_TLS_MASK)
90 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
92 if (esr & ESAI_ESR_TDE_MASK)
93 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
95 if (esr & ESAI_ESR_TED_MASK)
96 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
98 if (esr & ESAI_ESR_TD_MASK)
99 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
101 if (esr & ESAI_ESR_RLS_MASK)
102 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
104 if (esr & ESAI_ESR_RDE_MASK)
105 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
107 if (esr & ESAI_ESR_RED_MASK)
108 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
110 if (esr & ESAI_ESR_RD_MASK)
111 dev_dbg(&pdev->dev, "isr: Receiving data\n");
117 * This function is used to calculate the divisors of psr, pm, fp and it is
118 * supposed to be called in set_dai_sysclk() and set_bclk().
120 * @ratio: desired overall ratio for the paticipating dividers
121 * @usefp: for HCK setting, there is no need to set fp divider
122 * @fp: bypass other dividers by setting fp directly if fp != 0
123 * @tx: current setting is for playback or capture
125 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
128 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
129 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
131 maxfp = usefp ? 16 : 1;
136 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
137 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
138 2 * 8 * 256 * maxfp);
140 } else if (ratio % 2) {
141 dev_err(dai->dev, "the raio must be even if using upper divider\n");
147 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
149 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
156 /* Set the max fluctuation -- 0.1% of the max devisor */
157 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
159 /* Find the best value for PM */
160 for (i = 1; i <= 256; i++) {
161 for (j = 1; j <= maxfp; j++) {
162 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
163 prod = (psr ? 1 : 8) * i * j;
167 else if (prod / ratio == 1)
169 else if (ratio / prod == 1)
174 /* Calculate the fraction */
175 sub = sub * 1000 / ratio;
189 dev_err(dai->dev, "failed to calculate proper divisors\n");
194 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
195 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
196 psr | ESAI_xCCR_xPM(pm));
199 /* Bypass fp if not being required */
203 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
204 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
210 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
213 * clk_id: The clock source of HCKT/HCKR
214 * (Input from outside; output from inside, FSYS or EXTAL)
215 * freq: The required clock rate of HCKT/HCKR
216 * dir: The clock direction of HCKT/HCKR
218 * Note: If the direction is input, we do not care about clk_id.
220 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
221 unsigned int freq, int dir)
223 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
224 struct clk *clksrc = esai_priv->extalclk;
225 bool tx = clk_id <= ESAI_HCKT_EXTAL;
226 bool in = dir == SND_SOC_CLOCK_IN;
228 unsigned long clk_rate;
231 /* Bypass divider settings if the requirement doesn't change */
232 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
235 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
236 esai_priv->sck_div[tx] = true;
238 /* Set the direction of HCKT/HCKR pins */
239 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
240 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
248 clksrc = esai_priv->fsysclk;
250 case ESAI_HCKT_EXTAL:
252 case ESAI_HCKR_EXTAL:
259 if (IS_ERR(clksrc)) {
260 dev_err(dai->dev, "no assigned %s clock\n",
261 clk_id % 2 ? "extal" : "fsys");
262 return PTR_ERR(clksrc);
264 clk_rate = clk_get_rate(clksrc);
266 ratio = clk_rate / freq;
267 if (ratio * freq > clk_rate)
268 ret = ratio * freq - clk_rate;
269 else if (ratio * freq < clk_rate)
270 ret = clk_rate - ratio * freq;
274 /* Block if clock source can not be divided into the required rate */
275 if (ret != 0 && clk_rate / ret < 1000) {
276 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
281 /* Only EXTAL source can be output directly without using PSR and PM */
282 if (ratio == 1 && clksrc == esai_priv->extalclk) {
283 /* Bypass all the dividers if not being needed */
284 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
286 } else if (ratio < 2) {
287 /* The ratio should be no less than 2 if using other sources */
288 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
293 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
297 esai_priv->sck_div[tx] = false;
300 esai_priv->hck_dir[tx] = dir;
301 esai_priv->hck_rate[tx] = freq;
303 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
304 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
305 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
311 * This function configures the related dividers according to the bclk rate
313 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
315 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
316 u32 hck_rate = esai_priv->hck_rate[tx];
317 u32 sub, ratio = hck_rate / freq;
320 /* Don't apply for fully slave mode or unchanged bclk */
321 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
324 if (ratio * freq > hck_rate)
325 sub = ratio * freq - hck_rate;
326 else if (ratio * freq < hck_rate)
327 sub = hck_rate - ratio * freq;
331 /* Block if clock source can not be divided into the required rate */
332 if (sub != 0 && hck_rate / sub < 1000) {
333 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
338 /* The ratio should be contented by FP alone if bypassing PM and PSR */
339 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
340 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
344 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
345 esai_priv->sck_div[tx] ? 0 : ratio);
349 /* Save current bclk rate */
350 esai_priv->sck_rate[tx] = freq;
355 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
356 u32 rx_mask, int slots, int slot_width)
358 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
360 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
361 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
363 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
364 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
366 esai_priv->slot_width = slot_width;
367 esai_priv->slots = slots;
368 esai_priv->tx_mask = tx_mask;
369 esai_priv->rx_mask = rx_mask;
374 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
376 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
377 u32 xcr = 0, xccr = 0, mask;
380 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
381 case SND_SOC_DAIFMT_I2S:
382 /* Data on rising edge of bclk, frame low, 1clk before data */
383 xcr |= ESAI_xCR_xFSR;
384 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
386 case SND_SOC_DAIFMT_LEFT_J:
387 /* Data on rising edge of bclk, frame high */
388 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
390 case SND_SOC_DAIFMT_RIGHT_J:
391 /* Data on rising edge of bclk, frame high, right aligned */
392 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
395 case SND_SOC_DAIFMT_DSP_A:
396 /* Data on rising edge of bclk, frame high, 1clk before data */
397 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
398 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
400 case SND_SOC_DAIFMT_DSP_B:
401 /* Data on rising edge of bclk, frame high */
402 xcr |= ESAI_xCR_xFSL;
403 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
409 /* DAI clock inversion */
410 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
411 case SND_SOC_DAIFMT_NB_NF:
412 /* Nothing to do for both normal cases */
414 case SND_SOC_DAIFMT_IB_NF:
415 /* Invert bit clock */
416 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
418 case SND_SOC_DAIFMT_NB_IF:
419 /* Invert frame clock */
420 xccr ^= ESAI_xCCR_xFSP;
422 case SND_SOC_DAIFMT_IB_IF:
423 /* Invert both clocks */
424 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
430 esai_priv->slave_mode = false;
432 /* DAI clock master masks */
433 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
434 case SND_SOC_DAIFMT_CBM_CFM:
435 esai_priv->slave_mode = true;
437 case SND_SOC_DAIFMT_CBS_CFM:
438 xccr |= ESAI_xCCR_xCKD;
440 case SND_SOC_DAIFMT_CBM_CFS:
441 xccr |= ESAI_xCCR_xFSD;
443 case SND_SOC_DAIFMT_CBS_CFS:
444 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
450 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
451 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
452 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
454 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
455 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
456 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
457 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
462 static int fsl_esai_startup(struct snd_pcm_substream *substream,
463 struct snd_soc_dai *dai)
465 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
469 * Some platforms might use the same bit to gate all three or two of
470 * clocks, so keep all clocks open/close at the same time for safety
472 ret = clk_prepare_enable(esai_priv->coreclk);
475 if (!IS_ERR(esai_priv->spbaclk)) {
476 ret = clk_prepare_enable(esai_priv->spbaclk);
480 if (!IS_ERR(esai_priv->extalclk)) {
481 ret = clk_prepare_enable(esai_priv->extalclk);
485 if (!IS_ERR(esai_priv->fsysclk)) {
486 ret = clk_prepare_enable(esai_priv->fsysclk);
492 /* Set synchronous mode */
493 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
494 ESAI_SAICR_SYNC, esai_priv->synchronous ?
495 ESAI_SAICR_SYNC : 0);
497 /* Set slots count */
498 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
500 ESAI_xCCR_xDC(esai_priv->slots));
501 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
503 ESAI_xCCR_xDC(esai_priv->slots));
509 if (!IS_ERR(esai_priv->extalclk))
510 clk_disable_unprepare(esai_priv->extalclk);
512 if (!IS_ERR(esai_priv->spbaclk))
513 clk_disable_unprepare(esai_priv->spbaclk);
515 clk_disable_unprepare(esai_priv->coreclk);
520 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
521 struct snd_pcm_hw_params *params,
522 struct snd_soc_dai *dai)
524 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
525 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
526 u32 width = params_width(params);
527 u32 channels = params_channels(params);
528 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
529 u32 slot_width = width;
533 /* Override slot_width if being specifically set */
534 if (esai_priv->slot_width)
535 slot_width = esai_priv->slot_width;
537 bclk = params_rate(params) * slot_width * esai_priv->slots;
539 ret = fsl_esai_set_bclk(dai, tx, bclk);
543 /* Use Normal mode to support monaural audio */
544 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
545 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
546 ESAI_xCR_xMOD_NETWORK : 0);
548 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
549 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
551 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
552 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
553 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
554 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
556 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
558 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
559 val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
561 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
563 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
564 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
565 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
566 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
567 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
571 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
572 struct snd_soc_dai *dai)
574 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
576 if (!IS_ERR(esai_priv->fsysclk))
577 clk_disable_unprepare(esai_priv->fsysclk);
578 if (!IS_ERR(esai_priv->extalclk))
579 clk_disable_unprepare(esai_priv->extalclk);
580 if (!IS_ERR(esai_priv->spbaclk))
581 clk_disable_unprepare(esai_priv->spbaclk);
582 clk_disable_unprepare(esai_priv->coreclk);
585 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
586 struct snd_soc_dai *dai)
588 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
589 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
590 u8 i, channels = substream->runtime->channels;
591 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
595 case SNDRV_PCM_TRIGGER_START:
596 case SNDRV_PCM_TRIGGER_RESUME:
597 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
598 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
599 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
601 /* Write initial words reqiured by ESAI as normal procedure */
602 for (i = 0; tx && i < channels; i++)
603 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
606 * When set the TE/RE in the end of enablement flow, there
607 * will be channel swap issue for multi data line case.
608 * In order to workaround this issue, we switch the bit
609 * enablement sequence to below sequence
610 * 1) clear the xSMB & xSMA: which is done in probe and
614 * 4) set xSMA: xSMA is the last one in this flow, which
615 * will trigger esai to start.
617 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
618 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
619 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
620 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
622 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
623 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
624 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
625 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
628 case SNDRV_PCM_TRIGGER_SUSPEND:
629 case SNDRV_PCM_TRIGGER_STOP:
630 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
631 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
632 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
633 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
634 ESAI_xSMA_xS_MASK, 0);
635 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
636 ESAI_xSMB_xS_MASK, 0);
638 /* Disable and reset FIFO */
639 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
640 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
641 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
651 static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
652 .startup = fsl_esai_startup,
653 .shutdown = fsl_esai_shutdown,
654 .trigger = fsl_esai_trigger,
655 .hw_params = fsl_esai_hw_params,
656 .set_sysclk = fsl_esai_set_dai_sysclk,
657 .set_fmt = fsl_esai_set_dai_fmt,
658 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
661 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
663 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
665 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
666 &esai_priv->dma_params_rx);
671 static struct snd_soc_dai_driver fsl_esai_dai = {
672 .probe = fsl_esai_dai_probe,
674 .stream_name = "CPU-Playback",
677 .rates = SNDRV_PCM_RATE_8000_192000,
678 .formats = FSL_ESAI_FORMATS,
681 .stream_name = "CPU-Capture",
684 .rates = SNDRV_PCM_RATE_8000_192000,
685 .formats = FSL_ESAI_FORMATS,
687 .ops = &fsl_esai_dai_ops,
690 static const struct snd_soc_component_driver fsl_esai_component = {
694 static const struct reg_default fsl_esai_reg_defaults[] = {
695 {REG_ESAI_ETDR, 0x00000000},
696 {REG_ESAI_ECR, 0x00000000},
697 {REG_ESAI_TFCR, 0x00000000},
698 {REG_ESAI_RFCR, 0x00000000},
699 {REG_ESAI_TX0, 0x00000000},
700 {REG_ESAI_TX1, 0x00000000},
701 {REG_ESAI_TX2, 0x00000000},
702 {REG_ESAI_TX3, 0x00000000},
703 {REG_ESAI_TX4, 0x00000000},
704 {REG_ESAI_TX5, 0x00000000},
705 {REG_ESAI_TSR, 0x00000000},
706 {REG_ESAI_SAICR, 0x00000000},
707 {REG_ESAI_TCR, 0x00000000},
708 {REG_ESAI_TCCR, 0x00000000},
709 {REG_ESAI_RCR, 0x00000000},
710 {REG_ESAI_RCCR, 0x00000000},
711 {REG_ESAI_TSMA, 0x0000ffff},
712 {REG_ESAI_TSMB, 0x0000ffff},
713 {REG_ESAI_RSMA, 0x0000ffff},
714 {REG_ESAI_RSMB, 0x0000ffff},
715 {REG_ESAI_PRRC, 0x00000000},
716 {REG_ESAI_PCRC, 0x00000000},
719 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
751 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
769 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
800 static const struct regmap_config fsl_esai_regmap_config = {
805 .max_register = REG_ESAI_PCRC,
806 .reg_defaults = fsl_esai_reg_defaults,
807 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
808 .readable_reg = fsl_esai_readable_reg,
809 .volatile_reg = fsl_esai_volatile_reg,
810 .writeable_reg = fsl_esai_writeable_reg,
811 .cache_type = REGCACHE_FLAT,
814 static int fsl_esai_probe(struct platform_device *pdev)
816 struct device_node *np = pdev->dev.of_node;
817 struct fsl_esai *esai_priv;
818 struct resource *res;
819 const uint32_t *iprop;
823 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
827 esai_priv->pdev = pdev;
828 strncpy(esai_priv->name, np->name, sizeof(esai_priv->name) - 1);
830 /* Get the addresses and IRQ */
831 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
832 regs = devm_ioremap_resource(&pdev->dev, res);
834 return PTR_ERR(regs);
836 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
837 "core", regs, &fsl_esai_regmap_config);
838 if (IS_ERR(esai_priv->regmap)) {
839 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
840 PTR_ERR(esai_priv->regmap));
841 return PTR_ERR(esai_priv->regmap);
844 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
845 if (IS_ERR(esai_priv->coreclk)) {
846 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
847 PTR_ERR(esai_priv->coreclk));
848 return PTR_ERR(esai_priv->coreclk);
851 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
852 if (IS_ERR(esai_priv->extalclk))
853 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
854 PTR_ERR(esai_priv->extalclk));
856 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
857 if (IS_ERR(esai_priv->fsysclk))
858 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
859 PTR_ERR(esai_priv->fsysclk));
861 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
862 if (IS_ERR(esai_priv->spbaclk))
863 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
864 PTR_ERR(esai_priv->spbaclk));
866 irq = platform_get_irq(pdev, 0);
868 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
872 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
873 esai_priv->name, esai_priv);
875 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
879 /* Set a default slot number */
880 esai_priv->slots = 2;
882 /* Set a default master/slave state */
883 esai_priv->slave_mode = true;
885 /* Determine the FIFO depth */
886 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
888 esai_priv->fifo_depth = be32_to_cpup(iprop);
890 esai_priv->fifo_depth = 64;
892 esai_priv->dma_params_tx.maxburst = 16;
893 esai_priv->dma_params_rx.maxburst = 16;
894 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
895 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
897 esai_priv->synchronous =
898 of_property_read_bool(np, "fsl,esai-synchronous");
900 /* Implement full symmetry for synchronous mode */
901 if (esai_priv->synchronous) {
902 fsl_esai_dai.symmetric_rates = 1;
903 fsl_esai_dai.symmetric_channels = 1;
904 fsl_esai_dai.symmetric_samplebits = 1;
907 dev_set_drvdata(&pdev->dev, esai_priv);
909 /* Reset ESAI unit */
910 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
912 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
917 * We need to enable ESAI so as to access some of its registers.
918 * Otherwise, we would fail to dump regmap from user space.
920 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
922 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
926 esai_priv->tx_mask = 0xFFFFFFFF;
927 esai_priv->rx_mask = 0xFFFFFFFF;
929 /* Clear the TSMA, TSMB, RSMA, RSMB */
930 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
931 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
932 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
933 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
935 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
938 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
942 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
944 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
949 static const struct of_device_id fsl_esai_dt_ids[] = {
950 { .compatible = "fsl,imx35-esai", },
951 { .compatible = "fsl,vf610-esai", },
954 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
956 #ifdef CONFIG_PM_SLEEP
957 static int fsl_esai_suspend(struct device *dev)
959 struct fsl_esai *esai = dev_get_drvdata(dev);
961 regcache_cache_only(esai->regmap, true);
962 regcache_mark_dirty(esai->regmap);
967 static int fsl_esai_resume(struct device *dev)
969 struct fsl_esai *esai = dev_get_drvdata(dev);
972 regcache_cache_only(esai->regmap, false);
974 /* FIFO reset for safety */
975 regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
976 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
977 regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
978 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
980 ret = regcache_sync(esai->regmap);
984 /* FIFO reset done */
985 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
986 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
990 #endif /* CONFIG_PM_SLEEP */
992 static const struct dev_pm_ops fsl_esai_pm_ops = {
993 SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
996 static struct platform_driver fsl_esai_driver = {
997 .probe = fsl_esai_probe,
999 .name = "fsl-esai-dai",
1000 .pm = &fsl_esai_pm_ops,
1001 .of_match_table = fsl_esai_dt_ids,
1005 module_platform_driver(fsl_esai_driver);
1007 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1008 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
1009 MODULE_LICENSE("GPL v2");
1010 MODULE_ALIAS("platform:fsl-esai-dai");