sound/soc/hisilicon/hi6210-i2s.c

   1 /*
   2  * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
   3  *
   4  * Copyright (C) 2015 Linaro, Ltd
   5  * Author: Andy Green <andy.green@linaro.org>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * This driver only deals with S2 interface (BT)
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/device.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/io.h>
  26 #include <linux/gpio.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/dmaengine_pcm.h>
  31 #include <sound/initval.h>
  32 #include <sound/soc.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/reset.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/mfd/syscon.h>
  38 #include <linux/reset-controller.h>
  39 #include <linux/clk.h>
  40
  41 #include "hi6210-i2s.h"
  42
  43 struct hi6210_i2s {
  44         struct device *dev;
  45         struct reset_control *rc;
  46         struct clk *clk[8];
  47         int clocks;
  48         struct snd_soc_dai_driver dai;
  49         void __iomem *base;
  50         struct regmap *sysctrl;
  51         phys_addr_t base_phys;
  52         struct snd_dmaengine_dai_dma_data dma_data[2];
  53         int clk_rate;
  54         spinlock_t lock;
  55         int rate;
  56         int format;
  57         u8 bits;
  58         u8 channels;
  59         u8 id;
  60         u8 channel_length;
  61         u8 use;
  62         u32 master:1;
  63         u32 status:1;
  64 };
  65
  66 #define SC_PERIPH_CLKEN1        0x210
  67 #define SC_PERIPH_CLKDIS1       0x214
  68
  69 #define SC_PERIPH_CLKEN3        0x230
  70 #define SC_PERIPH_CLKDIS3       0x234
  71
  72 #define SC_PERIPH_CLKEN12       0x270
  73 #define SC_PERIPH_CLKDIS12      0x274
  74
  75 #define SC_PERIPH_RSTEN1        0x310
  76 #define SC_PERIPH_RSTDIS1       0x314
  77 #define SC_PERIPH_RSTSTAT1      0x318
  78
  79 #define SC_PERIPH_RSTEN2        0x320
  80 #define SC_PERIPH_RSTDIS2       0x324
  81 #define SC_PERIPH_RSTSTAT2      0x328
  82
  83 #define SOC_PMCTRL_BBPPLLALIAS  0x48
  84
  85 enum {
  86         CLK_DACODEC,
  87         CLK_I2S_BASE,
  88 };
  89
  90 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
  91 {
  92         writel(val, i2s->base + reg);
  93 }
  94
  95 static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
  96 {
  97         return readl(i2s->base + reg);
  98 }
  99
 100 static int hi6210_i2s_startup(struct snd_pcm_substream *substream,
 101                               struct snd_soc_dai *cpu_dai)
 102 {
 103         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 104         int ret, n;
 105         u32 val;
 106
 107         /* deassert reset on ABB */
 108         regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
 109         if (val & BIT(4))
 110                 regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
 111
 112         for (n = 0; n < i2s->clocks; n++) {
 113                 ret = clk_prepare_enable(i2s->clk[n]);
 114                 if (ret)
 115                         goto err_unprepare_clk;
 116         }
 117
 118         ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
 119         if (ret) {
 120                 dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
 121                         __func__, ret);
 122                 goto err_unprepare_clk;
 123         }
 124
 125         /* enable clock before frequency division */
 126         regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
 127
 128         /* enable codec working clock / == "codec bus clock" */
 129         regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
 130
 131         /* deassert reset on codec / interface clock / working clock */
 132         regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
 133         regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
 134
 135         /* not interested in i2s irqs */
 136         val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
 137         val |= 0x3f;
 138         hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
 139
 140
 141         /* reset the stereo downlink fifo */
 142         val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
 143         val |= (BIT(5) | BIT(4));
 144         hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
 145
 146         val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
 147         val &= ~(BIT(5) | BIT(4));
 148         hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
 149
 150
 151         val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
 152         val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
 153                         HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
 154         val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
 155         hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
 156
 157         val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
 158         /* mux 11/12 = APB not i2s */
 159         val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
 160         /* BT R ch  0 = mixer op of DACR ch */
 161         val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
 162         val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
 163
 164         val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
 165         /* BT L ch = 1 = mux 7 = "mixer output of DACL */
 166         val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
 167         hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
 168
 169         val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
 170         val |= HII2S_SW_RST_N__SW_RST_N;
 171         hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
 172
 173         return 0;
 174
 175 err_unprepare_clk:
 176         while (n--)
 177                 clk_disable_unprepare(i2s->clk[n]);
 178         return ret;
 179 }
 180
 181 static void hi6210_i2s_shutdown(struct snd_pcm_substream *substream,
 182                                 struct snd_soc_dai *cpu_dai)
 183 {
 184         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 185         int n;
 186
 187         for (n = 0; n < i2s->clocks; n++)
 188                 clk_disable_unprepare(i2s->clk[n]);
 189
 190         regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
 191 }
 192
 193 static void hi6210_i2s_txctrl(struct snd_soc_dai *cpu_dai, int on)
 194 {
 195         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 196         u32 val;
 197
 198         spin_lock(&i2s->lock);
 199         if (on) {
 200                 /* enable S2 TX */
 201                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 202                 val |= HII2S_I2S_CFG__S2_IF_TX_EN;
 203                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 204         } else {
 205                 /* disable S2 TX */
 206                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 207                 val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
 208                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 209         }
 210         spin_unlock(&i2s->lock);
 211 }
 212
 213 static void hi6210_i2s_rxctrl(struct snd_soc_dai *cpu_dai, int on)
 214 {
 215         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 216         u32 val;
 217
 218         spin_lock(&i2s->lock);
 219         if (on) {
 220                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 221                 val |= HII2S_I2S_CFG__S2_IF_RX_EN;
 222                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 223         } else {
 224                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 225                 val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
 226                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 227         }
 228         spin_unlock(&i2s->lock);
 229 }
 230
 231 static int hi6210_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 232 {
 233         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 234
 235         /*
 236          * We don't actually set the hardware until the hw_params
 237          * call, but we need to validate the user input here.
 238          */
 239         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 240         case SND_SOC_DAIFMT_CBM_CFM:
 241         case SND_SOC_DAIFMT_CBS_CFS:
 242                 break;
 243         default:
 244                 return -EINVAL;
 245         }
 246
 247         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 248         case SND_SOC_DAIFMT_I2S:
 249         case SND_SOC_DAIFMT_LEFT_J:
 250         case SND_SOC_DAIFMT_RIGHT_J:
 251                 break;
 252         default:
 253                 return -EINVAL;
 254         }
 255
 256         i2s->format = fmt;
 257         i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
 258                       SND_SOC_DAIFMT_CBS_CFS;
 259
 260         return 0;
 261 }
 262
 263 static int hi6210_i2s_hw_params(struct snd_pcm_substream *substream,
 264                             struct snd_pcm_hw_params *params,
 265                             struct snd_soc_dai *cpu_dai)
 266 {
 267         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 268         u32 bits = 0, rate = 0, signed_data = 0, fmt = 0;
 269         u32 val;
 270         struct snd_dmaengine_dai_dma_data *dma_data;
 271
 272         switch (params_format(params)) {
 273         case SNDRV_PCM_FORMAT_U16_LE:
 274                 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
 275                 /* fallthru */
 276         case SNDRV_PCM_FORMAT_S16_LE:
 277                 bits = HII2S_BITS_16;
 278                 break;
 279         case SNDRV_PCM_FORMAT_U24_LE:
 280                 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
 281                 /* fallthru */
 282         case SNDRV_PCM_FORMAT_S24_LE:
 283                 bits = HII2S_BITS_24;
 284                 break;
 285         default:
 286                 dev_err(cpu_dai->dev, "Bad format\n");
 287                 return -EINVAL;
 288         }
 289
 290
 291         switch (params_rate(params)) {
 292         case 8000:
 293                 rate = HII2S_FS_RATE_8KHZ;
 294                 break;
 295         case 16000:
 296                 rate = HII2S_FS_RATE_16KHZ;
 297                 break;
 298         case 32000:
 299                 rate = HII2S_FS_RATE_32KHZ;
 300                 break;
 301         case 48000:
 302                 rate = HII2S_FS_RATE_48KHZ;
 303                 break;
 304         case 96000:
 305                 rate = HII2S_FS_RATE_96KHZ;
 306                 break;
 307         case 192000:
 308                 rate = HII2S_FS_RATE_192KHZ;
 309                 break;
 310         default:
 311                 dev_err(cpu_dai->dev, "Bad rate: %d\n", params_rate(params));
 312                 return -EINVAL;
 313         }
 314
 315         if (!(params_channels(params))) {
 316                 dev_err(cpu_dai->dev, "Bad channels\n");
 317                 return -EINVAL;
 318         }
 319
 320         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
 321
 322         switch (bits) {
 323         case HII2S_BITS_24:
 324                 i2s->bits = 32;
 325                 dma_data->addr_width = 3;
 326                 break;
 327         default:
 328                 i2s->bits = 16;
 329                 dma_data->addr_width = 2;
 330                 break;
 331         }
 332         i2s->rate = params_rate(params);
 333         i2s->channels = params_channels(params);
 334         i2s->channel_length = i2s->channels * i2s->bits;
 335
 336         val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
 337         val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
 338                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
 339                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK <<
 340                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
 341                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK <<
 342                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
 343                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK <<
 344                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
 345         val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
 346                 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
 347                 (16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
 348                 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
 349         hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
 350
 351
 352         val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
 353         val |= (BIT(19) | BIT(18) | BIT(17) |
 354                 HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN |
 355                 HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN |
 356                 HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN |
 357                 HII2S_IF_CLK_EN_CFG__ST_DL_R_EN |
 358                 HII2S_IF_CLK_EN_CFG__ST_DL_L_EN);
 359         hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
 360
 361
 362         val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
 363         val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
 364                  HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN |
 365                  HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN |
 366                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN |
 367                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN |
 368                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN);
 369         val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
 370                 HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN);
 371         hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
 372
 373
 374         val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
 375         val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
 376                  HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE);
 377         hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
 378
 379         val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
 380         val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
 381                  HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE |
 382                  HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE |
 383                  HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE);
 384         hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
 385
 386
 387         switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
 388         case SND_SOC_DAIFMT_CBM_CFM:
 389                 i2s->master = false;
 390                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 391                 val |= HII2S_I2S_CFG__S2_MST_SLV;
 392                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 393                 break;
 394         case SND_SOC_DAIFMT_CBS_CFS:
 395                 i2s->master = true;
 396                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 397                 val &= ~HII2S_I2S_CFG__S2_MST_SLV;
 398                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 399                 break;
 400         default:
 401                 WARN_ONCE(1, "Invalid i2s->fmt MASTER_MASK. This shouldn't happen\n");
 402                 return -EINVAL;
 403         }
 404
 405         switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
 406         case SND_SOC_DAIFMT_I2S:
 407                 fmt = HII2S_FORMAT_I2S;
 408                 break;
 409         case SND_SOC_DAIFMT_LEFT_J:
 410                 fmt = HII2S_FORMAT_LEFT_JUST;
 411                 break;
 412         case SND_SOC_DAIFMT_RIGHT_J:
 413                 fmt = HII2S_FORMAT_RIGHT_JUST;
 414                 break;
 415         default:
 416                 WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
 417                 return -EINVAL;
 418         }
 419
 420         val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 421         val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
 422                         HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT);
 423         val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
 424         hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 425
 426
 427         val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
 428         val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
 429                         HII2S_CLK_SEL__EXT_12_288MHZ_SEL);
 430         hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
 431
 432         dma_data->maxburst = 2;
 433
 434         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 435                 dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
 436         else
 437                 dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
 438
 439         switch (i2s->channels) {
 440         case 1:
 441                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 442                 val |= HII2S_I2S_CFG__S2_FRAME_MODE;
 443                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 444                 break;
 445         default:
 446                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 447                 val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
 448                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 449                 break;
 450         }
 451
 452         /* clear loopback, set signed type and word length */
 453         val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 454         val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
 455         val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
 456                         HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
 457         val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
 458                         HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT);
 459         val |= signed_data;
 460         val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
 461         hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 462
 463
 464         if (!i2s->master)
 465                 return 0;
 466
 467         /* set DAC and related units to correct rate */
 468         val = hi6210_read_reg(i2s, HII2S_FS_CFG);
 469         val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
 470         val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
 471         val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
 472                                         HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
 473         val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
 474                                         HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
 475         val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
 476         val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
 477         val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
 478         val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
 479         hi6210_write_reg(i2s, HII2S_FS_CFG, val);
 480
 481         return 0;
 482 }
 483
 484 static int hi6210_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 485                           struct snd_soc_dai *cpu_dai)
 486 {
 487         pr_debug("%s\n", __func__);
 488         switch (cmd) {
 489         case SNDRV_PCM_TRIGGER_START:
 490         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 491                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 492                         hi6210_i2s_rxctrl(cpu_dai, 1);
 493                 else
 494                         hi6210_i2s_txctrl(cpu_dai, 1);
 495                 break;
 496         case SNDRV_PCM_TRIGGER_STOP:
 497         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 498                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 499                         hi6210_i2s_rxctrl(cpu_dai, 0);
 500                 else
 501                         hi6210_i2s_txctrl(cpu_dai, 0);
 502                 break;
 503         default:
 504                 dev_err(cpu_dai->dev, "uknown cmd\n");
 505                 return -EINVAL;
 506         }
 507         return 0;
 508 }
 509
 510 static int hi6210_i2s_dai_probe(struct snd_soc_dai *dai)
 511 {
 512         struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 513
 514         snd_soc_dai_init_dma_data(dai,
 515                                   &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
 516                                   &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
 517
 518         return 0;
 519 }
 520
 521
 522 static const struct snd_soc_dai_ops hi6210_i2s_dai_ops = {
 523         .trigger        = hi6210_i2s_trigger,
 524         .hw_params      = hi6210_i2s_hw_params,
 525         .set_fmt        = hi6210_i2s_set_fmt,
 526         .startup        = hi6210_i2s_startup,
 527         .shutdown       = hi6210_i2s_shutdown,
 528 };
 529
 530 static const struct snd_soc_dai_driver hi6210_i2s_dai_init = {
 531         .probe          = hi6210_i2s_dai_probe,
 532         .playback = {
 533                 .channels_min = 2,
 534                 .channels_max = 2,
 535                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 536                            SNDRV_PCM_FMTBIT_U16_LE,
 537                 .rates = SNDRV_PCM_RATE_48000,
 538         },
 539         .capture = {
 540                 .channels_min = 2,
 541                 .channels_max = 2,
 542                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 543                            SNDRV_PCM_FMTBIT_U16_LE,
 544                 .rates = SNDRV_PCM_RATE_48000,
 545         },
 546         .ops = &hi6210_i2s_dai_ops,
 547 };
 548
 549 static const struct snd_soc_component_driver hi6210_i2s_i2s_comp = {
 550         .name = "hi6210_i2s-i2s",
 551 };
 552
 553 static int hi6210_i2s_probe(struct platform_device *pdev)
 554 {
 555         struct device_node *node = pdev->dev.of_node;
 556         struct device *dev = &pdev->dev;
 557         struct hi6210_i2s *i2s;
 558         struct resource *res;
 559         int ret;
 560
 561         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 562         if (!i2s)
 563                 return -ENOMEM;
 564
 565         i2s->dev = dev;
 566         spin_lock_init(&i2s->lock);
 567
 568         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 569         i2s->base = devm_ioremap_resource(dev, res);
 570         if (IS_ERR(i2s->base))
 571                 return PTR_ERR(i2s->base);
 572
 573         i2s->base_phys = (phys_addr_t)res->start;
 574         i2s->dai = hi6210_i2s_dai_init;
 575
 576         dev_set_drvdata(&pdev->dev, i2s);
 577
 578         i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
 579                                                 "hisilicon,sysctrl-syscon");
 580         if (IS_ERR(i2s->sysctrl))
 581                 return PTR_ERR(i2s->sysctrl);
 582
 583         i2s->clk[CLK_DACODEC] = devm_clk_get(&pdev->dev, "dacodec");
 584         if (IS_ERR_OR_NULL(i2s->clk[CLK_DACODEC]))
 585                 return PTR_ERR(i2s->clk[CLK_DACODEC]);
 586         i2s->clocks++;
 587
 588         i2s->clk[CLK_I2S_BASE] = devm_clk_get(&pdev->dev, "i2s-base");
 589         if (IS_ERR_OR_NULL(i2s->clk[CLK_I2S_BASE]))
 590                 return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
 591         i2s->clocks++;
 592
 593         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 594         if (ret)
 595                 return ret;
 596
 597         ret = devm_snd_soc_register_component(&pdev->dev, &hi6210_i2s_i2s_comp,
 598                                          &i2s->dai, 1);
 599         return ret;
 600 }
 601
 602 static const struct of_device_id hi6210_i2s_dt_ids[] = {
 603         { .compatible = "hisilicon,hi6210-i2s" },
 604         { /* sentinel */ }
 605 };
 606
 607 MODULE_DEVICE_TABLE(of, hi6210_i2s_dt_ids);
 608
 609 static struct platform_driver hi6210_i2s_driver = {
 610         .probe = hi6210_i2s_probe,
 611         .driver = {
 612                 .name = "hi6210_i2s",
 613                 .of_match_table = hi6210_i2s_dt_ids,
 614         },
 615 };
 616
 617 module_platform_driver(hi6210_i2s_driver);
 618
 619 MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");
 620 MODULE_AUTHOR("Andy Green <andy.green@linaro.org>");
 621 MODULE_LICENSE("GPL");