sound/soc/qcom/lpass-platform.c

   1 /*
   2  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/export.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <sound/pcm_params.h>
  22 #include <linux/regmap.h>
  23 #include <sound/soc.h>
  24 #include "lpass-lpaif-reg.h"
  25 #include "lpass.h"
  26
  27 struct lpass_pcm_data {
  28         int dma_ch;
  29         int i2s_port;
  30 };
  31
  32 #define LPASS_PLATFORM_BUFFER_SIZE      (16 * 1024)
  33 #define LPASS_PLATFORM_PERIODS          2
  34
  35 static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {
  36         .info                   =       SNDRV_PCM_INFO_MMAP |
  37                                         SNDRV_PCM_INFO_MMAP_VALID |
  38                                         SNDRV_PCM_INFO_INTERLEAVED |
  39                                         SNDRV_PCM_INFO_PAUSE |
  40                                         SNDRV_PCM_INFO_RESUME,
  41         .formats                =       SNDRV_PCM_FMTBIT_S16 |
  42                                         SNDRV_PCM_FMTBIT_S24 |
  43                                         SNDRV_PCM_FMTBIT_S32,
  44         .rates                  =       SNDRV_PCM_RATE_8000_192000,
  45         .rate_min               =       8000,
  46         .rate_max               =       192000,
  47         .channels_min           =       1,
  48         .channels_max           =       8,
  49         .buffer_bytes_max       =       LPASS_PLATFORM_BUFFER_SIZE,
  50         .period_bytes_max       =       LPASS_PLATFORM_BUFFER_SIZE /
  51                                                 LPASS_PLATFORM_PERIODS,
  52         .period_bytes_min       =       LPASS_PLATFORM_BUFFER_SIZE /
  53                                                 LPASS_PLATFORM_PERIODS,
  54         .periods_min            =       LPASS_PLATFORM_PERIODS,
  55         .periods_max            =       LPASS_PLATFORM_PERIODS,
  56         .fifo_size              =       0,
  57 };
  58
  59 static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
  60 {
  61         struct snd_pcm_runtime *runtime = substream->runtime;
  62         struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
  63         struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
  64         struct lpass_data *drvdata =
  65                 snd_soc_platform_get_drvdata(soc_runtime->platform);
  66         struct lpass_variant *v = drvdata->variant;
  67         int ret, dma_ch, dir = substream->stream;
  68         struct lpass_pcm_data *data;
  69
  70         data = kzalloc(sizeof(*data), GFP_KERNEL);
  71         if (!data)
  72                 return -ENOMEM;
  73
  74         data->i2s_port = cpu_dai->driver->id;
  75         runtime->private_data = data;
  76
  77         dma_ch = 0;
  78         if (v->alloc_dma_channel)
  79                 dma_ch = v->alloc_dma_channel(drvdata, dir);
  80         else
  81                 dma_ch = 0;
  82
  83         if (dma_ch < 0) {
  84                 kfree(data);
  85                 return dma_ch;
  86         }
  87
  88         drvdata->substream[dma_ch] = substream;
  89
  90         ret = regmap_write(drvdata->lpaif_map,
  91                         LPAIF_DMACTL_REG(v, dma_ch, dir), 0);
  92         if (ret) {
  93                 dev_err(soc_runtime->dev,
  94                         "error writing to rdmactl reg: %d\n", ret);
  95                         return ret;
  96         }
  97
  98         data->dma_ch = dma_ch;
  99
 100         snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
 101
 102         runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
 103
 104         ret = snd_pcm_hw_constraint_integer(runtime,
 105                         SNDRV_PCM_HW_PARAM_PERIODS);
 106         if (ret < 0) {
 107                 kfree(data);
 108                 dev_err(soc_runtime->dev, "setting constraints failed: %d\n",
 109                         ret);
 110                 return -EINVAL;
 111         }
 112
 113         snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
 114
 115         return 0;
 116 }
 117
 118 static int lpass_platform_pcmops_close(struct snd_pcm_substream *substream)
 119 {
 120         struct snd_pcm_runtime *runtime = substream->runtime;
 121         struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
 122         struct lpass_data *drvdata =
 123                 snd_soc_platform_get_drvdata(soc_runtime->platform);
 124         struct lpass_variant *v = drvdata->variant;
 125         struct lpass_pcm_data *data;
 126
 127         data = runtime->private_data;
 128         v = drvdata->variant;
 129         drvdata->substream[data->dma_ch] = NULL;
 130         if (v->free_dma_channel)
 131                 v->free_dma_channel(drvdata, data->dma_ch);
 132
 133         kfree(data);
 134         return 0;
 135 }
 136
 137 static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
 138                 struct snd_pcm_hw_params *params)
 139 {
 140         struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
 141         struct lpass_data *drvdata =
 142                 snd_soc_platform_get_drvdata(soc_runtime->platform);
 143         struct snd_pcm_runtime *rt = substream->runtime;
 144         struct lpass_pcm_data *pcm_data = rt->private_data;
 145         struct lpass_variant *v = drvdata->variant;
 146         snd_pcm_format_t format = params_format(params);
 147         unsigned int channels = params_channels(params);
 148         unsigned int regval;
 149         int ch, dir = substream->stream;
 150         int bitwidth;
 151         int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
 152
 153         ch = pcm_data->dma_ch;
 154
 155         bitwidth = snd_pcm_format_width(format);
 156         if (bitwidth < 0) {
 157                 dev_err(soc_runtime->dev, "invalid bit width given: %d\n",
 158                                 bitwidth);
 159                 return bitwidth;
 160         }
 161
 162         regval = LPAIF_DMACTL_BURSTEN_INCR4 |
 163                         LPAIF_DMACTL_AUDINTF(dma_port) |
 164                         LPAIF_DMACTL_FIFOWM_8;
 165
 166         switch (bitwidth) {
 167         case 16:
 168                 switch (channels) {
 169                 case 1:
 170                 case 2:
 171                         regval |= LPAIF_DMACTL_WPSCNT_ONE;
 172                         break;
 173                 case 4:
 174                         regval |= LPAIF_DMACTL_WPSCNT_TWO;
 175                         break;
 176                 case 6:
 177                         regval |= LPAIF_DMACTL_WPSCNT_THREE;
 178                         break;
 179                 case 8:
 180                         regval |= LPAIF_DMACTL_WPSCNT_FOUR;
 181                         break;
 182                 default:
 183                         dev_err(soc_runtime->dev,
 184                                 "invalid PCM config given: bw=%d, ch=%u\n",
 185                                 bitwidth, channels);
 186                         return -EINVAL;
 187                 }
 188                 break;
 189         case 24:
 190         case 32:
 191                 switch (channels) {
 192                 case 1:
 193                         regval |= LPAIF_DMACTL_WPSCNT_ONE;
 194                         break;
 195                 case 2:
 196                         regval |= LPAIF_DMACTL_WPSCNT_TWO;
 197                         break;
 198                 case 4:
 199                         regval |= LPAIF_DMACTL_WPSCNT_FOUR;
 200                         break;
 201                 case 6:
 202                         regval |= LPAIF_DMACTL_WPSCNT_SIX;
 203                         break;
 204                 case 8:
 205                         regval |= LPAIF_DMACTL_WPSCNT_EIGHT;
 206                         break;
 207                 default:
 208                         dev_err(soc_runtime->dev,
 209                                 "invalid PCM config given: bw=%d, ch=%u\n",
 210                                 bitwidth, channels);
 211                         return -EINVAL;
 212                 }
 213                 break;
 214         default:
 215                 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
 216                         bitwidth, channels);
 217                 return -EINVAL;
 218         }
 219
 220         ret = regmap_write(drvdata->lpaif_map,
 221                         LPAIF_DMACTL_REG(v, ch, dir), regval);
 222         if (ret) {
 223                 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
 224                         ret);
 225                 return ret;
 226         }
 227
 228         return 0;
 229 }
 230
 231 static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
 232 {
 233         struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
 234         struct lpass_data *drvdata =
 235                 snd_soc_platform_get_drvdata(soc_runtime->platform);
 236         struct snd_pcm_runtime *rt = substream->runtime;
 237         struct lpass_pcm_data *pcm_data = rt->private_data;
 238         struct lpass_variant *v = drvdata->variant;
 239         unsigned int reg;
 240         int ret;
 241
 242         reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream);
 243         ret = regmap_write(drvdata->lpaif_map, reg, 0);
 244         if (ret)
 245                 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
 246                         ret);
 247
 248         return ret;
 249 }
 250
 251 static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
 252 {
 253         struct snd_pcm_runtime *runtime = substream->runtime;
 254         struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
 255         struct lpass_data *drvdata =
 256                 snd_soc_platform_get_drvdata(soc_runtime->platform);
 257         struct snd_pcm_runtime *rt = substream->runtime;
 258         struct lpass_pcm_data *pcm_data = rt->private_data;
 259         struct lpass_variant *v = drvdata->variant;
 260         int ret, ch, dir = substream->stream;
 261
 262         ch = pcm_data->dma_ch;
 263
 264         ret = regmap_write(drvdata->lpaif_map,
 265                         LPAIF_DMABASE_REG(v, ch, dir),
 266                         runtime->dma_addr);
 267         if (ret) {
 268                 dev_err(soc_runtime->dev, "error writing to rdmabase reg: %d\n",
 269                         ret);
 270                 return ret;
 271         }
 272
 273         ret = regmap_write(drvdata->lpaif_map,
 274                         LPAIF_DMABUFF_REG(v, ch, dir),
 275                         (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
 276         if (ret) {
 277                 dev_err(soc_runtime->dev, "error writing to rdmabuff reg: %d\n",
 278                         ret);
 279                 return ret;
 280         }
 281
 282         ret = regmap_write(drvdata->lpaif_map,
 283                         LPAIF_DMAPER_REG(v, ch, dir),
 284                         (snd_pcm_lib_period_bytes(substream) >> 2) - 1);
 285         if (ret) {
 286                 dev_err(soc_runtime->dev, "error writing to rdmaper reg: %d\n",
 287                         ret);
 288                 return ret;
 289         }
 290
 291         ret = regmap_update_bits(drvdata->lpaif_map,
 292                         LPAIF_DMACTL_REG(v, ch, dir),
 293                         LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
 294         if (ret) {
 295                 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
 296                         ret);
 297                 return ret;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
 304                 int cmd)
 305 {
 306         struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
 307         struct lpass_data *drvdata =
 308                 snd_soc_platform_get_drvdata(soc_runtime->platform);
 309         struct snd_pcm_runtime *rt = substream->runtime;
 310         struct lpass_pcm_data *pcm_data = rt->private_data;
 311         struct lpass_variant *v = drvdata->variant;
 312         int ret, ch, dir = substream->stream;
 313
 314         ch = pcm_data->dma_ch;
 315
 316         switch (cmd) {
 317         case SNDRV_PCM_TRIGGER_START:
 318         case SNDRV_PCM_TRIGGER_RESUME:
 319         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 320                 /* clear status before enabling interrupts */
 321                 ret = regmap_write(drvdata->lpaif_map,
 322                                 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
 323                                 LPAIF_IRQ_ALL(ch));
 324                 if (ret) {
 325                         dev_err(soc_runtime->dev,
 326                                 "error writing to irqclear reg: %d\n", ret);
 327                         return ret;
 328                 }
 329
 330                 ret = regmap_update_bits(drvdata->lpaif_map,
 331                                 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
 332                                 LPAIF_IRQ_ALL(ch),
 333                                 LPAIF_IRQ_ALL(ch));
 334                 if (ret) {
 335                         dev_err(soc_runtime->dev,
 336                                 "error writing to irqen reg: %d\n", ret);
 337                         return ret;
 338                 }
 339
 340                 ret = regmap_update_bits(drvdata->lpaif_map,
 341                                 LPAIF_DMACTL_REG(v, ch, dir),
 342                                 LPAIF_DMACTL_ENABLE_MASK,
 343                                 LPAIF_DMACTL_ENABLE_ON);
 344                 if (ret) {
 345                         dev_err(soc_runtime->dev,
 346                                 "error writing to rdmactl reg: %d\n", ret);
 347                         return ret;
 348                 }
 349                 break;
 350         case SNDRV_PCM_TRIGGER_STOP:
 351         case SNDRV_PCM_TRIGGER_SUSPEND:
 352         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 353                 ret = regmap_update_bits(drvdata->lpaif_map,
 354                                 LPAIF_DMACTL_REG(v, ch, dir),
 355                                 LPAIF_DMACTL_ENABLE_MASK,
 356                                 LPAIF_DMACTL_ENABLE_OFF);
 357                 if (ret) {
 358                         dev_err(soc_runtime->dev,
 359                                 "error writing to rdmactl reg: %d\n", ret);
 360                         return ret;
 361                 }
 362
 363                 ret = regmap_update_bits(drvdata->lpaif_map,
 364                                 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
 365                                 LPAIF_IRQ_ALL(ch), 0);
 366                 if (ret) {
 367                         dev_err(soc_runtime->dev,
 368                                 "error writing to irqen reg: %d\n", ret);
 369                         return ret;
 370                 }
 371                 break;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
 378                 struct snd_pcm_substream *substream)
 379 {
 380         struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
 381         struct lpass_data *drvdata =
 382                         snd_soc_platform_get_drvdata(soc_runtime->platform);
 383         struct snd_pcm_runtime *rt = substream->runtime;
 384         struct lpass_pcm_data *pcm_data = rt->private_data;
 385         struct lpass_variant *v = drvdata->variant;
 386         unsigned int base_addr, curr_addr;
 387         int ret, ch, dir = substream->stream;
 388
 389         ch = pcm_data->dma_ch;
 390
 391         ret = regmap_read(drvdata->lpaif_map,
 392                         LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
 393         if (ret) {
 394                 dev_err(soc_runtime->dev,
 395                         "error reading from rdmabase reg: %d\n", ret);
 396                 return ret;
 397         }
 398
 399         ret = regmap_read(drvdata->lpaif_map,
 400                         LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
 401         if (ret) {
 402                 dev_err(soc_runtime->dev,
 403                         "error reading from rdmacurr reg: %d\n", ret);
 404                 return ret;
 405         }
 406
 407         return bytes_to_frames(substream->runtime, curr_addr - base_addr);
 408 }
 409
 410 static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
 411                 struct vm_area_struct *vma)
 412 {
 413         struct snd_pcm_runtime *runtime = substream->runtime;
 414
 415         return dma_mmap_coherent(substream->pcm->card->dev, vma,
 416                         runtime->dma_area, runtime->dma_addr,
 417                         runtime->dma_bytes);
 418 }
 419
 420 static const struct snd_pcm_ops lpass_platform_pcm_ops = {
 421         .open           = lpass_platform_pcmops_open,
 422         .close          = lpass_platform_pcmops_close,
 423         .ioctl          = snd_pcm_lib_ioctl,
 424         .hw_params      = lpass_platform_pcmops_hw_params,
 425         .hw_free        = lpass_platform_pcmops_hw_free,
 426         .prepare        = lpass_platform_pcmops_prepare,
 427         .trigger        = lpass_platform_pcmops_trigger,
 428         .pointer        = lpass_platform_pcmops_pointer,
 429         .mmap           = lpass_platform_pcmops_mmap,
 430 };
 431
 432 static irqreturn_t lpass_dma_interrupt_handler(
 433                         struct snd_pcm_substream *substream,
 434                         struct lpass_data *drvdata,
 435                         int chan, u32 interrupts)
 436 {
 437         struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
 438         struct lpass_variant *v = drvdata->variant;
 439         irqreturn_t ret = IRQ_NONE;
 440         int rv;
 441
 442         if (interrupts & LPAIF_IRQ_PER(chan)) {
 443                 rv = regmap_write(drvdata->lpaif_map,
 444                                 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
 445                                 LPAIF_IRQ_PER(chan));
 446                 if (rv) {
 447                         dev_err(soc_runtime->dev,
 448                                 "error writing to irqclear reg: %d\n", rv);
 449                         return IRQ_NONE;
 450                 }
 451                 snd_pcm_period_elapsed(substream);
 452                 ret = IRQ_HANDLED;
 453         }
 454
 455         if (interrupts & LPAIF_IRQ_XRUN(chan)) {
 456                 rv = regmap_write(drvdata->lpaif_map,
 457                                 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
 458                                 LPAIF_IRQ_XRUN(chan));
 459                 if (rv) {
 460                         dev_err(soc_runtime->dev,
 461                                 "error writing to irqclear reg: %d\n", rv);
 462                         return IRQ_NONE;
 463                 }
 464                 dev_warn(soc_runtime->dev, "xrun warning\n");
 465                 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
 466                 ret = IRQ_HANDLED;
 467         }
 468
 469         if (interrupts & LPAIF_IRQ_ERR(chan)) {
 470                 rv = regmap_write(drvdata->lpaif_map,
 471                                 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
 472                                 LPAIF_IRQ_ERR(chan));
 473                 if (rv) {
 474                         dev_err(soc_runtime->dev,
 475                                 "error writing to irqclear reg: %d\n", rv);
 476                         return IRQ_NONE;
 477                 }
 478                 dev_err(soc_runtime->dev, "bus access error\n");
 479                 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
 480                 ret = IRQ_HANDLED;
 481         }
 482
 483         return ret;
 484 }
 485
 486 static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
 487 {
 488         struct lpass_data *drvdata = data;
 489         struct lpass_variant *v = drvdata->variant;
 490         unsigned int irqs;
 491         int rv, chan;
 492
 493         rv = regmap_read(drvdata->lpaif_map,
 494                         LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
 495         if (rv) {
 496                 pr_err("error reading from irqstat reg: %d\n", rv);
 497                 return IRQ_NONE;
 498         }
 499
 500         /* Handle per channel interrupts */
 501         for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
 502                 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
 503                         rv = lpass_dma_interrupt_handler(
 504                                                 drvdata->substream[chan],
 505                                                 drvdata, chan, irqs);
 506                         if (rv != IRQ_HANDLED)
 507                                 return rv;
 508                 }
 509         }
 510
 511         return IRQ_HANDLED;
 512 }
 513
 514 static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
 515 {
 516         struct snd_pcm *pcm = soc_runtime->pcm;
 517         struct snd_pcm_substream *psubstream, *csubstream;
 518         int ret = -EINVAL;
 519         size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
 520
 521         psubstream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
 522         if (psubstream) {
 523                 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 524                                         soc_runtime->platform->dev,
 525                                         size, &psubstream->dma_buffer);
 526                 if (ret) {
 527                         dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
 528                         return ret;
 529                 }
 530         }
 531
 532         csubstream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
 533         if (csubstream) {
 534                 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 535                                         soc_runtime->platform->dev,
 536                                         size, &csubstream->dma_buffer);
 537                 if (ret) {
 538                         dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
 539                         if (psubstream)
 540                                 snd_dma_free_pages(&psubstream->dma_buffer);
 541                         return ret;
 542                 }
 543
 544         }
 545
 546         return 0;
 547 }
 548
 549 static void lpass_platform_pcm_free(struct snd_pcm *pcm)
 550 {
 551         struct snd_pcm_substream *substream;
 552         int i;
 553
 554         for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
 555                 substream = pcm->streams[i].substream;
 556                 if (substream) {
 557                         snd_dma_free_pages(&substream->dma_buffer);
 558                         substream->dma_buffer.area = NULL;
 559                         substream->dma_buffer.addr = 0;
 560                 }
 561         }
 562 }
 563
 564 static const struct snd_soc_platform_driver lpass_platform_driver = {
 565         .pcm_new        = lpass_platform_pcm_new,
 566         .pcm_free       = lpass_platform_pcm_free,
 567         .ops            = &lpass_platform_pcm_ops,
 568 };
 569
 570 int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
 571 {
 572         struct lpass_data *drvdata = platform_get_drvdata(pdev);
 573         struct lpass_variant *v = drvdata->variant;
 574         int ret;
 575
 576         drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
 577         if (drvdata->lpaif_irq < 0) {
 578                 dev_err(&pdev->dev, "error getting irq handle: %d\n",
 579                         drvdata->lpaif_irq);
 580                 return -ENODEV;
 581         }
 582
 583         /* ensure audio hardware is disabled */
 584         ret = regmap_write(drvdata->lpaif_map,
 585                         LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
 586         if (ret) {
 587                 dev_err(&pdev->dev, "error writing to irqen reg: %d\n", ret);
 588                 return ret;
 589         }
 590
 591         ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
 592                         lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
 593                         "lpass-irq-lpaif", drvdata);
 594         if (ret) {
 595                 dev_err(&pdev->dev, "irq request failed: %d\n", ret);
 596                 return ret;
 597         }
 598
 599
 600         return devm_snd_soc_register_platform(&pdev->dev,
 601                         &lpass_platform_driver);
 602 }
 603 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
 604
 605 MODULE_DESCRIPTION("QTi LPASS Platform Driver");
 606 MODULE_LICENSE("GPL v2");