sound/soc/rockchip/rockchip_spdif.c

   1 /* sound/soc/rockchip/rk_spdif.c
   2  *
   3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
   4  *
   5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
   6  * Author: Jianqun <jay.xu@rock-chips.com>
   7  * Copyright (c) 2015 Collabora Ltd.
   8  * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/delay.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/mfd/syscon.h>
  21 #include <linux/regmap.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/dmaengine_pcm.h>
  24
  25 #include "rockchip_spdif.h"
  26
  27 enum rk_spdif_type {
  28         RK_SPDIF_RK3066,
  29         RK_SPDIF_RK3188,
  30         RK_SPDIF_RK3288,
  31         RK_SPDIF_RK3366,
  32 };
  33
  34 #define RK3288_GRF_SOC_CON2 0x24c
  35
  36 struct rk_spdif_dev {
  37         struct device *dev;
  38
  39         struct clk *mclk;
  40         struct clk *hclk;
  41
  42         struct snd_dmaengine_dai_dma_data playback_dma_data;
  43
  44         struct regmap *regmap;
  45 };
  46
  47 static const struct of_device_id rk_spdif_match[] = {
  48         { .compatible = "rockchip,rk3066-spdif",
  49           .data = (void *)RK_SPDIF_RK3066 },
  50         { .compatible = "rockchip,rk3188-spdif",
  51           .data = (void *)RK_SPDIF_RK3188 },
  52         { .compatible = "rockchip,rk3228-spdif",
  53           .data = (void *)RK_SPDIF_RK3366 },
  54         { .compatible = "rockchip,rk3288-spdif",
  55           .data = (void *)RK_SPDIF_RK3288 },
  56         { .compatible = "rockchip,rk3328-spdif",
  57           .data = (void *)RK_SPDIF_RK3366 },
  58         { .compatible = "rockchip,rk3366-spdif",
  59           .data = (void *)RK_SPDIF_RK3366 },
  60         { .compatible = "rockchip,rk3368-spdif",
  61           .data = (void *)RK_SPDIF_RK3366 },
  62         { .compatible = "rockchip,rk3399-spdif",
  63           .data = (void *)RK_SPDIF_RK3366 },
  64         {},
  65 };
  66 MODULE_DEVICE_TABLE(of, rk_spdif_match);
  67
  68 static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev)
  69 {
  70         struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
  71
  72         regcache_cache_only(spdif->regmap, true);
  73         clk_disable_unprepare(spdif->mclk);
  74         clk_disable_unprepare(spdif->hclk);
  75
  76         return 0;
  77 }
  78
  79 static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
  80 {
  81         struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
  82         int ret;
  83
  84         ret = clk_prepare_enable(spdif->mclk);
  85         if (ret) {
  86                 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
  87                 return ret;
  88         }
  89
  90         ret = clk_prepare_enable(spdif->hclk);
  91         if (ret) {
  92                 clk_disable_unprepare(spdif->mclk);
  93                 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
  94                 return ret;
  95         }
  96
  97         regcache_cache_only(spdif->regmap, false);
  98         regcache_mark_dirty(spdif->regmap);
  99
 100         ret = regcache_sync(spdif->regmap);
 101         if (ret) {
 102                 clk_disable_unprepare(spdif->mclk);
 103                 clk_disable_unprepare(spdif->hclk);
 104         }
 105
 106         return ret;
 107 }
 108
 109 static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
 110                                   struct snd_pcm_hw_params *params,
 111                                   struct snd_soc_dai *dai)
 112 {
 113         struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
 114         unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
 115         int srate, mclk;
 116         int ret;
 117
 118         srate = params_rate(params);
 119         mclk = srate * 128;
 120
 121         switch (params_format(params)) {
 122         case SNDRV_PCM_FORMAT_S16_LE:
 123                 val |= SPDIF_CFGR_VDW_16;
 124                 break;
 125         case SNDRV_PCM_FORMAT_S20_3LE:
 126                 val |= SPDIF_CFGR_VDW_20;
 127                 break;
 128         case SNDRV_PCM_FORMAT_S24_LE:
 129                 val |= SPDIF_CFGR_VDW_24;
 130                 break;
 131         default:
 132                 return -EINVAL;
 133         }
 134
 135         /* Set clock and calculate divider */
 136         ret = clk_set_rate(spdif->mclk, mclk);
 137         if (ret != 0) {
 138                 dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
 139                         ret);
 140                 return ret;
 141         }
 142
 143         ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
 144                 SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE |
 145                 SDPIF_CFGR_VDW_MASK,
 146                 val);
 147
 148         return ret;
 149 }
 150
 151 static int rk_spdif_trigger(struct snd_pcm_substream *substream,
 152                                 int cmd, struct snd_soc_dai *dai)
 153 {
 154         struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
 155         int ret;
 156
 157         switch (cmd) {
 158         case SNDRV_PCM_TRIGGER_START:
 159         case SNDRV_PCM_TRIGGER_RESUME:
 160         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 161                 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
 162                                    SPDIF_DMACR_TDE_ENABLE |
 163                                    SPDIF_DMACR_TDL_MASK,
 164                                    SPDIF_DMACR_TDE_ENABLE |
 165                                    SPDIF_DMACR_TDL(16));
 166
 167                 if (ret != 0)
 168                         return ret;
 169
 170                 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
 171                                    SPDIF_XFER_TXS_START,
 172                                    SPDIF_XFER_TXS_START);
 173                 break;
 174         case SNDRV_PCM_TRIGGER_SUSPEND:
 175         case SNDRV_PCM_TRIGGER_STOP:
 176         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 177                 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
 178                                    SPDIF_DMACR_TDE_ENABLE,
 179                                    SPDIF_DMACR_TDE_DISABLE);
 180
 181                 if (ret != 0)
 182                         return ret;
 183
 184                 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
 185                                    SPDIF_XFER_TXS_START,
 186                                    SPDIF_XFER_TXS_STOP);
 187                 break;
 188         default:
 189                 ret = -EINVAL;
 190                 break;
 191         }
 192
 193         return ret;
 194 }
 195
 196 static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
 197 {
 198         struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
 199
 200         dai->playback_dma_data = &spdif->playback_dma_data;
 201
 202         return 0;
 203 }
 204
 205 static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
 206         .hw_params = rk_spdif_hw_params,
 207         .trigger = rk_spdif_trigger,
 208 };
 209
 210 static struct snd_soc_dai_driver rk_spdif_dai = {
 211         .probe = rk_spdif_dai_probe,
 212         .playback = {
 213                 .stream_name = "Playback",
 214                 .channels_min = 2,
 215                 .channels_max = 2,
 216                 .rates = (SNDRV_PCM_RATE_32000 |
 217                           SNDRV_PCM_RATE_44100 |
 218                           SNDRV_PCM_RATE_48000 |
 219                           SNDRV_PCM_RATE_96000 |
 220                           SNDRV_PCM_RATE_192000),
 221                 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
 222                             SNDRV_PCM_FMTBIT_S20_3LE |
 223                             SNDRV_PCM_FMTBIT_S24_LE),
 224         },
 225         .ops = &rk_spdif_dai_ops,
 226 };
 227
 228 static const struct snd_soc_component_driver rk_spdif_component = {
 229         .name = "rockchip-spdif",
 230 };
 231
 232 static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
 233 {
 234         switch (reg) {
 235         case SPDIF_CFGR:
 236         case SPDIF_DMACR:
 237         case SPDIF_INTCR:
 238         case SPDIF_XFER:
 239         case SPDIF_SMPDR:
 240                 return true;
 241         default:
 242                 return false;
 243         }
 244 }
 245
 246 static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
 247 {
 248         switch (reg) {
 249         case SPDIF_CFGR:
 250         case SPDIF_SDBLR:
 251         case SPDIF_INTCR:
 252         case SPDIF_INTSR:
 253         case SPDIF_XFER:
 254                 return true;
 255         default:
 256                 return false;
 257         }
 258 }
 259
 260 static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
 261 {
 262         switch (reg) {
 263         case SPDIF_INTSR:
 264         case SPDIF_SDBLR:
 265                 return true;
 266         default:
 267                 return false;
 268         }
 269 }
 270
 271 static const struct regmap_config rk_spdif_regmap_config = {
 272         .reg_bits = 32,
 273         .reg_stride = 4,
 274         .val_bits = 32,
 275         .max_register = SPDIF_SMPDR,
 276         .writeable_reg = rk_spdif_wr_reg,
 277         .readable_reg = rk_spdif_rd_reg,
 278         .volatile_reg = rk_spdif_volatile_reg,
 279         .cache_type = REGCACHE_FLAT,
 280 };
 281
 282 static int rk_spdif_probe(struct platform_device *pdev)
 283 {
 284         struct device_node *np = pdev->dev.of_node;
 285         struct rk_spdif_dev *spdif;
 286         const struct of_device_id *match;
 287         struct resource *res;
 288         void __iomem *regs;
 289         int ret;
 290
 291         match = of_match_node(rk_spdif_match, np);
 292         if (match->data == (void *)RK_SPDIF_RK3288) {
 293                 struct regmap *grf;
 294
 295                 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 296                 if (IS_ERR(grf)) {
 297                         dev_err(&pdev->dev,
 298                                 "rockchip_spdif missing 'rockchip,grf' \n");
 299                         return PTR_ERR(grf);
 300                 }
 301
 302                 /* Select the 8 channel SPDIF solution on RK3288 as
 303                  * the 2 channel one does not appear to work
 304                  */
 305                 regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
 306         }
 307
 308         spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
 309         if (!spdif)
 310                 return -ENOMEM;
 311
 312         spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
 313         if (IS_ERR(spdif->hclk)) {
 314                 dev_err(&pdev->dev, "Can't retrieve rk_spdif bus clock\n");
 315                 return PTR_ERR(spdif->hclk);
 316         }
 317         ret = clk_prepare_enable(spdif->hclk);
 318         if (ret) {
 319                 dev_err(spdif->dev, "hclock enable failed %d\n", ret);
 320                 return ret;
 321         }
 322
 323         spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
 324         if (IS_ERR(spdif->mclk)) {
 325                 dev_err(&pdev->dev, "Can't retrieve rk_spdif master clock\n");
 326                 ret = PTR_ERR(spdif->mclk);
 327                 goto err_disable_hclk;
 328         }
 329
 330         ret = clk_prepare_enable(spdif->mclk);
 331         if (ret) {
 332                 dev_err(spdif->dev, "clock enable failed %d\n", ret);
 333                 goto err_disable_clocks;
 334         }
 335
 336         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 337         regs = devm_ioremap_resource(&pdev->dev, res);
 338         if (IS_ERR(regs)) {
 339                 ret = PTR_ERR(regs);
 340                 goto err_disable_clocks;
 341         }
 342
 343         spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
 344                                                   &rk_spdif_regmap_config);
 345         if (IS_ERR(spdif->regmap)) {
 346                 dev_err(&pdev->dev,
 347                         "Failed to initialise managed register map\n");
 348                 ret = PTR_ERR(spdif->regmap);
 349                 goto err_disable_clocks;
 350         }
 351
 352         spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
 353         spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 354         spdif->playback_dma_data.maxburst = 4;
 355
 356         spdif->dev = &pdev->dev;
 357         dev_set_drvdata(&pdev->dev, spdif);
 358
 359         pm_runtime_set_active(&pdev->dev);
 360         pm_runtime_enable(&pdev->dev);
 361         pm_request_idle(&pdev->dev);
 362
 363         ret = devm_snd_soc_register_component(&pdev->dev,
 364                                               &rk_spdif_component,
 365                                               &rk_spdif_dai, 1);
 366         if (ret) {
 367                 dev_err(&pdev->dev, "Could not register DAI\n");
 368                 goto err_pm_runtime;
 369         }
 370
 371         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 372         if (ret) {
 373                 dev_err(&pdev->dev, "Could not register PCM\n");
 374                 goto err_pm_runtime;
 375         }
 376
 377         return 0;
 378
 379 err_pm_runtime:
 380         pm_runtime_disable(&pdev->dev);
 381 err_disable_clocks:
 382         clk_disable_unprepare(spdif->mclk);
 383 err_disable_hclk:
 384         clk_disable_unprepare(spdif->hclk);
 385
 386         return ret;
 387 }
 388
 389 static int rk_spdif_remove(struct platform_device *pdev)
 390 {
 391         struct rk_spdif_dev *spdif = dev_get_drvdata(&pdev->dev);
 392
 393         pm_runtime_disable(&pdev->dev);
 394         if (!pm_runtime_status_suspended(&pdev->dev))
 395                 rk_spdif_runtime_suspend(&pdev->dev);
 396
 397         clk_disable_unprepare(spdif->mclk);
 398         clk_disable_unprepare(spdif->hclk);
 399
 400         return 0;
 401 }
 402
 403 static const struct dev_pm_ops rk_spdif_pm_ops = {
 404         SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
 405                            NULL)
 406 };
 407
 408 static struct platform_driver rk_spdif_driver = {
 409         .probe = rk_spdif_probe,
 410         .remove = rk_spdif_remove,
 411         .driver = {
 412                 .name = "rockchip-spdif",
 413                 .of_match_table = of_match_ptr(rk_spdif_match),
 414                 .pm = &rk_spdif_pm_ops,
 415         },
 416 };
 417 module_platform_driver(rk_spdif_driver);
 418
 419 MODULE_ALIAS("platform:rockchip-spdif");
 420 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
 421 MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
 422 MODULE_LICENSE("GPL v2");