sound/soc/stm/stm32_i2s.c

   1 /*
   2  *  STM32 ALSA SoC Digital Audio Interface (I2S) driver.
   3  *
   4  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   5  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
   6  *
   7  * License terms: GPL V2.0.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  16  * details.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/module.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/regmap.h>
  25 #include <linux/reset.h>
  26 #include <linux/spinlock.h>
  27
  28 #include <sound/dmaengine_pcm.h>
  29 #include <sound/pcm_params.h>
  30
  31 #define STM32_I2S_CR1_REG       0x0
  32 #define STM32_I2S_CFG1_REG      0x08
  33 #define STM32_I2S_CFG2_REG      0x0C
  34 #define STM32_I2S_IER_REG       0x10
  35 #define STM32_I2S_SR_REG        0x14
  36 #define STM32_I2S_IFCR_REG      0x18
  37 #define STM32_I2S_TXDR_REG      0X20
  38 #define STM32_I2S_RXDR_REG      0x30
  39 #define STM32_I2S_CGFR_REG      0X50
  40
  41 /* Bit definition for SPI2S_CR1 register */
  42 #define I2S_CR1_SPE             BIT(0)
  43 #define I2S_CR1_CSTART          BIT(9)
  44 #define I2S_CR1_CSUSP           BIT(10)
  45 #define I2S_CR1_HDDIR           BIT(11)
  46 #define I2S_CR1_SSI             BIT(12)
  47 #define I2S_CR1_CRC33_17        BIT(13)
  48 #define I2S_CR1_RCRCI           BIT(14)
  49 #define I2S_CR1_TCRCI           BIT(15)
  50
  51 /* Bit definition for SPI_CFG2 register */
  52 #define I2S_CFG2_IOSWP_SHIFT    15
  53 #define I2S_CFG2_IOSWP          BIT(I2S_CFG2_IOSWP_SHIFT)
  54 #define I2S_CFG2_LSBFRST        BIT(23)
  55 #define I2S_CFG2_AFCNTR         BIT(31)
  56
  57 /* Bit definition for SPI_CFG1 register */
  58 #define I2S_CFG1_FTHVL_SHIFT    5
  59 #define I2S_CFG1_FTHVL_MASK     GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
  60 #define I2S_CFG1_FTHVL_SET(x)   ((x) << I2S_CFG1_FTHVL_SHIFT)
  61
  62 #define I2S_CFG1_TXDMAEN        BIT(15)
  63 #define I2S_CFG1_RXDMAEN        BIT(14)
  64
  65 /* Bit definition for SPI2S_IER register */
  66 #define I2S_IER_RXPIE           BIT(0)
  67 #define I2S_IER_TXPIE           BIT(1)
  68 #define I2S_IER_DPXPIE          BIT(2)
  69 #define I2S_IER_EOTIE           BIT(3)
  70 #define I2S_IER_TXTFIE          BIT(4)
  71 #define I2S_IER_UDRIE           BIT(5)
  72 #define I2S_IER_OVRIE           BIT(6)
  73 #define I2S_IER_CRCEIE          BIT(7)
  74 #define I2S_IER_TIFREIE         BIT(8)
  75 #define I2S_IER_MODFIE          BIT(9)
  76 #define I2S_IER_TSERFIE         BIT(10)
  77
  78 /* Bit definition for SPI2S_SR register */
  79 #define I2S_SR_RXP              BIT(0)
  80 #define I2S_SR_TXP              BIT(1)
  81 #define I2S_SR_DPXP             BIT(2)
  82 #define I2S_SR_EOT              BIT(3)
  83 #define I2S_SR_TXTF             BIT(4)
  84 #define I2S_SR_UDR              BIT(5)
  85 #define I2S_SR_OVR              BIT(6)
  86 #define I2S_SR_CRCERR           BIT(7)
  87 #define I2S_SR_TIFRE            BIT(8)
  88 #define I2S_SR_MODF             BIT(9)
  89 #define I2S_SR_TSERF            BIT(10)
  90 #define I2S_SR_SUSP             BIT(11)
  91 #define I2S_SR_TXC              BIT(12)
  92 #define I2S_SR_RXPLVL           GENMASK(14, 13)
  93 #define I2S_SR_RXWNE            BIT(15)
  94
  95 #define I2S_SR_MASK             GENMASK(15, 0)
  96
  97 /* Bit definition for SPI_IFCR register */
  98 #define I2S_IFCR_EOTC           BIT(3)
  99 #define I2S_IFCR_TXTFC          BIT(4)
 100 #define I2S_IFCR_UDRC           BIT(5)
 101 #define I2S_IFCR_OVRC           BIT(6)
 102 #define I2S_IFCR_CRCEC          BIT(7)
 103 #define I2S_IFCR_TIFREC         BIT(8)
 104 #define I2S_IFCR_MODFC          BIT(9)
 105 #define I2S_IFCR_TSERFC         BIT(10)
 106 #define I2S_IFCR_SUSPC          BIT(11)
 107
 108 #define I2S_IFCR_MASK           GENMASK(11, 3)
 109
 110 /* Bit definition for SPI_I2SCGFR register */
 111 #define I2S_CGFR_I2SMOD         BIT(0)
 112
 113 #define I2S_CGFR_I2SCFG_SHIFT   1
 114 #define I2S_CGFR_I2SCFG_MASK    GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
 115 #define I2S_CGFR_I2SCFG_SET(x)  ((x) << I2S_CGFR_I2SCFG_SHIFT)
 116
 117 #define I2S_CGFR_I2SSTD_SHIFT   4
 118 #define I2S_CGFR_I2SSTD_MASK    GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
 119 #define I2S_CGFR_I2SSTD_SET(x)  ((x) << I2S_CGFR_I2SSTD_SHIFT)
 120
 121 #define I2S_CGFR_PCMSYNC        BIT(7)
 122
 123 #define I2S_CGFR_DATLEN_SHIFT   8
 124 #define I2S_CGFR_DATLEN_MASK    GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
 125 #define I2S_CGFR_DATLEN_SET(x)  ((x) << I2S_CGFR_DATLEN_SHIFT)
 126
 127 #define I2S_CGFR_CHLEN_SHIFT    10
 128 #define I2S_CGFR_CHLEN          BIT(I2S_CGFR_CHLEN_SHIFT)
 129 #define I2S_CGFR_CKPOL          BIT(11)
 130 #define I2S_CGFR_FIXCH          BIT(12)
 131 #define I2S_CGFR_WSINV          BIT(13)
 132 #define I2S_CGFR_DATFMT         BIT(14)
 133
 134 #define I2S_CGFR_I2SDIV_SHIFT   16
 135 #define I2S_CGFR_I2SDIV_BIT_H   23
 136 #define I2S_CGFR_I2SDIV_MASK    GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
 137                                 I2S_CGFR_I2SDIV_SHIFT)
 138 #define I2S_CGFR_I2SDIV_SET(x)  ((x) << I2S_CGFR_I2SDIV_SHIFT)
 139 #define I2S_CGFR_I2SDIV_MAX     ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
 140                                 I2S_CGFR_I2SDIV_SHIFT)) - 1)
 141
 142 #define I2S_CGFR_ODD_SHIFT      24
 143 #define I2S_CGFR_ODD            BIT(I2S_CGFR_ODD_SHIFT)
 144 #define I2S_CGFR_MCKOE          BIT(25)
 145
 146 enum i2s_master_mode {
 147         I2S_MS_NOT_SET,
 148         I2S_MS_MASTER,
 149         I2S_MS_SLAVE,
 150 };
 151
 152 enum i2s_mode {
 153         I2S_I2SMOD_TX_SLAVE,
 154         I2S_I2SMOD_RX_SLAVE,
 155         I2S_I2SMOD_TX_MASTER,
 156         I2S_I2SMOD_RX_MASTER,
 157         I2S_I2SMOD_FD_SLAVE,
 158         I2S_I2SMOD_FD_MASTER,
 159 };
 160
 161 enum i2s_fifo_th {
 162         I2S_FIFO_TH_NONE,
 163         I2S_FIFO_TH_ONE_QUARTER,
 164         I2S_FIFO_TH_HALF,
 165         I2S_FIFO_TH_THREE_QUARTER,
 166         I2S_FIFO_TH_FULL,
 167 };
 168
 169 enum i2s_std {
 170         I2S_STD_I2S,
 171         I2S_STD_LEFT_J,
 172         I2S_STD_RIGHT_J,
 173         I2S_STD_DSP,
 174 };
 175
 176 enum i2s_datlen {
 177         I2S_I2SMOD_DATLEN_16,
 178         I2S_I2SMOD_DATLEN_24,
 179         I2S_I2SMOD_DATLEN_32,
 180 };
 181
 182 #define STM32_I2S_DAI_NAME_SIZE         20
 183 #define STM32_I2S_FIFO_SIZE             16
 184
 185 #define STM32_I2S_IS_MASTER(x)          ((x)->ms_flg == I2S_MS_MASTER)
 186 #define STM32_I2S_IS_SLAVE(x)           ((x)->ms_flg == I2S_MS_SLAVE)
 187
 188 /**
 189  * @regmap_conf: I2S register map configuration pointer
 190  * @egmap: I2S register map pointer
 191  * @pdev: device data pointer
 192  * @dai_drv: DAI driver pointer
 193  * @dma_data_tx: dma configuration data for tx channel
 194  * @dma_data_rx: dma configuration data for tx channel
 195  * @substream: PCM substream data pointer
 196  * @i2sclk: kernel clock feeding the I2S clock generator
 197  * @pclk: peripheral clock driving bus interface
 198  * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
 199  * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
 200  * @base:  mmio register base virtual address
 201  * @phys_addr: I2S registers physical base address
 202  * @lock_fd: lock to manage race conditions in full duplex mode
 203  * @dais_name: DAI name
 204  * @mclk_rate: master clock frequency (Hz)
 205  * @fmt: DAI protocol
 206  * @refcount: keep count of opened streams on I2S
 207  * @ms_flg: master mode flag.
 208  */
 209 struct stm32_i2s_data {
 210         const struct regmap_config *regmap_conf;
 211         struct regmap *regmap;
 212         struct platform_device *pdev;
 213         struct snd_soc_dai_driver *dai_drv;
 214         struct snd_dmaengine_dai_dma_data dma_data_tx;
 215         struct snd_dmaengine_dai_dma_data dma_data_rx;
 216         struct snd_pcm_substream *substream;
 217         struct clk *i2sclk;
 218         struct clk *pclk;
 219         struct clk *x8kclk;
 220         struct clk *x11kclk;
 221         void __iomem *base;
 222         dma_addr_t phys_addr;
 223         spinlock_t lock_fd; /* Manage race conditions for full duplex */
 224         char dais_name[STM32_I2S_DAI_NAME_SIZE];
 225         unsigned int mclk_rate;
 226         unsigned int fmt;
 227         int refcount;
 228         int ms_flg;
 229 };
 230
 231 static irqreturn_t stm32_i2s_isr(int irq, void *devid)
 232 {
 233         struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
 234         struct platform_device *pdev = i2s->pdev;
 235         u32 sr, ier;
 236         unsigned long flags;
 237         int err = 0;
 238
 239         regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
 240         regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
 241
 242         flags = sr & ier;
 243         if (!flags) {
 244                 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
 245                         sr, ier);
 246                 return IRQ_NONE;
 247         }
 248
 249         regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 250                           I2S_IFCR_MASK, flags);
 251
 252         if (flags & I2S_SR_OVR) {
 253                 dev_dbg(&pdev->dev, "Overrun\n");
 254                 err = 1;
 255         }
 256
 257         if (flags & I2S_SR_UDR) {
 258                 dev_dbg(&pdev->dev, "Underrun\n");
 259                 err = 1;
 260         }
 261
 262         if (flags & I2S_SR_TIFRE)
 263                 dev_dbg(&pdev->dev, "Frame error\n");
 264
 265         if (err)
 266                 snd_pcm_stop_xrun(i2s->substream);
 267
 268         return IRQ_HANDLED;
 269 }
 270
 271 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
 272 {
 273         switch (reg) {
 274         case STM32_I2S_CR1_REG:
 275         case STM32_I2S_CFG1_REG:
 276         case STM32_I2S_CFG2_REG:
 277         case STM32_I2S_IER_REG:
 278         case STM32_I2S_SR_REG:
 279         case STM32_I2S_TXDR_REG:
 280         case STM32_I2S_RXDR_REG:
 281         case STM32_I2S_CGFR_REG:
 282                 return true;
 283         default:
 284                 return false;
 285         }
 286 }
 287
 288 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
 289 {
 290         switch (reg) {
 291         case STM32_I2S_TXDR_REG:
 292         case STM32_I2S_RXDR_REG:
 293                 return true;
 294         default:
 295                 return false;
 296         }
 297 }
 298
 299 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
 300 {
 301         switch (reg) {
 302         case STM32_I2S_CR1_REG:
 303         case STM32_I2S_CFG1_REG:
 304         case STM32_I2S_CFG2_REG:
 305         case STM32_I2S_IER_REG:
 306         case STM32_I2S_IFCR_REG:
 307         case STM32_I2S_TXDR_REG:
 308         case STM32_I2S_CGFR_REG:
 309                 return true;
 310         default:
 311                 return false;
 312         }
 313 }
 314
 315 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 316 {
 317         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 318         u32 cgfr;
 319         u32 cgfr_mask =  I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
 320                          I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
 321
 322         dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
 323
 324         /*
 325          * winv = 0 : default behavior (high/low) for all standards
 326          * ckpol = 0 for all standards.
 327          */
 328         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 329         case SND_SOC_DAIFMT_I2S:
 330                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
 331                 break;
 332         case SND_SOC_DAIFMT_MSB:
 333                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
 334                 break;
 335         case SND_SOC_DAIFMT_LSB:
 336                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
 337                 break;
 338         case SND_SOC_DAIFMT_DSP_A:
 339                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
 340                 break;
 341         /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
 342         default:
 343                 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
 344                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 345                 return -EINVAL;
 346         }
 347
 348         /* DAI clock strobing */
 349         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 350         case SND_SOC_DAIFMT_NB_NF:
 351                 break;
 352         case SND_SOC_DAIFMT_IB_NF:
 353                 cgfr |= I2S_CGFR_CKPOL;
 354                 break;
 355         case SND_SOC_DAIFMT_NB_IF:
 356                 cgfr |= I2S_CGFR_WSINV;
 357                 break;
 358         case SND_SOC_DAIFMT_IB_IF:
 359                 cgfr |= I2S_CGFR_CKPOL;
 360                 cgfr |= I2S_CGFR_WSINV;
 361                 break;
 362         default:
 363                 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
 364                         fmt & SND_SOC_DAIFMT_INV_MASK);
 365                 return -EINVAL;
 366         }
 367
 368         /* DAI clock master masks */
 369         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 370         case SND_SOC_DAIFMT_CBM_CFM:
 371                 i2s->ms_flg = I2S_MS_SLAVE;
 372                 break;
 373         case SND_SOC_DAIFMT_CBS_CFS:
 374                 i2s->ms_flg = I2S_MS_MASTER;
 375                 break;
 376         default:
 377                 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
 378                         fmt & SND_SOC_DAIFMT_MASTER_MASK);
 379                 return -EINVAL;
 380         }
 381
 382         i2s->fmt = fmt;
 383         return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 384                                   cgfr_mask, cgfr);
 385 }
 386
 387 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 388                                 int clk_id, unsigned int freq, int dir)
 389 {
 390         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 391
 392         dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq);
 393
 394         if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) {
 395                 i2s->mclk_rate = freq;
 396
 397                 /* Enable master clock if master mode and mclk-fs are set */
 398                 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 399                                           I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
 400         }
 401
 402         return 0;
 403 }
 404
 405 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
 406                                      struct snd_pcm_hw_params *params)
 407 {
 408         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 409         unsigned long i2s_clock_rate;
 410         unsigned int tmp, div, real_div, nb_bits, frame_len;
 411         unsigned int rate = params_rate(params);
 412         int ret;
 413         u32 cgfr, cgfr_mask;
 414         bool odd;
 415
 416         if (!(rate % 11025))
 417                 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
 418         else
 419                 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
 420         i2s_clock_rate = clk_get_rate(i2s->i2sclk);
 421
 422         /*
 423          * mckl = mclk_ratio x ws
 424          *   i2s mode : mclk_ratio = 256
 425          *   dsp mode : mclk_ratio = 128
 426          *
 427          * mclk on
 428          *   i2s mode : div = i2s_clk / (mclk_ratio * ws)
 429          *   dsp mode : div = i2s_clk / (mclk_ratio * ws)
 430          * mclk off
 431          *   i2s mode : div = i2s_clk / (nb_bits x ws)
 432          *   dsp mode : div = i2s_clk / (nb_bits x ws)
 433          */
 434         if (i2s->mclk_rate) {
 435                 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate);
 436         } else {
 437                 frame_len = 32;
 438                 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
 439                     SND_SOC_DAIFMT_DSP_A)
 440                         frame_len = 16;
 441
 442                 /* master clock not enabled */
 443                 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
 444                 if (ret < 0)
 445                         return ret;
 446
 447                 nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
 448                 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate));
 449         }
 450
 451         /* Check the parity of the divider */
 452         odd = tmp & 0x1;
 453
 454         /* Compute the div prescaler */
 455         div = tmp >> 1;
 456
 457         cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT);
 458         cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
 459
 460         real_div = ((2 * div) + odd);
 461         dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n",
 462                 i2s_clock_rate, rate);
 463         dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
 464                 div, odd, real_div);
 465
 466         if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) {
 467                 dev_err(cpu_dai->dev, "Wrong divider setting\n");
 468                 return -EINVAL;
 469         }
 470
 471         if (!div && !odd)
 472                 dev_warn(cpu_dai->dev, "real divider forced to 1\n");
 473
 474         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 475                                  cgfr_mask, cgfr);
 476         if (ret < 0)
 477                 return ret;
 478
 479         /* Set bitclock and frameclock to their inactive state */
 480         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
 481                                   I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
 482 }
 483
 484 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
 485                                struct snd_pcm_hw_params *params,
 486                                struct snd_pcm_substream *substream)
 487 {
 488         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 489         int format = params_width(params);
 490         u32 cfgr, cfgr_mask, cfg1;
 491         unsigned int fthlv;
 492         int ret;
 493
 494         if ((params_channels(params) == 1) &&
 495             ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)) {
 496                 dev_err(cpu_dai->dev, "Mono mode supported only by DSP_A\n");
 497                 return -EINVAL;
 498         }
 499
 500         switch (format) {
 501         case 16:
 502                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
 503                 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 504                 break;
 505         case 32:
 506                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
 507                                            I2S_CGFR_CHLEN;
 508                 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 509                 break;
 510         default:
 511                 dev_err(cpu_dai->dev, "Unexpected format %d", format);
 512                 return -EINVAL;
 513         }
 514
 515         if (STM32_I2S_IS_SLAVE(i2s)) {
 516                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
 517
 518                 /* As data length is either 16 or 32 bits, fixch always set */
 519                 cfgr |= I2S_CGFR_FIXCH;
 520                 cfgr_mask |= I2S_CGFR_FIXCH;
 521         } else {
 522                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
 523         }
 524         cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
 525
 526         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 527                                  cfgr_mask, cfgr);
 528         if (ret < 0)
 529                 return ret;
 530
 531         fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
 532         cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
 533
 534         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 535                                   I2S_CFG1_FTHVL_MASK, cfg1);
 536 }
 537
 538 static int stm32_i2s_startup(struct snd_pcm_substream *substream,
 539                              struct snd_soc_dai *cpu_dai)
 540 {
 541         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 542
 543         i2s->substream = substream;
 544
 545         spin_lock(&i2s->lock_fd);
 546         i2s->refcount++;
 547         spin_unlock(&i2s->lock_fd);
 548
 549         return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 550                                  I2S_IFCR_MASK, I2S_IFCR_MASK);
 551 }
 552
 553 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
 554                                struct snd_pcm_hw_params *params,
 555                                struct snd_soc_dai *cpu_dai)
 556 {
 557         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 558         int ret;
 559
 560         ret = stm32_i2s_configure(cpu_dai, params, substream);
 561         if (ret < 0) {
 562                 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
 563                 return ret;
 564         }
 565
 566         if (STM32_I2S_IS_MASTER(i2s))
 567                 ret = stm32_i2s_configure_clock(cpu_dai, params);
 568
 569         return ret;
 570 }
 571
 572 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 573                              struct snd_soc_dai *cpu_dai)
 574 {
 575         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 576         bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 577         u32 cfg1_mask, ier;
 578         int ret;
 579
 580         switch (cmd) {
 581         case SNDRV_PCM_TRIGGER_START:
 582         case SNDRV_PCM_TRIGGER_RESUME:
 583         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 584                 /* Enable i2s */
 585                 dev_dbg(cpu_dai->dev, "start I2S\n");
 586
 587                 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 588                 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 589                                    cfg1_mask, cfg1_mask);
 590
 591                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 592                                          I2S_CR1_SPE, I2S_CR1_SPE);
 593                 if (ret < 0) {
 594                         dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
 595                         return ret;
 596                 }
 597
 598                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 599                                          I2S_CR1_CSTART, I2S_CR1_CSTART);
 600                 if (ret < 0) {
 601                         dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
 602                         return ret;
 603                 }
 604
 605                 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 606                                   I2S_IFCR_MASK, I2S_IFCR_MASK);
 607
 608                 if (playback_flg) {
 609                         ier = I2S_IER_UDRIE;
 610                 } else {
 611                         ier = I2S_IER_OVRIE;
 612
 613                         spin_lock(&i2s->lock_fd);
 614                         if (i2s->refcount == 1)
 615                                 /* dummy write to trigger capture */
 616                                 regmap_write(i2s->regmap,
 617                                              STM32_I2S_TXDR_REG, 0);
 618                         spin_unlock(&i2s->lock_fd);
 619                 }
 620
 621                 if (STM32_I2S_IS_SLAVE(i2s))
 622                         ier |= I2S_IER_TIFREIE;
 623
 624                 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
 625                 break;
 626         case SNDRV_PCM_TRIGGER_STOP:
 627         case SNDRV_PCM_TRIGGER_SUSPEND:
 628         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 629                 if (playback_flg)
 630                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 631                                            I2S_IER_UDRIE,
 632                                            (unsigned int)~I2S_IER_UDRIE);
 633                 else
 634                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 635                                            I2S_IER_OVRIE,
 636                                            (unsigned int)~I2S_IER_OVRIE);
 637
 638                 spin_lock(&i2s->lock_fd);
 639                 i2s->refcount--;
 640                 if (i2s->refcount) {
 641                         spin_unlock(&i2s->lock_fd);
 642                         break;
 643                 }
 644                 spin_unlock(&i2s->lock_fd);
 645
 646                 dev_dbg(cpu_dai->dev, "stop I2S\n");
 647
 648                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 649                                          I2S_CR1_SPE, 0);
 650                 if (ret < 0) {
 651                         dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
 652                         return ret;
 653                 }
 654
 655                 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 656                 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 657                                    cfg1_mask, 0);
 658                 break;
 659         default:
 660                 return -EINVAL;
 661         }
 662
 663         return 0;
 664 }
 665
 666 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
 667                                struct snd_soc_dai *cpu_dai)
 668 {
 669         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 670
 671         i2s->substream = NULL;
 672
 673         regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 674                            I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
 675 }
 676
 677 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
 678 {
 679         struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
 680         struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
 681         struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
 682
 683         /* Buswidth will be set by framework */
 684         dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 685         dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
 686         dma_data_tx->maxburst = 1;
 687         dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 688         dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
 689         dma_data_rx->maxburst = 1;
 690
 691         snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
 692
 693         return 0;
 694 }
 695
 696 static const struct regmap_config stm32_h7_i2s_regmap_conf = {
 697         .reg_bits = 32,
 698         .reg_stride = 4,
 699         .val_bits = 32,
 700         .max_register = STM32_I2S_CGFR_REG,
 701         .readable_reg = stm32_i2s_readable_reg,
 702         .volatile_reg = stm32_i2s_volatile_reg,
 703         .writeable_reg = stm32_i2s_writeable_reg,
 704         .fast_io = true,
 705 };
 706
 707 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
 708         .set_sysclk     = stm32_i2s_set_sysclk,
 709         .set_fmt        = stm32_i2s_set_dai_fmt,
 710         .startup        = stm32_i2s_startup,
 711         .hw_params      = stm32_i2s_hw_params,
 712         .trigger        = stm32_i2s_trigger,
 713         .shutdown       = stm32_i2s_shutdown,
 714 };
 715
 716 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
 717         .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
 718         .buffer_bytes_max = 8 * PAGE_SIZE,
 719         .period_bytes_max = 2048,
 720         .periods_min = 2,
 721         .periods_max = 8,
 722 };
 723
 724 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
 725         .pcm_hardware   = &stm32_i2s_pcm_hw,
 726         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 727         .prealloc_buffer_size = PAGE_SIZE * 8,
 728 };
 729
 730 static const struct snd_soc_component_driver stm32_i2s_component = {
 731         .name = "stm32-i2s",
 732 };
 733
 734 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
 735                                char *stream_name)
 736 {
 737         stream->stream_name = stream_name;
 738         stream->channels_min = 1;
 739         stream->channels_max = 2;
 740         stream->rates = SNDRV_PCM_RATE_8000_192000;
 741         stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
 742                                    SNDRV_PCM_FMTBIT_S32_LE;
 743 }
 744
 745 static int stm32_i2s_dais_init(struct platform_device *pdev,
 746                                struct stm32_i2s_data *i2s)
 747 {
 748         struct snd_soc_dai_driver *dai_ptr;
 749
 750         dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
 751                                GFP_KERNEL);
 752         if (!dai_ptr)
 753                 return -ENOMEM;
 754
 755         snprintf(i2s->dais_name, STM32_I2S_DAI_NAME_SIZE,
 756                  "%s", dev_name(&pdev->dev));
 757
 758         dai_ptr->probe = stm32_i2s_dai_probe;
 759         dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
 760         dai_ptr->name = i2s->dais_name;
 761         dai_ptr->id = 1;
 762         stm32_i2s_dai_init(&dai_ptr->playback, "playback");
 763         stm32_i2s_dai_init(&dai_ptr->capture, "capture");
 764         i2s->dai_drv = dai_ptr;
 765
 766         return 0;
 767 }
 768
 769 static const struct of_device_id stm32_i2s_ids[] = {
 770         {
 771                 .compatible = "st,stm32h7-i2s",
 772                 .data = &stm32_h7_i2s_regmap_conf
 773         },
 774         {},
 775 };
 776
 777 static int stm32_i2s_parse_dt(struct platform_device *pdev,
 778                               struct stm32_i2s_data *i2s)
 779 {
 780         struct device_node *np = pdev->dev.of_node;
 781         const struct of_device_id *of_id;
 782         struct reset_control *rst;
 783         struct resource *res;
 784         int irq, ret;
 785
 786         if (!np)
 787                 return -ENODEV;
 788
 789         of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
 790         if (of_id)
 791                 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
 792         else
 793                 return -EINVAL;
 794
 795         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 796         i2s->base = devm_ioremap_resource(&pdev->dev, res);
 797         if (IS_ERR(i2s->base))
 798                 return PTR_ERR(i2s->base);
 799
 800         i2s->phys_addr = res->start;
 801
 802         /* Get clocks */
 803         i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
 804         if (IS_ERR(i2s->pclk)) {
 805                 dev_err(&pdev->dev, "Could not get pclk\n");
 806                 return PTR_ERR(i2s->pclk);
 807         }
 808
 809         i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
 810         if (IS_ERR(i2s->i2sclk)) {
 811                 dev_err(&pdev->dev, "Could not get i2sclk\n");
 812                 return PTR_ERR(i2s->i2sclk);
 813         }
 814
 815         i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
 816         if (IS_ERR(i2s->x8kclk)) {
 817                 dev_err(&pdev->dev, "missing x8k parent clock\n");
 818                 return PTR_ERR(i2s->x8kclk);
 819         }
 820
 821         i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
 822         if (IS_ERR(i2s->x11kclk)) {
 823                 dev_err(&pdev->dev, "missing x11k parent clock\n");
 824                 return PTR_ERR(i2s->x11kclk);
 825         }
 826
 827         /* Get irqs */
 828         irq = platform_get_irq(pdev, 0);
 829         if (irq < 0) {
 830                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
 831                 return -ENOENT;
 832         }
 833
 834         ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
 835                                dev_name(&pdev->dev), i2s);
 836         if (ret) {
 837                 dev_err(&pdev->dev, "irq request returned %d\n", ret);
 838                 return ret;
 839         }
 840
 841         /* Reset */
 842         rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 843         if (!IS_ERR(rst)) {
 844                 reset_control_assert(rst);
 845                 udelay(2);
 846                 reset_control_deassert(rst);
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int stm32_i2s_probe(struct platform_device *pdev)
 853 {
 854         struct stm32_i2s_data *i2s;
 855         int ret;
 856
 857         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 858         if (!i2s)
 859                 return -ENOMEM;
 860
 861         ret = stm32_i2s_parse_dt(pdev, i2s);
 862         if (ret)
 863                 return ret;
 864
 865         i2s->pdev = pdev;
 866         i2s->ms_flg = I2S_MS_NOT_SET;
 867         spin_lock_init(&i2s->lock_fd);
 868         platform_set_drvdata(pdev, i2s);
 869
 870         ret = stm32_i2s_dais_init(pdev, i2s);
 871         if (ret)
 872                 return ret;
 873
 874         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->base,
 875                                             i2s->regmap_conf);
 876         if (IS_ERR(i2s->regmap)) {
 877                 dev_err(&pdev->dev, "regmap init failed\n");
 878                 return PTR_ERR(i2s->regmap);
 879         }
 880
 881         ret = clk_prepare_enable(i2s->pclk);
 882         if (ret) {
 883                 dev_err(&pdev->dev, "Enable pclk failed: %d\n", ret);
 884                 return ret;
 885         }
 886
 887         ret = clk_prepare_enable(i2s->i2sclk);
 888         if (ret) {
 889                 dev_err(&pdev->dev, "Enable i2sclk failed: %d\n", ret);
 890                 goto err_pclk_disable;
 891         }
 892
 893         ret = devm_snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
 894                                               i2s->dai_drv, 1);
 895         if (ret)
 896                 goto err_clocks_disable;
 897
 898         ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
 899                                               &stm32_i2s_pcm_config, 0);
 900         if (ret)
 901                 goto err_clocks_disable;
 902
 903         /* Set SPI/I2S in i2s mode */
 904         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 905                                  I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
 906         if (ret)
 907                 goto err_clocks_disable;
 908
 909         return ret;
 910
 911 err_clocks_disable:
 912         clk_disable_unprepare(i2s->i2sclk);
 913 err_pclk_disable:
 914         clk_disable_unprepare(i2s->pclk);
 915
 916         return ret;
 917 }
 918
 919 static int stm32_i2s_remove(struct platform_device *pdev)
 920 {
 921         struct stm32_i2s_data *i2s = platform_get_drvdata(pdev);
 922
 923         clk_disable_unprepare(i2s->i2sclk);
 924         clk_disable_unprepare(i2s->pclk);
 925
 926         return 0;
 927 }
 928
 929 MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
 930
 931 static struct platform_driver stm32_i2s_driver = {
 932         .driver = {
 933                 .name = "st,stm32-i2s",
 934                 .of_match_table = stm32_i2s_ids,
 935         },
 936         .probe = stm32_i2s_probe,
 937         .remove = stm32_i2s_remove,
 938 };
 939
 940 module_platform_driver(stm32_i2s_driver);
 941
 942 MODULE_DESCRIPTION("STM32 Soc i2s Interface");
 943 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
 944 MODULE_ALIAS("platform:stm32-i2s");
 945 MODULE_LICENSE("GPL v2");