sound/soc/sunxi/sun4i-i2s.c

   1 /*
   2  * Copyright (C) 2015 Andrea Venturi
   3  * Andrea Venturi <be17068@iperbole.bo.it>
   4  *
   5  * Copyright (C) 2016 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <linux/reset.h>
  22
  23 #include <sound/dmaengine_pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dai.h>
  27
  28 #define SUN4I_I2S_CTRL_REG              0x00
  29 #define SUN4I_I2S_CTRL_SDO_EN_MASK              GENMASK(11, 8)
  30 #define SUN4I_I2S_CTRL_SDO_EN(sdo)                      BIT(8 + (sdo))
  31 #define SUN4I_I2S_CTRL_MODE_MASK                BIT(5)
  32 #define SUN4I_I2S_CTRL_MODE_SLAVE                       (1 << 5)
  33 #define SUN4I_I2S_CTRL_MODE_MASTER                      (0 << 5)
  34 #define SUN4I_I2S_CTRL_TX_EN                    BIT(2)
  35 #define SUN4I_I2S_CTRL_RX_EN                    BIT(1)
  36 #define SUN4I_I2S_CTRL_GL_EN                    BIT(0)
  37
  38 #define SUN4I_I2S_FMT0_REG              0x04
  39 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK      BIT(7)
  40 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED          (1 << 7)
  41 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL            (0 << 7)
  42 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK       BIT(6)
  43 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED           (1 << 6)
  44 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL             (0 << 6)
  45 #define SUN4I_I2S_FMT0_SR_MASK                  GENMASK(5, 4)
  46 #define SUN4I_I2S_FMT0_SR(sr)                           ((sr) << 4)
  47 #define SUN4I_I2S_FMT0_WSS_MASK                 GENMASK(3, 2)
  48 #define SUN4I_I2S_FMT0_WSS(wss)                         ((wss) << 2)
  49 #define SUN4I_I2S_FMT0_FMT_MASK                 GENMASK(1, 0)
  50 #define SUN4I_I2S_FMT0_FMT_RIGHT_J                      (2 << 0)
  51 #define SUN4I_I2S_FMT0_FMT_LEFT_J                       (1 << 0)
  52 #define SUN4I_I2S_FMT0_FMT_I2S                          (0 << 0)
  53 #define SUN4I_I2S_FMT0_POLARITY_INVERTED                (1)
  54 #define SUN4I_I2S_FMT0_POLARITY_NORMAL                  (0)
  55
  56 #define SUN4I_I2S_FMT1_REG              0x08
  57 #define SUN4I_I2S_FIFO_TX_REG           0x0c
  58 #define SUN4I_I2S_FIFO_RX_REG           0x10
  59
  60 #define SUN4I_I2S_FIFO_CTRL_REG         0x14
  61 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX            BIT(25)
  62 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX            BIT(24)
  63 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK        BIT(2)
  64 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode)               ((mode) << 2)
  65 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK        GENMASK(1, 0)
  66 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode)               (mode)
  67
  68 #define SUN4I_I2S_FIFO_STA_REG          0x18
  69
  70 #define SUN4I_I2S_DMA_INT_CTRL_REG      0x1c
  71 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN        BIT(7)
  72 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN        BIT(3)
  73
  74 #define SUN4I_I2S_INT_STA_REG           0x20
  75
  76 #define SUN4I_I2S_CLK_DIV_REG           0x24
  77 #define SUN4I_I2S_CLK_DIV_MCLK_EN               BIT(7)
  78 #define SUN4I_I2S_CLK_DIV_BCLK_MASK             GENMASK(6, 4)
  79 #define SUN4I_I2S_CLK_DIV_BCLK(bclk)                    ((bclk) << 4)
  80 #define SUN4I_I2S_CLK_DIV_MCLK_MASK             GENMASK(3, 0)
  81 #define SUN4I_I2S_CLK_DIV_MCLK(mclk)                    ((mclk) << 0)
  82
  83 #define SUN4I_I2S_TX_CNT_REG            0x28
  84 #define SUN4I_I2S_RX_CNT_REG            0x2c
  85
  86 #define SUN4I_I2S_TX_CHAN_SEL_REG       0x30
  87 #define SUN4I_I2S_CHAN_SEL(num_chan)            (((num_chan) - 1) << 0)
  88
  89 #define SUN4I_I2S_TX_CHAN_MAP_REG       0x34
  90 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample)     ((sample) << (chan << 2))
  91
  92 #define SUN4I_I2S_RX_CHAN_SEL_REG       0x38
  93 #define SUN4I_I2S_RX_CHAN_MAP_REG       0x3c
  94
  95 /* Defines required for sun8i-h3 support */
  96 #define SUN8I_I2S_CTRL_BCLK_OUT                 BIT(18)
  97 #define SUN8I_I2S_CTRL_LRCK_OUT                 BIT(17)
  98
  99 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK         GENMASK(17, 8)
 100 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period)      ((period - 1) << 8)
 101
 102 #define SUN8I_I2S_INT_STA_REG           0x0c
 103 #define SUN8I_I2S_FIFO_TX_REG           0x20
 104
 105 #define SUN8I_I2S_CHAN_CFG_REG          0x30
 106 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK     GENMASK(6, 4)
 107 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan)    ((chan - 1) << 4)
 108 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK     GENMASK(2, 0)
 109 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan)    (chan - 1)
 110
 111 #define SUN8I_I2S_TX_CHAN_MAP_REG       0x44
 112 #define SUN8I_I2S_TX_CHAN_SEL_REG       0x34
 113 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK           GENMASK(13, 12)
 114 #define SUN8I_I2S_TX_CHAN_OFFSET(offset)        (offset << 12)
 115 #define SUN8I_I2S_TX_CHAN_EN_MASK               GENMASK(11, 4)
 116 #define SUN8I_I2S_TX_CHAN_EN(num_chan)          (((1 << num_chan) - 1) << 4)
 117
 118 #define SUN8I_I2S_RX_CHAN_SEL_REG       0x54
 119 #define SUN8I_I2S_RX_CHAN_MAP_REG       0x58
 120
 121 /**
 122  * struct sun4i_i2s_quirks - Differences between SoC variants.
 123  *
 124  * @has_reset: SoC needs reset deasserted.
 125  * @has_slave_select_bit: SoC has a bit to enable slave mode.
 126  * @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
 127  * @has_chcfg: tx and rx slot number need to be set.
 128  * @has_chsel_tx_chen: SoC requires that the tx channels are enabled.
 129  * @has_chsel_offset: SoC uses offset for selecting dai operational mode.
 130  * @reg_offset_txdata: offset of the tx fifo.
 131  * @sun4i_i2s_regmap: regmap config to use.
 132  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
 133  * @bclk_offset: Value by which bclkdiv needs to be adjusted.
 134  * @fmt_offset: Value by which wss and sr needs to be adjusted.
 135  * @field_clkdiv_mclk_en: regmap field to enable mclk output.
 136  * @field_fmt_wss: regmap field to set word select size.
 137  * @field_fmt_sr: regmap field to set sample resolution.
 138  * @field_fmt_bclk: regmap field to set clk polarity.
 139  * @field_fmt_lrclk: regmap field to set frame polarity.
 140  * @field_fmt_mode: regmap field to set the operational mode.
 141  * @field_txchanmap: location of the tx channel mapping register.
 142  * @field_rxchanmap: location of the rx channel mapping register.
 143  * @field_txchansel: location of the tx channel select bit fields.
 144  * @field_rxchansel: location of the rx channel select bit fields.
 145  */
 146 struct sun4i_i2s_quirks {
 147         bool                            has_reset;
 148         bool                            has_slave_select_bit;
 149         bool                            has_fmt_set_lrck_period;
 150         bool                            has_chcfg;
 151         bool                            has_chsel_tx_chen;
 152         bool                            has_chsel_offset;
 153         unsigned int                    reg_offset_txdata;      /* TX FIFO */
 154         const struct regmap_config      *sun4i_i2s_regmap;
 155         unsigned int                    mclk_offset;
 156         unsigned int                    bclk_offset;
 157         unsigned int                    fmt_offset;
 158
 159         /* Register fields for i2s */
 160         struct reg_field                field_clkdiv_mclk_en;
 161         struct reg_field                field_fmt_wss;
 162         struct reg_field                field_fmt_sr;
 163         struct reg_field                field_fmt_bclk;
 164         struct reg_field                field_fmt_lrclk;
 165         struct reg_field                field_fmt_mode;
 166         struct reg_field                field_txchanmap;
 167         struct reg_field                field_rxchanmap;
 168         struct reg_field                field_txchansel;
 169         struct reg_field                field_rxchansel;
 170 };
 171
 172 struct sun4i_i2s {
 173         struct clk      *bus_clk;
 174         struct clk      *mod_clk;
 175         struct regmap   *regmap;
 176         struct reset_control *rst;
 177
 178         unsigned int    mclk_freq;
 179
 180         struct snd_dmaengine_dai_dma_data       capture_dma_data;
 181         struct snd_dmaengine_dai_dma_data       playback_dma_data;
 182
 183         /* Register fields for i2s */
 184         struct regmap_field     *field_clkdiv_mclk_en;
 185         struct regmap_field     *field_fmt_wss;
 186         struct regmap_field     *field_fmt_sr;
 187         struct regmap_field     *field_fmt_bclk;
 188         struct regmap_field     *field_fmt_lrclk;
 189         struct regmap_field     *field_fmt_mode;
 190         struct regmap_field     *field_txchanmap;
 191         struct regmap_field     *field_rxchanmap;
 192         struct regmap_field     *field_txchansel;
 193         struct regmap_field     *field_rxchansel;
 194
 195         const struct sun4i_i2s_quirks   *variant;
 196 };
 197
 198 struct sun4i_i2s_clk_div {
 199         u8      div;
 200         u8      val;
 201 };
 202
 203 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
 204         { .div = 2, .val = 0 },
 205         { .div = 4, .val = 1 },
 206         { .div = 6, .val = 2 },
 207         { .div = 8, .val = 3 },
 208         { .div = 12, .val = 4 },
 209         { .div = 16, .val = 5 },
 210         /* TODO - extend divide ratio supported by newer SoCs */
 211 };
 212
 213 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
 214         { .div = 1, .val = 0 },
 215         { .div = 2, .val = 1 },
 216         { .div = 4, .val = 2 },
 217         { .div = 6, .val = 3 },
 218         { .div = 8, .val = 4 },
 219         { .div = 12, .val = 5 },
 220         { .div = 16, .val = 6 },
 221         { .div = 24, .val = 7 },
 222         /* TODO - extend divide ratio supported by newer SoCs */
 223 };
 224
 225 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
 226                                   unsigned int oversample_rate,
 227                                   unsigned int word_size)
 228 {
 229         int div = oversample_rate / word_size / 2;
 230         int i;
 231
 232         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
 233                 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
 234
 235                 if (bdiv->div == div)
 236                         return bdiv->val;
 237         }
 238
 239         return -EINVAL;
 240 }
 241
 242 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
 243                                   unsigned int oversample_rate,
 244                                   unsigned int module_rate,
 245                                   unsigned int sampling_rate)
 246 {
 247         int div = module_rate / sampling_rate / oversample_rate;
 248         int i;
 249
 250         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
 251                 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
 252
 253                 if (mdiv->div == div)
 254                         return mdiv->val;
 255         }
 256
 257         return -EINVAL;
 258 }
 259
 260 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
 261 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
 262 {
 263         int i;
 264
 265         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
 266                 if (sun4i_i2s_oversample_rates[i] == oversample)
 267                         return true;
 268
 269         return false;
 270 }
 271
 272 static int sun4i_i2s_set_clk_rate(struct sun4i_i2s *i2s,
 273                                   unsigned int rate,
 274                                   unsigned int word_size)
 275 {
 276         unsigned int oversample_rate, clk_rate;
 277         int bclk_div, mclk_div;
 278         int ret;
 279
 280         switch (rate) {
 281         case 176400:
 282         case 88200:
 283         case 44100:
 284         case 22050:
 285         case 11025:
 286                 clk_rate = 22579200;
 287                 break;
 288
 289         case 192000:
 290         case 128000:
 291         case 96000:
 292         case 64000:
 293         case 48000:
 294         case 32000:
 295         case 24000:
 296         case 16000:
 297         case 12000:
 298         case 8000:
 299                 clk_rate = 24576000;
 300                 break;
 301
 302         default:
 303                 return -EINVAL;
 304         }
 305
 306         ret = clk_set_rate(i2s->mod_clk, clk_rate);
 307         if (ret)
 308                 return ret;
 309
 310         oversample_rate = i2s->mclk_freq / rate;
 311         if (!sun4i_i2s_oversample_is_valid(oversample_rate))
 312                 return -EINVAL;
 313
 314         bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
 315                                           word_size);
 316         if (bclk_div < 0)
 317                 return -EINVAL;
 318
 319         mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
 320                                           clk_rate, rate);
 321         if (mclk_div < 0)
 322                 return -EINVAL;
 323
 324         /* Adjust the clock division values if needed */
 325         bclk_div += i2s->variant->bclk_offset;
 326         mclk_div += i2s->variant->mclk_offset;
 327
 328         regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
 329                      SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
 330                      SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
 331
 332         regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
 333
 334         /* Set sync period */
 335         if (i2s->variant->has_fmt_set_lrck_period)
 336                 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
 337                                    SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
 338                                    SUN8I_I2S_FMT0_LRCK_PERIOD(32));
 339
 340         return 0;
 341 }
 342
 343 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
 344                                struct snd_pcm_hw_params *params,
 345                                struct snd_soc_dai *dai)
 346 {
 347         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 348         int sr, wss, channels;
 349         u32 width;
 350
 351         channels = params_channels(params);
 352         if (channels != 2)
 353                 return -EINVAL;
 354
 355         if (i2s->variant->has_chcfg) {
 356                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 357                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
 358                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
 359                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 360                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
 361                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
 362         }
 363
 364         /* Map the channels for playback and capture */
 365         regmap_field_write(i2s->field_txchanmap, 0x76543210);
 366         regmap_field_write(i2s->field_rxchanmap, 0x00003210);
 367
 368         /* Configure the channels */
 369         regmap_field_write(i2s->field_txchansel,
 370                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 371
 372         regmap_field_write(i2s->field_rxchansel,
 373                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 374
 375         if (i2s->variant->has_chsel_tx_chen)
 376                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 377                                    SUN8I_I2S_TX_CHAN_EN_MASK,
 378                                    SUN8I_I2S_TX_CHAN_EN(channels));
 379
 380         switch (params_physical_width(params)) {
 381         case 16:
 382                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 383                 break;
 384         default:
 385                 return -EINVAL;
 386         }
 387         i2s->playback_dma_data.addr_width = width;
 388
 389         switch (params_width(params)) {
 390         case 16:
 391                 sr = 0;
 392                 wss = 0;
 393                 break;
 394
 395         default:
 396                 return -EINVAL;
 397         }
 398
 399         regmap_field_write(i2s->field_fmt_wss,
 400                            wss + i2s->variant->fmt_offset);
 401         regmap_field_write(i2s->field_fmt_sr,
 402                            sr + i2s->variant->fmt_offset);
 403
 404         return sun4i_i2s_set_clk_rate(i2s, params_rate(params),
 405                                       params_width(params));
 406 }
 407
 408 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 409 {
 410         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 411         u32 val;
 412         u32 offset = 0;
 413         u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 414         u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 415
 416         /* DAI Mode */
 417         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 418         case SND_SOC_DAIFMT_I2S:
 419                 val = SUN4I_I2S_FMT0_FMT_I2S;
 420                 offset = 1;
 421                 break;
 422         case SND_SOC_DAIFMT_LEFT_J:
 423                 val = SUN4I_I2S_FMT0_FMT_LEFT_J;
 424                 break;
 425         case SND_SOC_DAIFMT_RIGHT_J:
 426                 val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
 427                 break;
 428         default:
 429                 return -EINVAL;
 430         }
 431
 432         if (i2s->variant->has_chsel_offset) {
 433                 /*
 434                  * offset being set indicates that we're connected to an i2s
 435                  * device, however offset is only used on the sun8i block and
 436                  * i2s shares the same setting with the LJ format. Increment
 437                  * val so that the bit to value to write is correct.
 438                  */
 439                 if (offset > 0)
 440                         val++;
 441                 /* blck offset determines whether i2s or LJ */
 442                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 443                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 444                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 445
 446                 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
 447                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 448                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 449         }
 450
 451         regmap_field_write(i2s->field_fmt_mode, val);
 452
 453         /* DAI clock polarity */
 454         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 455         case SND_SOC_DAIFMT_IB_IF:
 456                 /* Invert both clocks */
 457                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 458                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 459                 break;
 460         case SND_SOC_DAIFMT_IB_NF:
 461                 /* Invert bit clock */
 462                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 463                 break;
 464         case SND_SOC_DAIFMT_NB_IF:
 465                 /* Invert frame clock */
 466                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 467                 break;
 468         case SND_SOC_DAIFMT_NB_NF:
 469                 break;
 470         default:
 471                 return -EINVAL;
 472         }
 473
 474         regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
 475         regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
 476
 477         if (i2s->variant->has_slave_select_bit) {
 478                 /* DAI clock master masks */
 479                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 480                 case SND_SOC_DAIFMT_CBS_CFS:
 481                         /* BCLK and LRCLK master */
 482                         val = SUN4I_I2S_CTRL_MODE_MASTER;
 483                         break;
 484                 case SND_SOC_DAIFMT_CBM_CFM:
 485                         /* BCLK and LRCLK slave */
 486                         val = SUN4I_I2S_CTRL_MODE_SLAVE;
 487                         break;
 488                 default:
 489                         return -EINVAL;
 490                 }
 491                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 492                                    SUN4I_I2S_CTRL_MODE_MASK,
 493                                    val);
 494         } else {
 495                 /*
 496                  * The newer i2s block does not have a slave select bit,
 497                  * instead the clk pins are configured as inputs.
 498                  */
 499                 /* DAI clock master masks */
 500                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 501                 case SND_SOC_DAIFMT_CBS_CFS:
 502                         /* BCLK and LRCLK master */
 503                         val = SUN8I_I2S_CTRL_BCLK_OUT |
 504                                 SUN8I_I2S_CTRL_LRCK_OUT;
 505                         break;
 506                 case SND_SOC_DAIFMT_CBM_CFM:
 507                         /* BCLK and LRCLK slave */
 508                         val = 0;
 509                         break;
 510                 default:
 511                         return -EINVAL;
 512                 }
 513                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 514                                    SUN8I_I2S_CTRL_BCLK_OUT |
 515                                    SUN8I_I2S_CTRL_LRCK_OUT,
 516                                    val);
 517         }
 518
 519         /* Set significant bits in our FIFOs */
 520         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 521                            SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
 522                            SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
 523                            SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
 524                            SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
 525         return 0;
 526 }
 527
 528 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
 529 {
 530         /* Flush RX FIFO */
 531         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 532                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
 533                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
 534
 535         /* Clear RX counter */
 536         regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
 537
 538         /* Enable RX Block */
 539         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 540                            SUN4I_I2S_CTRL_RX_EN,
 541                            SUN4I_I2S_CTRL_RX_EN);
 542
 543         /* Enable RX DRQ */
 544         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 545                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 546                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
 547 }
 548
 549 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
 550 {
 551         /* Flush TX FIFO */
 552         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 553                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
 554                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
 555
 556         /* Clear TX counter */
 557         regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
 558
 559         /* Enable TX Block */
 560         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 561                            SUN4I_I2S_CTRL_TX_EN,
 562                            SUN4I_I2S_CTRL_TX_EN);
 563
 564         /* Enable TX DRQ */
 565         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 566                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 567                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
 568 }
 569
 570 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
 571 {
 572         /* Disable RX Block */
 573         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 574                            SUN4I_I2S_CTRL_RX_EN,
 575                            0);
 576
 577         /* Disable RX DRQ */
 578         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 579                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 580                            0);
 581 }
 582
 583 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
 584 {
 585         /* Disable TX Block */
 586         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 587                            SUN4I_I2S_CTRL_TX_EN,
 588                            0);
 589
 590         /* Disable TX DRQ */
 591         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 592                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 593                            0);
 594 }
 595
 596 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 597                              struct snd_soc_dai *dai)
 598 {
 599         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 600
 601         switch (cmd) {
 602         case SNDRV_PCM_TRIGGER_START:
 603         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 604         case SNDRV_PCM_TRIGGER_RESUME:
 605                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 606                         sun4i_i2s_start_playback(i2s);
 607                 else
 608                         sun4i_i2s_start_capture(i2s);
 609                 break;
 610
 611         case SNDRV_PCM_TRIGGER_STOP:
 612         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 613         case SNDRV_PCM_TRIGGER_SUSPEND:
 614                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 615                         sun4i_i2s_stop_playback(i2s);
 616                 else
 617                         sun4i_i2s_stop_capture(i2s);
 618                 break;
 619
 620         default:
 621                 return -EINVAL;
 622         }
 623
 624         return 0;
 625 }
 626
 627 static int sun4i_i2s_startup(struct snd_pcm_substream *substream,
 628                              struct snd_soc_dai *dai)
 629 {
 630         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 631
 632         /* Enable the whole hardware block */
 633         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 634                            SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
 635
 636         /* Enable the first output line */
 637         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 638                            SUN4I_I2S_CTRL_SDO_EN_MASK,
 639                            SUN4I_I2S_CTRL_SDO_EN(0));
 640
 641
 642         return clk_prepare_enable(i2s->mod_clk);
 643 }
 644
 645 static void sun4i_i2s_shutdown(struct snd_pcm_substream *substream,
 646                                struct snd_soc_dai *dai)
 647 {
 648         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 649
 650         clk_disable_unprepare(i2s->mod_clk);
 651
 652         /* Disable our output lines */
 653         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 654                            SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
 655
 656         /* Disable the whole hardware block */
 657         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 658                            SUN4I_I2S_CTRL_GL_EN, 0);
 659 }
 660
 661 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 662                                 unsigned int freq, int dir)
 663 {
 664         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 665
 666         if (clk_id != 0)
 667                 return -EINVAL;
 668
 669         i2s->mclk_freq = freq;
 670
 671         return 0;
 672 }
 673
 674 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
 675         .hw_params      = sun4i_i2s_hw_params,
 676         .set_fmt        = sun4i_i2s_set_fmt,
 677         .set_sysclk     = sun4i_i2s_set_sysclk,
 678         .shutdown       = sun4i_i2s_shutdown,
 679         .startup        = sun4i_i2s_startup,
 680         .trigger        = sun4i_i2s_trigger,
 681 };
 682
 683 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
 684 {
 685         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 686
 687         snd_soc_dai_init_dma_data(dai,
 688                                   &i2s->playback_dma_data,
 689                                   &i2s->capture_dma_data);
 690
 691         snd_soc_dai_set_drvdata(dai, i2s);
 692
 693         return 0;
 694 }
 695
 696 static struct snd_soc_dai_driver sun4i_i2s_dai = {
 697         .probe = sun4i_i2s_dai_probe,
 698         .capture = {
 699                 .stream_name = "Capture",
 700                 .channels_min = 2,
 701                 .channels_max = 2,
 702                 .rates = SNDRV_PCM_RATE_8000_192000,
 703                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 704         },
 705         .playback = {
 706                 .stream_name = "Playback",
 707                 .channels_min = 2,
 708                 .channels_max = 2,
 709                 .rates = SNDRV_PCM_RATE_8000_192000,
 710                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 711         },
 712         .ops = &sun4i_i2s_dai_ops,
 713         .symmetric_rates = 1,
 714 };
 715
 716 static const struct snd_soc_component_driver sun4i_i2s_component = {
 717         .name   = "sun4i-dai",
 718 };
 719
 720 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
 721 {
 722         switch (reg) {
 723         case SUN4I_I2S_FIFO_TX_REG:
 724                 return false;
 725
 726         default:
 727                 return true;
 728         }
 729 }
 730
 731 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
 732 {
 733         switch (reg) {
 734         case SUN4I_I2S_FIFO_RX_REG:
 735         case SUN4I_I2S_FIFO_STA_REG:
 736                 return false;
 737
 738         default:
 739                 return true;
 740         }
 741 }
 742
 743 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 744 {
 745         switch (reg) {
 746         case SUN4I_I2S_FIFO_RX_REG:
 747         case SUN4I_I2S_INT_STA_REG:
 748         case SUN4I_I2S_RX_CNT_REG:
 749         case SUN4I_I2S_TX_CNT_REG:
 750                 return true;
 751
 752         default:
 753                 return false;
 754         }
 755 }
 756
 757 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
 758 {
 759         switch (reg) {
 760         case SUN8I_I2S_FIFO_TX_REG:
 761                 return false;
 762
 763         default:
 764                 return true;
 765         }
 766 }
 767
 768 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 769 {
 770         if (reg == SUN8I_I2S_INT_STA_REG)
 771                 return true;
 772         if (reg == SUN8I_I2S_FIFO_TX_REG)
 773                 return false;
 774
 775         return sun4i_i2s_volatile_reg(dev, reg);
 776 }
 777
 778 static const struct reg_default sun4i_i2s_reg_defaults[] = {
 779         { SUN4I_I2S_CTRL_REG, 0x00000000 },
 780         { SUN4I_I2S_FMT0_REG, 0x0000000c },
 781         { SUN4I_I2S_FMT1_REG, 0x00004020 },
 782         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 783         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 784         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 785         { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
 786         { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
 787         { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
 788         { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
 789 };
 790
 791 static const struct reg_default sun8i_i2s_reg_defaults[] = {
 792         { SUN4I_I2S_CTRL_REG, 0x00060000 },
 793         { SUN4I_I2S_FMT0_REG, 0x00000033 },
 794         { SUN4I_I2S_FMT1_REG, 0x00000030 },
 795         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 796         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 797         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 798         { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
 799         { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
 800         { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
 801         { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
 802         { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
 803 };
 804
 805 static const struct regmap_config sun4i_i2s_regmap_config = {
 806         .reg_bits       = 32,
 807         .reg_stride     = 4,
 808         .val_bits       = 32,
 809         .max_register   = SUN4I_I2S_RX_CHAN_MAP_REG,
 810
 811         .cache_type     = REGCACHE_FLAT,
 812         .reg_defaults   = sun4i_i2s_reg_defaults,
 813         .num_reg_defaults       = ARRAY_SIZE(sun4i_i2s_reg_defaults),
 814         .writeable_reg  = sun4i_i2s_wr_reg,
 815         .readable_reg   = sun4i_i2s_rd_reg,
 816         .volatile_reg   = sun4i_i2s_volatile_reg,
 817 };
 818
 819 static const struct regmap_config sun8i_i2s_regmap_config = {
 820         .reg_bits       = 32,
 821         .reg_stride     = 4,
 822         .val_bits       = 32,
 823         .max_register   = SUN8I_I2S_RX_CHAN_MAP_REG,
 824         .cache_type     = REGCACHE_FLAT,
 825         .reg_defaults   = sun8i_i2s_reg_defaults,
 826         .num_reg_defaults       = ARRAY_SIZE(sun8i_i2s_reg_defaults),
 827         .writeable_reg  = sun4i_i2s_wr_reg,
 828         .readable_reg   = sun8i_i2s_rd_reg,
 829         .volatile_reg   = sun8i_i2s_volatile_reg,
 830 };
 831
 832 static int sun4i_i2s_runtime_resume(struct device *dev)
 833 {
 834         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 835         int ret;
 836
 837         ret = clk_prepare_enable(i2s->bus_clk);
 838         if (ret) {
 839                 dev_err(dev, "Failed to enable bus clock\n");
 840                 return ret;
 841         }
 842
 843         regcache_cache_only(i2s->regmap, false);
 844         regcache_mark_dirty(i2s->regmap);
 845
 846         ret = regcache_sync(i2s->regmap);
 847         if (ret) {
 848                 dev_err(dev, "Failed to sync regmap cache\n");
 849                 goto err_disable_clk;
 850         }
 851
 852         return 0;
 853
 854 err_disable_clk:
 855         clk_disable_unprepare(i2s->bus_clk);
 856         return ret;
 857 }
 858
 859 static int sun4i_i2s_runtime_suspend(struct device *dev)
 860 {
 861         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 862
 863         regcache_cache_only(i2s->regmap, true);
 864
 865         clk_disable_unprepare(i2s->bus_clk);
 866
 867         return 0;
 868 }
 869
 870 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
 871         .has_reset              = false,
 872         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 873         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 874         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 875         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 876         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 877         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 878         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 879         .has_slave_select_bit   = true,
 880         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 881         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 882         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 883         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 884         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 885 };
 886
 887 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
 888         .has_reset              = true,
 889         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 890         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 891         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 892         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 893         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 894         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 895         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 896         .has_slave_select_bit   = true,
 897         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 898         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 899         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 900         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 901         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 902 };
 903
 904 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
 905         .has_reset              = true,
 906         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 907         .sun4i_i2s_regmap       = &sun8i_i2s_regmap_config,
 908         .mclk_offset            = 1,
 909         .bclk_offset            = 2,
 910         .fmt_offset             = 3,
 911         .has_fmt_set_lrck_period = true,
 912         .has_chcfg              = true,
 913         .has_chsel_tx_chen      = true,
 914         .has_chsel_offset       = true,
 915         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
 916         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
 917         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
 918         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 919         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
 920         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
 921         .field_txchanmap        = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
 922         .field_rxchanmap        = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
 923         .field_txchansel        = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
 924         .field_rxchansel        = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
 925 };
 926
 927 static int sun4i_i2s_init_regmap_fields(struct device *dev,
 928                                         struct sun4i_i2s *i2s)
 929 {
 930         i2s->field_clkdiv_mclk_en =
 931                 devm_regmap_field_alloc(dev, i2s->regmap,
 932                                         i2s->variant->field_clkdiv_mclk_en);
 933         if (IS_ERR(i2s->field_clkdiv_mclk_en))
 934                 return PTR_ERR(i2s->field_clkdiv_mclk_en);
 935
 936         i2s->field_fmt_wss =
 937                         devm_regmap_field_alloc(dev, i2s->regmap,
 938                                                 i2s->variant->field_fmt_wss);
 939         if (IS_ERR(i2s->field_fmt_wss))
 940                 return PTR_ERR(i2s->field_fmt_wss);
 941
 942         i2s->field_fmt_sr =
 943                         devm_regmap_field_alloc(dev, i2s->regmap,
 944                                                 i2s->variant->field_fmt_sr);
 945         if (IS_ERR(i2s->field_fmt_sr))
 946                 return PTR_ERR(i2s->field_fmt_sr);
 947
 948         i2s->field_fmt_bclk =
 949                         devm_regmap_field_alloc(dev, i2s->regmap,
 950                                                 i2s->variant->field_fmt_bclk);
 951         if (IS_ERR(i2s->field_fmt_bclk))
 952                 return PTR_ERR(i2s->field_fmt_bclk);
 953
 954         i2s->field_fmt_lrclk =
 955                         devm_regmap_field_alloc(dev, i2s->regmap,
 956                                                 i2s->variant->field_fmt_lrclk);
 957         if (IS_ERR(i2s->field_fmt_lrclk))
 958                 return PTR_ERR(i2s->field_fmt_lrclk);
 959
 960         i2s->field_fmt_mode =
 961                         devm_regmap_field_alloc(dev, i2s->regmap,
 962                                                 i2s->variant->field_fmt_mode);
 963         if (IS_ERR(i2s->field_fmt_mode))
 964                 return PTR_ERR(i2s->field_fmt_mode);
 965
 966         i2s->field_txchanmap =
 967                         devm_regmap_field_alloc(dev, i2s->regmap,
 968                                                 i2s->variant->field_txchanmap);
 969         if (IS_ERR(i2s->field_txchanmap))
 970                 return PTR_ERR(i2s->field_txchanmap);
 971
 972         i2s->field_rxchanmap =
 973                         devm_regmap_field_alloc(dev, i2s->regmap,
 974                                                 i2s->variant->field_rxchanmap);
 975         if (IS_ERR(i2s->field_rxchanmap))
 976                 return PTR_ERR(i2s->field_rxchanmap);
 977
 978         i2s->field_txchansel =
 979                         devm_regmap_field_alloc(dev, i2s->regmap,
 980                                                 i2s->variant->field_txchansel);
 981         if (IS_ERR(i2s->field_txchansel))
 982                 return PTR_ERR(i2s->field_txchansel);
 983
 984         i2s->field_rxchansel =
 985                         devm_regmap_field_alloc(dev, i2s->regmap,
 986                                                 i2s->variant->field_rxchansel);
 987         return PTR_ERR_OR_ZERO(i2s->field_rxchansel);
 988 }
 989
 990 static int sun4i_i2s_probe(struct platform_device *pdev)
 991 {
 992         struct sun4i_i2s *i2s;
 993         struct resource *res;
 994         void __iomem *regs;
 995         int irq, ret;
 996
 997         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 998         if (!i2s)
 999                 return -ENOMEM;
1000         platform_set_drvdata(pdev, i2s);
1001
1002         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1003         regs = devm_ioremap_resource(&pdev->dev, res);
1004         if (IS_ERR(regs))
1005                 return PTR_ERR(regs);
1006
1007         irq = platform_get_irq(pdev, 0);
1008         if (irq < 0) {
1009                 dev_err(&pdev->dev, "Can't retrieve our interrupt\n");
1010                 return irq;
1011         }
1012
1013         i2s->variant = of_device_get_match_data(&pdev->dev);
1014         if (!i2s->variant) {
1015                 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1016                 return -ENODEV;
1017         }
1018
1019         i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
1020         if (IS_ERR(i2s->bus_clk)) {
1021                 dev_err(&pdev->dev, "Can't get our bus clock\n");
1022                 return PTR_ERR(i2s->bus_clk);
1023         }
1024
1025         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1026                                             i2s->variant->sun4i_i2s_regmap);
1027         if (IS_ERR(i2s->regmap)) {
1028                 dev_err(&pdev->dev, "Regmap initialisation failed\n");
1029                 return PTR_ERR(i2s->regmap);
1030         }
1031
1032         i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
1033         if (IS_ERR(i2s->mod_clk)) {
1034                 dev_err(&pdev->dev, "Can't get our mod clock\n");
1035                 return PTR_ERR(i2s->mod_clk);
1036         }
1037
1038         if (i2s->variant->has_reset) {
1039                 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1040                 if (IS_ERR(i2s->rst)) {
1041                         dev_err(&pdev->dev, "Failed to get reset control\n");
1042                         return PTR_ERR(i2s->rst);
1043                 }
1044         }
1045
1046         if (!IS_ERR(i2s->rst)) {
1047                 ret = reset_control_deassert(i2s->rst);
1048                 if (ret) {
1049                         dev_err(&pdev->dev,
1050                                 "Failed to deassert the reset control\n");
1051                         return -EINVAL;
1052                 }
1053         }
1054
1055         i2s->playback_dma_data.addr = res->start +
1056                                         i2s->variant->reg_offset_txdata;
1057         i2s->playback_dma_data.maxburst = 8;
1058
1059         i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
1060         i2s->capture_dma_data.maxburst = 8;
1061
1062         pm_runtime_enable(&pdev->dev);
1063         if (!pm_runtime_enabled(&pdev->dev)) {
1064                 ret = sun4i_i2s_runtime_resume(&pdev->dev);
1065                 if (ret)
1066                         goto err_pm_disable;
1067         }
1068
1069         ret = devm_snd_soc_register_component(&pdev->dev,
1070                                               &sun4i_i2s_component,
1071                                               &sun4i_i2s_dai, 1);
1072         if (ret) {
1073                 dev_err(&pdev->dev, "Could not register DAI\n");
1074                 goto err_suspend;
1075         }
1076
1077         ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1078         if (ret) {
1079                 dev_err(&pdev->dev, "Could not register PCM\n");
1080                 goto err_suspend;
1081         }
1082
1083         ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
1084         if (ret) {
1085                 dev_err(&pdev->dev, "Could not initialise regmap fields\n");
1086                 goto err_suspend;
1087         }
1088
1089         return 0;
1090
1091 err_suspend:
1092         if (!pm_runtime_status_suspended(&pdev->dev))
1093                 sun4i_i2s_runtime_suspend(&pdev->dev);
1094 err_pm_disable:
1095         pm_runtime_disable(&pdev->dev);
1096         if (!IS_ERR(i2s->rst))
1097                 reset_control_assert(i2s->rst);
1098
1099         return ret;
1100 }
1101
1102 static int sun4i_i2s_remove(struct platform_device *pdev)
1103 {
1104         struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
1105
1106         snd_dmaengine_pcm_unregister(&pdev->dev);
1107
1108         pm_runtime_disable(&pdev->dev);
1109         if (!pm_runtime_status_suspended(&pdev->dev))
1110                 sun4i_i2s_runtime_suspend(&pdev->dev);
1111
1112         if (!IS_ERR(i2s->rst))
1113                 reset_control_assert(i2s->rst);
1114
1115         return 0;
1116 }
1117
1118 static const struct of_device_id sun4i_i2s_match[] = {
1119         {
1120                 .compatible = "allwinner,sun4i-a10-i2s",
1121                 .data = &sun4i_a10_i2s_quirks,
1122         },
1123         {
1124                 .compatible = "allwinner,sun6i-a31-i2s",
1125                 .data = &sun6i_a31_i2s_quirks,
1126         },
1127         {
1128                 .compatible = "allwinner,sun8i-h3-i2s",
1129                 .data = &sun8i_h3_i2s_quirks,
1130         },
1131         {}
1132 };
1133 MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
1134
1135 static const struct dev_pm_ops sun4i_i2s_pm_ops = {
1136         .runtime_resume         = sun4i_i2s_runtime_resume,
1137         .runtime_suspend        = sun4i_i2s_runtime_suspend,
1138 };
1139
1140 static struct platform_driver sun4i_i2s_driver = {
1141         .probe  = sun4i_i2s_probe,
1142         .remove = sun4i_i2s_remove,
1143         .driver = {
1144                 .name           = "sun4i-i2s",
1145                 .of_match_table = sun4i_i2s_match,
1146                 .pm             = &sun4i_i2s_pm_ops,
1147         },
1148 };
1149 module_platform_driver(sun4i_i2s_driver);
1150
1151 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
1152 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1153 MODULE_DESCRIPTION("Allwinner A10 I2S driver");
1154 MODULE_LICENSE("GPL");