sound/soc/sunxi/sun4i-i2s.c

   1 /*
   2  * Copyright (C) 2015 Andrea Venturi
   3  * Andrea Venturi <be17068@iperbole.bo.it>
   4  *
   5  * Copyright (C) 2016 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <linux/reset.h>
  22
  23 #include <sound/dmaengine_pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dai.h>
  27
  28 #define SUN4I_I2S_CTRL_REG              0x00
  29 #define SUN4I_I2S_CTRL_SDO_EN_MASK              GENMASK(11, 8)
  30 #define SUN4I_I2S_CTRL_SDO_EN(sdo)                      BIT(8 + (sdo))
  31 #define SUN4I_I2S_CTRL_MODE_MASK                BIT(5)
  32 #define SUN4I_I2S_CTRL_MODE_SLAVE                       (1 << 5)
  33 #define SUN4I_I2S_CTRL_MODE_MASTER                      (0 << 5)
  34 #define SUN4I_I2S_CTRL_TX_EN                    BIT(2)
  35 #define SUN4I_I2S_CTRL_RX_EN                    BIT(1)
  36 #define SUN4I_I2S_CTRL_GL_EN                    BIT(0)
  37
  38 #define SUN4I_I2S_FMT0_REG              0x04
  39 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK      BIT(7)
  40 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED          (1 << 7)
  41 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL            (0 << 7)
  42 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK       BIT(6)
  43 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED           (1 << 6)
  44 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL             (0 << 6)
  45 #define SUN4I_I2S_FMT0_SR_MASK                  GENMASK(5, 4)
  46 #define SUN4I_I2S_FMT0_SR(sr)                           ((sr) << 4)
  47 #define SUN4I_I2S_FMT0_WSS_MASK                 GENMASK(3, 2)
  48 #define SUN4I_I2S_FMT0_WSS(wss)                         ((wss) << 2)
  49 #define SUN4I_I2S_FMT0_FMT_MASK                 GENMASK(1, 0)
  50 #define SUN4I_I2S_FMT0_FMT_RIGHT_J                      (2 << 0)
  51 #define SUN4I_I2S_FMT0_FMT_LEFT_J                       (1 << 0)
  52 #define SUN4I_I2S_FMT0_FMT_I2S                          (0 << 0)
  53 #define SUN4I_I2S_FMT0_POLARITY_INVERTED                (1)
  54 #define SUN4I_I2S_FMT0_POLARITY_NORMAL                  (0)
  55
  56 #define SUN4I_I2S_FMT1_REG              0x08
  57 #define SUN4I_I2S_FIFO_TX_REG           0x0c
  58 #define SUN4I_I2S_FIFO_RX_REG           0x10
  59
  60 #define SUN4I_I2S_FIFO_CTRL_REG         0x14
  61 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX            BIT(25)
  62 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX            BIT(24)
  63 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK        BIT(2)
  64 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode)               ((mode) << 2)
  65 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK        GENMASK(1, 0)
  66 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode)               (mode)
  67
  68 #define SUN4I_I2S_FIFO_STA_REG          0x18
  69
  70 #define SUN4I_I2S_DMA_INT_CTRL_REG      0x1c
  71 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN        BIT(7)
  72 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN        BIT(3)
  73
  74 #define SUN4I_I2S_INT_STA_REG           0x20
  75
  76 #define SUN4I_I2S_CLK_DIV_REG           0x24
  77 #define SUN4I_I2S_CLK_DIV_MCLK_EN               BIT(7)
  78 #define SUN4I_I2S_CLK_DIV_BCLK_MASK             GENMASK(6, 4)
  79 #define SUN4I_I2S_CLK_DIV_BCLK(bclk)                    ((bclk) << 4)
  80 #define SUN4I_I2S_CLK_DIV_MCLK_MASK             GENMASK(3, 0)
  81 #define SUN4I_I2S_CLK_DIV_MCLK(mclk)                    ((mclk) << 0)
  82
  83 #define SUN4I_I2S_TX_CNT_REG            0x28
  84 #define SUN4I_I2S_RX_CNT_REG            0x2c
  85
  86 #define SUN4I_I2S_TX_CHAN_SEL_REG       0x30
  87 #define SUN4I_I2S_CHAN_SEL(num_chan)            (((num_chan) - 1) << 0)
  88
  89 #define SUN4I_I2S_TX_CHAN_MAP_REG       0x34
  90 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample)     ((sample) << (chan << 2))
  91
  92 #define SUN4I_I2S_RX_CHAN_SEL_REG       0x38
  93 #define SUN4I_I2S_RX_CHAN_MAP_REG       0x3c
  94
  95 /* Defines required for sun8i-h3 support */
  96 #define SUN8I_I2S_CTRL_BCLK_OUT                 BIT(18)
  97 #define SUN8I_I2S_CTRL_LRCK_OUT                 BIT(17)
  98
  99 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK         GENMASK(17, 8)
 100 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period)      ((period - 1) << 8)
 101
 102 #define SUN8I_I2S_INT_STA_REG           0x0c
 103 #define SUN8I_I2S_FIFO_TX_REG           0x20
 104
 105 #define SUN8I_I2S_CHAN_CFG_REG          0x30
 106 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK     GENMASK(6, 4)
 107 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan)    ((chan - 1) << 4)
 108 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK     GENMASK(2, 0)
 109 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan)    (chan - 1)
 110
 111 #define SUN8I_I2S_TX_CHAN_MAP_REG       0x44
 112 #define SUN8I_I2S_TX_CHAN_SEL_REG       0x34
 113 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK           GENMASK(13, 12)
 114 #define SUN8I_I2S_TX_CHAN_OFFSET(offset)        (offset << 12)
 115 #define SUN8I_I2S_TX_CHAN_EN_MASK               GENMASK(11, 4)
 116 #define SUN8I_I2S_TX_CHAN_EN(num_chan)          (((1 << num_chan) - 1) << 4)
 117
 118 #define SUN8I_I2S_RX_CHAN_SEL_REG       0x54
 119 #define SUN8I_I2S_RX_CHAN_MAP_REG       0x58
 120
 121 /**
 122  * struct sun4i_i2s_quirks - Differences between SoC variants.
 123  *
 124  * @has_reset: SoC needs reset deasserted.
 125  * @has_slave_select_bit: SoC has a bit to enable slave mode.
 126  * @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
 127  * @has_chcfg: tx and rx slot number need to be set.
 128  * @has_chsel_tx_chen: SoC requires that the tx channels are enabled.
 129  * @has_chsel_offset: SoC uses offset for selecting dai operational mode.
 130  * @reg_offset_txdata: offset of the tx fifo.
 131  * @sun4i_i2s_regmap: regmap config to use.
 132  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
 133  * @bclk_offset: Value by which bclkdiv needs to be adjusted.
 134  * @fmt_offset: Value by which wss and sr needs to be adjusted.
 135  * @field_clkdiv_mclk_en: regmap field to enable mclk output.
 136  * @field_fmt_wss: regmap field to set word select size.
 137  * @field_fmt_sr: regmap field to set sample resolution.
 138  * @field_fmt_bclk: regmap field to set clk polarity.
 139  * @field_fmt_lrclk: regmap field to set frame polarity.
 140  * @field_fmt_mode: regmap field to set the operational mode.
 141  * @field_txchanmap: location of the tx channel mapping register.
 142  * @field_rxchanmap: location of the rx channel mapping register.
 143  * @field_txchansel: location of the tx channel select bit fields.
 144  * @field_rxchansel: location of the rx channel select bit fields.
 145  */
 146 struct sun4i_i2s_quirks {
 147         bool                            has_reset;
 148         bool                            has_slave_select_bit;
 149         bool                            has_fmt_set_lrck_period;
 150         bool                            has_chcfg;
 151         bool                            has_chsel_tx_chen;
 152         bool                            has_chsel_offset;
 153         unsigned int                    reg_offset_txdata;      /* TX FIFO */
 154         const struct regmap_config      *sun4i_i2s_regmap;
 155         unsigned int                    mclk_offset;
 156         unsigned int                    bclk_offset;
 157         unsigned int                    fmt_offset;
 158
 159         /* Register fields for i2s */
 160         struct reg_field                field_clkdiv_mclk_en;
 161         struct reg_field                field_fmt_wss;
 162         struct reg_field                field_fmt_sr;
 163         struct reg_field                field_fmt_bclk;
 164         struct reg_field                field_fmt_lrclk;
 165         struct reg_field                field_fmt_mode;
 166         struct reg_field                field_txchanmap;
 167         struct reg_field                field_rxchanmap;
 168         struct reg_field                field_txchansel;
 169         struct reg_field                field_rxchansel;
 170 };
 171
 172 struct sun4i_i2s {
 173         struct clk      *bus_clk;
 174         struct clk      *mod_clk;
 175         struct regmap   *regmap;
 176         struct reset_control *rst;
 177
 178         unsigned int    mclk_freq;
 179
 180         struct snd_dmaengine_dai_dma_data       capture_dma_data;
 181         struct snd_dmaengine_dai_dma_data       playback_dma_data;
 182
 183         /* Register fields for i2s */
 184         struct regmap_field     *field_clkdiv_mclk_en;
 185         struct regmap_field     *field_fmt_wss;
 186         struct regmap_field     *field_fmt_sr;
 187         struct regmap_field     *field_fmt_bclk;
 188         struct regmap_field     *field_fmt_lrclk;
 189         struct regmap_field     *field_fmt_mode;
 190         struct regmap_field     *field_txchanmap;
 191         struct regmap_field     *field_rxchanmap;
 192         struct regmap_field     *field_txchansel;
 193         struct regmap_field     *field_rxchansel;
 194
 195         const struct sun4i_i2s_quirks   *variant;
 196 };
 197
 198 struct sun4i_i2s_clk_div {
 199         u8      div;
 200         u8      val;
 201 };
 202
 203 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
 204         { .div = 2, .val = 0 },
 205         { .div = 4, .val = 1 },
 206         { .div = 6, .val = 2 },
 207         { .div = 8, .val = 3 },
 208         { .div = 12, .val = 4 },
 209         { .div = 16, .val = 5 },
 210         /* TODO - extend divide ratio supported by newer SoCs */
 211 };
 212
 213 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
 214         { .div = 1, .val = 0 },
 215         { .div = 2, .val = 1 },
 216         { .div = 4, .val = 2 },
 217         { .div = 6, .val = 3 },
 218         { .div = 8, .val = 4 },
 219         { .div = 12, .val = 5 },
 220         { .div = 16, .val = 6 },
 221         { .div = 24, .val = 7 },
 222         /* TODO - extend divide ratio supported by newer SoCs */
 223 };
 224
 225 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
 226                                   unsigned long parent_rate,
 227                                   unsigned int sampling_rate,
 228                                   unsigned int word_size)
 229 {
 230         int div = parent_rate / sampling_rate / word_size / 2;
 231         int i;
 232
 233         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
 234                 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
 235
 236                 if (bdiv->div == div)
 237                         return bdiv->val;
 238         }
 239
 240         return -EINVAL;
 241 }
 242
 243 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
 244                                   unsigned int oversample_rate,
 245                                   unsigned int module_rate,
 246                                   unsigned int sampling_rate)
 247 {
 248         int div = module_rate / sampling_rate / oversample_rate;
 249         int i;
 250
 251         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
 252                 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
 253
 254                 if (mdiv->div == div)
 255                         return mdiv->val;
 256         }
 257
 258         return -EINVAL;
 259 }
 260
 261 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
 262 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
 263 {
 264         int i;
 265
 266         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
 267                 if (sun4i_i2s_oversample_rates[i] == oversample)
 268                         return true;
 269
 270         return false;
 271 }
 272
 273 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
 274                                   unsigned int rate,
 275                                   unsigned int word_size)
 276 {
 277         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 278         unsigned int oversample_rate, clk_rate;
 279         int bclk_div, mclk_div;
 280         int ret;
 281
 282         switch (rate) {
 283         case 176400:
 284         case 88200:
 285         case 44100:
 286         case 22050:
 287         case 11025:
 288                 clk_rate = 22579200;
 289                 break;
 290
 291         case 192000:
 292         case 128000:
 293         case 96000:
 294         case 64000:
 295         case 48000:
 296         case 32000:
 297         case 24000:
 298         case 16000:
 299         case 12000:
 300         case 8000:
 301                 clk_rate = 24576000;
 302                 break;
 303
 304         default:
 305                 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
 306                 return -EINVAL;
 307         }
 308
 309         ret = clk_set_rate(i2s->mod_clk, clk_rate);
 310         if (ret)
 311                 return ret;
 312
 313         oversample_rate = i2s->mclk_freq / rate;
 314         if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
 315                 dev_err(dai->dev, "Unsupported oversample rate: %d\n",
 316                         oversample_rate);
 317                 return -EINVAL;
 318         }
 319
 320         bclk_div = sun4i_i2s_get_bclk_div(i2s, i2s->mclk_freq,
 321                                           rate, word_size);
 322         if (bclk_div < 0) {
 323                 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
 324                 return -EINVAL;
 325         }
 326
 327         mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
 328                                           clk_rate, rate);
 329         if (mclk_div < 0) {
 330                 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
 331                 return -EINVAL;
 332         }
 333
 334         /* Adjust the clock division values if needed */
 335         bclk_div += i2s->variant->bclk_offset;
 336         mclk_div += i2s->variant->mclk_offset;
 337
 338         regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
 339                      SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
 340                      SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
 341
 342         regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
 343
 344         /* Set sync period */
 345         if (i2s->variant->has_fmt_set_lrck_period)
 346                 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
 347                                    SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
 348                                    SUN8I_I2S_FMT0_LRCK_PERIOD(32));
 349
 350         return 0;
 351 }
 352
 353 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
 354                                struct snd_pcm_hw_params *params,
 355                                struct snd_soc_dai *dai)
 356 {
 357         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 358         int sr, wss, channels;
 359         u32 width;
 360
 361         channels = params_channels(params);
 362         if (channels != 2) {
 363                 dev_err(dai->dev, "Unsupported number of channels: %d\n",
 364                         channels);
 365                 return -EINVAL;
 366         }
 367
 368         if (i2s->variant->has_chcfg) {
 369                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 370                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
 371                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
 372                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 373                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
 374                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
 375         }
 376
 377         /* Map the channels for playback and capture */
 378         regmap_field_write(i2s->field_txchanmap, 0x76543210);
 379         regmap_field_write(i2s->field_rxchanmap, 0x00003210);
 380
 381         /* Configure the channels */
 382         regmap_field_write(i2s->field_txchansel,
 383                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 384
 385         regmap_field_write(i2s->field_rxchansel,
 386                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 387
 388         if (i2s->variant->has_chsel_tx_chen)
 389                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 390                                    SUN8I_I2S_TX_CHAN_EN_MASK,
 391                                    SUN8I_I2S_TX_CHAN_EN(channels));
 392
 393         switch (params_physical_width(params)) {
 394         case 16:
 395                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 396                 break;
 397         default:
 398                 dev_err(dai->dev, "Unsupported physical sample width: %d\n",
 399                         params_physical_width(params));
 400                 return -EINVAL;
 401         }
 402         i2s->playback_dma_data.addr_width = width;
 403
 404         switch (params_width(params)) {
 405         case 16:
 406                 sr = 0;
 407                 wss = 0;
 408                 break;
 409
 410         default:
 411                 dev_err(dai->dev, "Unsupported sample width: %d\n",
 412                         params_width(params));
 413                 return -EINVAL;
 414         }
 415
 416         regmap_field_write(i2s->field_fmt_wss,
 417                            wss + i2s->variant->fmt_offset);
 418         regmap_field_write(i2s->field_fmt_sr,
 419                            sr + i2s->variant->fmt_offset);
 420
 421         return sun4i_i2s_set_clk_rate(dai, params_rate(params),
 422                                       params_width(params));
 423 }
 424
 425 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 426 {
 427         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 428         u32 val;
 429         u32 offset = 0;
 430         u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 431         u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 432
 433         /* DAI Mode */
 434         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 435         case SND_SOC_DAIFMT_I2S:
 436                 val = SUN4I_I2S_FMT0_FMT_I2S;
 437                 offset = 1;
 438                 break;
 439         case SND_SOC_DAIFMT_LEFT_J:
 440                 val = SUN4I_I2S_FMT0_FMT_LEFT_J;
 441                 break;
 442         case SND_SOC_DAIFMT_RIGHT_J:
 443                 val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
 444                 break;
 445         default:
 446                 dev_err(dai->dev, "Unsupported format: %d\n",
 447                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 448                 return -EINVAL;
 449         }
 450
 451         if (i2s->variant->has_chsel_offset) {
 452                 /*
 453                  * offset being set indicates that we're connected to an i2s
 454                  * device, however offset is only used on the sun8i block and
 455                  * i2s shares the same setting with the LJ format. Increment
 456                  * val so that the bit to value to write is correct.
 457                  */
 458                 if (offset > 0)
 459                         val++;
 460                 /* blck offset determines whether i2s or LJ */
 461                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 462                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 463                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 464
 465                 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
 466                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 467                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 468         }
 469
 470         regmap_field_write(i2s->field_fmt_mode, val);
 471
 472         /* DAI clock polarity */
 473         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 474         case SND_SOC_DAIFMT_IB_IF:
 475                 /* Invert both clocks */
 476                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 477                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 478                 break;
 479         case SND_SOC_DAIFMT_IB_NF:
 480                 /* Invert bit clock */
 481                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 482                 break;
 483         case SND_SOC_DAIFMT_NB_IF:
 484                 /* Invert frame clock */
 485                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 486                 break;
 487         case SND_SOC_DAIFMT_NB_NF:
 488                 break;
 489         default:
 490                 dev_err(dai->dev, "Unsupported clock polarity: %d\n",
 491                         fmt & SND_SOC_DAIFMT_INV_MASK);
 492                 return -EINVAL;
 493         }
 494
 495         regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
 496         regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
 497
 498         if (i2s->variant->has_slave_select_bit) {
 499                 /* DAI clock master masks */
 500                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 501                 case SND_SOC_DAIFMT_CBS_CFS:
 502                         /* BCLK and LRCLK master */
 503                         val = SUN4I_I2S_CTRL_MODE_MASTER;
 504                         break;
 505                 case SND_SOC_DAIFMT_CBM_CFM:
 506                         /* BCLK and LRCLK slave */
 507                         val = SUN4I_I2S_CTRL_MODE_SLAVE;
 508                         break;
 509                 default:
 510                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 511                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 512                         return -EINVAL;
 513                 }
 514                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 515                                    SUN4I_I2S_CTRL_MODE_MASK,
 516                                    val);
 517         } else {
 518                 /*
 519                  * The newer i2s block does not have a slave select bit,
 520                  * instead the clk pins are configured as inputs.
 521                  */
 522                 /* DAI clock master masks */
 523                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 524                 case SND_SOC_DAIFMT_CBS_CFS:
 525                         /* BCLK and LRCLK master */
 526                         val = SUN8I_I2S_CTRL_BCLK_OUT |
 527                                 SUN8I_I2S_CTRL_LRCK_OUT;
 528                         break;
 529                 case SND_SOC_DAIFMT_CBM_CFM:
 530                         /* BCLK and LRCLK slave */
 531                         val = 0;
 532                         break;
 533                 default:
 534                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 535                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 536                         return -EINVAL;
 537                 }
 538                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 539                                    SUN8I_I2S_CTRL_BCLK_OUT |
 540                                    SUN8I_I2S_CTRL_LRCK_OUT,
 541                                    val);
 542         }
 543
 544         /* Set significant bits in our FIFOs */
 545         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 546                            SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
 547                            SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
 548                            SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
 549                            SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
 550         return 0;
 551 }
 552
 553 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
 554 {
 555         /* Flush RX FIFO */
 556         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 557                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
 558                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
 559
 560         /* Clear RX counter */
 561         regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
 562
 563         /* Enable RX Block */
 564         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 565                            SUN4I_I2S_CTRL_RX_EN,
 566                            SUN4I_I2S_CTRL_RX_EN);
 567
 568         /* Enable RX DRQ */
 569         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 570                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 571                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
 572 }
 573
 574 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
 575 {
 576         /* Flush TX FIFO */
 577         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 578                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
 579                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
 580
 581         /* Clear TX counter */
 582         regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
 583
 584         /* Enable TX Block */
 585         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 586                            SUN4I_I2S_CTRL_TX_EN,
 587                            SUN4I_I2S_CTRL_TX_EN);
 588
 589         /* Enable TX DRQ */
 590         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 591                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 592                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
 593 }
 594
 595 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
 596 {
 597         /* Disable RX Block */
 598         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 599                            SUN4I_I2S_CTRL_RX_EN,
 600                            0);
 601
 602         /* Disable RX DRQ */
 603         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 604                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 605                            0);
 606 }
 607
 608 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
 609 {
 610         /* Disable TX Block */
 611         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 612                            SUN4I_I2S_CTRL_TX_EN,
 613                            0);
 614
 615         /* Disable TX DRQ */
 616         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 617                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 618                            0);
 619 }
 620
 621 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 622                              struct snd_soc_dai *dai)
 623 {
 624         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 625
 626         switch (cmd) {
 627         case SNDRV_PCM_TRIGGER_START:
 628         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 629         case SNDRV_PCM_TRIGGER_RESUME:
 630                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 631                         sun4i_i2s_start_playback(i2s);
 632                 else
 633                         sun4i_i2s_start_capture(i2s);
 634                 break;
 635
 636         case SNDRV_PCM_TRIGGER_STOP:
 637         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 638         case SNDRV_PCM_TRIGGER_SUSPEND:
 639                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 640                         sun4i_i2s_stop_playback(i2s);
 641                 else
 642                         sun4i_i2s_stop_capture(i2s);
 643                 break;
 644
 645         default:
 646                 return -EINVAL;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static int sun4i_i2s_startup(struct snd_pcm_substream *substream,
 653                              struct snd_soc_dai *dai)
 654 {
 655         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 656
 657         /* Enable the whole hardware block */
 658         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 659                            SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
 660
 661         /* Enable the first output line */
 662         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 663                            SUN4I_I2S_CTRL_SDO_EN_MASK,
 664                            SUN4I_I2S_CTRL_SDO_EN(0));
 665
 666
 667         return clk_prepare_enable(i2s->mod_clk);
 668 }
 669
 670 static void sun4i_i2s_shutdown(struct snd_pcm_substream *substream,
 671                                struct snd_soc_dai *dai)
 672 {
 673         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 674
 675         clk_disable_unprepare(i2s->mod_clk);
 676
 677         /* Disable our output lines */
 678         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 679                            SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
 680
 681         /* Disable the whole hardware block */
 682         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 683                            SUN4I_I2S_CTRL_GL_EN, 0);
 684 }
 685
 686 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 687                                 unsigned int freq, int dir)
 688 {
 689         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 690
 691         if (clk_id != 0)
 692                 return -EINVAL;
 693
 694         i2s->mclk_freq = freq;
 695
 696         return 0;
 697 }
 698
 699 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
 700         .hw_params      = sun4i_i2s_hw_params,
 701         .set_fmt        = sun4i_i2s_set_fmt,
 702         .set_sysclk     = sun4i_i2s_set_sysclk,
 703         .shutdown       = sun4i_i2s_shutdown,
 704         .startup        = sun4i_i2s_startup,
 705         .trigger        = sun4i_i2s_trigger,
 706 };
 707
 708 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
 709 {
 710         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 711
 712         snd_soc_dai_init_dma_data(dai,
 713                                   &i2s->playback_dma_data,
 714                                   &i2s->capture_dma_data);
 715
 716         snd_soc_dai_set_drvdata(dai, i2s);
 717
 718         return 0;
 719 }
 720
 721 static struct snd_soc_dai_driver sun4i_i2s_dai = {
 722         .probe = sun4i_i2s_dai_probe,
 723         .capture = {
 724                 .stream_name = "Capture",
 725                 .channels_min = 2,
 726                 .channels_max = 2,
 727                 .rates = SNDRV_PCM_RATE_8000_192000,
 728                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 729         },
 730         .playback = {
 731                 .stream_name = "Playback",
 732                 .channels_min = 2,
 733                 .channels_max = 2,
 734                 .rates = SNDRV_PCM_RATE_8000_192000,
 735                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 736         },
 737         .ops = &sun4i_i2s_dai_ops,
 738         .symmetric_rates = 1,
 739 };
 740
 741 static const struct snd_soc_component_driver sun4i_i2s_component = {
 742         .name   = "sun4i-dai",
 743 };
 744
 745 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
 746 {
 747         switch (reg) {
 748         case SUN4I_I2S_FIFO_TX_REG:
 749                 return false;
 750
 751         default:
 752                 return true;
 753         }
 754 }
 755
 756 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
 757 {
 758         switch (reg) {
 759         case SUN4I_I2S_FIFO_RX_REG:
 760         case SUN4I_I2S_FIFO_STA_REG:
 761                 return false;
 762
 763         default:
 764                 return true;
 765         }
 766 }
 767
 768 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 769 {
 770         switch (reg) {
 771         case SUN4I_I2S_FIFO_RX_REG:
 772         case SUN4I_I2S_INT_STA_REG:
 773         case SUN4I_I2S_RX_CNT_REG:
 774         case SUN4I_I2S_TX_CNT_REG:
 775                 return true;
 776
 777         default:
 778                 return false;
 779         }
 780 }
 781
 782 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
 783 {
 784         switch (reg) {
 785         case SUN8I_I2S_FIFO_TX_REG:
 786                 return false;
 787
 788         default:
 789                 return true;
 790         }
 791 }
 792
 793 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 794 {
 795         if (reg == SUN8I_I2S_INT_STA_REG)
 796                 return true;
 797         if (reg == SUN8I_I2S_FIFO_TX_REG)
 798                 return false;
 799
 800         return sun4i_i2s_volatile_reg(dev, reg);
 801 }
 802
 803 static const struct reg_default sun4i_i2s_reg_defaults[] = {
 804         { SUN4I_I2S_CTRL_REG, 0x00000000 },
 805         { SUN4I_I2S_FMT0_REG, 0x0000000c },
 806         { SUN4I_I2S_FMT1_REG, 0x00004020 },
 807         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 808         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 809         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 810         { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
 811         { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
 812         { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
 813         { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
 814 };
 815
 816 static const struct reg_default sun8i_i2s_reg_defaults[] = {
 817         { SUN4I_I2S_CTRL_REG, 0x00060000 },
 818         { SUN4I_I2S_FMT0_REG, 0x00000033 },
 819         { SUN4I_I2S_FMT1_REG, 0x00000030 },
 820         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 821         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 822         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 823         { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
 824         { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
 825         { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
 826         { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
 827         { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
 828 };
 829
 830 static const struct regmap_config sun4i_i2s_regmap_config = {
 831         .reg_bits       = 32,
 832         .reg_stride     = 4,
 833         .val_bits       = 32,
 834         .max_register   = SUN4I_I2S_RX_CHAN_MAP_REG,
 835
 836         .cache_type     = REGCACHE_FLAT,
 837         .reg_defaults   = sun4i_i2s_reg_defaults,
 838         .num_reg_defaults       = ARRAY_SIZE(sun4i_i2s_reg_defaults),
 839         .writeable_reg  = sun4i_i2s_wr_reg,
 840         .readable_reg   = sun4i_i2s_rd_reg,
 841         .volatile_reg   = sun4i_i2s_volatile_reg,
 842 };
 843
 844 static const struct regmap_config sun8i_i2s_regmap_config = {
 845         .reg_bits       = 32,
 846         .reg_stride     = 4,
 847         .val_bits       = 32,
 848         .max_register   = SUN8I_I2S_RX_CHAN_MAP_REG,
 849         .cache_type     = REGCACHE_FLAT,
 850         .reg_defaults   = sun8i_i2s_reg_defaults,
 851         .num_reg_defaults       = ARRAY_SIZE(sun8i_i2s_reg_defaults),
 852         .writeable_reg  = sun4i_i2s_wr_reg,
 853         .readable_reg   = sun8i_i2s_rd_reg,
 854         .volatile_reg   = sun8i_i2s_volatile_reg,
 855 };
 856
 857 static int sun4i_i2s_runtime_resume(struct device *dev)
 858 {
 859         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 860         int ret;
 861
 862         ret = clk_prepare_enable(i2s->bus_clk);
 863         if (ret) {
 864                 dev_err(dev, "Failed to enable bus clock\n");
 865                 return ret;
 866         }
 867
 868         regcache_cache_only(i2s->regmap, false);
 869         regcache_mark_dirty(i2s->regmap);
 870
 871         ret = regcache_sync(i2s->regmap);
 872         if (ret) {
 873                 dev_err(dev, "Failed to sync regmap cache\n");
 874                 goto err_disable_clk;
 875         }
 876
 877         return 0;
 878
 879 err_disable_clk:
 880         clk_disable_unprepare(i2s->bus_clk);
 881         return ret;
 882 }
 883
 884 static int sun4i_i2s_runtime_suspend(struct device *dev)
 885 {
 886         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 887
 888         regcache_cache_only(i2s->regmap, true);
 889
 890         clk_disable_unprepare(i2s->bus_clk);
 891
 892         return 0;
 893 }
 894
 895 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
 896         .has_reset              = false,
 897         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 898         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 899         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 900         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 901         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 902         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 903         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 904         .has_slave_select_bit   = true,
 905         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 906         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 907         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 908         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 909         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 910 };
 911
 912 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
 913         .has_reset              = true,
 914         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 915         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 916         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 917         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 918         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 919         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 920         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 921         .has_slave_select_bit   = true,
 922         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 923         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 924         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 925         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 926         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 927 };
 928
 929 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
 930         .has_reset              = true,
 931         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 932         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 933         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 934         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 935         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 936         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 937         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 938         .has_slave_select_bit   = true,
 939         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 940         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 941         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 942         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 943         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 944 };
 945
 946 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
 947         .has_reset              = true,
 948         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 949         .sun4i_i2s_regmap       = &sun8i_i2s_regmap_config,
 950         .mclk_offset            = 1,
 951         .bclk_offset            = 2,
 952         .fmt_offset             = 3,
 953         .has_fmt_set_lrck_period = true,
 954         .has_chcfg              = true,
 955         .has_chsel_tx_chen      = true,
 956         .has_chsel_offset       = true,
 957         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
 958         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
 959         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
 960         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 961         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
 962         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
 963         .field_txchanmap        = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
 964         .field_rxchanmap        = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
 965         .field_txchansel        = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
 966         .field_rxchansel        = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
 967 };
 968
 969 static int sun4i_i2s_init_regmap_fields(struct device *dev,
 970                                         struct sun4i_i2s *i2s)
 971 {
 972         i2s->field_clkdiv_mclk_en =
 973                 devm_regmap_field_alloc(dev, i2s->regmap,
 974                                         i2s->variant->field_clkdiv_mclk_en);
 975         if (IS_ERR(i2s->field_clkdiv_mclk_en))
 976                 return PTR_ERR(i2s->field_clkdiv_mclk_en);
 977
 978         i2s->field_fmt_wss =
 979                         devm_regmap_field_alloc(dev, i2s->regmap,
 980                                                 i2s->variant->field_fmt_wss);
 981         if (IS_ERR(i2s->field_fmt_wss))
 982                 return PTR_ERR(i2s->field_fmt_wss);
 983
 984         i2s->field_fmt_sr =
 985                         devm_regmap_field_alloc(dev, i2s->regmap,
 986                                                 i2s->variant->field_fmt_sr);
 987         if (IS_ERR(i2s->field_fmt_sr))
 988                 return PTR_ERR(i2s->field_fmt_sr);
 989
 990         i2s->field_fmt_bclk =
 991                         devm_regmap_field_alloc(dev, i2s->regmap,
 992                                                 i2s->variant->field_fmt_bclk);
 993         if (IS_ERR(i2s->field_fmt_bclk))
 994                 return PTR_ERR(i2s->field_fmt_bclk);
 995
 996         i2s->field_fmt_lrclk =
 997                         devm_regmap_field_alloc(dev, i2s->regmap,
 998                                                 i2s->variant->field_fmt_lrclk);
 999         if (IS_ERR(i2s->field_fmt_lrclk))
1000                 return PTR_ERR(i2s->field_fmt_lrclk);
1001
1002         i2s->field_fmt_mode =
1003                         devm_regmap_field_alloc(dev, i2s->regmap,
1004                                                 i2s->variant->field_fmt_mode);
1005         if (IS_ERR(i2s->field_fmt_mode))
1006                 return PTR_ERR(i2s->field_fmt_mode);
1007
1008         i2s->field_txchanmap =
1009                         devm_regmap_field_alloc(dev, i2s->regmap,
1010                                                 i2s->variant->field_txchanmap);
1011         if (IS_ERR(i2s->field_txchanmap))
1012                 return PTR_ERR(i2s->field_txchanmap);
1013
1014         i2s->field_rxchanmap =
1015                         devm_regmap_field_alloc(dev, i2s->regmap,
1016                                                 i2s->variant->field_rxchanmap);
1017         if (IS_ERR(i2s->field_rxchanmap))
1018                 return PTR_ERR(i2s->field_rxchanmap);
1019
1020         i2s->field_txchansel =
1021                         devm_regmap_field_alloc(dev, i2s->regmap,
1022                                                 i2s->variant->field_txchansel);
1023         if (IS_ERR(i2s->field_txchansel))
1024                 return PTR_ERR(i2s->field_txchansel);
1025
1026         i2s->field_rxchansel =
1027                         devm_regmap_field_alloc(dev, i2s->regmap,
1028                                                 i2s->variant->field_rxchansel);
1029         return PTR_ERR_OR_ZERO(i2s->field_rxchansel);
1030 }
1031
1032 static int sun4i_i2s_probe(struct platform_device *pdev)
1033 {
1034         struct sun4i_i2s *i2s;
1035         struct resource *res;
1036         void __iomem *regs;
1037         int irq, ret;
1038
1039         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1040         if (!i2s)
1041                 return -ENOMEM;
1042         platform_set_drvdata(pdev, i2s);
1043
1044         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1045         regs = devm_ioremap_resource(&pdev->dev, res);
1046         if (IS_ERR(regs))
1047                 return PTR_ERR(regs);
1048
1049         irq = platform_get_irq(pdev, 0);
1050         if (irq < 0) {
1051                 dev_err(&pdev->dev, "Can't retrieve our interrupt\n");
1052                 return irq;
1053         }
1054
1055         i2s->variant = of_device_get_match_data(&pdev->dev);
1056         if (!i2s->variant) {
1057                 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1058                 return -ENODEV;
1059         }
1060
1061         i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
1062         if (IS_ERR(i2s->bus_clk)) {
1063                 dev_err(&pdev->dev, "Can't get our bus clock\n");
1064                 return PTR_ERR(i2s->bus_clk);
1065         }
1066
1067         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1068                                             i2s->variant->sun4i_i2s_regmap);
1069         if (IS_ERR(i2s->regmap)) {
1070                 dev_err(&pdev->dev, "Regmap initialisation failed\n");
1071                 return PTR_ERR(i2s->regmap);
1072         }
1073
1074         i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
1075         if (IS_ERR(i2s->mod_clk)) {
1076                 dev_err(&pdev->dev, "Can't get our mod clock\n");
1077                 return PTR_ERR(i2s->mod_clk);
1078         }
1079
1080         if (i2s->variant->has_reset) {
1081                 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1082                 if (IS_ERR(i2s->rst)) {
1083                         dev_err(&pdev->dev, "Failed to get reset control\n");
1084                         return PTR_ERR(i2s->rst);
1085                 }
1086         }
1087
1088         if (!IS_ERR(i2s->rst)) {
1089                 ret = reset_control_deassert(i2s->rst);
1090                 if (ret) {
1091                         dev_err(&pdev->dev,
1092                                 "Failed to deassert the reset control\n");
1093                         return -EINVAL;
1094                 }
1095         }
1096
1097         i2s->playback_dma_data.addr = res->start +
1098                                         i2s->variant->reg_offset_txdata;
1099         i2s->playback_dma_data.maxburst = 8;
1100
1101         i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
1102         i2s->capture_dma_data.maxburst = 8;
1103
1104         pm_runtime_enable(&pdev->dev);
1105         if (!pm_runtime_enabled(&pdev->dev)) {
1106                 ret = sun4i_i2s_runtime_resume(&pdev->dev);
1107                 if (ret)
1108                         goto err_pm_disable;
1109         }
1110
1111         ret = devm_snd_soc_register_component(&pdev->dev,
1112                                               &sun4i_i2s_component,
1113                                               &sun4i_i2s_dai, 1);
1114         if (ret) {
1115                 dev_err(&pdev->dev, "Could not register DAI\n");
1116                 goto err_suspend;
1117         }
1118
1119         ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1120         if (ret) {
1121                 dev_err(&pdev->dev, "Could not register PCM\n");
1122                 goto err_suspend;
1123         }
1124
1125         ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
1126         if (ret) {
1127                 dev_err(&pdev->dev, "Could not initialise regmap fields\n");
1128                 goto err_suspend;
1129         }
1130
1131         return 0;
1132
1133 err_suspend:
1134         if (!pm_runtime_status_suspended(&pdev->dev))
1135                 sun4i_i2s_runtime_suspend(&pdev->dev);
1136 err_pm_disable:
1137         pm_runtime_disable(&pdev->dev);
1138         if (!IS_ERR(i2s->rst))
1139                 reset_control_assert(i2s->rst);
1140
1141         return ret;
1142 }
1143
1144 static int sun4i_i2s_remove(struct platform_device *pdev)
1145 {
1146         struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
1147
1148         snd_dmaengine_pcm_unregister(&pdev->dev);
1149
1150         pm_runtime_disable(&pdev->dev);
1151         if (!pm_runtime_status_suspended(&pdev->dev))
1152                 sun4i_i2s_runtime_suspend(&pdev->dev);
1153
1154         if (!IS_ERR(i2s->rst))
1155                 reset_control_assert(i2s->rst);
1156
1157         return 0;
1158 }
1159
1160 static const struct of_device_id sun4i_i2s_match[] = {
1161         {
1162                 .compatible = "allwinner,sun4i-a10-i2s",
1163                 .data = &sun4i_a10_i2s_quirks,
1164         },
1165         {
1166                 .compatible = "allwinner,sun6i-a31-i2s",
1167                 .data = &sun6i_a31_i2s_quirks,
1168         },
1169         {
1170                 .compatible = "allwinner,sun8i-a83t-i2s",
1171                 .data = &sun8i_a83t_i2s_quirks,
1172         },
1173         {
1174                 .compatible = "allwinner,sun8i-h3-i2s",
1175                 .data = &sun8i_h3_i2s_quirks,
1176         },
1177         {}
1178 };
1179 MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
1180
1181 static const struct dev_pm_ops sun4i_i2s_pm_ops = {
1182         .runtime_resume         = sun4i_i2s_runtime_resume,
1183         .runtime_suspend        = sun4i_i2s_runtime_suspend,
1184 };
1185
1186 static struct platform_driver sun4i_i2s_driver = {
1187         .probe  = sun4i_i2s_probe,
1188         .remove = sun4i_i2s_remove,
1189         .driver = {
1190                 .name           = "sun4i-i2s",
1191                 .of_match_table = sun4i_i2s_match,
1192                 .pm             = &sun4i_i2s_pm_ops,
1193         },
1194 };
1195 module_platform_driver(sun4i_i2s_driver);
1196
1197 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
1198 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1199 MODULE_DESCRIPTION("Allwinner A10 I2S driver");
1200 MODULE_LICENSE("GPL");