sound/soc/sunxi/sun8i-codec.c

   1 /*
   2  * This driver supports the digital controls for the internal codec
   3  * found in Allwinner's A33 SoCs.
   4  *
   5  * (C) Copyright 2010-2016
   6  * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
   7  * huangxin <huangxin@Reuuimllatech.com>
   8  * Mylène Josserand <mylene.josserand@free-electrons.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regmap.h>
  27
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <sound/soc-dapm.h>
  31
  32 #define SUN8I_SYSCLK_CTL                                0x00c
  33 #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA                    11
  34 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL                9
  35 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC                    8
  36 #define SUN8I_SYSCLK_CTL_SYSCLK_ENA                     3
  37 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC                     0
  38 #define SUN8I_MOD_CLK_ENA                               0x010
  39 #define SUN8I_MOD_CLK_ENA_AIF1                          15
  40 #define SUN8I_MOD_CLK_ENA_DAC                           2
  41 #define SUN8I_MOD_RST_CTL                               0x014
  42 #define SUN8I_MOD_RST_CTL_AIF1                          15
  43 #define SUN8I_MOD_RST_CTL_DAC                           2
  44 #define SUN8I_SYS_SR_CTRL                               0x018
  45 #define SUN8I_SYS_SR_CTRL_AIF1_FS                       12
  46 #define SUN8I_SYS_SR_CTRL_AIF2_FS                       8
  47 #define SUN8I_AIF1CLK_CTRL                              0x040
  48 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD                15
  49 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV                14
  50 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV                13
  51 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV                9
  52 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV                6
  53 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16             (1 << 6)
  54 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ                4
  55 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16             (1 << 4)
  56 #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT                2
  57 #define SUN8I_AIF1_DACDAT_CTRL                          0x048
  58 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA            15
  59 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA            14
  60 #define SUN8I_DAC_DIG_CTRL                              0x120
  61 #define SUN8I_DAC_DIG_CTRL_ENDA                 15
  62 #define SUN8I_DAC_MXR_SRC                               0x130
  63 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
  64 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
  65 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
  66 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL             12
  67 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
  68 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
  69 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
  70 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR             8
  71
  72 #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK          GENMASK(15, 12)
  73 #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK          GENMASK(11, 8)
  74 #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK   GENMASK(3, 2)
  75 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK   GENMASK(5, 4)
  76 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK   GENMASK(8, 6)
  77 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK   GENMASK(12, 9)
  78
  79 struct sun8i_codec {
  80         struct device   *dev;
  81         struct regmap   *regmap;
  82         struct clk      *clk_module;
  83         struct clk      *clk_bus;
  84 };
  85
  86 static int sun8i_codec_runtime_resume(struct device *dev)
  87 {
  88         struct sun8i_codec *scodec = dev_get_drvdata(dev);
  89         int ret;
  90
  91         ret = clk_prepare_enable(scodec->clk_module);
  92         if (ret) {
  93                 dev_err(dev, "Failed to enable the module clock\n");
  94                 return ret;
  95         }
  96
  97         ret = clk_prepare_enable(scodec->clk_bus);
  98         if (ret) {
  99                 dev_err(dev, "Failed to enable the bus clock\n");
 100                 goto err_disable_modclk;
 101         }
 102
 103         regcache_cache_only(scodec->regmap, false);
 104
 105         ret = regcache_sync(scodec->regmap);
 106         if (ret) {
 107                 dev_err(dev, "Failed to sync regmap cache\n");
 108                 goto err_disable_clk;
 109         }
 110
 111         return 0;
 112
 113 err_disable_clk:
 114         clk_disable_unprepare(scodec->clk_bus);
 115
 116 err_disable_modclk:
 117         clk_disable_unprepare(scodec->clk_module);
 118
 119         return ret;
 120 }
 121
 122 static int sun8i_codec_runtime_suspend(struct device *dev)
 123 {
 124         struct sun8i_codec *scodec = dev_get_drvdata(dev);
 125
 126         regcache_cache_only(scodec->regmap, true);
 127         regcache_mark_dirty(scodec->regmap);
 128
 129         clk_disable_unprepare(scodec->clk_module);
 130         clk_disable_unprepare(scodec->clk_bus);
 131
 132         return 0;
 133 }
 134
 135 static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
 136 {
 137         unsigned int rate = params_rate(params);
 138
 139         switch (rate) {
 140         case 8000:
 141         case 7350:
 142                 return 0x0;
 143         case 11025:
 144                 return 0x1;
 145         case 12000:
 146                 return 0x2;
 147         case 16000:
 148                 return 0x3;
 149         case 22050:
 150                 return 0x4;
 151         case 24000:
 152                 return 0x5;
 153         case 32000:
 154                 return 0x6;
 155         case 44100:
 156                 return 0x7;
 157         case 48000:
 158                 return 0x8;
 159         case 96000:
 160                 return 0x9;
 161         case 192000:
 162                 return 0xa;
 163         default:
 164                 return -EINVAL;
 165         }
 166 }
 167
 168 static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 169 {
 170         struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
 171         u32 value;
 172
 173         /* clock masters */
 174         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 175         case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */
 176                 value = 0x1;
 177                 break;
 178         case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */
 179                 value = 0x0;
 180                 break;
 181         default:
 182                 return -EINVAL;
 183         }
 184         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 185                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
 186                            value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
 187
 188         /* clock inversion */
 189         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 190         case SND_SOC_DAIFMT_NB_NF: /* Normal */
 191                 value = 0x0;
 192                 break;
 193         case SND_SOC_DAIFMT_IB_IF: /* Inversion */
 194                 value = 0x1;
 195                 break;
 196         default:
 197                 return -EINVAL;
 198         }
 199         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 200                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
 201                            value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
 202         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 203                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
 204                            !value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
 205
 206         /* DAI format */
 207         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 208         case SND_SOC_DAIFMT_I2S:
 209                 value = 0x0;
 210                 break;
 211         case SND_SOC_DAIFMT_LEFT_J:
 212                 value = 0x1;
 213                 break;
 214         case SND_SOC_DAIFMT_RIGHT_J:
 215                 value = 0x2;
 216                 break;
 217         case SND_SOC_DAIFMT_DSP_A:
 218         case SND_SOC_DAIFMT_DSP_B:
 219                 value = 0x3;
 220                 break;
 221         default:
 222                 return -EINVAL;
 223         }
 224         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 225                            SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK,
 226                            value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
 227
 228         return 0;
 229 }
 230
 231 struct sun8i_codec_clk_div {
 232         u8      div;
 233         u8      val;
 234 };
 235
 236 static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = {
 237         { .div = 1,     .val = 0 },
 238         { .div = 2,     .val = 1 },
 239         { .div = 4,     .val = 2 },
 240         { .div = 6,     .val = 3 },
 241         { .div = 8,     .val = 4 },
 242         { .div = 12,    .val = 5 },
 243         { .div = 16,    .val = 6 },
 244         { .div = 24,    .val = 7 },
 245         { .div = 32,    .val = 8 },
 246         { .div = 48,    .val = 9 },
 247         { .div = 64,    .val = 10 },
 248         { .div = 96,    .val = 11 },
 249         { .div = 128,   .val = 12 },
 250         { .div = 192,   .val = 13 },
 251 };
 252
 253 static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec,
 254                                    unsigned int rate,
 255                                    unsigned int word_size)
 256 {
 257         unsigned long clk_rate = clk_get_rate(scodec->clk_module);
 258         unsigned int div = clk_rate / rate / word_size / 2;
 259         unsigned int best_val = 0, best_diff = ~0;
 260         int i;
 261
 262         for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) {
 263                 const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i];
 264                 unsigned int diff = abs(bdiv->div - div);
 265
 266                 if (diff < best_diff) {
 267                         best_diff = diff;
 268                         best_val = bdiv->val;
 269                 }
 270         }
 271
 272         return best_val;
 273 }
 274
 275 static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
 276                                  struct snd_pcm_hw_params *params,
 277                                  struct snd_soc_dai *dai)
 278 {
 279         struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
 280         int sample_rate;
 281         u8 bclk_div;
 282
 283         /*
 284          * The CPU DAI handles only a sample of 16 bits. Configure the
 285          * codec to handle this type of sample resolution.
 286          */
 287         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 288                            SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
 289                            SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);
 290
 291         bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16);
 292         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 293                            SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK,
 294                            bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
 295
 296         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 297                            SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
 298                            SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
 299
 300         sample_rate = sun8i_codec_get_hw_rate(params);
 301         if (sample_rate < 0)
 302                 return sample_rate;
 303
 304         regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
 305                            SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
 306                            sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
 307         regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
 308                            SUN8I_SYS_SR_CTRL_AIF2_FS_MASK,
 309                            sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS);
 310
 311         return 0;
 312 }
 313
 314 static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
 315         SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
 316                         SUN8I_DAC_MXR_SRC,
 317                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
 318                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
 319         SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
 320                         SUN8I_DAC_MXR_SRC,
 321                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
 322                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
 323         SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
 324                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
 325                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
 326         SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
 327                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
 328                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
 329 };
 330
 331 static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
 332         /* Digital parts of the DACs */
 333         SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
 334                             0, NULL, 0),
 335
 336         /* Analog DAC AIF */
 337         SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
 338                             SUN8I_AIF1_DACDAT_CTRL,
 339                             SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
 340         SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
 341                             SUN8I_AIF1_DACDAT_CTRL,
 342                             SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
 343
 344         /* DAC Mixers */
 345         SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
 346                         sun8i_dac_mixer_controls),
 347         SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
 348                         sun8i_dac_mixer_controls),
 349
 350         /* Clocks */
 351         SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
 352                             SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
 353         SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
 354                             SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
 355         SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
 356                             SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
 357         SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
 358                             SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
 359
 360         SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL,
 361                             SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0),
 362         /* Inversion as 0=AIF1, 1=AIF2 */
 363         SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL,
 364                             SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),
 365
 366         /* Module reset */
 367         SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL,
 368                             SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
 369         SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
 370                             SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
 371 };
 372
 373 static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
 374         /* Clock Routes */
 375         { "AIF1", NULL, "SYSCLK AIF1" },
 376         { "AIF1 PLL", NULL, "AIF1" },
 377         { "RST AIF1", NULL, "AIF1 PLL" },
 378         { "MODCLK AFI1", NULL, "RST AIF1" },
 379         { "DAC", NULL, "MODCLK AFI1" },
 380
 381         { "RST DAC", NULL, "SYSCLK" },
 382         { "MODCLK DAC", NULL, "RST DAC" },
 383         { "DAC", NULL, "MODCLK DAC" },
 384
 385         /* DAC Routes */
 386         { "AIF1 Slot 0 Right", NULL, "DAC" },
 387         { "AIF1 Slot 0 Left", NULL, "DAC" },
 388
 389         /* DAC Mixer Routes */
 390         { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
 391           "AIF1 Slot 0 Left"},
 392         { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
 393           "AIF1 Slot 0 Right"},
 394 };
 395
 396 static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
 397         .hw_params = sun8i_codec_hw_params,
 398         .set_fmt = sun8i_set_fmt,
 399 };
 400
 401 static struct snd_soc_dai_driver sun8i_codec_dai = {
 402         .name = "sun8i",
 403         /* playback capabilities */
 404         .playback = {
 405                 .stream_name = "Playback",
 406                 .channels_min = 1,
 407                 .channels_max = 2,
 408                 .rates = SNDRV_PCM_RATE_8000_192000,
 409                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 410         },
 411         /* pcm operations */
 412         .ops = &sun8i_codec_dai_ops,
 413 };
 414
 415 static const struct snd_soc_codec_driver sun8i_soc_codec = {
 416         .component_driver = {
 417                 .dapm_widgets           = sun8i_codec_dapm_widgets,
 418                 .num_dapm_widgets       = ARRAY_SIZE(sun8i_codec_dapm_widgets),
 419                 .dapm_routes            = sun8i_codec_dapm_routes,
 420                 .num_dapm_routes        = ARRAY_SIZE(sun8i_codec_dapm_routes),
 421         },
 422 };
 423
 424 static const struct regmap_config sun8i_codec_regmap_config = {
 425         .reg_bits       = 32,
 426         .reg_stride     = 4,
 427         .val_bits       = 32,
 428         .max_register   = SUN8I_DAC_MXR_SRC,
 429
 430         .cache_type     = REGCACHE_FLAT,
 431 };
 432
 433 static int sun8i_codec_probe(struct platform_device *pdev)
 434 {
 435         struct resource *res_base;
 436         struct sun8i_codec *scodec;
 437         void __iomem *base;
 438         int ret;
 439
 440         scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
 441         if (!scodec)
 442                 return -ENOMEM;
 443
 444         scodec->dev = &pdev->dev;
 445
 446         scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
 447         if (IS_ERR(scodec->clk_module)) {
 448                 dev_err(&pdev->dev, "Failed to get the module clock\n");
 449                 return PTR_ERR(scodec->clk_module);
 450         }
 451
 452         scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
 453         if (IS_ERR(scodec->clk_bus)) {
 454                 dev_err(&pdev->dev, "Failed to get the bus clock\n");
 455                 return PTR_ERR(scodec->clk_bus);
 456         }
 457
 458         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 459         base = devm_ioremap_resource(&pdev->dev, res_base);
 460         if (IS_ERR(base)) {
 461                 dev_err(&pdev->dev, "Failed to map the registers\n");
 462                 return PTR_ERR(base);
 463         }
 464
 465         scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 466                                                &sun8i_codec_regmap_config);
 467         if (IS_ERR(scodec->regmap)) {
 468                 dev_err(&pdev->dev, "Failed to create our regmap\n");
 469                 return PTR_ERR(scodec->regmap);
 470         }
 471
 472         platform_set_drvdata(pdev, scodec);
 473
 474         pm_runtime_enable(&pdev->dev);
 475         if (!pm_runtime_enabled(&pdev->dev)) {
 476                 ret = sun8i_codec_runtime_resume(&pdev->dev);
 477                 if (ret)
 478                         goto err_pm_disable;
 479         }
 480
 481         ret = snd_soc_register_codec(&pdev->dev, &sun8i_soc_codec,
 482                                      &sun8i_codec_dai, 1);
 483         if (ret) {
 484                 dev_err(&pdev->dev, "Failed to register codec\n");
 485                 goto err_suspend;
 486         }
 487
 488         return ret;
 489
 490 err_suspend:
 491         if (!pm_runtime_status_suspended(&pdev->dev))
 492                 sun8i_codec_runtime_suspend(&pdev->dev);
 493
 494 err_pm_disable:
 495         pm_runtime_disable(&pdev->dev);
 496
 497         return ret;
 498 }
 499
 500 static int sun8i_codec_remove(struct platform_device *pdev)
 501 {
 502         struct snd_soc_card *card = platform_get_drvdata(pdev);
 503         struct sun8i_codec *scodec = snd_soc_card_get_drvdata(card);
 504
 505         pm_runtime_disable(&pdev->dev);
 506         if (!pm_runtime_status_suspended(&pdev->dev))
 507                 sun8i_codec_runtime_suspend(&pdev->dev);
 508
 509         snd_soc_unregister_codec(&pdev->dev);
 510         clk_disable_unprepare(scodec->clk_module);
 511         clk_disable_unprepare(scodec->clk_bus);
 512
 513         return 0;
 514 }
 515
 516 static const struct of_device_id sun8i_codec_of_match[] = {
 517         { .compatible = "allwinner,sun8i-a33-codec" },
 518         {}
 519 };
 520 MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
 521
 522 static const struct dev_pm_ops sun8i_codec_pm_ops = {
 523         SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
 524                            sun8i_codec_runtime_resume, NULL)
 525 };
 526
 527 static struct platform_driver sun8i_codec_driver = {
 528         .driver = {
 529                 .name = "sun8i-codec",
 530                 .of_match_table = sun8i_codec_of_match,
 531                 .pm = &sun8i_codec_pm_ops,
 532         },
 533         .probe = sun8i_codec_probe,
 534         .remove = sun8i_codec_remove,
 535 };
 536 module_platform_driver(sun8i_codec_driver);
 537
 538 MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
 539 MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>");
 540 MODULE_LICENSE("GPL");
 541 MODULE_ALIAS("platform:sun8i-codec");