tools/perf/pmu-events/arch/x86/haswellx/cache.json

   1 [
   2     {
   3         "EventCode": "0x24",
   4         "UMask": "0x21",
   5         "BriefDescription": "Demand Data Read miss L2, no rejects",
   6         "Counter": "0,1,2,3",
   7         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
   8         "Errata": "HSD78",
   9         "PublicDescription": "Demand data read requests that missed L2, no rejects.",
  10         "SampleAfterValue": "200003",
  11         "CounterHTOff": "0,1,2,3,4,5,6,7"
  12     },
  13     {
  14         "EventCode": "0x24",
  15         "UMask": "0x41",
  16         "BriefDescription": "Demand Data Read requests that hit L2 cache",
  17         "Counter": "0,1,2,3",
  18         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
  19         "Errata": "HSD78",
  20         "PublicDescription": "Demand data read requests that hit L2 cache.",
  21         "SampleAfterValue": "200003",
  22         "CounterHTOff": "0,1,2,3,4,5,6,7"
  23     },
  24     {
  25         "EventCode": "0x24",
  26         "UMask": "0x30",
  27         "BriefDescription": "L2 prefetch requests that miss L2 cache",
  28         "Counter": "0,1,2,3",
  29         "EventName": "L2_RQSTS.L2_PF_MISS",
  30         "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
  31         "SampleAfterValue": "200003",
  32         "CounterHTOff": "0,1,2,3,4,5,6,7"
  33     },
  34     {
  35         "EventCode": "0x24",
  36         "UMask": "0x50",
  37         "BriefDescription": "L2 prefetch requests that hit L2 cache",
  38         "Counter": "0,1,2,3",
  39         "EventName": "L2_RQSTS.L2_PF_HIT",
  40         "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
  41         "SampleAfterValue": "200003",
  42         "CounterHTOff": "0,1,2,3,4,5,6,7"
  43     },
  44     {
  45         "EventCode": "0x24",
  46         "UMask": "0xe1",
  47         "BriefDescription": "Demand Data Read requests",
  48         "Counter": "0,1,2,3",
  49         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
  50         "Errata": "HSD78",
  51         "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
  52         "SampleAfterValue": "200003",
  53         "CounterHTOff": "0,1,2,3,4,5,6,7"
  54     },
  55     {
  56         "EventCode": "0x24",
  57         "UMask": "0xe2",
  58         "BriefDescription": "RFO requests to L2 cache",
  59         "Counter": "0,1,2,3",
  60         "EventName": "L2_RQSTS.ALL_RFO",
  61         "PublicDescription": "Counts all L2 store RFO requests.",
  62         "SampleAfterValue": "200003",
  63         "CounterHTOff": "0,1,2,3,4,5,6,7"
  64     },
  65     {
  66         "EventCode": "0x24",
  67         "UMask": "0xe4",
  68         "BriefDescription": "L2 code requests",
  69         "Counter": "0,1,2,3",
  70         "EventName": "L2_RQSTS.ALL_CODE_RD",
  71         "PublicDescription": "Counts all L2 code requests.",
  72         "SampleAfterValue": "200003",
  73         "CounterHTOff": "0,1,2,3,4,5,6,7"
  74     },
  75     {
  76         "EventCode": "0x24",
  77         "UMask": "0xf8",
  78         "BriefDescription": "Requests from L2 hardware prefetchers",
  79         "Counter": "0,1,2,3",
  80         "EventName": "L2_RQSTS.ALL_PF",
  81         "PublicDescription": "Counts all L2 HW prefetcher requests.",
  82         "SampleAfterValue": "200003",
  83         "CounterHTOff": "0,1,2,3,4,5,6,7"
  84     },
  85     {
  86         "EventCode": "0x27",
  87         "UMask": "0x50",
  88         "BriefDescription": "Not rejected writebacks that hit L2 cache",
  89         "Counter": "0,1,2,3",
  90         "EventName": "L2_DEMAND_RQSTS.WB_HIT",
  91         "PublicDescription": "Not rejected writebacks that hit L2 cache.",
  92         "SampleAfterValue": "200003",
  93         "CounterHTOff": "0,1,2,3,4,5,6,7"
  94     },
  95     {
  96         "EventCode": "0x2E",
  97         "UMask": "0x41",
  98         "BriefDescription": "Core-originated cacheable demand requests missed L3",
  99         "Counter": "0,1,2,3",
 100         "EventName": "LONGEST_LAT_CACHE.MISS",
 101         "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
 102         "SampleAfterValue": "100003",
 103         "CounterHTOff": "0,1,2,3,4,5,6,7"
 104     },
 105     {
 106         "EventCode": "0x2E",
 107         "UMask": "0x4f",
 108         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
 109         "Counter": "0,1,2,3",
 110         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
 111         "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
 112         "SampleAfterValue": "100003",
 113         "CounterHTOff": "0,1,2,3,4,5,6,7"
 114     },
 115     {
 116         "EventCode": "0x48",
 117         "UMask": "0x1",
 118         "BriefDescription": "L1D miss oustandings duration in cycles",
 119         "Counter": "2",
 120         "EventName": "L1D_PEND_MISS.PENDING",
 121         "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
 122         "SampleAfterValue": "2000003",
 123         "CounterHTOff": "2"
 124     },
 125     {
 126         "EventCode": "0x48",
 127         "UMask": "0x2",
 128         "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
 129         "Counter": "0,1,2,3",
 130         "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
 131         "SampleAfterValue": "2000003",
 132         "CounterHTOff": "0,1,2,3,4,5,6,7"
 133     },
 134     {
 135         "EventCode": "0x48",
 136         "UMask": "0x1",
 137         "BriefDescription": "Cycles with L1D load Misses outstanding.",
 138         "Counter": "2",
 139         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
 140         "CounterMask": "1",
 141         "SampleAfterValue": "2000003",
 142         "CounterHTOff": "2"
 143     },
 144     {
 145         "EventCode": "0x51",
 146         "UMask": "0x1",
 147         "BriefDescription": "L1D data line replacements",
 148         "Counter": "0,1,2,3",
 149         "EventName": "L1D.REPLACEMENT",
 150         "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
 151         "SampleAfterValue": "2000003",
 152         "CounterHTOff": "0,1,2,3,4,5,6,7"
 153     },
 154     {
 155         "EventCode": "0x60",
 156         "UMask": "0x1",
 157         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
 158         "Counter": "0,1,2,3",
 159         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
 160         "Errata": "HSD78, HSD62, HSD61",
 161         "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
 162         "SampleAfterValue": "2000003",
 163         "CounterHTOff": "0,1,2,3,4,5,6,7"
 164     },
 165     {
 166         "EventCode": "0x60",
 167         "UMask": "0x2",
 168         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
 169         "Counter": "0,1,2,3",
 170         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
 171         "Errata": "HSD62, HSD61",
 172         "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
 173         "SampleAfterValue": "2000003",
 174         "CounterHTOff": "0,1,2,3,4,5,6,7"
 175     },
 176     {
 177         "EventCode": "0x60",
 178         "UMask": "0x4",
 179         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
 180         "Counter": "0,1,2,3",
 181         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
 182         "Errata": "HSD62, HSD61",
 183         "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
 184         "SampleAfterValue": "2000003",
 185         "CounterHTOff": "0,1,2,3,4,5,6,7"
 186     },
 187     {
 188         "EventCode": "0x60",
 189         "UMask": "0x8",
 190         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
 191         "Counter": "0,1,2,3",
 192         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
 193         "Errata": "HSD62, HSD61",
 194         "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
 195         "SampleAfterValue": "2000003",
 196         "CounterHTOff": "0,1,2,3,4,5,6,7"
 197     },
 198     {
 199         "EventCode": "0x60",
 200         "UMask": "0x1",
 201         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
 202         "Counter": "0,1,2,3",
 203         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
 204         "CounterMask": "1",
 205         "Errata": "HSD78, HSD62, HSD61",
 206         "SampleAfterValue": "2000003",
 207         "CounterHTOff": "0,1,2,3,4,5,6,7"
 208     },
 209     {
 210         "EventCode": "0x60",
 211         "UMask": "0x8",
 212         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
 213         "Counter": "0,1,2,3",
 214         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
 215         "CounterMask": "1",
 216         "Errata": "HSD62, HSD61",
 217         "SampleAfterValue": "2000003",
 218         "CounterHTOff": "0,1,2,3,4,5,6,7"
 219     },
 220     {
 221         "EventCode": "0x60",
 222         "UMask": "0x4",
 223         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
 224         "Counter": "0,1,2,3",
 225         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
 226         "CounterMask": "1",
 227         "Errata": "HSD62, HSD61",
 228         "SampleAfterValue": "2000003",
 229         "CounterHTOff": "0,1,2,3,4,5,6,7"
 230     },
 231     {
 232         "EventCode": "0x63",
 233         "UMask": "0x2",
 234         "BriefDescription": "Cycles when L1D is locked",
 235         "Counter": "0,1,2,3",
 236         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
 237         "PublicDescription": "Cycles in which the L1D is locked.",
 238         "SampleAfterValue": "2000003",
 239         "CounterHTOff": "0,1,2,3,4,5,6,7"
 240     },
 241     {
 242         "EventCode": "0xB0",
 243         "UMask": "0x1",
 244         "BriefDescription": "Demand Data Read requests sent to uncore",
 245         "Counter": "0,1,2,3",
 246         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
 247         "Errata": "HSD78",
 248         "PublicDescription": "Demand data read requests sent to uncore.",
 249         "SampleAfterValue": "100003",
 250         "CounterHTOff": "0,1,2,3,4,5,6,7"
 251     },
 252     {
 253         "EventCode": "0xB0",
 254         "UMask": "0x2",
 255         "BriefDescription": "Cacheable and noncachaeble code read requests",
 256         "Counter": "0,1,2,3",
 257         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
 258         "PublicDescription": "Demand code read requests sent to uncore.",
 259         "SampleAfterValue": "100003",
 260         "CounterHTOff": "0,1,2,3,4,5,6,7"
 261     },
 262     {
 263         "EventCode": "0xB0",
 264         "UMask": "0x4",
 265         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
 266         "Counter": "0,1,2,3",
 267         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
 268         "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
 269         "SampleAfterValue": "100003",
 270         "CounterHTOff": "0,1,2,3,4,5,6,7"
 271     },
 272     {
 273         "EventCode": "0xB0",
 274         "UMask": "0x8",
 275         "BriefDescription": "Demand and prefetch data reads",
 276         "Counter": "0,1,2,3",
 277         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
 278         "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
 279         "SampleAfterValue": "100003",
 280         "CounterHTOff": "0,1,2,3,4,5,6,7"
 281     },
 282     {
 283         "EventCode": "0xb2",
 284         "UMask": "0x1",
 285         "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
 286         "Counter": "0,1,2,3",
 287         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
 288         "SampleAfterValue": "2000003",
 289         "CounterHTOff": "0,1,2,3,4,5,6,7"
 290     },
 291     {
 292         "EventCode": "0xD0",
 293         "UMask": "0x11",
 294         "BriefDescription": "Retired load uops that miss the STLB.",
 295         "Data_LA": "1",
 296         "PEBS": "1",
 297         "Counter": "0,1,2,3",
 298         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
 299         "Errata": "HSD29, HSM30",
 300         "SampleAfterValue": "100003",
 301         "CounterHTOff": "0,1,2,3"
 302     },
 303     {
 304         "EventCode": "0xD0",
 305         "UMask": "0x12",
 306         "BriefDescription": "Retired store uops that miss the STLB.",
 307         "Data_LA": "1",
 308         "PEBS": "1",
 309         "Counter": "0,1,2,3",
 310         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
 311         "Errata": "HSD29, HSM30",
 312         "SampleAfterValue": "100003",
 313         "L1_Hit_Indication": "1",
 314         "CounterHTOff": "0,1,2,3"
 315     },
 316     {
 317         "EventCode": "0xD0",
 318         "UMask": "0x21",
 319         "BriefDescription": "Retired load uops with locked access.",
 320         "Data_LA": "1",
 321         "PEBS": "1",
 322         "Counter": "0,1,2,3",
 323         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
 324         "Errata": "HSD76, HSD29, HSM30",
 325         "SampleAfterValue": "100003",
 326         "CounterHTOff": "0,1,2,3"
 327     },
 328     {
 329         "EventCode": "0xD0",
 330         "UMask": "0x41",
 331         "BriefDescription": "Retired load uops that split across a cacheline boundary.",
 332         "Data_LA": "1",
 333         "PEBS": "1",
 334         "Counter": "0,1,2,3",
 335         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
 336         "Errata": "HSD29, HSM30",
 337         "SampleAfterValue": "100003",
 338         "CounterHTOff": "0,1,2,3"
 339     },
 340     {
 341         "EventCode": "0xD0",
 342         "UMask": "0x42",
 343         "BriefDescription": "Retired store uops that split across a cacheline boundary.",
 344         "Data_LA": "1",
 345         "PEBS": "1",
 346         "Counter": "0,1,2,3",
 347         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
 348         "Errata": "HSD29, HSM30",
 349         "SampleAfterValue": "100003",
 350         "L1_Hit_Indication": "1",
 351         "CounterHTOff": "0,1,2,3"
 352     },
 353     {
 354         "EventCode": "0xD0",
 355         "UMask": "0x81",
 356         "BriefDescription": "All retired load uops.",
 357         "Data_LA": "1",
 358         "PEBS": "1",
 359         "Counter": "0,1,2,3",
 360         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
 361         "Errata": "HSD29, HSM30",
 362         "SampleAfterValue": "2000003",
 363         "CounterHTOff": "0,1,2,3"
 364     },
 365     {
 366         "EventCode": "0xD0",
 367         "UMask": "0x82",
 368         "BriefDescription": "All retired store uops.",
 369         "Data_LA": "1",
 370         "PEBS": "1",
 371         "Counter": "0,1,2,3",
 372         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
 373         "Errata": "HSD29, HSM30",
 374         "SampleAfterValue": "2000003",
 375         "L1_Hit_Indication": "1",
 376         "CounterHTOff": "0,1,2,3"
 377     },
 378     {
 379         "EventCode": "0xD1",
 380         "UMask": "0x1",
 381         "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
 382         "Data_LA": "1",
 383         "PEBS": "1",
 384         "Counter": "0,1,2,3",
 385         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
 386         "Errata": "HSD29, HSM30",
 387         "SampleAfterValue": "2000003",
 388         "CounterHTOff": "0,1,2,3"
 389     },
 390     {
 391         "EventCode": "0xD1",
 392         "UMask": "0x2",
 393         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
 394         "Data_LA": "1",
 395         "PEBS": "1",
 396         "Counter": "0,1,2,3",
 397         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
 398         "Errata": "HSD76, HSD29, HSM30",
 399         "SampleAfterValue": "100003",
 400         "CounterHTOff": "0,1,2,3"
 401     },
 402     {
 403         "EventCode": "0xD1",
 404         "UMask": "0x4",
 405         "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
 406         "Data_LA": "1",
 407         "PEBS": "1",
 408         "Counter": "0,1,2,3",
 409         "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
 410         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
 411         "PublicDescription": "Retired load uops with L3 cache hits as data sources.",
 412         "SampleAfterValue": "50021",
 413         "CounterHTOff": "0,1,2,3"
 414     },
 415     {
 416         "EventCode": "0xD1",
 417         "UMask": "0x8",
 418         "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
 419         "Data_LA": "1",
 420         "PEBS": "1",
 421         "Counter": "0,1,2,3",
 422         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
 423         "Errata": "HSM30",
 424         "PublicDescription": "Retired load uops missed L1 cache as data sources.",
 425         "SampleAfterValue": "100003",
 426         "CounterHTOff": "0,1,2,3"
 427     },
 428     {
 429         "EventCode": "0xD1",
 430         "UMask": "0x10",
 431         "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
 432         "Data_LA": "1",
 433         "PEBS": "1",
 434         "Counter": "0,1,2,3",
 435         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
 436         "Errata": "HSD29, HSM30",
 437         "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
 438         "SampleAfterValue": "50021",
 439         "CounterHTOff": "0,1,2,3"
 440     },
 441     {
 442         "EventCode": "0xD1",
 443         "UMask": "0x20",
 444         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
 445         "Data_LA": "1",
 446         "PEBS": "1",
 447         "Counter": "0,1,2,3",
 448         "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
 449         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
 450         "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",
 451         "SampleAfterValue": "100003",
 452         "CounterHTOff": "0,1,2,3"
 453     },
 454     {
 455         "EventCode": "0xD1",
 456         "UMask": "0x40",
 457         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
 458         "Data_LA": "1",
 459         "PEBS": "1",
 460         "Counter": "0,1,2,3",
 461         "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
 462         "Errata": "HSM30",
 463         "SampleAfterValue": "100003",
 464         "CounterHTOff": "0,1,2,3"
 465     },
 466     {
 467         "EventCode": "0xD2",
 468         "UMask": "0x1",
 469         "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
 470         "Data_LA": "1",
 471         "PEBS": "1",
 472         "Counter": "0,1,2,3",
 473         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
 474         "Errata": "HSD29, HSD25, HSM26, HSM30",
 475         "SampleAfterValue": "20011",
 476         "CounterHTOff": "0,1,2,3"
 477     },
 478     {
 479         "EventCode": "0xD2",
 480         "UMask": "0x2",
 481         "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
 482         "Data_LA": "1",
 483         "PEBS": "1",
 484         "Counter": "0,1,2,3",
 485         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
 486         "Errata": "HSD29, HSD25, HSM26, HSM30",
 487         "SampleAfterValue": "20011",
 488         "CounterHTOff": "0,1,2,3"
 489     },
 490     {
 491         "EventCode": "0xD2",
 492         "UMask": "0x4",
 493         "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
 494         "Data_LA": "1",
 495         "PEBS": "1",
 496         "Counter": "0,1,2,3",
 497         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
 498         "Errata": "HSD29, HSD25, HSM26, HSM30",
 499         "SampleAfterValue": "20011",
 500         "CounterHTOff": "0,1,2,3"
 501     },
 502     {
 503         "EventCode": "0xD2",
 504         "UMask": "0x8",
 505         "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
 506         "Data_LA": "1",
 507         "PEBS": "1",
 508         "Counter": "0,1,2,3",
 509         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
 510         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
 511         "SampleAfterValue": "100003",
 512         "CounterHTOff": "0,1,2,3"
 513     },
 514     {
 515         "EventCode": "0xD3",
 516         "UMask": "0x1",
 517         "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
 518         "Data_LA": "1",
 519         "PEBS": "1",
 520         "Counter": "0,1,2,3",
 521         "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
 522         "Errata": "HSD74, HSD29, HSD25, HSM30",
 523         "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",
 524         "SampleAfterValue": "100003",
 525         "CounterHTOff": "0,1,2,3"
 526     },
 527     {
 528         "EventCode": "0xD3",
 529         "UMask": "0x4",
 530         "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
 531         "Data_LA": "1",
 532         "PEBS": "1",
 533         "Counter": "0,1,2,3",
 534         "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM",
 535         "Errata": "HSD29, HSM30",
 536         "SampleAfterValue": "100003",
 537         "CounterHTOff": "0,1,2,3"
 538     },
 539     {
 540         "EventCode": "0xD3",
 541         "UMask": "0x10",
 542         "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
 543         "Data_LA": "1",
 544         "PEBS": "1",
 545         "Counter": "0,1,2,3",
 546         "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM",
 547         "Errata": "HSM30",
 548         "SampleAfterValue": "100003",
 549         "CounterHTOff": "0,1,2,3"
 550     },
 551     {
 552         "EventCode": "0xD3",
 553         "UMask": "0x20",
 554         "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
 555         "Data_LA": "1",
 556         "PEBS": "1",
 557         "Counter": "0,1,2,3",
 558         "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD",
 559         "Errata": "HSM30",
 560         "SampleAfterValue": "100003",
 561         "CounterHTOff": "0,1,2,3"
 562     },
 563     {
 564         "EventCode": "0xf0",
 565         "UMask": "0x1",
 566         "BriefDescription": "Demand Data Read requests that access L2 cache",
 567         "Counter": "0,1,2,3",
 568         "EventName": "L2_TRANS.DEMAND_DATA_RD",
 569         "PublicDescription": "Demand data read requests that access L2 cache.",
 570         "SampleAfterValue": "200003",
 571         "CounterHTOff": "0,1,2,3,4,5,6,7"
 572     },
 573     {
 574         "EventCode": "0xf0",
 575         "UMask": "0x2",
 576         "BriefDescription": "RFO requests that access L2 cache",
 577         "Counter": "0,1,2,3",
 578         "EventName": "L2_TRANS.RFO",
 579         "PublicDescription": "RFO requests that access L2 cache.",
 580         "SampleAfterValue": "200003",
 581         "CounterHTOff": "0,1,2,3,4,5,6,7"
 582     },
 583     {
 584         "EventCode": "0xf0",
 585         "UMask": "0x4",
 586         "BriefDescription": "L2 cache accesses when fetching instructions",
 587         "Counter": "0,1,2,3",
 588         "EventName": "L2_TRANS.CODE_RD",
 589         "PublicDescription": "L2 cache accesses when fetching instructions.",
 590         "SampleAfterValue": "200003",
 591         "CounterHTOff": "0,1,2,3,4,5,6,7"
 592     },
 593     {
 594         "EventCode": "0xf0",
 595         "UMask": "0x8",
 596         "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
 597         "Counter": "0,1,2,3",
 598         "EventName": "L2_TRANS.ALL_PF",
 599         "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
 600         "SampleAfterValue": "200003",
 601         "CounterHTOff": "0,1,2,3,4,5,6,7"
 602     },
 603     {
 604         "EventCode": "0xf0",
 605         "UMask": "0x10",
 606         "BriefDescription": "L1D writebacks that access L2 cache",
 607         "Counter": "0,1,2,3",
 608         "EventName": "L2_TRANS.L1D_WB",
 609         "PublicDescription": "L1D writebacks that access L2 cache.",
 610         "SampleAfterValue": "200003",
 611         "CounterHTOff": "0,1,2,3,4,5,6,7"
 612     },
 613     {
 614         "EventCode": "0xf0",
 615         "UMask": "0x20",
 616         "BriefDescription": "L2 fill requests that access L2 cache",
 617         "Counter": "0,1,2,3",
 618         "EventName": "L2_TRANS.L2_FILL",
 619         "PublicDescription": "L2 fill requests that access L2 cache.",
 620         "SampleAfterValue": "200003",
 621         "CounterHTOff": "0,1,2,3,4,5,6,7"
 622     },
 623     {
 624         "EventCode": "0xf0",
 625         "UMask": "0x40",
 626         "BriefDescription": "L2 writebacks that access L2 cache",
 627         "Counter": "0,1,2,3",
 628         "EventName": "L2_TRANS.L2_WB",
 629         "PublicDescription": "L2 writebacks that access L2 cache.",
 630         "SampleAfterValue": "200003",
 631         "CounterHTOff": "0,1,2,3,4,5,6,7"
 632     },
 633     {
 634         "EventCode": "0xf0",
 635         "UMask": "0x80",
 636         "BriefDescription": "Transactions accessing L2 pipe",
 637         "Counter": "0,1,2,3",
 638         "EventName": "L2_TRANS.ALL_REQUESTS",
 639         "PublicDescription": "Transactions accessing L2 pipe.",
 640         "SampleAfterValue": "200003",
 641         "CounterHTOff": "0,1,2,3,4,5,6,7"
 642     },
 643     {
 644         "EventCode": "0xF1",
 645         "UMask": "0x1",
 646         "BriefDescription": "L2 cache lines in I state filling L2",
 647         "Counter": "0,1,2,3",
 648         "EventName": "L2_LINES_IN.I",
 649         "PublicDescription": "L2 cache lines in I state filling L2.",
 650         "SampleAfterValue": "100003",
 651         "CounterHTOff": "0,1,2,3,4,5,6,7"
 652     },
 653     {
 654         "EventCode": "0xF1",
 655         "UMask": "0x2",
 656         "BriefDescription": "L2 cache lines in S state filling L2",
 657         "Counter": "0,1,2,3",
 658         "EventName": "L2_LINES_IN.S",
 659         "PublicDescription": "L2 cache lines in S state filling L2.",
 660         "SampleAfterValue": "100003",
 661         "CounterHTOff": "0,1,2,3,4,5,6,7"
 662     },
 663     {
 664         "EventCode": "0xF1",
 665         "UMask": "0x4",
 666         "BriefDescription": "L2 cache lines in E state filling L2",
 667         "Counter": "0,1,2,3",
 668         "EventName": "L2_LINES_IN.E",
 669         "PublicDescription": "L2 cache lines in E state filling L2.",
 670         "SampleAfterValue": "100003",
 671         "CounterHTOff": "0,1,2,3,4,5,6,7"
 672     },
 673     {
 674         "EventCode": "0xF1",
 675         "UMask": "0x7",
 676         "BriefDescription": "L2 cache lines filling L2",
 677         "Counter": "0,1,2,3",
 678         "EventName": "L2_LINES_IN.ALL",
 679         "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",
 680         "SampleAfterValue": "100003",
 681         "CounterHTOff": "0,1,2,3,4,5,6,7"
 682     },
 683     {
 684         "EventCode": "0xF2",
 685         "UMask": "0x5",
 686         "BriefDescription": "Clean L2 cache lines evicted by demand",
 687         "Counter": "0,1,2,3",
 688         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
 689         "PublicDescription": "Clean L2 cache lines evicted by demand.",
 690         "SampleAfterValue": "100003",
 691         "CounterHTOff": "0,1,2,3,4,5,6,7"
 692     },
 693     {
 694         "EventCode": "0xF2",
 695         "UMask": "0x6",
 696         "BriefDescription": "Dirty L2 cache lines evicted by demand",
 697         "Counter": "0,1,2,3",
 698         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
 699         "PublicDescription": "Dirty L2 cache lines evicted by demand.",
 700         "SampleAfterValue": "100003",
 701         "CounterHTOff": "0,1,2,3,4,5,6,7"
 702     },
 703     {
 704         "EventCode": "0xf4",
 705         "UMask": "0x10",
 706         "BriefDescription": "Split locks in SQ",
 707         "Counter": "0,1,2,3",
 708         "EventName": "SQ_MISC.SPLIT_LOCK",
 709         "SampleAfterValue": "100003",
 710         "CounterHTOff": "0,1,2,3,4,5,6,7"
 711     },
 712     {
 713         "EventCode": "0x24",
 714         "UMask": "0x42",
 715         "BriefDescription": "RFO requests that hit L2 cache",
 716         "Counter": "0,1,2,3",
 717         "EventName": "L2_RQSTS.RFO_HIT",
 718         "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
 719         "SampleAfterValue": "200003",
 720         "CounterHTOff": "0,1,2,3,4,5,6,7"
 721     },
 722     {
 723         "EventCode": "0x24",
 724         "UMask": "0x22",
 725         "BriefDescription": "RFO requests that miss L2 cache",
 726         "Counter": "0,1,2,3",
 727         "EventName": "L2_RQSTS.RFO_MISS",
 728         "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
 729         "SampleAfterValue": "200003",
 730         "CounterHTOff": "0,1,2,3,4,5,6,7"
 731     },
 732     {
 733         "EventCode": "0x24",
 734         "UMask": "0x44",
 735         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
 736         "Counter": "0,1,2,3",
 737         "EventName": "L2_RQSTS.CODE_RD_HIT",
 738         "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
 739         "SampleAfterValue": "200003",
 740         "CounterHTOff": "0,1,2,3,4,5,6,7"
 741     },
 742     {
 743         "EventCode": "0x24",
 744         "UMask": "0x24",
 745         "BriefDescription": "L2 cache misses when fetching instructions",
 746         "Counter": "0,1,2,3",
 747         "EventName": "L2_RQSTS.CODE_RD_MISS",
 748         "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
 749         "SampleAfterValue": "200003",
 750         "CounterHTOff": "0,1,2,3,4,5,6,7"
 751     },
 752     {
 753         "EventCode": "0x24",
 754         "UMask": "0x27",
 755         "BriefDescription": "Demand requests that miss L2 cache",
 756         "Counter": "0,1,2,3",
 757         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
 758         "Errata": "HSD78",
 759         "PublicDescription": "Demand requests that miss L2 cache.",
 760         "SampleAfterValue": "200003",
 761         "CounterHTOff": "0,1,2,3,4,5,6,7"
 762     },
 763     {
 764         "EventCode": "0x24",
 765         "UMask": "0xe7",
 766         "BriefDescription": "Demand requests to L2 cache",
 767         "Counter": "0,1,2,3",
 768         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
 769         "Errata": "HSD78",
 770         "PublicDescription": "Demand requests to L2 cache.",
 771         "SampleAfterValue": "200003",
 772         "CounterHTOff": "0,1,2,3,4,5,6,7"
 773     },
 774     {
 775         "EventCode": "0x24",
 776         "UMask": "0x3f",
 777         "BriefDescription": "All requests that miss L2 cache",
 778         "Counter": "0,1,2,3",
 779         "EventName": "L2_RQSTS.MISS",
 780         "Errata": "HSD78",
 781         "PublicDescription": "All requests that missed L2.",
 782         "SampleAfterValue": "200003",
 783         "CounterHTOff": "0,1,2,3,4,5,6,7"
 784     },
 785     {
 786         "EventCode": "0x24",
 787         "UMask": "0xff",
 788         "BriefDescription": "All L2 requests",
 789         "Counter": "0,1,2,3",
 790         "EventName": "L2_RQSTS.REFERENCES",
 791         "Errata": "HSD78",
 792         "PublicDescription": "All requests to L2 cache.",
 793         "SampleAfterValue": "200003",
 794         "CounterHTOff": "0,1,2,3,4,5,6,7"
 795     },
 796     {
 797         "EventCode": "0xB7, 0xBB",
 798         "UMask": "0x1",
 799         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
 800         "Counter": "0,1,2,3",
 801         "EventName": "OFFCORE_RESPONSE",
 802         "SampleAfterValue": "100003",
 803         "CounterHTOff": "0,1,2,3"
 804     },
 805     {
 806         "EventCode": "0x60",
 807         "UMask": "0x1",
 808         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
 809         "Counter": "0,1,2,3",
 810         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
 811         "CounterMask": "6",
 812         "Errata": "HSD78, HSD62, HSD61",
 813         "SampleAfterValue": "2000003",
 814         "CounterHTOff": "0,1,2,3,4,5,6,7"
 815     },
 816     {
 817         "EventCode": "0x48",
 818         "UMask": "0x1",
 819         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
 820         "Counter": "2",
 821         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
 822         "AnyThread": "1",
 823         "CounterMask": "1",
 824         "SampleAfterValue": "2000003",
 825         "CounterHTOff": "2"
 826     },
 827     {
 828         "EventCode": "0x48",
 829         "UMask": "0x2",
 830         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
 831         "Counter": "0,1,2,3",
 832         "EventName": "L1D_PEND_MISS.FB_FULL",
 833         "CounterMask": "1",
 834         "SampleAfterValue": "2000003",
 835         "CounterHTOff": "0,1,2,3,4,5,6,7"
 836     },
 837     {
 838         "Offcore": "1",
 839         "EventCode": "0xB7, 0xBB",
 840         "UMask": "0x1",
 841         "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
 842         "MSRValue": "0x04003c0001",
 843         "Counter": "0,1,2,3",
 844         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
 845         "MSRIndex": "0x1a6,0x1a7",
 846         "SampleAfterValue": "100003",
 847         "CounterHTOff": "0,1,2,3"
 848     },
 849     {
 850         "Offcore": "1",
 851         "EventCode": "0xB7, 0xBB",
 852         "UMask": "0x1",
 853         "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
 854         "MSRValue": "0x10003c0001",
 855         "Counter": "0,1,2,3",
 856         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
 857         "MSRIndex": "0x1a6,0x1a7",
 858         "SampleAfterValue": "100003",
 859         "CounterHTOff": "0,1,2,3"
 860     },
 861     {
 862         "Offcore": "1",
 863         "EventCode": "0xB7, 0xBB",
 864         "UMask": "0x1",
 865         "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
 866         "MSRValue": "0x04003c0002",
 867         "Counter": "0,1,2,3",
 868         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
 869         "MSRIndex": "0x1a6,0x1a7",
 870         "SampleAfterValue": "100003",
 871         "CounterHTOff": "0,1,2,3"
 872     },
 873     {
 874         "Offcore": "1",
 875         "EventCode": "0xB7, 0xBB",
 876         "UMask": "0x1",
 877         "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
 878         "MSRValue": "0x10003c0002",
 879         "Counter": "0,1,2,3",
 880         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
 881         "MSRIndex": "0x1a6,0x1a7",
 882         "SampleAfterValue": "100003",
 883         "CounterHTOff": "0,1,2,3"
 884     },
 885     {
 886         "Offcore": "1",
 887         "EventCode": "0xB7, 0xBB",
 888         "UMask": "0x1",
 889         "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
 890         "MSRValue": "0x04003c0004",
 891         "Counter": "0,1,2,3",
 892         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
 893         "MSRIndex": "0x1a6,0x1a7",
 894         "SampleAfterValue": "100003",
 895         "CounterHTOff": "0,1,2,3"
 896     },
 897     {
 898         "Offcore": "1",
 899         "EventCode": "0xB7, 0xBB",
 900         "UMask": "0x1",
 901         "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
 902         "MSRValue": "0x10003c0004",
 903         "Counter": "0,1,2,3",
 904         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
 905         "MSRIndex": "0x1a6,0x1a7",
 906         "SampleAfterValue": "100003",
 907         "CounterHTOff": "0,1,2,3"
 908     },
 909     {
 910         "Offcore": "1",
 911         "EventCode": "0xB7, 0xBB",
 912         "UMask": "0x1",
 913         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3",
 914         "MSRValue": "0x3f803c0010",
 915         "Counter": "0,1,2,3",
 916         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
 917         "MSRIndex": "0x1a6,0x1a7",
 918         "SampleAfterValue": "100003",
 919         "CounterHTOff": "0,1,2,3"
 920     },
 921     {
 922         "Offcore": "1",
 923         "EventCode": "0xB7, 0xBB",
 924         "UMask": "0x1",
 925         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3",
 926         "MSRValue": "0x3f803c0020",
 927         "Counter": "0,1,2,3",
 928         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
 929         "MSRIndex": "0x1a6,0x1a7",
 930         "SampleAfterValue": "100003",
 931         "CounterHTOff": "0,1,2,3"
 932     },
 933     {
 934         "Offcore": "1",
 935         "EventCode": "0xB7, 0xBB",
 936         "UMask": "0x1",
 937         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3",
 938         "MSRValue": "0x3f803c0040",
 939         "Counter": "0,1,2,3",
 940         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
 941         "MSRIndex": "0x1a6,0x1a7",
 942         "SampleAfterValue": "100003",
 943         "CounterHTOff": "0,1,2,3"
 944     },
 945     {
 946         "Offcore": "1",
 947         "EventCode": "0xB7, 0xBB",
 948         "UMask": "0x1",
 949         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3",
 950         "MSRValue": "0x3f803c0080",
 951         "Counter": "0,1,2,3",
 952         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
 953         "MSRIndex": "0x1a6,0x1a7",
 954         "SampleAfterValue": "100003",
 955         "CounterHTOff": "0,1,2,3"
 956     },
 957     {
 958         "Offcore": "1",
 959         "EventCode": "0xB7, 0xBB",
 960         "UMask": "0x1",
 961         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3",
 962         "MSRValue": "0x3f803c0100",
 963         "Counter": "0,1,2,3",
 964         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
 965         "MSRIndex": "0x1a6,0x1a7",
 966         "SampleAfterValue": "100003",
 967         "CounterHTOff": "0,1,2,3"
 968     },
 969     {
 970         "Offcore": "1",
 971         "EventCode": "0xB7, 0xBB",
 972         "UMask": "0x1",
 973         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3",
 974         "MSRValue": "0x3f803c0200",
 975         "Counter": "0,1,2,3",
 976         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
 977         "MSRIndex": "0x1a6,0x1a7",
 978         "SampleAfterValue": "100003",
 979         "CounterHTOff": "0,1,2,3"
 980     },
 981     {
 982         "Offcore": "1",
 983         "EventCode": "0xB7, 0xBB",
 984         "UMask": "0x1",
 985         "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
 986         "MSRValue": "0x04003c0091",
 987         "Counter": "0,1,2,3",
 988         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
 989         "MSRIndex": "0x1a6,0x1a7",
 990         "SampleAfterValue": "100003",
 991         "CounterHTOff": "0,1,2,3"
 992     },
 993     {
 994         "Offcore": "1",
 995         "EventCode": "0xB7, 0xBB",
 996         "UMask": "0x1",
 997         "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
 998         "MSRValue": "0x10003c0091",
 999         "Counter": "0,1,2,3",
1000         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1001         "MSRIndex": "0x1a6,0x1a7",
1002         "SampleAfterValue": "100003",
1003         "CounterHTOff": "0,1,2,3"
1004     },
1005     {
1006         "Offcore": "1",
1007         "EventCode": "0xB7, 0xBB",
1008         "UMask": "0x1",
1009         "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1010         "MSRValue": "0x04003c0122",
1011         "Counter": "0,1,2,3",
1012         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1013         "MSRIndex": "0x1a6,0x1a7",
1014         "SampleAfterValue": "100003",
1015         "CounterHTOff": "0,1,2,3"
1016     },
1017     {
1018         "Offcore": "1",
1019         "EventCode": "0xB7, 0xBB",
1020         "UMask": "0x1",
1021         "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1022         "MSRValue": "0x10003c0122",
1023         "Counter": "0,1,2,3",
1024         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
1025         "MSRIndex": "0x1a6,0x1a7",
1026         "SampleAfterValue": "100003",
1027         "CounterHTOff": "0,1,2,3"
1028     },
1029     {
1030         "Offcore": "1",
1031         "EventCode": "0xB7, 0xBB",
1032         "UMask": "0x1",
1033         "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1034         "MSRValue": "0x04003c0244",
1035         "Counter": "0,1,2,3",
1036         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1037         "MSRIndex": "0x1a6,0x1a7",
1038         "SampleAfterValue": "100003",
1039         "CounterHTOff": "0,1,2,3"
1040     },
1041     {
1042         "Offcore": "1",
1043         "EventCode": "0xB7, 0xBB",
1044         "UMask": "0x1",
1045         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1046         "MSRValue": "0x04003c07f7",
1047         "Counter": "0,1,2,3",
1048         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1049         "MSRIndex": "0x1a6,0x1a7",
1050         "SampleAfterValue": "100003",
1051         "CounterHTOff": "0,1,2,3"
1052     },
1053     {
1054         "Offcore": "1",
1055         "EventCode": "0xB7, 0xBB",
1056         "UMask": "0x1",
1057         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1058         "MSRValue": "0x10003c07f7",
1059         "Counter": "0,1,2,3",
1060         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
1061         "MSRIndex": "0x1a6,0x1a7",
1062         "SampleAfterValue": "100003",
1063         "CounterHTOff": "0,1,2,3"
1064     },
1065     {
1066         "Offcore": "1",
1067         "EventCode": "0xB7, 0xBB",
1068         "UMask": "0x1",
1069         "BriefDescription": "Counts all requests that hit in the L3",
1070         "MSRValue": "0x3f803c8fff",
1071         "Counter": "0,1,2,3",
1072         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
1073         "MSRIndex": "0x1a6,0x1a7",
1074         "SampleAfterValue": "100003",
1075         "CounterHTOff": "0,1,2,3"
1076     }
1077 ]