3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
7 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
8 "SampleAfterValue": "200003",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
13 "PublicDescription": "RFO requests that hit L2 cache.",
17 "EventName": "L2_RQSTS.RFO_HIT",
18 "SampleAfterValue": "200003",
19 "BriefDescription": "RFO requests that hit L2 cache",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
23 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
27 "EventName": "L2_RQSTS.RFO_MISS",
28 "SampleAfterValue": "200003",
29 "BriefDescription": "RFO requests that miss L2 cache",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
33 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
37 "EventName": "L2_RQSTS.CODE_RD_HIT",
38 "SampleAfterValue": "200003",
39 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
40 "CounterHTOff": "0,1,2,3,4,5,6,7"
43 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
47 "EventName": "L2_RQSTS.CODE_RD_MISS",
48 "SampleAfterValue": "200003",
49 "BriefDescription": "L2 cache misses when fetching instructions",
50 "CounterHTOff": "0,1,2,3,4,5,6,7"
53 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
57 "EventName": "L2_RQSTS.PF_HIT",
58 "SampleAfterValue": "200003",
59 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
60 "CounterHTOff": "0,1,2,3,4,5,6,7"
63 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
67 "EventName": "L2_RQSTS.PF_MISS",
68 "SampleAfterValue": "200003",
69 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
70 "CounterHTOff": "0,1,2,3,4,5,6,7"
73 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
77 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
78 "SampleAfterValue": "200003",
79 "BriefDescription": "Demand Data Read requests",
80 "CounterHTOff": "0,1,2,3,4,5,6,7"
83 "PublicDescription": "Counts all L2 store RFO requests.",
87 "EventName": "L2_RQSTS.ALL_RFO",
88 "SampleAfterValue": "200003",
89 "BriefDescription": "RFO requests to L2 cache",
90 "CounterHTOff": "0,1,2,3,4,5,6,7"
93 "PublicDescription": "Counts all L2 code requests.",
97 "EventName": "L2_RQSTS.ALL_CODE_RD",
98 "SampleAfterValue": "200003",
99 "BriefDescription": "L2 code requests",
100 "CounterHTOff": "0,1,2,3,4,5,6,7"
103 "PublicDescription": "Counts all L2 HW prefetcher requests.",
105 "Counter": "0,1,2,3",
107 "EventName": "L2_RQSTS.ALL_PF",
108 "SampleAfterValue": "200003",
109 "BriefDescription": "Requests from L2 hardware prefetchers",
110 "CounterHTOff": "0,1,2,3,4,5,6,7"
113 "PublicDescription": "RFOs that miss cache lines.",
115 "Counter": "0,1,2,3",
117 "EventName": "L2_STORE_LOCK_RQSTS.MISS",
118 "SampleAfterValue": "200003",
119 "BriefDescription": "RFOs that miss cache lines",
120 "CounterHTOff": "0,1,2,3,4,5,6,7"
123 "PublicDescription": "RFOs that hit cache lines in M state.",
125 "Counter": "0,1,2,3",
127 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
128 "SampleAfterValue": "200003",
129 "BriefDescription": "RFOs that hit cache lines in M state",
130 "CounterHTOff": "0,1,2,3,4,5,6,7"
133 "PublicDescription": "RFOs that access cache lines in any state.",
135 "Counter": "0,1,2,3",
137 "EventName": "L2_STORE_LOCK_RQSTS.ALL",
138 "SampleAfterValue": "200003",
139 "BriefDescription": "RFOs that access cache lines in any state",
140 "CounterHTOff": "0,1,2,3,4,5,6,7"
143 "PublicDescription": "Not rejected writebacks that missed LLC.",
145 "Counter": "0,1,2,3",
147 "EventName": "L2_L1D_WB_RQSTS.MISS",
148 "SampleAfterValue": "200003",
149 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
150 "CounterHTOff": "0,1,2,3,4,5,6,7"
153 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
155 "Counter": "0,1,2,3",
157 "EventName": "L2_L1D_WB_RQSTS.HIT_E",
158 "SampleAfterValue": "200003",
159 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
160 "CounterHTOff": "0,1,2,3,4,5,6,7"
163 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
165 "Counter": "0,1,2,3",
167 "EventName": "L2_L1D_WB_RQSTS.HIT_M",
168 "SampleAfterValue": "200003",
169 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
170 "CounterHTOff": "0,1,2,3,4,5,6,7"
174 "Counter": "0,1,2,3",
176 "EventName": "L2_L1D_WB_RQSTS.ALL",
177 "SampleAfterValue": "200003",
178 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
179 "CounterHTOff": "0,1,2,3,4,5,6,7"
182 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
184 "Counter": "0,1,2,3",
186 "EventName": "LONGEST_LAT_CACHE.MISS",
187 "SampleAfterValue": "100003",
188 "BriefDescription": "Core-originated cacheable demand requests missed LLC",
189 "CounterHTOff": "0,1,2,3,4,5,6,7"
192 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
194 "Counter": "0,1,2,3",
196 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
197 "SampleAfterValue": "100003",
198 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
199 "CounterHTOff": "0,1,2,3,4,5,6,7"
202 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
206 "EventName": "L1D_PEND_MISS.PENDING",
207 "SampleAfterValue": "2000003",
208 "BriefDescription": "L1D miss oustandings duration in cycles",
215 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
216 "SampleAfterValue": "2000003",
217 "BriefDescription": "Cycles with L1D load Misses outstanding.",
222 "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
224 "Counter": "0,1,2,3",
226 "EventName": "L1D.REPLACEMENT",
227 "SampleAfterValue": "2000003",
228 "BriefDescription": "L1D data line replacements",
229 "CounterHTOff": "0,1,2,3,4,5,6,7"
232 "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
234 "Counter": "0,1,2,3",
236 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
237 "SampleAfterValue": "2000003",
238 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
239 "CounterHTOff": "0,1,2,3,4,5,6,7"
242 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
244 "Counter": "0,1,2,3",
246 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
247 "SampleAfterValue": "2000003",
248 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
249 "CounterHTOff": "0,1,2,3,4,5,6,7"
252 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
254 "Counter": "0,1,2,3",
256 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
257 "SampleAfterValue": "2000003",
258 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
259 "CounterHTOff": "0,1,2,3,4,5,6,7"
262 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
264 "Counter": "0,1,2,3",
266 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
267 "SampleAfterValue": "2000003",
268 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
269 "CounterHTOff": "0,1,2,3,4,5,6,7"
272 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
274 "Counter": "0,1,2,3",
276 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
277 "SampleAfterValue": "2000003",
278 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
280 "CounterHTOff": "0,1,2,3,4,5,6,7"
283 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
285 "Counter": "0,1,2,3",
287 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
288 "SampleAfterValue": "2000003",
289 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
291 "CounterHTOff": "0,1,2,3,4,5,6,7"
294 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
296 "Counter": "0,1,2,3",
298 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
299 "SampleAfterValue": "2000003",
300 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
302 "CounterHTOff": "0,1,2,3,4,5,6,7"
305 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
307 "Counter": "0,1,2,3",
309 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
310 "SampleAfterValue": "2000003",
311 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
313 "CounterHTOff": "0,1,2,3,4,5,6,7"
316 "PublicDescription": "Cycles in which the L1D is locked.",
318 "Counter": "0,1,2,3",
320 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
321 "SampleAfterValue": "2000003",
322 "BriefDescription": "Cycles when L1D is locked",
323 "CounterHTOff": "0,1,2,3,4,5,6,7"
326 "PublicDescription": "Demand data read requests sent to uncore.",
328 "Counter": "0,1,2,3",
330 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
331 "SampleAfterValue": "100003",
332 "BriefDescription": "Demand Data Read requests sent to uncore",
333 "CounterHTOff": "0,1,2,3,4,5,6,7"
336 "PublicDescription": "Demand code read requests sent to uncore.",
338 "Counter": "0,1,2,3",
340 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
341 "SampleAfterValue": "100003",
342 "BriefDescription": "Cacheable and noncachaeble code read requests",
343 "CounterHTOff": "0,1,2,3,4,5,6,7"
346 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
348 "Counter": "0,1,2,3",
350 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
351 "SampleAfterValue": "100003",
352 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
353 "CounterHTOff": "0,1,2,3,4,5,6,7"
356 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
358 "Counter": "0,1,2,3",
360 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
361 "SampleAfterValue": "100003",
362 "BriefDescription": "Demand and prefetch data reads",
363 "CounterHTOff": "0,1,2,3,4,5,6,7"
366 "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
368 "Counter": "0,1,2,3",
370 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
371 "SampleAfterValue": "2000003",
372 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
373 "CounterHTOff": "0,1,2,3,4,5,6,7"
378 "Counter": "0,1,2,3",
380 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
381 "SampleAfterValue": "100003",
382 "BriefDescription": "Retired load uops that miss the STLB.",
383 "CounterHTOff": "0,1,2,3"
388 "Counter": "0,1,2,3",
390 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
391 "SampleAfterValue": "100003",
392 "BriefDescription": "Retired store uops that miss the STLB.",
393 "CounterHTOff": "0,1,2,3"
398 "Counter": "0,1,2,3",
400 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
401 "SampleAfterValue": "100007",
402 "BriefDescription": "Retired load uops with locked access.",
403 "CounterHTOff": "0,1,2,3"
408 "Counter": "0,1,2,3",
410 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
411 "SampleAfterValue": "100003",
412 "BriefDescription": "Retired load uops that split across a cacheline boundary.",
413 "CounterHTOff": "0,1,2,3"
418 "Counter": "0,1,2,3",
420 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
421 "SampleAfterValue": "100003",
422 "BriefDescription": "Retired store uops that split across a cacheline boundary.",
423 "CounterHTOff": "0,1,2,3"
428 "Counter": "0,1,2,3",
430 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
431 "SampleAfterValue": "2000003",
432 "BriefDescription": "All retired load uops.",
433 "CounterHTOff": "0,1,2,3"
438 "Counter": "0,1,2,3",
440 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
441 "SampleAfterValue": "2000003",
442 "BriefDescription": "All retired store uops.",
443 "CounterHTOff": "0,1,2,3"
447 "PublicDescription": "Retired load uops with L1 cache hits as data sources.",
449 "Counter": "0,1,2,3",
451 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
452 "SampleAfterValue": "2000003",
453 "BriefDescription": "Retired load uops with L1 cache hits as data sources. ",
454 "CounterHTOff": "0,1,2,3"
458 "PublicDescription": "Retired load uops with L2 cache hits as data sources.",
460 "Counter": "0,1,2,3",
462 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
463 "SampleAfterValue": "100003",
464 "BriefDescription": "Retired load uops with L2 cache hits as data sources. ",
465 "CounterHTOff": "0,1,2,3"
469 "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.",
471 "Counter": "0,1,2,3",
473 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
474 "SampleAfterValue": "50021",
475 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ",
476 "CounterHTOff": "0,1,2,3"
480 "PublicDescription": "Retired load uops whose data source followed an L1 miss.",
482 "Counter": "0,1,2,3",
484 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
485 "SampleAfterValue": "100003",
486 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss",
487 "CounterHTOff": "0,1,2,3"
491 "PublicDescription": "Retired load uops that missed L2, excluding unknown sources.",
493 "Counter": "0,1,2,3",
495 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
496 "SampleAfterValue": "50021",
497 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
498 "CounterHTOff": "0,1,2,3"
502 "PublicDescription": "Retired load uops whose data source is LLC miss.",
504 "Counter": "0,1,2,3",
506 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
507 "SampleAfterValue": "100007",
508 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
509 "CounterHTOff": "0,1,2,3"
513 "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
515 "Counter": "0,1,2,3",
517 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
518 "SampleAfterValue": "100003",
519 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",
520 "CounterHTOff": "0,1,2,3"
524 "PublicDescription": "Retired load uops whose data source was an on-package core cache LLC hit and cross-core snoop missed.",
526 "Counter": "0,1,2,3",
528 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
529 "SampleAfterValue": "20011",
530 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",
531 "CounterHTOff": "0,1,2,3"
535 "PublicDescription": "Retired load uops whose data source was an on-package LLC hit and cross-core snoop hits.",
537 "Counter": "0,1,2,3",
539 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
540 "SampleAfterValue": "20011",
541 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ",
542 "CounterHTOff": "0,1,2,3"
546 "PublicDescription": "Retired load uops whose data source was an on-package core cache with HitM responses.",
548 "Counter": "0,1,2,3",
550 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
551 "SampleAfterValue": "20011",
552 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ",
553 "CounterHTOff": "0,1,2,3"
557 "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.",
559 "Counter": "0,1,2,3",
561 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
562 "SampleAfterValue": "100003",
563 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",
564 "CounterHTOff": "0,1,2,3"
567 "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)",
569 "Counter": "0,1,2,3",
571 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
572 "SampleAfterValue": "100007",
573 "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",
574 "CounterHTOff": "0,1,2,3"
577 "PublicDescription": "Demand Data Read requests that access L2 cache.",
579 "Counter": "0,1,2,3",
581 "EventName": "L2_TRANS.DEMAND_DATA_RD",
582 "SampleAfterValue": "200003",
583 "BriefDescription": "Demand Data Read requests that access L2 cache",
584 "CounterHTOff": "0,1,2,3,4,5,6,7"
587 "PublicDescription": "RFO requests that access L2 cache.",
589 "Counter": "0,1,2,3",
591 "EventName": "L2_TRANS.RFO",
592 "SampleAfterValue": "200003",
593 "BriefDescription": "RFO requests that access L2 cache",
594 "CounterHTOff": "0,1,2,3,4,5,6,7"
597 "PublicDescription": "L2 cache accesses when fetching instructions.",
599 "Counter": "0,1,2,3",
601 "EventName": "L2_TRANS.CODE_RD",
602 "SampleAfterValue": "200003",
603 "BriefDescription": "L2 cache accesses when fetching instructions",
604 "CounterHTOff": "0,1,2,3,4,5,6,7"
607 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
609 "Counter": "0,1,2,3",
611 "EventName": "L2_TRANS.ALL_PF",
612 "SampleAfterValue": "200003",
613 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
614 "CounterHTOff": "0,1,2,3,4,5,6,7"
617 "PublicDescription": "L1D writebacks that access L2 cache.",
619 "Counter": "0,1,2,3",
621 "EventName": "L2_TRANS.L1D_WB",
622 "SampleAfterValue": "200003",
623 "BriefDescription": "L1D writebacks that access L2 cache",
624 "CounterHTOff": "0,1,2,3,4,5,6,7"
627 "PublicDescription": "L2 fill requests that access L2 cache.",
629 "Counter": "0,1,2,3",
631 "EventName": "L2_TRANS.L2_FILL",
632 "SampleAfterValue": "200003",
633 "BriefDescription": "L2 fill requests that access L2 cache",
634 "CounterHTOff": "0,1,2,3,4,5,6,7"
637 "PublicDescription": "L2 writebacks that access L2 cache.",
639 "Counter": "0,1,2,3",
641 "EventName": "L2_TRANS.L2_WB",
642 "SampleAfterValue": "200003",
643 "BriefDescription": "L2 writebacks that access L2 cache",
644 "CounterHTOff": "0,1,2,3,4,5,6,7"
647 "PublicDescription": "Transactions accessing L2 pipe.",
649 "Counter": "0,1,2,3",
651 "EventName": "L2_TRANS.ALL_REQUESTS",
652 "SampleAfterValue": "200003",
653 "BriefDescription": "Transactions accessing L2 pipe",
654 "CounterHTOff": "0,1,2,3,4,5,6,7"
657 "PublicDescription": "L2 cache lines in I state filling L2.",
659 "Counter": "0,1,2,3",
661 "EventName": "L2_LINES_IN.I",
662 "SampleAfterValue": "100003",
663 "BriefDescription": "L2 cache lines in I state filling L2",
664 "CounterHTOff": "0,1,2,3,4,5,6,7"
667 "PublicDescription": "L2 cache lines in S state filling L2.",
669 "Counter": "0,1,2,3",
671 "EventName": "L2_LINES_IN.S",
672 "SampleAfterValue": "100003",
673 "BriefDescription": "L2 cache lines in S state filling L2",
674 "CounterHTOff": "0,1,2,3,4,5,6,7"
677 "PublicDescription": "L2 cache lines in E state filling L2.",
679 "Counter": "0,1,2,3",
681 "EventName": "L2_LINES_IN.E",
682 "SampleAfterValue": "100003",
683 "BriefDescription": "L2 cache lines in E state filling L2",
684 "CounterHTOff": "0,1,2,3,4,5,6,7"
687 "PublicDescription": "L2 cache lines filling L2.",
689 "Counter": "0,1,2,3",
691 "EventName": "L2_LINES_IN.ALL",
692 "SampleAfterValue": "100003",
693 "BriefDescription": "L2 cache lines filling L2",
694 "CounterHTOff": "0,1,2,3,4,5,6,7"
697 "PublicDescription": "Clean L2 cache lines evicted by demand.",
699 "Counter": "0,1,2,3",
701 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
702 "SampleAfterValue": "100003",
703 "BriefDescription": "Clean L2 cache lines evicted by demand",
704 "CounterHTOff": "0,1,2,3,4,5,6,7"
707 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
709 "Counter": "0,1,2,3",
711 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
712 "SampleAfterValue": "100003",
713 "BriefDescription": "Dirty L2 cache lines evicted by demand",
714 "CounterHTOff": "0,1,2,3,4,5,6,7"
717 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
719 "Counter": "0,1,2,3",
721 "EventName": "L2_LINES_OUT.PF_CLEAN",
722 "SampleAfterValue": "100003",
723 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
724 "CounterHTOff": "0,1,2,3,4,5,6,7"
727 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
729 "Counter": "0,1,2,3",
731 "EventName": "L2_LINES_OUT.PF_DIRTY",
732 "SampleAfterValue": "100003",
733 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
734 "CounterHTOff": "0,1,2,3,4,5,6,7"
737 "PublicDescription": "Dirty L2 cache lines filling the L2.",
739 "Counter": "0,1,2,3",
741 "EventName": "L2_LINES_OUT.DIRTY_ALL",
742 "SampleAfterValue": "100003",
743 "BriefDescription": "Dirty L2 cache lines filling the L2",
744 "CounterHTOff": "0,1,2,3,4,5,6,7"
748 "Counter": "0,1,2,3",
750 "EventName": "SQ_MISC.SPLIT_LOCK",
751 "SampleAfterValue": "100003",
752 "BriefDescription": "Split locks in SQ",
753 "CounterHTOff": "0,1,2,3,4,5,6,7"
756 "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).",
758 "Counter": "0,1,2,3",
760 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
761 "SampleAfterValue": "100007",
762 "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",
763 "CounterHTOff": "0,1,2,3"
766 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
768 "Counter": "0,1,2,3",
770 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
771 "SampleAfterValue": "2000003",
772 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
774 "CounterHTOff": "0,1,2,3,4,5,6,7"
777 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
782 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
783 "SampleAfterValue": "2000003",
784 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
789 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
791 "Counter": "0,1,2,3",
793 "EventName": "L1D_PEND_MISS.FB_FULL",
794 "SampleAfterValue": "2000003",
795 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
797 "CounterHTOff": "0,1,2,3,4,5,6,7"
800 "EventCode": "0xB7, 0xBB",
801 "MSRValue": "0x3f803c0244",
802 "Counter": "0,1,2,3",
805 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",
806 "MSRIndex": "0x1a6,0x1a7",
807 "SampleAfterValue": "100003",
808 "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC",
809 "CounterHTOff": "0,1,2,3"
812 "EventCode": "0xB7, 0xBB",
813 "MSRValue": "0x1003c0244",
814 "Counter": "0,1,2,3",
817 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
818 "MSRIndex": "0x1a6,0x1a7",
819 "SampleAfterValue": "100003",
820 "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
821 "CounterHTOff": "0,1,2,3"
824 "EventCode": "0xB7, 0xBB",
825 "MSRValue": "0x3f803c0091",
826 "Counter": "0,1,2,3",
829 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
830 "MSRIndex": "0x1a6,0x1a7",
831 "SampleAfterValue": "100003",
832 "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC",
833 "CounterHTOff": "0,1,2,3"
836 "EventCode": "0xB7, 0xBB",
837 "MSRValue": "0x4003c0091",
838 "Counter": "0,1,2,3",
841 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
842 "MSRIndex": "0x1a6,0x1a7",
843 "SampleAfterValue": "100003",
844 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
845 "CounterHTOff": "0,1,2,3"
848 "EventCode": "0xB7, 0xBB",
849 "MSRValue": "0x10003c0091",
850 "Counter": "0,1,2,3",
853 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
854 "MSRIndex": "0x1a6,0x1a7",
855 "SampleAfterValue": "100003",
856 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
857 "CounterHTOff": "0,1,2,3"
860 "EventCode": "0xB7, 0xBB",
861 "MSRValue": "0x1003c0091",
862 "Counter": "0,1,2,3",
865 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
866 "MSRIndex": "0x1a6,0x1a7",
867 "SampleAfterValue": "100003",
868 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
869 "CounterHTOff": "0,1,2,3"
872 "EventCode": "0xB7, 0xBB",
873 "MSRValue": "0x3f803c0122",
874 "Counter": "0,1,2,3",
877 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
878 "MSRIndex": "0x1a6,0x1a7",
879 "SampleAfterValue": "100003",
880 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC",
881 "CounterHTOff": "0,1,2,3"
884 "EventCode": "0xB7, 0xBB",
885 "MSRValue": "0x1003c0122",
886 "Counter": "0,1,2,3",
889 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
890 "MSRIndex": "0x1a6,0x1a7",
891 "SampleAfterValue": "100003",
892 "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
893 "CounterHTOff": "0,1,2,3"
896 "EventCode": "0xB7, 0xBB",
897 "MSRValue": "0x10008",
898 "Counter": "0,1,2,3",
901 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
902 "MSRIndex": "0x1a6,0x1a7",
903 "SampleAfterValue": "100003",
904 "BriefDescription": "Counts all writebacks from the core to the LLC",
905 "CounterHTOff": "0,1,2,3"
908 "EventCode": "0xB7, 0xBB",
909 "MSRValue": "0x3f803c0004",
910 "Counter": "0,1,2,3",
913 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
914 "MSRIndex": "0x1a6,0x1a7",
915 "SampleAfterValue": "100003",
916 "BriefDescription": "Counts all demand code reads that hit in the LLC",
917 "CounterHTOff": "0,1,2,3"
920 "EventCode": "0xB7, 0xBB",
921 "MSRValue": "0x1003c0004",
922 "Counter": "0,1,2,3",
925 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
926 "MSRIndex": "0x1a6,0x1a7",
927 "SampleAfterValue": "100003",
928 "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
929 "CounterHTOff": "0,1,2,3"
932 "EventCode": "0xB7, 0xBB",
933 "MSRValue": "0x3f803c0001",
934 "Counter": "0,1,2,3",
937 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
938 "MSRIndex": "0x1a6,0x1a7",
939 "SampleAfterValue": "100003",
940 "BriefDescription": "Counts all demand data reads that hit in the LLC",
941 "CounterHTOff": "0,1,2,3"
944 "EventCode": "0xB7, 0xBB",
945 "MSRValue": "0x4003c0001",
946 "Counter": "0,1,2,3",
949 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
950 "MSRIndex": "0x1a6,0x1a7",
951 "SampleAfterValue": "100003",
952 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
953 "CounterHTOff": "0,1,2,3"
956 "EventCode": "0xB7, 0xBB",
957 "MSRValue": "0x10003c0001",
958 "Counter": "0,1,2,3",
961 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
962 "MSRIndex": "0x1a6,0x1a7",
963 "SampleAfterValue": "100003",
964 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
965 "CounterHTOff": "0,1,2,3"
968 "EventCode": "0xB7, 0xBB",
969 "MSRValue": "0x1003c0001",
970 "Counter": "0,1,2,3",
973 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
974 "MSRIndex": "0x1a6,0x1a7",
975 "SampleAfterValue": "100003",
976 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
977 "CounterHTOff": "0,1,2,3"
980 "EventCode": "0xB7, 0xBB",
981 "MSRValue": "0x3f803c0002",
982 "Counter": "0,1,2,3",
985 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
986 "MSRIndex": "0x1a6,0x1a7",
987 "SampleAfterValue": "100003",
988 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC",
989 "CounterHTOff": "0,1,2,3"
992 "EventCode": "0xB7, 0xBB",
993 "MSRValue": "0x10003c0002",
994 "Counter": "0,1,2,3",
997 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
998 "MSRIndex": "0x1a6,0x1a7",
999 "SampleAfterValue": "100003",
1000 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1001 "CounterHTOff": "0,1,2,3"
1004 "EventCode": "0xB7, 0xBB",
1005 "MSRValue": "0x1003c0002",
1006 "Counter": "0,1,2,3",
1009 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
1010 "MSRIndex": "0x1a6,0x1a7",
1011 "SampleAfterValue": "100003",
1012 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1013 "CounterHTOff": "0,1,2,3"
1016 "EventCode": "0xB7, 0xBB",
1017 "MSRValue": "0x18000",
1018 "Counter": "0,1,2,3",
1021 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
1022 "MSRIndex": "0x1a6,0x1a7",
1023 "SampleAfterValue": "100003",
1024 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",
1025 "CounterHTOff": "0,1,2,3"
1028 "EventCode": "0xB7, 0xBB",
1029 "MSRValue": "0x10400",
1030 "Counter": "0,1,2,3",
1033 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
1034 "MSRIndex": "0x1a6,0x1a7",
1035 "SampleAfterValue": "100003",
1036 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address ",
1037 "CounterHTOff": "0,1,2,3"
1040 "EventCode": "0xB7, 0xBB",
1041 "MSRValue": "0x10800",
1042 "Counter": "0,1,2,3",
1045 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
1046 "MSRIndex": "0x1a6,0x1a7",
1047 "SampleAfterValue": "100003",
1048 "BriefDescription": "Counts non-temporal stores",
1049 "CounterHTOff": "0,1,2,3"
1052 "EventCode": "0xB7, 0xBB",
1053 "MSRValue": "0x00010001",
1054 "Counter": "0,1,2,3",
1057 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
1058 "MSRIndex": "0x1a6,0x1a7",
1059 "SampleAfterValue": "100003",
1060 "BriefDescription": "Counts all demand data reads ",
1061 "CounterHTOff": "0,1,2,3"
1064 "EventCode": "0xB7, 0xBB",
1065 "MSRValue": "0x00010002",
1066 "Counter": "0,1,2,3",
1069 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
1070 "MSRIndex": "0x1a6,0x1a7",
1071 "SampleAfterValue": "100003",
1072 "BriefDescription": "Counts all demand rfo's ",
1073 "CounterHTOff": "0,1,2,3"
1076 "EventCode": "0xB7, 0xBB",
1077 "MSRValue": "0x00010004",
1078 "Counter": "0,1,2,3",
1081 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
1082 "MSRIndex": "0x1a6,0x1a7",
1083 "SampleAfterValue": "100003",
1084 "BriefDescription": "Counts all demand code reads",
1085 "CounterHTOff": "0,1,2,3"
1088 "EventCode": "0xB7, 0xBB",
1089 "MSRValue": "0x000105B3",
1090 "Counter": "0,1,2,3",
1093 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
1094 "MSRIndex": "0x1a6,0x1a7",
1095 "SampleAfterValue": "100003",
1096 "BriefDescription": "Counts all demand & prefetch data reads",
1097 "CounterHTOff": "0,1,2,3"
1100 "EventCode": "0xB7, 0xBB",
1101 "MSRValue": "0x00010122",
1102 "Counter": "0,1,2,3",
1105 "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
1106 "MSRIndex": "0x1a6,0x1a7",
1107 "SampleAfterValue": "100003",
1108 "BriefDescription": "Counts all demand & prefetch prefetch RFOs ",
1109 "CounterHTOff": "0,1,2,3"
1112 "EventCode": "0xB7, 0xBB",
1113 "MSRValue": "0x000107F7",
1114 "Counter": "0,1,2,3",
1117 "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
1118 "MSRIndex": "0x1a6,0x1a7",
1119 "SampleAfterValue": "100003",
1120 "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) ",
1121 "CounterHTOff": "0,1,2,3"