tools/testing/nvdimm/test/nfit.c

   1 /*
   2  * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of version 2 of the GNU General Public License as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/libnvdimm.h>
  18 #include <linux/genalloc.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/mutex.h>
  23 #include <linux/ndctl.h>
  24 #include <linux/sizes.h>
  25 #include <linux/list.h>
  26 #include <linux/slab.h>
  27 #include <nd-core.h>
  28 #include <nfit.h>
  29 #include <nd.h>
  30 #include "nfit_test.h"
  31 #include "../watermark.h"
  32
  33 #include <asm/mcsafe_test.h>
  34
  35 /*
  36  * Generate an NFIT table to describe the following topology:
  37  *
  38  * BUS0: Interleaved PMEM regions, and aliasing with BLK regions
  39  *
  40  *                     (a)                       (b)            DIMM   BLK-REGION
  41  *           +----------+--------------+----------+---------+
  42  * +------+  |  blk2.0  |     pm0.0    |  blk2.1  |  pm1.0  |    0      region2
  43  * | imc0 +--+- - - - - region0 - - - -+----------+         +
  44  * +--+---+  |  blk3.0  |     pm0.0    |  blk3.1  |  pm1.0  |    1      region3
  45  *    |      +----------+--------------v----------v         v
  46  * +--+---+                            |                    |
  47  * | cpu0 |                                    region1
  48  * +--+---+                            |                    |
  49  *    |      +-------------------------^----------^         ^
  50  * +--+---+  |                 blk4.0             |  pm1.0  |    2      region4
  51  * | imc1 +--+-------------------------+----------+         +
  52  * +------+  |                 blk5.0             |  pm1.0  |    3      region5
  53  *           +-------------------------+----------+-+-------+
  54  *
  55  * +--+---+
  56  * | cpu1 |
  57  * +--+---+                   (Hotplug DIMM)
  58  *    |      +----------------------------------------------+
  59  * +--+---+  |                 blk6.0/pm7.0                 |    4      region6/7
  60  * | imc0 +--+----------------------------------------------+
  61  * +------+
  62  *
  63  *
  64  * *) In this layout we have four dimms and two memory controllers in one
  65  *    socket.  Each unique interface (BLK or PMEM) to DPA space
  66  *    is identified by a region device with a dynamically assigned id.
  67  *
  68  * *) The first portion of dimm0 and dimm1 are interleaved as REGION0.
  69  *    A single PMEM namespace "pm0.0" is created using half of the
  70  *    REGION0 SPA-range.  REGION0 spans dimm0 and dimm1.  PMEM namespace
  71  *    allocate from from the bottom of a region.  The unallocated
  72  *    portion of REGION0 aliases with REGION2 and REGION3.  That
  73  *    unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and
  74  *    "blk3.0") starting at the base of each DIMM to offset (a) in those
  75  *    DIMMs.  "pm0.0", "blk2.0" and "blk3.0" are free-form readable
  76  *    names that can be assigned to a namespace.
  77  *
  78  * *) In the last portion of dimm0 and dimm1 we have an interleaved
  79  *    SPA range, REGION1, that spans those two dimms as well as dimm2
  80  *    and dimm3.  Some of REGION1 allocated to a PMEM namespace named
  81  *    "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each
  82  *    dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
  83  *    "blk5.0".
  84  *
  85  * *) The portion of dimm2 and dimm3 that do not participate in the
  86  *    REGION1 interleaved SPA range (i.e. the DPA address below offset
  87  *    (b) are also included in the "blk4.0" and "blk5.0" namespaces.
  88  *    Note, that BLK namespaces need not be contiguous in DPA-space, and
  89  *    can consume aliased capacity from multiple interleave sets.
  90  *
  91  * BUS1: Legacy NVDIMM (single contiguous range)
  92  *
  93  *  region2
  94  * +---------------------+
  95  * |---------------------|
  96  * ||       pm2.0       ||
  97  * |---------------------|
  98  * +---------------------+
  99  *
 100  * *) A NFIT-table may describe a simple system-physical-address range
 101  *    with no BLK aliasing.  This type of region may optionally
 102  *    reference an NVDIMM.
 103  */
 104 enum {
 105         NUM_PM  = 3,
 106         NUM_DCR = 5,
 107         NUM_HINTS = 8,
 108         NUM_BDW = NUM_DCR,
 109         NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
 110         NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */
 111                 + 4 /* spa1 iset */ + 1 /* spa11 iset */,
 112         DIMM_SIZE = SZ_32M,
 113         LABEL_SIZE = SZ_128K,
 114         SPA_VCD_SIZE = SZ_4M,
 115         SPA0_SIZE = DIMM_SIZE,
 116         SPA1_SIZE = DIMM_SIZE*2,
 117         SPA2_SIZE = DIMM_SIZE,
 118         BDW_SIZE = 64 << 8,
 119         DCR_SIZE = 12,
 120         NUM_NFITS = 2, /* permit testing multiple NFITs per system */
 121 };
 122
 123 struct nfit_test_dcr {
 124         __le64 bdw_addr;
 125         __le32 bdw_status;
 126         __u8 aperature[BDW_SIZE];
 127 };
 128
 129 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \
 130         (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \
 131          | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf))
 132
 133 static u32 handle[] = {
 134         [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0),
 135         [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1),
 136         [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0),
 137         [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1),
 138         [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0),
 139         [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0),
 140         [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1),
 141 };
 142
 143 static unsigned long dimm_fail_cmd_flags[ARRAY_SIZE(handle)];
 144 static int dimm_fail_cmd_code[ARRAY_SIZE(handle)];
 145
 146 static const struct nd_intel_smart smart_def = {
 147         .flags = ND_INTEL_SMART_HEALTH_VALID
 148                 | ND_INTEL_SMART_SPARES_VALID
 149                 | ND_INTEL_SMART_ALARM_VALID
 150                 | ND_INTEL_SMART_USED_VALID
 151                 | ND_INTEL_SMART_SHUTDOWN_VALID
 152                 | ND_INTEL_SMART_MTEMP_VALID
 153                 | ND_INTEL_SMART_CTEMP_VALID,
 154         .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH,
 155         .media_temperature = 23 * 16,
 156         .ctrl_temperature = 25 * 16,
 157         .pmic_temperature = 40 * 16,
 158         .spares = 75,
 159         .alarm_flags = ND_INTEL_SMART_SPARE_TRIP
 160                 | ND_INTEL_SMART_TEMP_TRIP,
 161         .ait_status = 1,
 162         .life_used = 5,
 163         .shutdown_state = 0,
 164         .vendor_size = 0,
 165         .shutdown_count = 100,
 166 };
 167
 168 struct nfit_test_fw {
 169         enum intel_fw_update_state state;
 170         u32 context;
 171         u64 version;
 172         u32 size_received;
 173         u64 end_time;
 174 };
 175
 176 struct nfit_test {
 177         struct acpi_nfit_desc acpi_desc;
 178         struct platform_device pdev;
 179         struct list_head resources;
 180         void *nfit_buf;
 181         dma_addr_t nfit_dma;
 182         size_t nfit_size;
 183         size_t nfit_filled;
 184         int dcr_idx;
 185         int num_dcr;
 186         int num_pm;
 187         void **dimm;
 188         dma_addr_t *dimm_dma;
 189         void **flush;
 190         dma_addr_t *flush_dma;
 191         void **label;
 192         dma_addr_t *label_dma;
 193         void **spa_set;
 194         dma_addr_t *spa_set_dma;
 195         struct nfit_test_dcr **dcr;
 196         dma_addr_t *dcr_dma;
 197         int (*alloc)(struct nfit_test *t);
 198         void (*setup)(struct nfit_test *t);
 199         int setup_hotplug;
 200         union acpi_object **_fit;
 201         dma_addr_t _fit_dma;
 202         struct ars_state {
 203                 struct nd_cmd_ars_status *ars_status;
 204                 unsigned long deadline;
 205                 spinlock_t lock;
 206         } ars_state;
 207         struct device *dimm_dev[ARRAY_SIZE(handle)];
 208         struct nd_intel_smart *smart;
 209         struct nd_intel_smart_threshold *smart_threshold;
 210         struct badrange badrange;
 211         struct work_struct work;
 212         struct nfit_test_fw *fw;
 213 };
 214
 215 static struct workqueue_struct *nfit_wq;
 216
 217 static struct gen_pool *nfit_pool;
 218
 219 static struct nfit_test *to_nfit_test(struct device *dev)
 220 {
 221         struct platform_device *pdev = to_platform_device(dev);
 222
 223         return container_of(pdev, struct nfit_test, pdev);
 224 }
 225
 226 static int nd_intel_test_get_fw_info(struct nfit_test *t,
 227                 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len,
 228                 int idx)
 229 {
 230         struct device *dev = &t->pdev.dev;
 231         struct nfit_test_fw *fw = &t->fw[idx];
 232
 233         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n",
 234                         __func__, t, nd_cmd, buf_len, idx);
 235
 236         if (buf_len < sizeof(*nd_cmd))
 237                 return -EINVAL;
 238
 239         nd_cmd->status = 0;
 240         nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE;
 241         nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN;
 242         nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL;
 243         nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME;
 244         nd_cmd->update_cap = 0;
 245         nd_cmd->fis_version = INTEL_FW_FIS_VERSION;
 246         nd_cmd->run_version = 0;
 247         nd_cmd->updated_version = fw->version;
 248
 249         return 0;
 250 }
 251
 252 static int nd_intel_test_start_update(struct nfit_test *t,
 253                 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len,
 254                 int idx)
 255 {
 256         struct device *dev = &t->pdev.dev;
 257         struct nfit_test_fw *fw = &t->fw[idx];
 258
 259         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 260                         __func__, t, nd_cmd, buf_len, idx);
 261
 262         if (buf_len < sizeof(*nd_cmd))
 263                 return -EINVAL;
 264
 265         if (fw->state != FW_STATE_NEW) {
 266                 /* extended status, FW update in progress */
 267                 nd_cmd->status = 0x10007;
 268                 return 0;
 269         }
 270
 271         fw->state = FW_STATE_IN_PROGRESS;
 272         fw->context++;
 273         fw->size_received = 0;
 274         nd_cmd->status = 0;
 275         nd_cmd->context = fw->context;
 276
 277         dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context);
 278
 279         return 0;
 280 }
 281
 282 static int nd_intel_test_send_data(struct nfit_test *t,
 283                 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len,
 284                 int idx)
 285 {
 286         struct device *dev = &t->pdev.dev;
 287         struct nfit_test_fw *fw = &t->fw[idx];
 288         u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length];
 289
 290         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 291                         __func__, t, nd_cmd, buf_len, idx);
 292
 293         if (buf_len < sizeof(*nd_cmd))
 294                 return -EINVAL;
 295
 296
 297         dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status);
 298         dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]);
 299         dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1,
 300                         nd_cmd->data[nd_cmd->length-1]);
 301
 302         if (fw->state != FW_STATE_IN_PROGRESS) {
 303                 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__);
 304                 *status = 0x5;
 305                 return 0;
 306         }
 307
 308         if (nd_cmd->context != fw->context) {
 309                 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
 310                                 __func__, nd_cmd->context, fw->context);
 311                 *status = 0x10007;
 312                 return 0;
 313         }
 314
 315         /*
 316          * check offset + len > size of fw storage
 317          * check length is > max send length
 318          */
 319         if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE ||
 320                         nd_cmd->length > INTEL_FW_MAX_SEND_LEN) {
 321                 *status = 0x3;
 322                 dev_dbg(dev, "%s: buffer boundary violation\n", __func__);
 323                 return 0;
 324         }
 325
 326         fw->size_received += nd_cmd->length;
 327         dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n",
 328                         __func__, nd_cmd->length, fw->size_received);
 329         *status = 0;
 330         return 0;
 331 }
 332
 333 static int nd_intel_test_finish_fw(struct nfit_test *t,
 334                 struct nd_intel_fw_finish_update *nd_cmd,
 335                 unsigned int buf_len, int idx)
 336 {
 337         struct device *dev = &t->pdev.dev;
 338         struct nfit_test_fw *fw = &t->fw[idx];
 339
 340         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 341                         __func__, t, nd_cmd, buf_len, idx);
 342
 343         if (fw->state == FW_STATE_UPDATED) {
 344                 /* update already done, need cold boot */
 345                 nd_cmd->status = 0x20007;
 346                 return 0;
 347         }
 348
 349         dev_dbg(dev, "%s: context: %#x  ctrl_flags: %#x\n",
 350                         __func__, nd_cmd->context, nd_cmd->ctrl_flags);
 351
 352         switch (nd_cmd->ctrl_flags) {
 353         case 0: /* finish */
 354                 if (nd_cmd->context != fw->context) {
 355                         dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
 356                                         __func__, nd_cmd->context,
 357                                         fw->context);
 358                         nd_cmd->status = 0x10007;
 359                         return 0;
 360                 }
 361                 nd_cmd->status = 0;
 362                 fw->state = FW_STATE_VERIFY;
 363                 /* set 1 second of time for firmware "update" */
 364                 fw->end_time = jiffies + HZ;
 365                 break;
 366
 367         case 1: /* abort */
 368                 fw->size_received = 0;
 369                 /* successfully aborted status */
 370                 nd_cmd->status = 0x40007;
 371                 fw->state = FW_STATE_NEW;
 372                 dev_dbg(dev, "%s: abort successful\n", __func__);
 373                 break;
 374
 375         default: /* bad control flag */
 376                 dev_warn(dev, "%s: unknown control flag: %#x\n",
 377                                 __func__, nd_cmd->ctrl_flags);
 378                 return -EINVAL;
 379         }
 380
 381         return 0;
 382 }
 383
 384 static int nd_intel_test_finish_query(struct nfit_test *t,
 385                 struct nd_intel_fw_finish_query *nd_cmd,
 386                 unsigned int buf_len, int idx)
 387 {
 388         struct device *dev = &t->pdev.dev;
 389         struct nfit_test_fw *fw = &t->fw[idx];
 390
 391         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 392                         __func__, t, nd_cmd, buf_len, idx);
 393
 394         if (buf_len < sizeof(*nd_cmd))
 395                 return -EINVAL;
 396
 397         if (nd_cmd->context != fw->context) {
 398                 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
 399                                 __func__, nd_cmd->context, fw->context);
 400                 nd_cmd->status = 0x10007;
 401                 return 0;
 402         }
 403
 404         dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context);
 405
 406         switch (fw->state) {
 407         case FW_STATE_NEW:
 408                 nd_cmd->updated_fw_rev = 0;
 409                 nd_cmd->status = 0;
 410                 dev_dbg(dev, "%s: new state\n", __func__);
 411                 break;
 412
 413         case FW_STATE_IN_PROGRESS:
 414                 /* sequencing error */
 415                 nd_cmd->status = 0x40007;
 416                 nd_cmd->updated_fw_rev = 0;
 417                 dev_dbg(dev, "%s: sequence error\n", __func__);
 418                 break;
 419
 420         case FW_STATE_VERIFY:
 421                 if (time_is_after_jiffies64(fw->end_time)) {
 422                         nd_cmd->updated_fw_rev = 0;
 423                         nd_cmd->status = 0x20007;
 424                         dev_dbg(dev, "%s: still verifying\n", __func__);
 425                         break;
 426                 }
 427
 428                 dev_dbg(dev, "%s: transition out verify\n", __func__);
 429                 fw->state = FW_STATE_UPDATED;
 430                 /* we are going to fall through if it's "done" */
 431         case FW_STATE_UPDATED:
 432                 nd_cmd->status = 0;
 433                 /* bogus test version */
 434                 fw->version = nd_cmd->updated_fw_rev =
 435                         INTEL_FW_FAKE_VERSION;
 436                 dev_dbg(dev, "%s: updated\n", __func__);
 437                 break;
 438
 439         default: /* we should never get here */
 440                 return -EINVAL;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd,
 447                 unsigned int buf_len)
 448 {
 449         if (buf_len < sizeof(*nd_cmd))
 450                 return -EINVAL;
 451
 452         nd_cmd->status = 0;
 453         nd_cmd->config_size = LABEL_SIZE;
 454         nd_cmd->max_xfer = SZ_4K;
 455
 456         return 0;
 457 }
 458
 459 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr
 460                 *nd_cmd, unsigned int buf_len, void *label)
 461 {
 462         unsigned int len, offset = nd_cmd->in_offset;
 463         int rc;
 464
 465         if (buf_len < sizeof(*nd_cmd))
 466                 return -EINVAL;
 467         if (offset >= LABEL_SIZE)
 468                 return -EINVAL;
 469         if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len)
 470                 return -EINVAL;
 471
 472         nd_cmd->status = 0;
 473         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
 474         memcpy(nd_cmd->out_buf, label + offset, len);
 475         rc = buf_len - sizeof(*nd_cmd) - len;
 476
 477         return rc;
 478 }
 479
 480 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd,
 481                 unsigned int buf_len, void *label)
 482 {
 483         unsigned int len, offset = nd_cmd->in_offset;
 484         u32 *status;
 485         int rc;
 486
 487         if (buf_len < sizeof(*nd_cmd))
 488                 return -EINVAL;
 489         if (offset >= LABEL_SIZE)
 490                 return -EINVAL;
 491         if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len)
 492                 return -EINVAL;
 493
 494         status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd);
 495         *status = 0;
 496         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
 497         memcpy(label + offset, nd_cmd->in_buf, len);
 498         rc = buf_len - sizeof(*nd_cmd) - (len + 4);
 499
 500         return rc;
 501 }
 502
 503 #define NFIT_TEST_CLEAR_ERR_UNIT 256
 504
 505 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd,
 506                 unsigned int buf_len)
 507 {
 508         int ars_recs;
 509
 510         if (buf_len < sizeof(*nd_cmd))
 511                 return -EINVAL;
 512
 513         /* for testing, only store up to n records that fit within 4k */
 514         ars_recs = SZ_4K / sizeof(struct nd_ars_record);
 515
 516         nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status)
 517                 + ars_recs * sizeof(struct nd_ars_record);
 518         nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16;
 519         nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT;
 520
 521         return 0;
 522 }
 523
 524 static void post_ars_status(struct ars_state *ars_state,
 525                 struct badrange *badrange, u64 addr, u64 len)
 526 {
 527         struct nd_cmd_ars_status *ars_status;
 528         struct nd_ars_record *ars_record;
 529         struct badrange_entry *be;
 530         u64 end = addr + len - 1;
 531         int i = 0;
 532
 533         ars_state->deadline = jiffies + 1*HZ;
 534         ars_status = ars_state->ars_status;
 535         ars_status->status = 0;
 536         ars_status->address = addr;
 537         ars_status->length = len;
 538         ars_status->type = ND_ARS_PERSISTENT;
 539
 540         spin_lock(&badrange->lock);
 541         list_for_each_entry(be, &badrange->list, list) {
 542                 u64 be_end = be->start + be->length - 1;
 543                 u64 rstart, rend;
 544
 545                 /* skip entries outside the range */
 546                 if (be_end < addr || be->start > end)
 547                         continue;
 548
 549                 rstart = (be->start < addr) ? addr : be->start;
 550                 rend = (be_end < end) ? be_end : end;
 551                 ars_record = &ars_status->records[i];
 552                 ars_record->handle = 0;
 553                 ars_record->err_address = rstart;
 554                 ars_record->length = rend - rstart + 1;
 555                 i++;
 556         }
 557         spin_unlock(&badrange->lock);
 558         ars_status->num_records = i;
 559         ars_status->out_length = sizeof(struct nd_cmd_ars_status)
 560                 + i * sizeof(struct nd_ars_record);
 561 }
 562
 563 static int nfit_test_cmd_ars_start(struct nfit_test *t,
 564                 struct ars_state *ars_state,
 565                 struct nd_cmd_ars_start *ars_start, unsigned int buf_len,
 566                 int *cmd_rc)
 567 {
 568         if (buf_len < sizeof(*ars_start))
 569                 return -EINVAL;
 570
 571         spin_lock(&ars_state->lock);
 572         if (time_before(jiffies, ars_state->deadline)) {
 573                 ars_start->status = NFIT_ARS_START_BUSY;
 574                 *cmd_rc = -EBUSY;
 575         } else {
 576                 ars_start->status = 0;
 577                 ars_start->scrub_time = 1;
 578                 post_ars_status(ars_state, &t->badrange, ars_start->address,
 579                                 ars_start->length);
 580                 *cmd_rc = 0;
 581         }
 582         spin_unlock(&ars_state->lock);
 583
 584         return 0;
 585 }
 586
 587 static int nfit_test_cmd_ars_status(struct ars_state *ars_state,
 588                 struct nd_cmd_ars_status *ars_status, unsigned int buf_len,
 589                 int *cmd_rc)
 590 {
 591         if (buf_len < ars_state->ars_status->out_length)
 592                 return -EINVAL;
 593
 594         spin_lock(&ars_state->lock);
 595         if (time_before(jiffies, ars_state->deadline)) {
 596                 memset(ars_status, 0, buf_len);
 597                 ars_status->status = NFIT_ARS_STATUS_BUSY;
 598                 ars_status->out_length = sizeof(*ars_status);
 599                 *cmd_rc = -EBUSY;
 600         } else {
 601                 memcpy(ars_status, ars_state->ars_status,
 602                                 ars_state->ars_status->out_length);
 603                 *cmd_rc = 0;
 604         }
 605         spin_unlock(&ars_state->lock);
 606         return 0;
 607 }
 608
 609 static int nfit_test_cmd_clear_error(struct nfit_test *t,
 610                 struct nd_cmd_clear_error *clear_err,
 611                 unsigned int buf_len, int *cmd_rc)
 612 {
 613         const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1;
 614         if (buf_len < sizeof(*clear_err))
 615                 return -EINVAL;
 616
 617         if ((clear_err->address & mask) || (clear_err->length & mask))
 618                 return -EINVAL;
 619
 620         badrange_forget(&t->badrange, clear_err->address, clear_err->length);
 621         clear_err->status = 0;
 622         clear_err->cleared = clear_err->length;
 623         *cmd_rc = 0;
 624         return 0;
 625 }
 626
 627 struct region_search_spa {
 628         u64 addr;
 629         struct nd_region *region;
 630 };
 631
 632 static int is_region_device(struct device *dev)
 633 {
 634         return !strncmp(dev->kobj.name, "region", 6);
 635 }
 636
 637 static int nfit_test_search_region_spa(struct device *dev, void *data)
 638 {
 639         struct region_search_spa *ctx = data;
 640         struct nd_region *nd_region;
 641         resource_size_t ndr_end;
 642
 643         if (!is_region_device(dev))
 644                 return 0;
 645
 646         nd_region = to_nd_region(dev);
 647         ndr_end = nd_region->ndr_start + nd_region->ndr_size;
 648
 649         if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) {
 650                 ctx->region = nd_region;
 651                 return 1;
 652         }
 653
 654         return 0;
 655 }
 656
 657 static int nfit_test_search_spa(struct nvdimm_bus *bus,
 658                 struct nd_cmd_translate_spa *spa)
 659 {
 660         int ret;
 661         struct nd_region *nd_region = NULL;
 662         struct nvdimm *nvdimm = NULL;
 663         struct nd_mapping *nd_mapping = NULL;
 664         struct region_search_spa ctx = {
 665                 .addr = spa->spa,
 666                 .region = NULL,
 667         };
 668         u64 dpa;
 669
 670         ret = device_for_each_child(&bus->dev, &ctx,
 671                                 nfit_test_search_region_spa);
 672
 673         if (!ret)
 674                 return -ENODEV;
 675
 676         nd_region = ctx.region;
 677
 678         dpa = ctx.addr - nd_region->ndr_start;
 679
 680         /*
 681          * last dimm is selected for test
 682          */
 683         nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1];
 684         nvdimm = nd_mapping->nvdimm;
 685
 686         spa->devices[0].nfit_device_handle = handle[nvdimm->id];
 687         spa->num_nvdimms = 1;
 688         spa->devices[0].dpa = dpa;
 689
 690         return 0;
 691 }
 692
 693 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus,
 694                 struct nd_cmd_translate_spa *spa, unsigned int buf_len)
 695 {
 696         if (buf_len < spa->translate_length)
 697                 return -EINVAL;
 698
 699         if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms)
 700                 spa->status = 2;
 701
 702         return 0;
 703 }
 704
 705 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len,
 706                 struct nd_intel_smart *smart_data)
 707 {
 708         if (buf_len < sizeof(*smart))
 709                 return -EINVAL;
 710         memcpy(smart, smart_data, sizeof(*smart));
 711         return 0;
 712 }
 713
 714 static int nfit_test_cmd_smart_threshold(
 715                 struct nd_intel_smart_threshold *out,
 716                 unsigned int buf_len,
 717                 struct nd_intel_smart_threshold *smart_t)
 718 {
 719         if (buf_len < sizeof(*smart_t))
 720                 return -EINVAL;
 721         memcpy(out, smart_t, sizeof(*smart_t));
 722         return 0;
 723 }
 724
 725 static void smart_notify(struct device *bus_dev,
 726                 struct device *dimm_dev, struct nd_intel_smart *smart,
 727                 struct nd_intel_smart_threshold *thresh)
 728 {
 729         dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n",
 730                         __func__, thresh->alarm_control, thresh->spares,
 731                         smart->spares, thresh->media_temperature,
 732                         smart->media_temperature, thresh->ctrl_temperature,
 733                         smart->ctrl_temperature);
 734         if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP)
 735                                 && smart->spares
 736                                 <= thresh->spares)
 737                         || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP)
 738                                 && smart->media_temperature
 739                                 >= thresh->media_temperature)
 740                         || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP)
 741                                 && smart->ctrl_temperature
 742                                 >= thresh->ctrl_temperature)
 743                         || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH)
 744                         || (smart->shutdown_state != 0)) {
 745                 device_lock(bus_dev);
 746                 __acpi_nvdimm_notify(dimm_dev, 0x81);
 747                 device_unlock(bus_dev);
 748         }
 749 }
 750
 751 static int nfit_test_cmd_smart_set_threshold(
 752                 struct nd_intel_smart_set_threshold *in,
 753                 unsigned int buf_len,
 754                 struct nd_intel_smart_threshold *thresh,
 755                 struct nd_intel_smart *smart,
 756                 struct device *bus_dev, struct device *dimm_dev)
 757 {
 758         unsigned int size;
 759
 760         size = sizeof(*in) - 4;
 761         if (buf_len < size)
 762                 return -EINVAL;
 763         memcpy(thresh->data, in, size);
 764         in->status = 0;
 765         smart_notify(bus_dev, dimm_dev, smart, thresh);
 766
 767         return 0;
 768 }
 769
 770 static int nfit_test_cmd_smart_inject(
 771                 struct nd_intel_smart_inject *inj,
 772                 unsigned int buf_len,
 773                 struct nd_intel_smart_threshold *thresh,
 774                 struct nd_intel_smart *smart,
 775                 struct device *bus_dev, struct device *dimm_dev)
 776 {
 777         if (buf_len != sizeof(*inj))
 778                 return -EINVAL;
 779
 780         if (inj->flags & ND_INTEL_SMART_INJECT_MTEMP) {
 781                 if (inj->mtemp_enable)
 782                         smart->media_temperature = inj->media_temperature;
 783                 else
 784                         smart->media_temperature = smart_def.media_temperature;
 785         }
 786         if (inj->flags & ND_INTEL_SMART_INJECT_SPARE) {
 787                 if (inj->spare_enable)
 788                         smart->spares = inj->spares;
 789                 else
 790                         smart->spares = smart_def.spares;
 791         }
 792         if (inj->flags & ND_INTEL_SMART_INJECT_FATAL) {
 793                 if (inj->fatal_enable)
 794                         smart->health = ND_INTEL_SMART_FATAL_HEALTH;
 795                 else
 796                         smart->health = ND_INTEL_SMART_NON_CRITICAL_HEALTH;
 797         }
 798         if (inj->flags & ND_INTEL_SMART_INJECT_SHUTDOWN) {
 799                 if (inj->unsafe_shutdown_enable) {
 800                         smart->shutdown_state = 1;
 801                         smart->shutdown_count++;
 802                 } else
 803                         smart->shutdown_state = 0;
 804         }
 805         inj->status = 0;
 806         smart_notify(bus_dev, dimm_dev, smart, thresh);
 807
 808         return 0;
 809 }
 810
 811 static void uc_error_notify(struct work_struct *work)
 812 {
 813         struct nfit_test *t = container_of(work, typeof(*t), work);
 814
 815         __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR);
 816 }
 817
 818 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t,
 819                 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len)
 820 {
 821         int rc;
 822
 823         if (buf_len != sizeof(*err_inj)) {
 824                 rc = -EINVAL;
 825                 goto err;
 826         }
 827
 828         if (err_inj->err_inj_spa_range_length <= 0) {
 829                 rc = -EINVAL;
 830                 goto err;
 831         }
 832
 833         rc =  badrange_add(&t->badrange, err_inj->err_inj_spa_range_base,
 834                         err_inj->err_inj_spa_range_length);
 835         if (rc < 0)
 836                 goto err;
 837
 838         if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY))
 839                 queue_work(nfit_wq, &t->work);
 840
 841         err_inj->status = 0;
 842         return 0;
 843
 844 err:
 845         err_inj->status = NFIT_ARS_INJECT_INVALID;
 846         return rc;
 847 }
 848
 849 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t,
 850                 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len)
 851 {
 852         int rc;
 853
 854         if (buf_len != sizeof(*err_clr)) {
 855                 rc = -EINVAL;
 856                 goto err;
 857         }
 858
 859         if (err_clr->err_inj_clr_spa_range_length <= 0) {
 860                 rc = -EINVAL;
 861                 goto err;
 862         }
 863
 864         badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base,
 865                         err_clr->err_inj_clr_spa_range_length);
 866
 867         err_clr->status = 0;
 868         return 0;
 869
 870 err:
 871         err_clr->status = NFIT_ARS_INJECT_INVALID;
 872         return rc;
 873 }
 874
 875 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t,
 876                 struct nd_cmd_ars_err_inj_stat *err_stat,
 877                 unsigned int buf_len)
 878 {
 879         struct badrange_entry *be;
 880         int max = SZ_4K / sizeof(struct nd_error_stat_query_record);
 881         int i = 0;
 882
 883         err_stat->status = 0;
 884         spin_lock(&t->badrange.lock);
 885         list_for_each_entry(be, &t->badrange.list, list) {
 886                 err_stat->record[i].err_inj_stat_spa_range_base = be->start;
 887                 err_stat->record[i].err_inj_stat_spa_range_length = be->length;
 888                 i++;
 889                 if (i > max)
 890                         break;
 891         }
 892         spin_unlock(&t->badrange.lock);
 893         err_stat->inj_err_rec_count = i;
 894
 895         return 0;
 896 }
 897
 898 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t,
 899                 struct nd_intel_lss *nd_cmd, unsigned int buf_len)
 900 {
 901         struct device *dev = &t->pdev.dev;
 902
 903         if (buf_len < sizeof(*nd_cmd))
 904                 return -EINVAL;
 905
 906         switch (nd_cmd->enable) {
 907         case 0:
 908                 nd_cmd->status = 0;
 909                 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n",
 910                                 __func__);
 911                 break;
 912         case 1:
 913                 nd_cmd->status = 0;
 914                 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n",
 915                                 __func__);
 916                 break;
 917         default:
 918                 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable);
 919                 nd_cmd->status = 0x3;
 920                 break;
 921         }
 922
 923
 924         return 0;
 925 }
 926
 927 static int override_return_code(int dimm, unsigned int func, int rc)
 928 {
 929         if ((1 << func) & dimm_fail_cmd_flags[dimm]) {
 930                 if (dimm_fail_cmd_code[dimm])
 931                         return dimm_fail_cmd_code[dimm];
 932                 return -EIO;
 933         }
 934         return rc;
 935 }
 936
 937 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func)
 938 {
 939         int i;
 940
 941         /* lookup per-dimm data */
 942         for (i = 0; i < ARRAY_SIZE(handle); i++)
 943                 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i])
 944                         break;
 945         if (i >= ARRAY_SIZE(handle))
 946                 return -ENXIO;
 947         return i;
 948 }
 949
 950 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
 951                 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
 952                 unsigned int buf_len, int *cmd_rc)
 953 {
 954         struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
 955         struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
 956         unsigned int func = cmd;
 957         int i, rc = 0, __cmd_rc;
 958
 959         if (!cmd_rc)
 960                 cmd_rc = &__cmd_rc;
 961         *cmd_rc = 0;
 962
 963         if (nvdimm) {
 964                 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
 965                 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
 966
 967                 if (!nfit_mem)
 968                         return -ENOTTY;
 969
 970                 if (cmd == ND_CMD_CALL) {
 971                         struct nd_cmd_pkg *call_pkg = buf;
 972
 973                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
 974                         buf = (void *) call_pkg->nd_payload;
 975                         func = call_pkg->nd_command;
 976                         if (call_pkg->nd_family != nfit_mem->family)
 977                                 return -ENOTTY;
 978
 979                         i = get_dimm(nfit_mem, func);
 980                         if (i < 0)
 981                                 return i;
 982
 983                         switch (func) {
 984                         case ND_INTEL_ENABLE_LSS_STATUS:
 985                                 rc = nd_intel_test_cmd_set_lss_status(t,
 986                                                 buf, buf_len);
 987                                 break;
 988                         case ND_INTEL_FW_GET_INFO:
 989                                 rc = nd_intel_test_get_fw_info(t, buf,
 990                                                 buf_len, i - t->dcr_idx);
 991                                 break;
 992                         case ND_INTEL_FW_START_UPDATE:
 993                                 rc = nd_intel_test_start_update(t, buf,
 994                                                 buf_len, i - t->dcr_idx);
 995                                 break;
 996                         case ND_INTEL_FW_SEND_DATA:
 997                                 rc = nd_intel_test_send_data(t, buf,
 998                                                 buf_len, i - t->dcr_idx);
 999                                 break;
1000                         case ND_INTEL_FW_FINISH_UPDATE:
1001                                 rc = nd_intel_test_finish_fw(t, buf,
1002                                                 buf_len, i - t->dcr_idx);
1003                                 break;
1004                         case ND_INTEL_FW_FINISH_QUERY:
1005                                 rc = nd_intel_test_finish_query(t, buf,
1006                                                 buf_len, i - t->dcr_idx);
1007                                 break;
1008                         case ND_INTEL_SMART:
1009                                 rc = nfit_test_cmd_smart(buf, buf_len,
1010                                                 &t->smart[i - t->dcr_idx]);
1011                                 break;
1012                         case ND_INTEL_SMART_THRESHOLD:
1013                                 rc = nfit_test_cmd_smart_threshold(buf,
1014                                                 buf_len,
1015                                                 &t->smart_threshold[i -
1016                                                         t->dcr_idx]);
1017                                 break;
1018                         case ND_INTEL_SMART_SET_THRESHOLD:
1019                                 rc = nfit_test_cmd_smart_set_threshold(buf,
1020                                                 buf_len,
1021                                                 &t->smart_threshold[i -
1022                                                         t->dcr_idx],
1023                                                 &t->smart[i - t->dcr_idx],
1024                                                 &t->pdev.dev, t->dimm_dev[i]);
1025                                 break;
1026                         case ND_INTEL_SMART_INJECT:
1027                                 rc = nfit_test_cmd_smart_inject(buf,
1028                                                 buf_len,
1029                                                 &t->smart_threshold[i -
1030                                                         t->dcr_idx],
1031                                                 &t->smart[i - t->dcr_idx],
1032                                                 &t->pdev.dev, t->dimm_dev[i]);
1033                                 break;
1034                         default:
1035                                 return -ENOTTY;
1036                         }
1037                         return override_return_code(i, func, rc);
1038                 }
1039
1040                 if (!test_bit(cmd, &cmd_mask)
1041                                 || !test_bit(func, &nfit_mem->dsm_mask))
1042                         return -ENOTTY;
1043
1044                 i = get_dimm(nfit_mem, func);
1045                 if (i < 0)
1046                         return i;
1047
1048                 switch (func) {
1049                 case ND_CMD_GET_CONFIG_SIZE:
1050                         rc = nfit_test_cmd_get_config_size(buf, buf_len);
1051                         break;
1052                 case ND_CMD_GET_CONFIG_DATA:
1053                         rc = nfit_test_cmd_get_config_data(buf, buf_len,
1054                                 t->label[i - t->dcr_idx]);
1055                         break;
1056                 case ND_CMD_SET_CONFIG_DATA:
1057                         rc = nfit_test_cmd_set_config_data(buf, buf_len,
1058                                 t->label[i - t->dcr_idx]);
1059                         break;
1060                 default:
1061                         return -ENOTTY;
1062                 }
1063                 return override_return_code(i, func, rc);
1064         } else {
1065                 struct ars_state *ars_state = &t->ars_state;
1066                 struct nd_cmd_pkg *call_pkg = buf;
1067
1068                 if (!nd_desc)
1069                         return -ENOTTY;
1070
1071                 if (cmd == ND_CMD_CALL) {
1072                         func = call_pkg->nd_command;
1073
1074                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1075                         buf = (void *) call_pkg->nd_payload;
1076
1077                         switch (func) {
1078                         case NFIT_CMD_TRANSLATE_SPA:
1079                                 rc = nfit_test_cmd_translate_spa(
1080                                         acpi_desc->nvdimm_bus, buf, buf_len);
1081                                 return rc;
1082                         case NFIT_CMD_ARS_INJECT_SET:
1083                                 rc = nfit_test_cmd_ars_error_inject(t, buf,
1084                                         buf_len);
1085                                 return rc;
1086                         case NFIT_CMD_ARS_INJECT_CLEAR:
1087                                 rc = nfit_test_cmd_ars_inject_clear(t, buf,
1088                                         buf_len);
1089                                 return rc;
1090                         case NFIT_CMD_ARS_INJECT_GET:
1091                                 rc = nfit_test_cmd_ars_inject_status(t, buf,
1092                                         buf_len);
1093                                 return rc;
1094                         default:
1095                                 return -ENOTTY;
1096                         }
1097                 }
1098
1099                 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
1100                         return -ENOTTY;
1101
1102                 switch (func) {
1103                 case ND_CMD_ARS_CAP:
1104                         rc = nfit_test_cmd_ars_cap(buf, buf_len);
1105                         break;
1106                 case ND_CMD_ARS_START:
1107                         rc = nfit_test_cmd_ars_start(t, ars_state, buf,
1108                                         buf_len, cmd_rc);
1109                         break;
1110                 case ND_CMD_ARS_STATUS:
1111                         rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len,
1112                                         cmd_rc);
1113                         break;
1114                 case ND_CMD_CLEAR_ERROR:
1115                         rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc);
1116                         break;
1117                 default:
1118                         return -ENOTTY;
1119                 }
1120         }
1121
1122         return rc;
1123 }
1124
1125 static DEFINE_SPINLOCK(nfit_test_lock);
1126 static struct nfit_test *instances[NUM_NFITS];
1127
1128 static void release_nfit_res(void *data)
1129 {
1130         struct nfit_test_resource *nfit_res = data;
1131
1132         spin_lock(&nfit_test_lock);
1133         list_del(&nfit_res->list);
1134         spin_unlock(&nfit_test_lock);
1135
1136         if (resource_size(&nfit_res->res) >= DIMM_SIZE)
1137                 gen_pool_free(nfit_pool, nfit_res->res.start,
1138                                 resource_size(&nfit_res->res));
1139         vfree(nfit_res->buf);
1140         kfree(nfit_res);
1141 }
1142
1143 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma,
1144                 void *buf)
1145 {
1146         struct device *dev = &t->pdev.dev;
1147         struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res),
1148                         GFP_KERNEL);
1149         int rc;
1150
1151         if (!buf || !nfit_res || !*dma)
1152                 goto err;
1153         rc = devm_add_action(dev, release_nfit_res, nfit_res);
1154         if (rc)
1155                 goto err;
1156         INIT_LIST_HEAD(&nfit_res->list);
1157         memset(buf, 0, size);
1158         nfit_res->dev = dev;
1159         nfit_res->buf = buf;
1160         nfit_res->res.start = *dma;
1161         nfit_res->res.end = *dma + size - 1;
1162         nfit_res->res.name = "NFIT";
1163         spin_lock_init(&nfit_res->lock);
1164         INIT_LIST_HEAD(&nfit_res->requests);
1165         spin_lock(&nfit_test_lock);
1166         list_add(&nfit_res->list, &t->resources);
1167         spin_unlock(&nfit_test_lock);
1168
1169         return nfit_res->buf;
1170  err:
1171         if (*dma && size >= DIMM_SIZE)
1172                 gen_pool_free(nfit_pool, *dma, size);
1173         if (buf)
1174                 vfree(buf);
1175         kfree(nfit_res);
1176         return NULL;
1177 }
1178
1179 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma)
1180 {
1181         struct genpool_data_align data = {
1182                 .align = SZ_128M,
1183         };
1184         void *buf = vmalloc(size);
1185
1186         if (size >= DIMM_SIZE)
1187                 *dma = gen_pool_alloc_algo(nfit_pool, size,
1188                                 gen_pool_first_fit_align, &data);
1189         else
1190                 *dma = (unsigned long) buf;
1191         return __test_alloc(t, size, dma, buf);
1192 }
1193
1194 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr)
1195 {
1196         int i;
1197
1198         for (i = 0; i < ARRAY_SIZE(instances); i++) {
1199                 struct nfit_test_resource *n, *nfit_res = NULL;
1200                 struct nfit_test *t = instances[i];
1201
1202                 if (!t)
1203                         continue;
1204                 spin_lock(&nfit_test_lock);
1205                 list_for_each_entry(n, &t->resources, list) {
1206                         if (addr >= n->res.start && (addr < n->res.start
1207                                                 + resource_size(&n->res))) {
1208                                 nfit_res = n;
1209                                 break;
1210                         } else if (addr >= (unsigned long) n->buf
1211                                         && (addr < (unsigned long) n->buf
1212                                                 + resource_size(&n->res))) {
1213                                 nfit_res = n;
1214                                 break;
1215                         }
1216                 }
1217                 spin_unlock(&nfit_test_lock);
1218                 if (nfit_res)
1219                         return nfit_res;
1220         }
1221
1222         return NULL;
1223 }
1224
1225 static int ars_state_init(struct device *dev, struct ars_state *ars_state)
1226 {
1227         /* for testing, only store up to n records that fit within 4k */
1228         ars_state->ars_status = devm_kzalloc(dev,
1229                         sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL);
1230         if (!ars_state->ars_status)
1231                 return -ENOMEM;
1232         spin_lock_init(&ars_state->lock);
1233         return 0;
1234 }
1235
1236 static void put_dimms(void *data)
1237 {
1238         struct nfit_test *t = data;
1239         int i;
1240
1241         for (i = 0; i < t->num_dcr; i++)
1242                 if (t->dimm_dev[i])
1243                         device_unregister(t->dimm_dev[i]);
1244 }
1245
1246 static struct class *nfit_test_dimm;
1247
1248 static int dimm_name_to_id(struct device *dev)
1249 {
1250         int dimm;
1251
1252         if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1)
1253                 return -ENXIO;
1254         return dimm;
1255 }
1256
1257 static ssize_t handle_show(struct device *dev, struct device_attribute *attr,
1258                 char *buf)
1259 {
1260         int dimm = dimm_name_to_id(dev);
1261
1262         if (dimm < 0)
1263                 return dimm;
1264
1265         return sprintf(buf, "%#x\n", handle[dimm]);
1266 }
1267 DEVICE_ATTR_RO(handle);
1268
1269 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr,
1270                 char *buf)
1271 {
1272         int dimm = dimm_name_to_id(dev);
1273
1274         if (dimm < 0)
1275                 return dimm;
1276
1277         return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]);
1278 }
1279
1280 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr,
1281                 const char *buf, size_t size)
1282 {
1283         int dimm = dimm_name_to_id(dev);
1284         unsigned long val;
1285         ssize_t rc;
1286
1287         if (dimm < 0)
1288                 return dimm;
1289
1290         rc = kstrtol(buf, 0, &val);
1291         if (rc)
1292                 return rc;
1293
1294         dimm_fail_cmd_flags[dimm] = val;
1295         return size;
1296 }
1297 static DEVICE_ATTR_RW(fail_cmd);
1298
1299 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr,
1300                 char *buf)
1301 {
1302         int dimm = dimm_name_to_id(dev);
1303
1304         if (dimm < 0)
1305                 return dimm;
1306
1307         return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]);
1308 }
1309
1310 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr,
1311                 const char *buf, size_t size)
1312 {
1313         int dimm = dimm_name_to_id(dev);
1314         unsigned long val;
1315         ssize_t rc;
1316
1317         if (dimm < 0)
1318                 return dimm;
1319
1320         rc = kstrtol(buf, 0, &val);
1321         if (rc)
1322                 return rc;
1323
1324         dimm_fail_cmd_code[dimm] = val;
1325         return size;
1326 }
1327 static DEVICE_ATTR_RW(fail_cmd_code);
1328
1329 static struct attribute *nfit_test_dimm_attributes[] = {
1330         &dev_attr_fail_cmd.attr,
1331         &dev_attr_fail_cmd_code.attr,
1332         &dev_attr_handle.attr,
1333         NULL,
1334 };
1335
1336 static struct attribute_group nfit_test_dimm_attribute_group = {
1337         .attrs = nfit_test_dimm_attributes,
1338 };
1339
1340 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = {
1341         &nfit_test_dimm_attribute_group,
1342         NULL,
1343 };
1344
1345 static int nfit_test_dimm_init(struct nfit_test *t)
1346 {
1347         int i;
1348
1349         if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t))
1350                 return -ENOMEM;
1351         for (i = 0; i < t->num_dcr; i++) {
1352                 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm,
1353                                 &t->pdev.dev, 0, NULL,
1354                                 nfit_test_dimm_attribute_groups,
1355                                 "test_dimm%d", i + t->dcr_idx);
1356                 if (!t->dimm_dev[i])
1357                         return -ENOMEM;
1358         }
1359         return 0;
1360 }
1361
1362 static void smart_init(struct nfit_test *t)
1363 {
1364         int i;
1365         const struct nd_intel_smart_threshold smart_t_data = {
1366                 .alarm_control = ND_INTEL_SMART_SPARE_TRIP
1367                         | ND_INTEL_SMART_TEMP_TRIP,
1368                 .media_temperature = 40 * 16,
1369                 .ctrl_temperature = 30 * 16,
1370                 .spares = 5,
1371         };
1372
1373         for (i = 0; i < t->num_dcr; i++) {
1374                 memcpy(&t->smart[i], &smart_def, sizeof(smart_def));
1375                 memcpy(&t->smart_threshold[i], &smart_t_data,
1376                                 sizeof(smart_t_data));
1377         }
1378 }
1379
1380 static int nfit_test0_alloc(struct nfit_test *t)
1381 {
1382         size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA
1383                         + sizeof(struct acpi_nfit_memory_map) * NUM_MEM
1384                         + sizeof(struct acpi_nfit_control_region) * NUM_DCR
1385                         + offsetof(struct acpi_nfit_control_region,
1386                                         window_size) * NUM_DCR
1387                         + sizeof(struct acpi_nfit_data_region) * NUM_BDW
1388                         + (sizeof(struct acpi_nfit_flush_address)
1389                                         + sizeof(u64) * NUM_HINTS) * NUM_DCR
1390                         + sizeof(struct acpi_nfit_capabilities);
1391         int i;
1392
1393         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1394         if (!t->nfit_buf)
1395                 return -ENOMEM;
1396         t->nfit_size = nfit_size;
1397
1398         t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]);
1399         if (!t->spa_set[0])
1400                 return -ENOMEM;
1401
1402         t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]);
1403         if (!t->spa_set[1])
1404                 return -ENOMEM;
1405
1406         t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]);
1407         if (!t->spa_set[2])
1408                 return -ENOMEM;
1409
1410         for (i = 0; i < t->num_dcr; i++) {
1411                 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]);
1412                 if (!t->dimm[i])
1413                         return -ENOMEM;
1414
1415                 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1416                 if (!t->label[i])
1417                         return -ENOMEM;
1418                 sprintf(t->label[i], "label%d", i);
1419
1420                 t->flush[i] = test_alloc(t, max(PAGE_SIZE,
1421                                         sizeof(u64) * NUM_HINTS),
1422                                 &t->flush_dma[i]);
1423                 if (!t->flush[i])
1424                         return -ENOMEM;
1425         }
1426
1427         for (i = 0; i < t->num_dcr; i++) {
1428                 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]);
1429                 if (!t->dcr[i])
1430                         return -ENOMEM;
1431         }
1432
1433         t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma);
1434         if (!t->_fit)
1435                 return -ENOMEM;
1436
1437         if (nfit_test_dimm_init(t))
1438                 return -ENOMEM;
1439         smart_init(t);
1440         return ars_state_init(&t->pdev.dev, &t->ars_state);
1441 }
1442
1443 static int nfit_test1_alloc(struct nfit_test *t)
1444 {
1445         size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2
1446                 + sizeof(struct acpi_nfit_memory_map) * 2
1447                 + offsetof(struct acpi_nfit_control_region, window_size) * 2;
1448         int i;
1449
1450         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1451         if (!t->nfit_buf)
1452                 return -ENOMEM;
1453         t->nfit_size = nfit_size;
1454
1455         t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]);
1456         if (!t->spa_set[0])
1457                 return -ENOMEM;
1458
1459         for (i = 0; i < t->num_dcr; i++) {
1460                 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1461                 if (!t->label[i])
1462                         return -ENOMEM;
1463                 sprintf(t->label[i], "label%d", i);
1464         }
1465
1466         t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]);
1467         if (!t->spa_set[1])
1468                 return -ENOMEM;
1469
1470         if (nfit_test_dimm_init(t))
1471                 return -ENOMEM;
1472         smart_init(t);
1473         return ars_state_init(&t->pdev.dev, &t->ars_state);
1474 }
1475
1476 static void dcr_common_init(struct acpi_nfit_control_region *dcr)
1477 {
1478         dcr->vendor_id = 0xabcd;
1479         dcr->device_id = 0;
1480         dcr->revision_id = 1;
1481         dcr->valid_fields = 1;
1482         dcr->manufacturing_location = 0xa;
1483         dcr->manufacturing_date = cpu_to_be16(2016);
1484 }
1485
1486 static void nfit_test0_setup(struct nfit_test *t)
1487 {
1488         const int flush_hint_size = sizeof(struct acpi_nfit_flush_address)
1489                 + (sizeof(u64) * NUM_HINTS);
1490         struct acpi_nfit_desc *acpi_desc;
1491         struct acpi_nfit_memory_map *memdev;
1492         void *nfit_buf = t->nfit_buf;
1493         struct acpi_nfit_system_address *spa;
1494         struct acpi_nfit_control_region *dcr;
1495         struct acpi_nfit_data_region *bdw;
1496         struct acpi_nfit_flush_address *flush;
1497         struct acpi_nfit_capabilities *pcap;
1498         unsigned int offset = 0, i;
1499
1500         /*
1501          * spa0 (interleave first half of dimm0 and dimm1, note storage
1502          * does not actually alias the related block-data-window
1503          * regions)
1504          */
1505         spa = nfit_buf;
1506         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1507         spa->header.length = sizeof(*spa);
1508         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1509         spa->range_index = 0+1;
1510         spa->address = t->spa_set_dma[0];
1511         spa->length = SPA0_SIZE;
1512         offset += spa->header.length;
1513
1514         /*
1515          * spa1 (interleave last half of the 4 DIMMS, note storage
1516          * does not actually alias the related block-data-window
1517          * regions)
1518          */
1519         spa = nfit_buf + offset;
1520         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1521         spa->header.length = sizeof(*spa);
1522         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1523         spa->range_index = 1+1;
1524         spa->address = t->spa_set_dma[1];
1525         spa->length = SPA1_SIZE;
1526         offset += spa->header.length;
1527
1528         /* spa2 (dcr0) dimm0 */
1529         spa = nfit_buf + offset;
1530         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1531         spa->header.length = sizeof(*spa);
1532         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1533         spa->range_index = 2+1;
1534         spa->address = t->dcr_dma[0];
1535         spa->length = DCR_SIZE;
1536         offset += spa->header.length;
1537
1538         /* spa3 (dcr1) dimm1 */
1539         spa = nfit_buf + offset;
1540         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1541         spa->header.length = sizeof(*spa);
1542         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1543         spa->range_index = 3+1;
1544         spa->address = t->dcr_dma[1];
1545         spa->length = DCR_SIZE;
1546         offset += spa->header.length;
1547
1548         /* spa4 (dcr2) dimm2 */
1549         spa = nfit_buf + offset;
1550         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1551         spa->header.length = sizeof(*spa);
1552         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1553         spa->range_index = 4+1;
1554         spa->address = t->dcr_dma[2];
1555         spa->length = DCR_SIZE;
1556         offset += spa->header.length;
1557
1558         /* spa5 (dcr3) dimm3 */
1559         spa = nfit_buf + offset;
1560         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1561         spa->header.length = sizeof(*spa);
1562         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1563         spa->range_index = 5+1;
1564         spa->address = t->dcr_dma[3];
1565         spa->length = DCR_SIZE;
1566         offset += spa->header.length;
1567
1568         /* spa6 (bdw for dcr0) dimm0 */
1569         spa = nfit_buf + offset;
1570         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1571         spa->header.length = sizeof(*spa);
1572         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1573         spa->range_index = 6+1;
1574         spa->address = t->dimm_dma[0];
1575         spa->length = DIMM_SIZE;
1576         offset += spa->header.length;
1577
1578         /* spa7 (bdw for dcr1) dimm1 */
1579         spa = nfit_buf + offset;
1580         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1581         spa->header.length = sizeof(*spa);
1582         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1583         spa->range_index = 7+1;
1584         spa->address = t->dimm_dma[1];
1585         spa->length = DIMM_SIZE;
1586         offset += spa->header.length;
1587
1588         /* spa8 (bdw for dcr2) dimm2 */
1589         spa = nfit_buf + offset;
1590         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1591         spa->header.length = sizeof(*spa);
1592         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1593         spa->range_index = 8+1;
1594         spa->address = t->dimm_dma[2];
1595         spa->length = DIMM_SIZE;
1596         offset += spa->header.length;
1597
1598         /* spa9 (bdw for dcr3) dimm3 */
1599         spa = nfit_buf + offset;
1600         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1601         spa->header.length = sizeof(*spa);
1602         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1603         spa->range_index = 9+1;
1604         spa->address = t->dimm_dma[3];
1605         spa->length = DIMM_SIZE;
1606         offset += spa->header.length;
1607
1608         /* mem-region0 (spa0, dimm0) */
1609         memdev = nfit_buf + offset;
1610         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1611         memdev->header.length = sizeof(*memdev);
1612         memdev->device_handle = handle[0];
1613         memdev->physical_id = 0;
1614         memdev->region_id = 0;
1615         memdev->range_index = 0+1;
1616         memdev->region_index = 4+1;
1617         memdev->region_size = SPA0_SIZE/2;
1618         memdev->region_offset = 1;
1619         memdev->address = 0;
1620         memdev->interleave_index = 0;
1621         memdev->interleave_ways = 2;
1622         offset += memdev->header.length;
1623
1624         /* mem-region1 (spa0, dimm1) */
1625         memdev = nfit_buf + offset;
1626         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1627         memdev->header.length = sizeof(*memdev);
1628         memdev->device_handle = handle[1];
1629         memdev->physical_id = 1;
1630         memdev->region_id = 0;
1631         memdev->range_index = 0+1;
1632         memdev->region_index = 5+1;
1633         memdev->region_size = SPA0_SIZE/2;
1634         memdev->region_offset = (1 << 8);
1635         memdev->address = 0;
1636         memdev->interleave_index = 0;
1637         memdev->interleave_ways = 2;
1638         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1639         offset += memdev->header.length;
1640
1641         /* mem-region2 (spa1, dimm0) */
1642         memdev = nfit_buf + offset;
1643         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1644         memdev->header.length = sizeof(*memdev);
1645         memdev->device_handle = handle[0];
1646         memdev->physical_id = 0;
1647         memdev->region_id = 1;
1648         memdev->range_index = 1+1;
1649         memdev->region_index = 4+1;
1650         memdev->region_size = SPA1_SIZE/4;
1651         memdev->region_offset = (1 << 16);
1652         memdev->address = SPA0_SIZE/2;
1653         memdev->interleave_index = 0;
1654         memdev->interleave_ways = 4;
1655         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1656         offset += memdev->header.length;
1657
1658         /* mem-region3 (spa1, dimm1) */
1659         memdev = nfit_buf + offset;
1660         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1661         memdev->header.length = sizeof(*memdev);
1662         memdev->device_handle = handle[1];
1663         memdev->physical_id = 1;
1664         memdev->region_id = 1;
1665         memdev->range_index = 1+1;
1666         memdev->region_index = 5+1;
1667         memdev->region_size = SPA1_SIZE/4;
1668         memdev->region_offset = (1 << 24);
1669         memdev->address = SPA0_SIZE/2;
1670         memdev->interleave_index = 0;
1671         memdev->interleave_ways = 4;
1672         offset += memdev->header.length;
1673
1674         /* mem-region4 (spa1, dimm2) */
1675         memdev = nfit_buf + offset;
1676         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1677         memdev->header.length = sizeof(*memdev);
1678         memdev->device_handle = handle[2];
1679         memdev->physical_id = 2;
1680         memdev->region_id = 0;
1681         memdev->range_index = 1+1;
1682         memdev->region_index = 6+1;
1683         memdev->region_size = SPA1_SIZE/4;
1684         memdev->region_offset = (1ULL << 32);
1685         memdev->address = SPA0_SIZE/2;
1686         memdev->interleave_index = 0;
1687         memdev->interleave_ways = 4;
1688         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1689         offset += memdev->header.length;
1690
1691         /* mem-region5 (spa1, dimm3) */
1692         memdev = nfit_buf + offset;
1693         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1694         memdev->header.length = sizeof(*memdev);
1695         memdev->device_handle = handle[3];
1696         memdev->physical_id = 3;
1697         memdev->region_id = 0;
1698         memdev->range_index = 1+1;
1699         memdev->region_index = 7+1;
1700         memdev->region_size = SPA1_SIZE/4;
1701         memdev->region_offset = (1ULL << 40);
1702         memdev->address = SPA0_SIZE/2;
1703         memdev->interleave_index = 0;
1704         memdev->interleave_ways = 4;
1705         offset += memdev->header.length;
1706
1707         /* mem-region6 (spa/dcr0, dimm0) */
1708         memdev = nfit_buf + offset;
1709         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1710         memdev->header.length = sizeof(*memdev);
1711         memdev->device_handle = handle[0];
1712         memdev->physical_id = 0;
1713         memdev->region_id = 0;
1714         memdev->range_index = 2+1;
1715         memdev->region_index = 0+1;
1716         memdev->region_size = 0;
1717         memdev->region_offset = 0;
1718         memdev->address = 0;
1719         memdev->interleave_index = 0;
1720         memdev->interleave_ways = 1;
1721         offset += memdev->header.length;
1722
1723         /* mem-region7 (spa/dcr1, dimm1) */
1724         memdev = nfit_buf + offset;
1725         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1726         memdev->header.length = sizeof(*memdev);
1727         memdev->device_handle = handle[1];
1728         memdev->physical_id = 1;
1729         memdev->region_id = 0;
1730         memdev->range_index = 3+1;
1731         memdev->region_index = 1+1;
1732         memdev->region_size = 0;
1733         memdev->region_offset = 0;
1734         memdev->address = 0;
1735         memdev->interleave_index = 0;
1736         memdev->interleave_ways = 1;
1737         offset += memdev->header.length;
1738
1739         /* mem-region8 (spa/dcr2, dimm2) */
1740         memdev = nfit_buf + offset;
1741         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1742         memdev->header.length = sizeof(*memdev);
1743         memdev->device_handle = handle[2];
1744         memdev->physical_id = 2;
1745         memdev->region_id = 0;
1746         memdev->range_index = 4+1;
1747         memdev->region_index = 2+1;
1748         memdev->region_size = 0;
1749         memdev->region_offset = 0;
1750         memdev->address = 0;
1751         memdev->interleave_index = 0;
1752         memdev->interleave_ways = 1;
1753         offset += memdev->header.length;
1754
1755         /* mem-region9 (spa/dcr3, dimm3) */
1756         memdev = nfit_buf + offset;
1757         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1758         memdev->header.length = sizeof(*memdev);
1759         memdev->device_handle = handle[3];
1760         memdev->physical_id = 3;
1761         memdev->region_id = 0;
1762         memdev->range_index = 5+1;
1763         memdev->region_index = 3+1;
1764         memdev->region_size = 0;
1765         memdev->region_offset = 0;
1766         memdev->address = 0;
1767         memdev->interleave_index = 0;
1768         memdev->interleave_ways = 1;
1769         offset += memdev->header.length;
1770
1771         /* mem-region10 (spa/bdw0, dimm0) */
1772         memdev = nfit_buf + offset;
1773         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1774         memdev->header.length = sizeof(*memdev);
1775         memdev->device_handle = handle[0];
1776         memdev->physical_id = 0;
1777         memdev->region_id = 0;
1778         memdev->range_index = 6+1;
1779         memdev->region_index = 0+1;
1780         memdev->region_size = 0;
1781         memdev->region_offset = 0;
1782         memdev->address = 0;
1783         memdev->interleave_index = 0;
1784         memdev->interleave_ways = 1;
1785         offset += memdev->header.length;
1786
1787         /* mem-region11 (spa/bdw1, dimm1) */
1788         memdev = nfit_buf + offset;
1789         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1790         memdev->header.length = sizeof(*memdev);
1791         memdev->device_handle = handle[1];
1792         memdev->physical_id = 1;
1793         memdev->region_id = 0;
1794         memdev->range_index = 7+1;
1795         memdev->region_index = 1+1;
1796         memdev->region_size = 0;
1797         memdev->region_offset = 0;
1798         memdev->address = 0;
1799         memdev->interleave_index = 0;
1800         memdev->interleave_ways = 1;
1801         offset += memdev->header.length;
1802
1803         /* mem-region12 (spa/bdw2, dimm2) */
1804         memdev = nfit_buf + offset;
1805         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1806         memdev->header.length = sizeof(*memdev);
1807         memdev->device_handle = handle[2];
1808         memdev->physical_id = 2;
1809         memdev->region_id = 0;
1810         memdev->range_index = 8+1;
1811         memdev->region_index = 2+1;
1812         memdev->region_size = 0;
1813         memdev->region_offset = 0;
1814         memdev->address = 0;
1815         memdev->interleave_index = 0;
1816         memdev->interleave_ways = 1;
1817         offset += memdev->header.length;
1818
1819         /* mem-region13 (spa/dcr3, dimm3) */
1820         memdev = nfit_buf + offset;
1821         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1822         memdev->header.length = sizeof(*memdev);
1823         memdev->device_handle = handle[3];
1824         memdev->physical_id = 3;
1825         memdev->region_id = 0;
1826         memdev->range_index = 9+1;
1827         memdev->region_index = 3+1;
1828         memdev->region_size = 0;
1829         memdev->region_offset = 0;
1830         memdev->address = 0;
1831         memdev->interleave_index = 0;
1832         memdev->interleave_ways = 1;
1833         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1834         offset += memdev->header.length;
1835
1836         /* dcr-descriptor0: blk */
1837         dcr = nfit_buf + offset;
1838         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1839         dcr->header.length = sizeof(*dcr);
1840         dcr->region_index = 0+1;
1841         dcr_common_init(dcr);
1842         dcr->serial_number = ~handle[0];
1843         dcr->code = NFIT_FIC_BLK;
1844         dcr->windows = 1;
1845         dcr->window_size = DCR_SIZE;
1846         dcr->command_offset = 0;
1847         dcr->command_size = 8;
1848         dcr->status_offset = 8;
1849         dcr->status_size = 4;
1850         offset += dcr->header.length;
1851
1852         /* dcr-descriptor1: blk */
1853         dcr = nfit_buf + offset;
1854         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1855         dcr->header.length = sizeof(*dcr);
1856         dcr->region_index = 1+1;
1857         dcr_common_init(dcr);
1858         dcr->serial_number = ~handle[1];
1859         dcr->code = NFIT_FIC_BLK;
1860         dcr->windows = 1;
1861         dcr->window_size = DCR_SIZE;
1862         dcr->command_offset = 0;
1863         dcr->command_size = 8;
1864         dcr->status_offset = 8;
1865         dcr->status_size = 4;
1866         offset += dcr->header.length;
1867
1868         /* dcr-descriptor2: blk */
1869         dcr = nfit_buf + offset;
1870         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1871         dcr->header.length = sizeof(*dcr);
1872         dcr->region_index = 2+1;
1873         dcr_common_init(dcr);
1874         dcr->serial_number = ~handle[2];
1875         dcr->code = NFIT_FIC_BLK;
1876         dcr->windows = 1;
1877         dcr->window_size = DCR_SIZE;
1878         dcr->command_offset = 0;
1879         dcr->command_size = 8;
1880         dcr->status_offset = 8;
1881         dcr->status_size = 4;
1882         offset += dcr->header.length;
1883
1884         /* dcr-descriptor3: blk */
1885         dcr = nfit_buf + offset;
1886         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1887         dcr->header.length = sizeof(*dcr);
1888         dcr->region_index = 3+1;
1889         dcr_common_init(dcr);
1890         dcr->serial_number = ~handle[3];
1891         dcr->code = NFIT_FIC_BLK;
1892         dcr->windows = 1;
1893         dcr->window_size = DCR_SIZE;
1894         dcr->command_offset = 0;
1895         dcr->command_size = 8;
1896         dcr->status_offset = 8;
1897         dcr->status_size = 4;
1898         offset += dcr->header.length;
1899
1900         /* dcr-descriptor0: pmem */
1901         dcr = nfit_buf + offset;
1902         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1903         dcr->header.length = offsetof(struct acpi_nfit_control_region,
1904                         window_size);
1905         dcr->region_index = 4+1;
1906         dcr_common_init(dcr);
1907         dcr->serial_number = ~handle[0];
1908         dcr->code = NFIT_FIC_BYTEN;
1909         dcr->windows = 0;
1910         offset += dcr->header.length;
1911
1912         /* dcr-descriptor1: pmem */
1913         dcr = nfit_buf + offset;
1914         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1915         dcr->header.length = offsetof(struct acpi_nfit_control_region,
1916                         window_size);
1917         dcr->region_index = 5+1;
1918         dcr_common_init(dcr);
1919         dcr->serial_number = ~handle[1];
1920         dcr->code = NFIT_FIC_BYTEN;
1921         dcr->windows = 0;
1922         offset += dcr->header.length;
1923
1924         /* dcr-descriptor2: pmem */
1925         dcr = nfit_buf + offset;
1926         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1927         dcr->header.length = offsetof(struct acpi_nfit_control_region,
1928                         window_size);
1929         dcr->region_index = 6+1;
1930         dcr_common_init(dcr);
1931         dcr->serial_number = ~handle[2];
1932         dcr->code = NFIT_FIC_BYTEN;
1933         dcr->windows = 0;
1934         offset += dcr->header.length;
1935
1936         /* dcr-descriptor3: pmem */
1937         dcr = nfit_buf + offset;
1938         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1939         dcr->header.length = offsetof(struct acpi_nfit_control_region,
1940                         window_size);
1941         dcr->region_index = 7+1;
1942         dcr_common_init(dcr);
1943         dcr->serial_number = ~handle[3];
1944         dcr->code = NFIT_FIC_BYTEN;
1945         dcr->windows = 0;
1946         offset += dcr->header.length;
1947
1948         /* bdw0 (spa/dcr0, dimm0) */
1949         bdw = nfit_buf + offset;
1950         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1951         bdw->header.length = sizeof(*bdw);
1952         bdw->region_index = 0+1;
1953         bdw->windows = 1;
1954         bdw->offset = 0;
1955         bdw->size = BDW_SIZE;
1956         bdw->capacity = DIMM_SIZE;
1957         bdw->start_address = 0;
1958         offset += bdw->header.length;
1959
1960         /* bdw1 (spa/dcr1, dimm1) */
1961         bdw = nfit_buf + offset;
1962         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1963         bdw->header.length = sizeof(*bdw);
1964         bdw->region_index = 1+1;
1965         bdw->windows = 1;
1966         bdw->offset = 0;
1967         bdw->size = BDW_SIZE;
1968         bdw->capacity = DIMM_SIZE;
1969         bdw->start_address = 0;
1970         offset += bdw->header.length;
1971
1972         /* bdw2 (spa/dcr2, dimm2) */
1973         bdw = nfit_buf + offset;
1974         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1975         bdw->header.length = sizeof(*bdw);
1976         bdw->region_index = 2+1;
1977         bdw->windows = 1;
1978         bdw->offset = 0;
1979         bdw->size = BDW_SIZE;
1980         bdw->capacity = DIMM_SIZE;
1981         bdw->start_address = 0;
1982         offset += bdw->header.length;
1983
1984         /* bdw3 (spa/dcr3, dimm3) */
1985         bdw = nfit_buf + offset;
1986         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1987         bdw->header.length = sizeof(*bdw);
1988         bdw->region_index = 3+1;
1989         bdw->windows = 1;
1990         bdw->offset = 0;
1991         bdw->size = BDW_SIZE;
1992         bdw->capacity = DIMM_SIZE;
1993         bdw->start_address = 0;
1994         offset += bdw->header.length;
1995
1996         /* flush0 (dimm0) */
1997         flush = nfit_buf + offset;
1998         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1999         flush->header.length = flush_hint_size;
2000         flush->device_handle = handle[0];
2001         flush->hint_count = NUM_HINTS;
2002         for (i = 0; i < NUM_HINTS; i++)
2003                 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64);
2004         offset += flush->header.length;
2005
2006         /* flush1 (dimm1) */
2007         flush = nfit_buf + offset;
2008         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2009         flush->header.length = flush_hint_size;
2010         flush->device_handle = handle[1];
2011         flush->hint_count = NUM_HINTS;
2012         for (i = 0; i < NUM_HINTS; i++)
2013                 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64);
2014         offset += flush->header.length;
2015
2016         /* flush2 (dimm2) */
2017         flush = nfit_buf + offset;
2018         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2019         flush->header.length = flush_hint_size;
2020         flush->device_handle = handle[2];
2021         flush->hint_count = NUM_HINTS;
2022         for (i = 0; i < NUM_HINTS; i++)
2023                 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64);
2024         offset += flush->header.length;
2025
2026         /* flush3 (dimm3) */
2027         flush = nfit_buf + offset;
2028         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2029         flush->header.length = flush_hint_size;
2030         flush->device_handle = handle[3];
2031         flush->hint_count = NUM_HINTS;
2032         for (i = 0; i < NUM_HINTS; i++)
2033                 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64);
2034         offset += flush->header.length;
2035
2036         /* platform capabilities */
2037         pcap = nfit_buf + offset;
2038         pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES;
2039         pcap->header.length = sizeof(*pcap);
2040         pcap->highest_capability = 1;
2041         pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH;
2042         offset += pcap->header.length;
2043
2044         if (t->setup_hotplug) {
2045                 /* dcr-descriptor4: blk */
2046                 dcr = nfit_buf + offset;
2047                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2048                 dcr->header.length = sizeof(*dcr);
2049                 dcr->region_index = 8+1;
2050                 dcr_common_init(dcr);
2051                 dcr->serial_number = ~handle[4];
2052                 dcr->code = NFIT_FIC_BLK;
2053                 dcr->windows = 1;
2054                 dcr->window_size = DCR_SIZE;
2055                 dcr->command_offset = 0;
2056                 dcr->command_size = 8;
2057                 dcr->status_offset = 8;
2058                 dcr->status_size = 4;
2059                 offset += dcr->header.length;
2060
2061                 /* dcr-descriptor4: pmem */
2062                 dcr = nfit_buf + offset;
2063                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2064                 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2065                                 window_size);
2066                 dcr->region_index = 9+1;
2067                 dcr_common_init(dcr);
2068                 dcr->serial_number = ~handle[4];
2069                 dcr->code = NFIT_FIC_BYTEN;
2070                 dcr->windows = 0;
2071                 offset += dcr->header.length;
2072
2073                 /* bdw4 (spa/dcr4, dimm4) */
2074                 bdw = nfit_buf + offset;
2075                 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2076                 bdw->header.length = sizeof(*bdw);
2077                 bdw->region_index = 8+1;
2078                 bdw->windows = 1;
2079                 bdw->offset = 0;
2080                 bdw->size = BDW_SIZE;
2081                 bdw->capacity = DIMM_SIZE;
2082                 bdw->start_address = 0;
2083                 offset += bdw->header.length;
2084
2085                 /* spa10 (dcr4) dimm4 */
2086                 spa = nfit_buf + offset;
2087                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2088                 spa->header.length = sizeof(*spa);
2089                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2090                 spa->range_index = 10+1;
2091                 spa->address = t->dcr_dma[4];
2092                 spa->length = DCR_SIZE;
2093                 offset += spa->header.length;
2094
2095                 /*
2096                  * spa11 (single-dimm interleave for hotplug, note storage
2097                  * does not actually alias the related block-data-window
2098                  * regions)
2099                  */
2100                 spa = nfit_buf + offset;
2101                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2102                 spa->header.length = sizeof(*spa);
2103                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2104                 spa->range_index = 11+1;
2105                 spa->address = t->spa_set_dma[2];
2106                 spa->length = SPA0_SIZE;
2107                 offset += spa->header.length;
2108
2109                 /* spa12 (bdw for dcr4) dimm4 */
2110                 spa = nfit_buf + offset;
2111                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2112                 spa->header.length = sizeof(*spa);
2113                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2114                 spa->range_index = 12+1;
2115                 spa->address = t->dimm_dma[4];
2116                 spa->length = DIMM_SIZE;
2117                 offset += spa->header.length;
2118
2119                 /* mem-region14 (spa/dcr4, dimm4) */
2120                 memdev = nfit_buf + offset;
2121                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2122                 memdev->header.length = sizeof(*memdev);
2123                 memdev->device_handle = handle[4];
2124                 memdev->physical_id = 4;
2125                 memdev->region_id = 0;
2126                 memdev->range_index = 10+1;
2127                 memdev->region_index = 8+1;
2128                 memdev->region_size = 0;
2129                 memdev->region_offset = 0;
2130                 memdev->address = 0;
2131                 memdev->interleave_index = 0;
2132                 memdev->interleave_ways = 1;
2133                 offset += memdev->header.length;
2134
2135                 /* mem-region15 (spa11, dimm4) */
2136                 memdev = nfit_buf + offset;
2137                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2138                 memdev->header.length = sizeof(*memdev);
2139                 memdev->device_handle = handle[4];
2140                 memdev->physical_id = 4;
2141                 memdev->region_id = 0;
2142                 memdev->range_index = 11+1;
2143                 memdev->region_index = 9+1;
2144                 memdev->region_size = SPA0_SIZE;
2145                 memdev->region_offset = (1ULL << 48);
2146                 memdev->address = 0;
2147                 memdev->interleave_index = 0;
2148                 memdev->interleave_ways = 1;
2149                 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2150                 offset += memdev->header.length;
2151
2152                 /* mem-region16 (spa/bdw4, dimm4) */
2153                 memdev = nfit_buf + offset;
2154                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2155                 memdev->header.length = sizeof(*memdev);
2156                 memdev->device_handle = handle[4];
2157                 memdev->physical_id = 4;
2158                 memdev->region_id = 0;
2159                 memdev->range_index = 12+1;
2160                 memdev->region_index = 8+1;
2161                 memdev->region_size = 0;
2162                 memdev->region_offset = 0;
2163                 memdev->address = 0;
2164                 memdev->interleave_index = 0;
2165                 memdev->interleave_ways = 1;
2166                 offset += memdev->header.length;
2167
2168                 /* flush3 (dimm4) */
2169                 flush = nfit_buf + offset;
2170                 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2171                 flush->header.length = flush_hint_size;
2172                 flush->device_handle = handle[4];
2173                 flush->hint_count = NUM_HINTS;
2174                 for (i = 0; i < NUM_HINTS; i++)
2175                         flush->hint_address[i] = t->flush_dma[4]
2176                                 + i * sizeof(u64);
2177                 offset += flush->header.length;
2178
2179                 /* sanity check to make sure we've filled the buffer */
2180                 WARN_ON(offset != t->nfit_size);
2181         }
2182
2183         t->nfit_filled = offset;
2184
2185         post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2186                         SPA0_SIZE);
2187
2188         acpi_desc = &t->acpi_desc;
2189         set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2190         set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2191         set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2192         set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en);
2193         set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2194         set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2195         set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en);
2196         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2197         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2198         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2199         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2200         set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en);
2201         set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_nfit_cmd_force_en);
2202         set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_nfit_cmd_force_en);
2203         set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_nfit_cmd_force_en);
2204         set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_nfit_cmd_force_en);
2205         set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en);
2206         set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en);
2207         set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en);
2208         set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en);
2209         set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en);
2210         set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2211 }
2212
2213 static void nfit_test1_setup(struct nfit_test *t)
2214 {
2215         size_t offset;
2216         void *nfit_buf = t->nfit_buf;
2217         struct acpi_nfit_memory_map *memdev;
2218         struct acpi_nfit_control_region *dcr;
2219         struct acpi_nfit_system_address *spa;
2220         struct acpi_nfit_desc *acpi_desc;
2221
2222         offset = 0;
2223         /* spa0 (flat range with no bdw aliasing) */
2224         spa = nfit_buf + offset;
2225         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2226         spa->header.length = sizeof(*spa);
2227         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2228         spa->range_index = 0+1;
2229         spa->address = t->spa_set_dma[0];
2230         spa->length = SPA2_SIZE;
2231         offset += spa->header.length;
2232
2233         /* virtual cd region */
2234         spa = nfit_buf + offset;
2235         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2236         spa->header.length = sizeof(*spa);
2237         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16);
2238         spa->range_index = 0;
2239         spa->address = t->spa_set_dma[1];
2240         spa->length = SPA_VCD_SIZE;
2241         offset += spa->header.length;
2242
2243         /* mem-region0 (spa0, dimm0) */
2244         memdev = nfit_buf + offset;
2245         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2246         memdev->header.length = sizeof(*memdev);
2247         memdev->device_handle = handle[5];
2248         memdev->physical_id = 0;
2249         memdev->region_id = 0;
2250         memdev->range_index = 0+1;
2251         memdev->region_index = 0+1;
2252         memdev->region_size = SPA2_SIZE;
2253         memdev->region_offset = 0;
2254         memdev->address = 0;
2255         memdev->interleave_index = 0;
2256         memdev->interleave_ways = 1;
2257         memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED
2258                 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED
2259                 | ACPI_NFIT_MEM_NOT_ARMED;
2260         offset += memdev->header.length;
2261
2262         /* dcr-descriptor0 */
2263         dcr = nfit_buf + offset;
2264         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2265         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2266                         window_size);
2267         dcr->region_index = 0+1;
2268         dcr_common_init(dcr);
2269         dcr->serial_number = ~handle[5];
2270         dcr->code = NFIT_FIC_BYTE;
2271         dcr->windows = 0;
2272         offset += dcr->header.length;
2273
2274         memdev = nfit_buf + offset;
2275         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2276         memdev->header.length = sizeof(*memdev);
2277         memdev->device_handle = handle[6];
2278         memdev->physical_id = 0;
2279         memdev->region_id = 0;
2280         memdev->range_index = 0;
2281         memdev->region_index = 0+2;
2282         memdev->region_size = SPA2_SIZE;
2283         memdev->region_offset = 0;
2284         memdev->address = 0;
2285         memdev->interleave_index = 0;
2286         memdev->interleave_ways = 1;
2287         memdev->flags = ACPI_NFIT_MEM_MAP_FAILED;
2288         offset += memdev->header.length;
2289
2290         /* dcr-descriptor1 */
2291         dcr = nfit_buf + offset;
2292         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2293         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2294                         window_size);
2295         dcr->region_index = 0+2;
2296         dcr_common_init(dcr);
2297         dcr->serial_number = ~handle[6];
2298         dcr->code = NFIT_FIC_BYTE;
2299         dcr->windows = 0;
2300         offset += dcr->header.length;
2301
2302         /* sanity check to make sure we've filled the buffer */
2303         WARN_ON(offset != t->nfit_size);
2304
2305         t->nfit_filled = offset;
2306
2307         post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2308                         SPA2_SIZE);
2309
2310         acpi_desc = &t->acpi_desc;
2311         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2312         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2313         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2314         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2315         set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2316         set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2317         set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2318         set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2319 }
2320
2321 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
2322                 void *iobuf, u64 len, int rw)
2323 {
2324         struct nfit_blk *nfit_blk = ndbr->blk_provider_data;
2325         struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
2326         struct nd_region *nd_region = &ndbr->nd_region;
2327         unsigned int lane;
2328
2329         lane = nd_region_acquire_lane(nd_region);
2330         if (rw)
2331                 memcpy(mmio->addr.base + dpa, iobuf, len);
2332         else {
2333                 memcpy(iobuf, mmio->addr.base + dpa, len);
2334
2335                 /* give us some some coverage of the arch_invalidate_pmem() API */
2336                 arch_invalidate_pmem(mmio->addr.base + dpa, len);
2337         }
2338         nd_region_release_lane(nd_region, lane);
2339
2340         return 0;
2341 }
2342
2343 static unsigned long nfit_ctl_handle;
2344
2345 union acpi_object *result;
2346
2347 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle,
2348                 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4)
2349 {
2350         if (handle != &nfit_ctl_handle)
2351                 return ERR_PTR(-ENXIO);
2352
2353         return result;
2354 }
2355
2356 static int setup_result(void *buf, size_t size)
2357 {
2358         result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL);
2359         if (!result)
2360                 return -ENOMEM;
2361         result->package.type = ACPI_TYPE_BUFFER,
2362         result->buffer.pointer = (void *) (result + 1);
2363         result->buffer.length = size;
2364         memcpy(result->buffer.pointer, buf, size);
2365         memset(buf, 0, size);
2366         return 0;
2367 }
2368
2369 static int nfit_ctl_test(struct device *dev)
2370 {
2371         int rc, cmd_rc;
2372         struct nvdimm *nvdimm;
2373         struct acpi_device *adev;
2374         struct nfit_mem *nfit_mem;
2375         struct nd_ars_record *record;
2376         struct acpi_nfit_desc *acpi_desc;
2377         const u64 test_val = 0x0123456789abcdefULL;
2378         unsigned long mask, cmd_size, offset;
2379         union {
2380                 struct nd_cmd_get_config_size cfg_size;
2381                 struct nd_cmd_clear_error clear_err;
2382                 struct nd_cmd_ars_status ars_stat;
2383                 struct nd_cmd_ars_cap ars_cap;
2384                 char buf[sizeof(struct nd_cmd_ars_status)
2385                         + sizeof(struct nd_ars_record)];
2386         } cmds;
2387
2388         adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
2389         if (!adev)
2390                 return -ENOMEM;
2391         *adev = (struct acpi_device) {
2392                 .handle = &nfit_ctl_handle,
2393                 .dev = {
2394                         .init_name = "test-adev",
2395                 },
2396         };
2397
2398         acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL);
2399         if (!acpi_desc)
2400                 return -ENOMEM;
2401         *acpi_desc = (struct acpi_nfit_desc) {
2402                 .nd_desc = {
2403                         .cmd_mask = 1UL << ND_CMD_ARS_CAP
2404                                 | 1UL << ND_CMD_ARS_START
2405                                 | 1UL << ND_CMD_ARS_STATUS
2406                                 | 1UL << ND_CMD_CLEAR_ERROR
2407                                 | 1UL << ND_CMD_CALL,
2408                         .module = THIS_MODULE,
2409                         .provider_name = "ACPI.NFIT",
2410                         .ndctl = acpi_nfit_ctl,
2411                         .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA
2412                                 | 1UL << NFIT_CMD_ARS_INJECT_SET
2413                                 | 1UL << NFIT_CMD_ARS_INJECT_CLEAR
2414                                 | 1UL << NFIT_CMD_ARS_INJECT_GET,
2415                 },
2416                 .dev = &adev->dev,
2417         };
2418
2419         nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL);
2420         if (!nfit_mem)
2421                 return -ENOMEM;
2422
2423         mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD
2424                 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE
2425                 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA
2426                 | 1UL << ND_CMD_VENDOR;
2427         *nfit_mem = (struct nfit_mem) {
2428                 .adev = adev,
2429                 .family = NVDIMM_FAMILY_INTEL,
2430                 .dsm_mask = mask,
2431         };
2432
2433         nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL);
2434         if (!nvdimm)
2435                 return -ENOMEM;
2436         *nvdimm = (struct nvdimm) {
2437                 .provider_data = nfit_mem,
2438                 .cmd_mask = mask,
2439                 .dev = {
2440                         .init_name = "test-dimm",
2441                 },
2442         };
2443
2444
2445         /* basic checkout of a typical 'get config size' command */
2446         cmd_size = sizeof(cmds.cfg_size);
2447         cmds.cfg_size = (struct nd_cmd_get_config_size) {
2448                 .status = 0,
2449                 .config_size = SZ_128K,
2450                 .max_xfer = SZ_4K,
2451         };
2452         rc = setup_result(cmds.buf, cmd_size);
2453         if (rc)
2454                 return rc;
2455         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2456                         cmds.buf, cmd_size, &cmd_rc);
2457
2458         if (rc < 0 || cmd_rc || cmds.cfg_size.status != 0
2459                         || cmds.cfg_size.config_size != SZ_128K
2460                         || cmds.cfg_size.max_xfer != SZ_4K) {
2461                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2462                                 __func__, __LINE__, rc, cmd_rc);
2463                 return -EIO;
2464         }
2465
2466
2467         /* test ars_status with zero output */
2468         cmd_size = offsetof(struct nd_cmd_ars_status, address);
2469         cmds.ars_stat = (struct nd_cmd_ars_status) {
2470                 .out_length = 0,
2471         };
2472         rc = setup_result(cmds.buf, cmd_size);
2473         if (rc)
2474                 return rc;
2475         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2476                         cmds.buf, cmd_size, &cmd_rc);
2477
2478         if (rc < 0 || cmd_rc) {
2479                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2480                                 __func__, __LINE__, rc, cmd_rc);
2481                 return -EIO;
2482         }
2483
2484
2485         /* test ars_cap with benign extended status */
2486         cmd_size = sizeof(cmds.ars_cap);
2487         cmds.ars_cap = (struct nd_cmd_ars_cap) {
2488                 .status = ND_ARS_PERSISTENT << 16,
2489         };
2490         offset = offsetof(struct nd_cmd_ars_cap, status);
2491         rc = setup_result(cmds.buf + offset, cmd_size - offset);
2492         if (rc)
2493                 return rc;
2494         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP,
2495                         cmds.buf, cmd_size, &cmd_rc);
2496
2497         if (rc < 0 || cmd_rc) {
2498                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2499                                 __func__, __LINE__, rc, cmd_rc);
2500                 return -EIO;
2501         }
2502
2503
2504         /* test ars_status with 'status' trimmed from 'out_length' */
2505         cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record);
2506         cmds.ars_stat = (struct nd_cmd_ars_status) {
2507                 .out_length = cmd_size - 4,
2508         };
2509         record = &cmds.ars_stat.records[0];
2510         *record = (struct nd_ars_record) {
2511                 .length = test_val,
2512         };
2513         rc = setup_result(cmds.buf, cmd_size);
2514         if (rc)
2515                 return rc;
2516         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2517                         cmds.buf, cmd_size, &cmd_rc);
2518
2519         if (rc < 0 || cmd_rc || record->length != test_val) {
2520                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2521                                 __func__, __LINE__, rc, cmd_rc);
2522                 return -EIO;
2523         }
2524
2525
2526         /* test ars_status with 'Output (Size)' including 'status' */
2527         cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record);
2528         cmds.ars_stat = (struct nd_cmd_ars_status) {
2529                 .out_length = cmd_size,
2530         };
2531         record = &cmds.ars_stat.records[0];
2532         *record = (struct nd_ars_record) {
2533                 .length = test_val,
2534         };
2535         rc = setup_result(cmds.buf, cmd_size);
2536         if (rc)
2537                 return rc;
2538         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2539                         cmds.buf, cmd_size, &cmd_rc);
2540
2541         if (rc < 0 || cmd_rc || record->length != test_val) {
2542                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2543                                 __func__, __LINE__, rc, cmd_rc);
2544                 return -EIO;
2545         }
2546
2547
2548         /* test extended status for get_config_size results in failure */
2549         cmd_size = sizeof(cmds.cfg_size);
2550         cmds.cfg_size = (struct nd_cmd_get_config_size) {
2551                 .status = 1 << 16,
2552         };
2553         rc = setup_result(cmds.buf, cmd_size);
2554         if (rc)
2555                 return rc;
2556         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2557                         cmds.buf, cmd_size, &cmd_rc);
2558
2559         if (rc < 0 || cmd_rc >= 0) {
2560                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2561                                 __func__, __LINE__, rc, cmd_rc);
2562                 return -EIO;
2563         }
2564
2565         /* test clear error */
2566         cmd_size = sizeof(cmds.clear_err);
2567         cmds.clear_err = (struct nd_cmd_clear_error) {
2568                 .length = 512,
2569                 .cleared = 512,
2570         };
2571         rc = setup_result(cmds.buf, cmd_size);
2572         if (rc)
2573                 return rc;
2574         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR,
2575                         cmds.buf, cmd_size, &cmd_rc);
2576         if (rc < 0 || cmd_rc) {
2577                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2578                                 __func__, __LINE__, rc, cmd_rc);
2579                 return -EIO;
2580         }
2581
2582         return 0;
2583 }
2584
2585 static int nfit_test_probe(struct platform_device *pdev)
2586 {
2587         struct nvdimm_bus_descriptor *nd_desc;
2588         struct acpi_nfit_desc *acpi_desc;
2589         struct device *dev = &pdev->dev;
2590         struct nfit_test *nfit_test;
2591         struct nfit_mem *nfit_mem;
2592         union acpi_object *obj;
2593         int rc;
2594
2595         if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) {
2596                 rc = nfit_ctl_test(&pdev->dev);
2597                 if (rc)
2598                         return rc;
2599         }
2600
2601         nfit_test = to_nfit_test(&pdev->dev);
2602
2603         /* common alloc */
2604         if (nfit_test->num_dcr) {
2605                 int num = nfit_test->num_dcr;
2606
2607                 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *),
2608                                 GFP_KERNEL);
2609                 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
2610                                 GFP_KERNEL);
2611                 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *),
2612                                 GFP_KERNEL);
2613                 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
2614                                 GFP_KERNEL);
2615                 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *),
2616                                 GFP_KERNEL);
2617                 nfit_test->label_dma = devm_kcalloc(dev, num,
2618                                 sizeof(dma_addr_t), GFP_KERNEL);
2619                 nfit_test->dcr = devm_kcalloc(dev, num,
2620                                 sizeof(struct nfit_test_dcr *), GFP_KERNEL);
2621                 nfit_test->dcr_dma = devm_kcalloc(dev, num,
2622                                 sizeof(dma_addr_t), GFP_KERNEL);
2623                 nfit_test->smart = devm_kcalloc(dev, num,
2624                                 sizeof(struct nd_intel_smart), GFP_KERNEL);
2625                 nfit_test->smart_threshold = devm_kcalloc(dev, num,
2626                                 sizeof(struct nd_intel_smart_threshold),
2627                                 GFP_KERNEL);
2628                 nfit_test->fw = devm_kcalloc(dev, num,
2629                                 sizeof(struct nfit_test_fw), GFP_KERNEL);
2630                 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label
2631                                 && nfit_test->label_dma && nfit_test->dcr
2632                                 && nfit_test->dcr_dma && nfit_test->flush
2633                                 && nfit_test->flush_dma
2634                                 && nfit_test->fw)
2635                         /* pass */;
2636                 else
2637                         return -ENOMEM;
2638         }
2639
2640         if (nfit_test->num_pm) {
2641                 int num = nfit_test->num_pm;
2642
2643                 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *),
2644                                 GFP_KERNEL);
2645                 nfit_test->spa_set_dma = devm_kcalloc(dev, num,
2646                                 sizeof(dma_addr_t), GFP_KERNEL);
2647                 if (nfit_test->spa_set && nfit_test->spa_set_dma)
2648                         /* pass */;
2649                 else
2650                         return -ENOMEM;
2651         }
2652
2653         /* per-nfit specific alloc */
2654         if (nfit_test->alloc(nfit_test))
2655                 return -ENOMEM;
2656
2657         nfit_test->setup(nfit_test);
2658         acpi_desc = &nfit_test->acpi_desc;
2659         acpi_nfit_desc_init(acpi_desc, &pdev->dev);
2660         acpi_desc->blk_do_io = nfit_test_blk_do_io;
2661         nd_desc = &acpi_desc->nd_desc;
2662         nd_desc->provider_name = NULL;
2663         nd_desc->module = THIS_MODULE;
2664         nd_desc->ndctl = nfit_test_ctl;
2665
2666         rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf,
2667                         nfit_test->nfit_filled);
2668         if (rc)
2669                 return rc;
2670
2671         rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc);
2672         if (rc)
2673                 return rc;
2674
2675         if (nfit_test->setup != nfit_test0_setup)
2676                 return 0;
2677
2678         nfit_test->setup_hotplug = 1;
2679         nfit_test->setup(nfit_test);
2680
2681         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
2682         if (!obj)
2683                 return -ENOMEM;
2684         obj->type = ACPI_TYPE_BUFFER;
2685         obj->buffer.length = nfit_test->nfit_size;
2686         obj->buffer.pointer = nfit_test->nfit_buf;
2687         *(nfit_test->_fit) = obj;
2688         __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80);
2689
2690         /* associate dimm devices with nfit_mem data for notification testing */
2691         mutex_lock(&acpi_desc->init_mutex);
2692         list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) {
2693                 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle;
2694                 int i;
2695
2696                 for (i = 0; i < ARRAY_SIZE(handle); i++)
2697                         if (nfit_handle == handle[i])
2698                                 dev_set_drvdata(nfit_test->dimm_dev[i],
2699                                                 nfit_mem);
2700         }
2701         mutex_unlock(&acpi_desc->init_mutex);
2702
2703         return 0;
2704 }
2705
2706 static int nfit_test_remove(struct platform_device *pdev)
2707 {
2708         return 0;
2709 }
2710
2711 static void nfit_test_release(struct device *dev)
2712 {
2713         struct nfit_test *nfit_test = to_nfit_test(dev);
2714
2715         kfree(nfit_test);
2716 }
2717
2718 static const struct platform_device_id nfit_test_id[] = {
2719         { KBUILD_MODNAME },
2720         { },
2721 };
2722
2723 static struct platform_driver nfit_test_driver = {
2724         .probe = nfit_test_probe,
2725         .remove = nfit_test_remove,
2726         .driver = {
2727                 .name = KBUILD_MODNAME,
2728         },
2729         .id_table = nfit_test_id,
2730 };
2731
2732 static char mcsafe_buf[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE)));
2733
2734 enum INJECT {
2735         INJECT_NONE,
2736         INJECT_SRC,
2737         INJECT_DST,
2738 };
2739
2740 static void mcsafe_test_init(char *dst, char *src, size_t size)
2741 {
2742         size_t i;
2743
2744         memset(dst, 0xff, size);
2745         for (i = 0; i < size; i++)
2746                 src[i] = (char) i;
2747 }
2748
2749 static bool mcsafe_test_validate(unsigned char *dst, unsigned char *src,
2750                 size_t size, unsigned long rem)
2751 {
2752         size_t i;
2753
2754         for (i = 0; i < size - rem; i++)
2755                 if (dst[i] != (unsigned char) i) {
2756                         pr_info_once("%s:%d: offset: %zd got: %#x expect: %#x\n",
2757                                         __func__, __LINE__, i, dst[i],
2758                                         (unsigned char) i);
2759                         return false;
2760                 }
2761         for (i = size - rem; i < size; i++)
2762                 if (dst[i] != 0xffU) {
2763                         pr_info_once("%s:%d: offset: %zd got: %#x expect: 0xff\n",
2764                                         __func__, __LINE__, i, dst[i]);
2765                         return false;
2766                 }
2767         return true;
2768 }
2769
2770 void mcsafe_test(void)
2771 {
2772         char *inject_desc[] = { "none", "source", "destination" };
2773         enum INJECT inj;
2774
2775         if (IS_ENABLED(CONFIG_MCSAFE_TEST)) {
2776                 pr_info("%s: run...\n", __func__);
2777         } else {
2778                 pr_info("%s: disabled, skip.\n", __func__);
2779                 return;
2780         }
2781
2782         for (inj = INJECT_NONE; inj <= INJECT_DST; inj++) {
2783                 int i;
2784
2785                 pr_info("%s: inject: %s\n", __func__, inject_desc[inj]);
2786                 for (i = 0; i < 512; i++) {
2787                         unsigned long expect, rem;
2788                         void *src, *dst;
2789                         bool valid;
2790
2791                         switch (inj) {
2792                         case INJECT_NONE:
2793                                 mcsafe_inject_src(NULL);
2794                                 mcsafe_inject_dst(NULL);
2795                                 dst = &mcsafe_buf[2048];
2796                                 src = &mcsafe_buf[1024 - i];
2797                                 expect = 0;
2798                                 break;
2799                         case INJECT_SRC:
2800                                 mcsafe_inject_src(&mcsafe_buf[1024]);
2801                                 mcsafe_inject_dst(NULL);
2802                                 dst = &mcsafe_buf[2048];
2803                                 src = &mcsafe_buf[1024 - i];
2804                                 expect = 512 - i;
2805                                 break;
2806                         case INJECT_DST:
2807                                 mcsafe_inject_src(NULL);
2808                                 mcsafe_inject_dst(&mcsafe_buf[2048]);
2809                                 dst = &mcsafe_buf[2048 - i];
2810                                 src = &mcsafe_buf[1024];
2811                                 expect = 512 - i;
2812                                 break;
2813                         }
2814
2815                         mcsafe_test_init(dst, src, 512);
2816                         rem = __memcpy_mcsafe(dst, src, 512);
2817                         valid = mcsafe_test_validate(dst, src, 512, expect);
2818                         if (rem == expect && valid)
2819                                 continue;
2820                         pr_info("%s: copy(%#lx, %#lx, %d) off: %d rem: %ld %s expect: %ld\n",
2821                                         __func__,
2822                                         ((unsigned long) dst) & ~PAGE_MASK,
2823                                         ((unsigned long ) src) & ~PAGE_MASK,
2824                                         512, i, rem, valid ? "valid" : "bad",
2825                                         expect);
2826                 }
2827         }
2828
2829         mcsafe_inject_src(NULL);
2830         mcsafe_inject_dst(NULL);
2831 }
2832
2833 static __init int nfit_test_init(void)
2834 {
2835         int rc, i;
2836
2837         pmem_test();
2838         libnvdimm_test();
2839         acpi_nfit_test();
2840         device_dax_test();
2841         mcsafe_test();
2842
2843         nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm);
2844
2845         nfit_wq = create_singlethread_workqueue("nfit");
2846         if (!nfit_wq)
2847                 return -ENOMEM;
2848
2849         nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm");
2850         if (IS_ERR(nfit_test_dimm)) {
2851                 rc = PTR_ERR(nfit_test_dimm);
2852                 goto err_register;
2853         }
2854
2855         nfit_pool = gen_pool_create(ilog2(SZ_4M), NUMA_NO_NODE);
2856         if (!nfit_pool) {
2857                 rc = -ENOMEM;
2858                 goto err_register;
2859         }
2860
2861         if (gen_pool_add(nfit_pool, SZ_4G, SZ_4G, NUMA_NO_NODE)) {
2862                 rc = -ENOMEM;
2863                 goto err_register;
2864         }
2865
2866         for (i = 0; i < NUM_NFITS; i++) {
2867                 struct nfit_test *nfit_test;
2868                 struct platform_device *pdev;
2869
2870                 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL);
2871                 if (!nfit_test) {
2872                         rc = -ENOMEM;
2873                         goto err_register;
2874                 }
2875                 INIT_LIST_HEAD(&nfit_test->resources);
2876                 badrange_init(&nfit_test->badrange);
2877                 switch (i) {
2878                 case 0:
2879                         nfit_test->num_pm = NUM_PM;
2880                         nfit_test->dcr_idx = 0;
2881                         nfit_test->num_dcr = NUM_DCR;
2882                         nfit_test->alloc = nfit_test0_alloc;
2883                         nfit_test->setup = nfit_test0_setup;
2884                         break;
2885                 case 1:
2886                         nfit_test->num_pm = 2;
2887                         nfit_test->dcr_idx = NUM_DCR;
2888                         nfit_test->num_dcr = 2;
2889                         nfit_test->alloc = nfit_test1_alloc;
2890                         nfit_test->setup = nfit_test1_setup;
2891                         break;
2892                 default:
2893                         rc = -EINVAL;
2894                         goto err_register;
2895                 }
2896                 pdev = &nfit_test->pdev;
2897                 pdev->name = KBUILD_MODNAME;
2898                 pdev->id = i;
2899                 pdev->dev.release = nfit_test_release;
2900                 rc = platform_device_register(pdev);
2901                 if (rc) {
2902                         put_device(&pdev->dev);
2903                         goto err_register;
2904                 }
2905                 get_device(&pdev->dev);
2906
2907                 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2908                 if (rc)
2909                         goto err_register;
2910
2911                 instances[i] = nfit_test;
2912                 INIT_WORK(&nfit_test->work, uc_error_notify);
2913         }
2914
2915         rc = platform_driver_register(&nfit_test_driver);
2916         if (rc)
2917                 goto err_register;
2918         return 0;
2919
2920  err_register:
2921         if (nfit_pool)
2922                 gen_pool_destroy(nfit_pool);
2923
2924         destroy_workqueue(nfit_wq);
2925         for (i = 0; i < NUM_NFITS; i++)
2926                 if (instances[i])
2927                         platform_device_unregister(&instances[i]->pdev);
2928         nfit_test_teardown();
2929         for (i = 0; i < NUM_NFITS; i++)
2930                 if (instances[i])
2931                         put_device(&instances[i]->pdev.dev);
2932
2933         return rc;
2934 }
2935
2936 static __exit void nfit_test_exit(void)
2937 {
2938         int i;
2939
2940         flush_workqueue(nfit_wq);
2941         destroy_workqueue(nfit_wq);
2942         for (i = 0; i < NUM_NFITS; i++)
2943                 platform_device_unregister(&instances[i]->pdev);
2944         platform_driver_unregister(&nfit_test_driver);
2945         nfit_test_teardown();
2946
2947         gen_pool_destroy(nfit_pool);
2948
2949         for (i = 0; i < NUM_NFITS; i++)
2950                 put_device(&instances[i]->pdev.dev);
2951         class_destroy(nfit_test_dimm);
2952 }
2953
2954 module_init(nfit_test_init);
2955 module_exit(nfit_test_exit);
2956 MODULE_LICENSE("GPL v2");
2957 MODULE_AUTHOR("Intel Corporation");