virt/kvm/arm/hyp/vgic-v2-sr.c

   1 /*
   2  * Copyright (C) 2012-2015 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/compiler.h>
  19 #include <linux/irqchip/arm-gic.h>
  20 #include <linux/kvm_host.h>
  21
  22 #include <asm/kvm_emulate.h>
  23 #include <asm/kvm_hyp.h>
  24
  25 static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu,
  26                                             void __iomem *base)
  27 {
  28         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
  29         int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
  30         u32 eisr0, eisr1;
  31         int i;
  32         bool expect_mi;
  33
  34         expect_mi = !!(cpu_if->vgic_hcr & GICH_HCR_UIE);
  35
  36         for (i = 0; i < nr_lr; i++) {
  37                 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
  38                                 continue;
  39
  40                 expect_mi |= (!(cpu_if->vgic_lr[i] & GICH_LR_HW) &&
  41                               (cpu_if->vgic_lr[i] & GICH_LR_EOI));
  42         }
  43
  44         if (expect_mi) {
  45                 cpu_if->vgic_misr = readl_relaxed(base + GICH_MISR);
  46
  47                 if (cpu_if->vgic_misr & GICH_MISR_EOI) {
  48                         eisr0  = readl_relaxed(base + GICH_EISR0);
  49                         if (unlikely(nr_lr > 32))
  50                                 eisr1  = readl_relaxed(base + GICH_EISR1);
  51                         else
  52                                 eisr1 = 0;
  53                 } else {
  54                         eisr0 = eisr1 = 0;
  55                 }
  56         } else {
  57                 cpu_if->vgic_misr = 0;
  58                 eisr0 = eisr1 = 0;
  59         }
  60
  61 #ifdef CONFIG_CPU_BIG_ENDIAN
  62         cpu_if->vgic_eisr = ((u64)eisr0 << 32) | eisr1;
  63 #else
  64         cpu_if->vgic_eisr = ((u64)eisr1 << 32) | eisr0;
  65 #endif
  66 }
  67
  68 static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base)
  69 {
  70         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
  71         int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
  72         u32 elrsr0, elrsr1;
  73
  74         elrsr0 = readl_relaxed(base + GICH_ELRSR0);
  75         if (unlikely(nr_lr > 32))
  76                 elrsr1 = readl_relaxed(base + GICH_ELRSR1);
  77         else
  78                 elrsr1 = 0;
  79
  80         cpu_if->vgic_elrsr = ((u64)elrsr1 << 32) | elrsr0;
  81 }
  82
  83 static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
  84 {
  85         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
  86         int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
  87         int i;
  88
  89         for (i = 0; i < nr_lr; i++) {
  90                 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
  91                         continue;
  92
  93                 if (cpu_if->vgic_elrsr & (1UL << i))
  94                         cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
  95                 else
  96                         cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
  97
  98                 writel_relaxed(0, base + GICH_LR0 + (i * 4));
  99         }
 100 }
 101
 102 /* vcpu is already in the HYP VA space */
 103 void __hyp_text __vgic_v2_save_state(struct kvm_vcpu *vcpu)
 104 {
 105         struct kvm *kvm = kern_hyp_va(vcpu->kvm);
 106         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 107         struct vgic_dist *vgic = &kvm->arch.vgic;
 108         void __iomem *base = kern_hyp_va(vgic->vctrl_base);
 109
 110         if (!base)
 111                 return;
 112
 113         cpu_if->vgic_vmcr = readl_relaxed(base + GICH_VMCR);
 114
 115         if (vcpu->arch.vgic_cpu.live_lrs) {
 116                 cpu_if->vgic_apr = readl_relaxed(base + GICH_APR);
 117
 118                 save_maint_int_state(vcpu, base);
 119                 save_elrsr(vcpu, base);
 120                 save_lrs(vcpu, base);
 121
 122                 writel_relaxed(0, base + GICH_HCR);
 123
 124                 vcpu->arch.vgic_cpu.live_lrs = 0;
 125         } else {
 126                 cpu_if->vgic_eisr = 0;
 127                 cpu_if->vgic_elrsr = ~0UL;
 128                 cpu_if->vgic_misr = 0;
 129                 cpu_if->vgic_apr = 0;
 130         }
 131 }
 132
 133 /* vcpu is already in the HYP VA space */
 134 void __hyp_text __vgic_v2_restore_state(struct kvm_vcpu *vcpu)
 135 {
 136         struct kvm *kvm = kern_hyp_va(vcpu->kvm);
 137         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 138         struct vgic_dist *vgic = &kvm->arch.vgic;
 139         void __iomem *base = kern_hyp_va(vgic->vctrl_base);
 140         int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
 141         int i;
 142         u64 live_lrs = 0;
 143
 144         if (!base)
 145                 return;
 146
 147
 148         for (i = 0; i < nr_lr; i++)
 149                 if (cpu_if->vgic_lr[i] & GICH_LR_STATE)
 150                         live_lrs |= 1UL << i;
 151
 152         if (live_lrs) {
 153                 writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
 154                 writel_relaxed(cpu_if->vgic_apr, base + GICH_APR);
 155                 for (i = 0; i < nr_lr; i++) {
 156                         if (!(live_lrs & (1UL << i)))
 157                                 continue;
 158
 159                         writel_relaxed(cpu_if->vgic_lr[i],
 160                                        base + GICH_LR0 + (i * 4));
 161                 }
 162         }
 163
 164         writel_relaxed(cpu_if->vgic_vmcr, base + GICH_VMCR);
 165         vcpu->arch.vgic_cpu.live_lrs = live_lrs;
 166 }
 167
 168 #ifdef CONFIG_ARM64
 169 /*
 170  * __vgic_v2_perform_cpuif_access -- perform a GICV access on behalf of the
 171  *                                   guest.
 172  *
 173  * @vcpu: the offending vcpu
 174  *
 175  * Returns:
 176  *  1: GICV access successfully performed
 177  *  0: Not a GICV access
 178  * -1: Illegal GICV access
 179  */
 180 int __hyp_text __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu)
 181 {
 182         struct kvm *kvm = kern_hyp_va(vcpu->kvm);
 183         struct vgic_dist *vgic = &kvm->arch.vgic;
 184         phys_addr_t fault_ipa;
 185         void __iomem *addr;
 186         int rd;
 187
 188         /* Build the full address */
 189         fault_ipa  = kvm_vcpu_get_fault_ipa(vcpu);
 190         fault_ipa |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
 191
 192         /* If not for GICV, move on */
 193         if (fault_ipa <  vgic->vgic_cpu_base ||
 194             fault_ipa >= (vgic->vgic_cpu_base + KVM_VGIC_V2_CPU_SIZE))
 195                 return 0;
 196
 197         /* Reject anything but a 32bit access */
 198         if (kvm_vcpu_dabt_get_as(vcpu) != sizeof(u32))
 199                 return -1;
 200
 201         /* Not aligned? Don't bother */
 202         if (fault_ipa & 3)
 203                 return -1;
 204
 205         rd = kvm_vcpu_dabt_get_rd(vcpu);
 206         addr  = kern_hyp_va(hyp_symbol_addr(kvm_vgic_global_state)->vcpu_base_va);
 207         addr += fault_ipa - vgic->vgic_cpu_base;
 208
 209         if (kvm_vcpu_dabt_iswrite(vcpu)) {
 210                 u32 data = vcpu_data_guest_to_host(vcpu,
 211                                                    vcpu_get_reg(vcpu, rd),
 212                                                    sizeof(u32));
 213                 writel_relaxed(data, addr);
 214         } else {
 215                 u32 data = readl_relaxed(addr);
 216                 vcpu_set_reg(vcpu, rd, vcpu_data_host_to_guest(vcpu, data,
 217                                                                sizeof(u32)));
 218         }
 219
 220         return 1;
 221 }
 222 #endif