virt/kvm/arm/hyp/vgic-v2-sr.c

   1 /*
   2  * Copyright (C) 2012-2015 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/compiler.h>
  19 #include <linux/irqchip/arm-gic.h>
  20 #include <linux/kvm_host.h>
  21
  22 #include <asm/kvm_emulate.h>
  23 #include <asm/kvm_hyp.h>
  24
  25 static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu,
  26                                             void __iomem *base)
  27 {
  28         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
  29         int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
  30         u32 eisr0, eisr1;
  31         int i;
  32         bool expect_mi;
  33
  34         expect_mi = !!(cpu_if->vgic_hcr & GICH_HCR_UIE);
  35
  36         for (i = 0; i < nr_lr; i++) {
  37                 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
  38                                 continue;
  39
  40                 expect_mi |= (!(cpu_if->vgic_lr[i] & GICH_LR_HW) &&
  41                               (cpu_if->vgic_lr[i] & GICH_LR_EOI));
  42         }
  43
  44         if (expect_mi) {
  45                 cpu_if->vgic_misr = readl_relaxed(base + GICH_MISR);
  46
  47                 if (cpu_if->vgic_misr & GICH_MISR_EOI) {
  48                         eisr0  = readl_relaxed(base + GICH_EISR0);
  49                         if (unlikely(nr_lr > 32))
  50                                 eisr1  = readl_relaxed(base + GICH_EISR1);
  51                         else
  52                                 eisr1 = 0;
  53                 } else {
  54                         eisr0 = eisr1 = 0;
  55                 }
  56         } else {
  57                 cpu_if->vgic_misr = 0;
  58                 eisr0 = eisr1 = 0;
  59         }
  60
  61 #ifdef CONFIG_CPU_BIG_ENDIAN
  62         cpu_if->vgic_eisr = ((u64)eisr0 << 32) | eisr1;
  63 #else
  64         cpu_if->vgic_eisr = ((u64)eisr1 << 32) | eisr0;
  65 #endif
  66 }
  67
  68 static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base)
  69 {
  70         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
  71         int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
  72         u32 elrsr0, elrsr1;
  73
  74         elrsr0 = readl_relaxed(base + GICH_ELRSR0);
  75         if (unlikely(nr_lr > 32))
  76                 elrsr1 = readl_relaxed(base + GICH_ELRSR1);
  77         else
  78                 elrsr1 = 0;
  79
  80 #ifdef CONFIG_CPU_BIG_ENDIAN
  81         cpu_if->vgic_elrsr = ((u64)elrsr0 << 32) | elrsr1;
  82 #else
  83         cpu_if->vgic_elrsr = ((u64)elrsr1 << 32) | elrsr0;
  84 #endif
  85 }
  86
  87 static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
  88 {
  89         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
  90         int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
  91         int i;
  92
  93         for (i = 0; i < nr_lr; i++) {
  94                 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
  95                         continue;
  96
  97                 if (cpu_if->vgic_elrsr & (1UL << i))
  98                         cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
  99                 else
 100                         cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
 101
 102                 writel_relaxed(0, base + GICH_LR0 + (i * 4));
 103         }
 104 }
 105
 106 /* vcpu is already in the HYP VA space */
 107 void __hyp_text __vgic_v2_save_state(struct kvm_vcpu *vcpu)
 108 {
 109         struct kvm *kvm = kern_hyp_va(vcpu->kvm);
 110         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 111         struct vgic_dist *vgic = &kvm->arch.vgic;
 112         void __iomem *base = kern_hyp_va(vgic->vctrl_base);
 113
 114         if (!base)
 115                 return;
 116
 117         cpu_if->vgic_vmcr = readl_relaxed(base + GICH_VMCR);
 118
 119         if (vcpu->arch.vgic_cpu.live_lrs) {
 120                 cpu_if->vgic_apr = readl_relaxed(base + GICH_APR);
 121
 122                 save_maint_int_state(vcpu, base);
 123                 save_elrsr(vcpu, base);
 124                 save_lrs(vcpu, base);
 125
 126                 writel_relaxed(0, base + GICH_HCR);
 127
 128                 vcpu->arch.vgic_cpu.live_lrs = 0;
 129         } else {
 130                 cpu_if->vgic_eisr = 0;
 131                 cpu_if->vgic_elrsr = ~0UL;
 132                 cpu_if->vgic_misr = 0;
 133                 cpu_if->vgic_apr = 0;
 134         }
 135 }
 136
 137 /* vcpu is already in the HYP VA space */
 138 void __hyp_text __vgic_v2_restore_state(struct kvm_vcpu *vcpu)
 139 {
 140         struct kvm *kvm = kern_hyp_va(vcpu->kvm);
 141         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 142         struct vgic_dist *vgic = &kvm->arch.vgic;
 143         void __iomem *base = kern_hyp_va(vgic->vctrl_base);
 144         int nr_lr = (kern_hyp_va(&kvm_vgic_global_state))->nr_lr;
 145         int i;
 146         u64 live_lrs = 0;
 147
 148         if (!base)
 149                 return;
 150
 151
 152         for (i = 0; i < nr_lr; i++)
 153                 if (cpu_if->vgic_lr[i] & GICH_LR_STATE)
 154                         live_lrs |= 1UL << i;
 155
 156         if (live_lrs) {
 157                 writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
 158                 writel_relaxed(cpu_if->vgic_apr, base + GICH_APR);
 159                 for (i = 0; i < nr_lr; i++) {
 160                         if (!(live_lrs & (1UL << i)))
 161                                 continue;
 162
 163                         writel_relaxed(cpu_if->vgic_lr[i],
 164                                        base + GICH_LR0 + (i * 4));
 165                 }
 166         }
 167
 168         writel_relaxed(cpu_if->vgic_vmcr, base + GICH_VMCR);
 169         vcpu->arch.vgic_cpu.live_lrs = live_lrs;
 170 }
 171
 172 #ifdef CONFIG_ARM64
 173 /*
 174  * __vgic_v2_perform_cpuif_access -- perform a GICV access on behalf of the
 175  *                                   guest.
 176  *
 177  * @vcpu: the offending vcpu
 178  *
 179  * Returns:
 180  *  1: GICV access successfully performed
 181  *  0: Not a GICV access
 182  * -1: Illegal GICV access
 183  */
 184 int __hyp_text __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu)
 185 {
 186         struct kvm *kvm = kern_hyp_va(vcpu->kvm);
 187         struct vgic_dist *vgic = &kvm->arch.vgic;
 188         phys_addr_t fault_ipa;
 189         void __iomem *addr;
 190         int rd;
 191
 192         /* Build the full address */
 193         fault_ipa  = kvm_vcpu_get_fault_ipa(vcpu);
 194         fault_ipa |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
 195
 196         /* If not for GICV, move on */
 197         if (fault_ipa <  vgic->vgic_cpu_base ||
 198             fault_ipa >= (vgic->vgic_cpu_base + KVM_VGIC_V2_CPU_SIZE))
 199                 return 0;
 200
 201         /* Reject anything but a 32bit access */
 202         if (kvm_vcpu_dabt_get_as(vcpu) != sizeof(u32))
 203                 return -1;
 204
 205         /* Not aligned? Don't bother */
 206         if (fault_ipa & 3)
 207                 return -1;
 208
 209         rd = kvm_vcpu_dabt_get_rd(vcpu);
 210         addr  = kern_hyp_va((kern_hyp_va(&kvm_vgic_global_state))->vcpu_base_va);
 211         addr += fault_ipa - vgic->vgic_cpu_base;
 212
 213         if (kvm_vcpu_dabt_iswrite(vcpu)) {
 214                 u32 data = vcpu_data_guest_to_host(vcpu,
 215                                                    vcpu_get_reg(vcpu, rd),
 216                                                    sizeof(u32));
 217                 writel_relaxed(data, addr);
 218         } else {
 219                 u32 data = readl_relaxed(addr);
 220                 vcpu_set_reg(vcpu, rd, vcpu_data_host_to_guest(vcpu, data,
 221                                                                sizeof(u32)));
 222         }
 223
 224         return 1;
 225 }
 226 #endif