virt/kvm/arm/hyp/vgic-v3-sr.c

   1 /*
   2  * Copyright (C) 2012-2015 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/compiler.h>
  19 #include <linux/irqchip/arm-gic-v3.h>
  20 #include <linux/kvm_host.h>
  21
  22 #include <asm/kvm_emulate.h>
  23 #include <asm/kvm_hyp.h>
  24
  25 #define vtr_to_max_lr_idx(v)            ((v) & 0xf)
  26 #define vtr_to_nr_pre_bits(v)           ((((u32)(v) >> 26) & 7) + 1)
  27 #define vtr_to_nr_apr_regs(v)           (1 << (vtr_to_nr_pre_bits(v) - 5))
  28
  29 static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
  30 {
  31         switch (lr & 0xf) {
  32         case 0:
  33                 return read_gicreg(ICH_LR0_EL2);
  34         case 1:
  35                 return read_gicreg(ICH_LR1_EL2);
  36         case 2:
  37                 return read_gicreg(ICH_LR2_EL2);
  38         case 3:
  39                 return read_gicreg(ICH_LR3_EL2);
  40         case 4:
  41                 return read_gicreg(ICH_LR4_EL2);
  42         case 5:
  43                 return read_gicreg(ICH_LR5_EL2);
  44         case 6:
  45                 return read_gicreg(ICH_LR6_EL2);
  46         case 7:
  47                 return read_gicreg(ICH_LR7_EL2);
  48         case 8:
  49                 return read_gicreg(ICH_LR8_EL2);
  50         case 9:
  51                 return read_gicreg(ICH_LR9_EL2);
  52         case 10:
  53                 return read_gicreg(ICH_LR10_EL2);
  54         case 11:
  55                 return read_gicreg(ICH_LR11_EL2);
  56         case 12:
  57                 return read_gicreg(ICH_LR12_EL2);
  58         case 13:
  59                 return read_gicreg(ICH_LR13_EL2);
  60         case 14:
  61                 return read_gicreg(ICH_LR14_EL2);
  62         case 15:
  63                 return read_gicreg(ICH_LR15_EL2);
  64         }
  65
  66         unreachable();
  67 }
  68
  69 static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
  70 {
  71         switch (lr & 0xf) {
  72         case 0:
  73                 write_gicreg(val, ICH_LR0_EL2);
  74                 break;
  75         case 1:
  76                 write_gicreg(val, ICH_LR1_EL2);
  77                 break;
  78         case 2:
  79                 write_gicreg(val, ICH_LR2_EL2);
  80                 break;
  81         case 3:
  82                 write_gicreg(val, ICH_LR3_EL2);
  83                 break;
  84         case 4:
  85                 write_gicreg(val, ICH_LR4_EL2);
  86                 break;
  87         case 5:
  88                 write_gicreg(val, ICH_LR5_EL2);
  89                 break;
  90         case 6:
  91                 write_gicreg(val, ICH_LR6_EL2);
  92                 break;
  93         case 7:
  94                 write_gicreg(val, ICH_LR7_EL2);
  95                 break;
  96         case 8:
  97                 write_gicreg(val, ICH_LR8_EL2);
  98                 break;
  99         case 9:
 100                 write_gicreg(val, ICH_LR9_EL2);
 101                 break;
 102         case 10:
 103                 write_gicreg(val, ICH_LR10_EL2);
 104                 break;
 105         case 11:
 106                 write_gicreg(val, ICH_LR11_EL2);
 107                 break;
 108         case 12:
 109                 write_gicreg(val, ICH_LR12_EL2);
 110                 break;
 111         case 13:
 112                 write_gicreg(val, ICH_LR13_EL2);
 113                 break;
 114         case 14:
 115                 write_gicreg(val, ICH_LR14_EL2);
 116                 break;
 117         case 15:
 118                 write_gicreg(val, ICH_LR15_EL2);
 119                 break;
 120         }
 121 }
 122
 123 static void __hyp_text __vgic_v3_write_ap0rn(u32 val, int n)
 124 {
 125         switch (n) {
 126         case 0:
 127                 write_gicreg(val, ICH_AP0R0_EL2);
 128                 break;
 129         case 1:
 130                 write_gicreg(val, ICH_AP0R1_EL2);
 131                 break;
 132         case 2:
 133                 write_gicreg(val, ICH_AP0R2_EL2);
 134                 break;
 135         case 3:
 136                 write_gicreg(val, ICH_AP0R3_EL2);
 137                 break;
 138         }
 139 }
 140
 141 static void __hyp_text __vgic_v3_write_ap1rn(u32 val, int n)
 142 {
 143         switch (n) {
 144         case 0:
 145                 write_gicreg(val, ICH_AP1R0_EL2);
 146                 break;
 147         case 1:
 148                 write_gicreg(val, ICH_AP1R1_EL2);
 149                 break;
 150         case 2:
 151                 write_gicreg(val, ICH_AP1R2_EL2);
 152                 break;
 153         case 3:
 154                 write_gicreg(val, ICH_AP1R3_EL2);
 155                 break;
 156         }
 157 }
 158
 159 static u32 __hyp_text __vgic_v3_read_ap0rn(int n)
 160 {
 161         u32 val;
 162
 163         switch (n) {
 164         case 0:
 165                 val = read_gicreg(ICH_AP0R0_EL2);
 166                 break;
 167         case 1:
 168                 val = read_gicreg(ICH_AP0R1_EL2);
 169                 break;
 170         case 2:
 171                 val = read_gicreg(ICH_AP0R2_EL2);
 172                 break;
 173         case 3:
 174                 val = read_gicreg(ICH_AP0R3_EL2);
 175                 break;
 176         default:
 177                 unreachable();
 178         }
 179
 180         return val;
 181 }
 182
 183 static u32 __hyp_text __vgic_v3_read_ap1rn(int n)
 184 {
 185         u32 val;
 186
 187         switch (n) {
 188         case 0:
 189                 val = read_gicreg(ICH_AP1R0_EL2);
 190                 break;
 191         case 1:
 192                 val = read_gicreg(ICH_AP1R1_EL2);
 193                 break;
 194         case 2:
 195                 val = read_gicreg(ICH_AP1R2_EL2);
 196                 break;
 197         case 3:
 198                 val = read_gicreg(ICH_AP1R3_EL2);
 199                 break;
 200         default:
 201                 unreachable();
 202         }
 203
 204         return val;
 205 }
 206
 207 void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
 208 {
 209         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 210         u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 211         u64 val;
 212
 213         /*
 214          * Make sure stores to the GIC via the memory mapped interface
 215          * are now visible to the system register interface.
 216          */
 217         if (!cpu_if->vgic_sre) {
 218                 dsb(sy);
 219                 isb();
 220                 cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);
 221         }
 222
 223         if (used_lrs) {
 224                 int i;
 225                 u32 nr_pre_bits;
 226
 227                 cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
 228
 229                 write_gicreg(0, ICH_HCR_EL2);
 230                 val = read_gicreg(ICH_VTR_EL2);
 231                 nr_pre_bits = vtr_to_nr_pre_bits(val);
 232
 233                 for (i = 0; i < used_lrs; i++) {
 234                         if (cpu_if->vgic_elrsr & (1 << i))
 235                                 cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
 236                         else
 237                                 cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
 238
 239                         __gic_v3_set_lr(0, i);
 240                 }
 241
 242                 switch (nr_pre_bits) {
 243                 case 7:
 244                         cpu_if->vgic_ap0r[3] = __vgic_v3_read_ap0rn(3);
 245                         cpu_if->vgic_ap0r[2] = __vgic_v3_read_ap0rn(2);
 246                 case 6:
 247                         cpu_if->vgic_ap0r[1] = __vgic_v3_read_ap0rn(1);
 248                 default:
 249                         cpu_if->vgic_ap0r[0] = __vgic_v3_read_ap0rn(0);
 250                 }
 251
 252                 switch (nr_pre_bits) {
 253                 case 7:
 254                         cpu_if->vgic_ap1r[3] = __vgic_v3_read_ap1rn(3);
 255                         cpu_if->vgic_ap1r[2] = __vgic_v3_read_ap1rn(2);
 256                 case 6:
 257                         cpu_if->vgic_ap1r[1] = __vgic_v3_read_ap1rn(1);
 258                 default:
 259                         cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0);
 260                 }
 261         } else {
 262                 if (static_branch_unlikely(&vgic_v3_cpuif_trap))
 263                         write_gicreg(0, ICH_HCR_EL2);
 264
 265                 cpu_if->vgic_elrsr = 0xffff;
 266                 cpu_if->vgic_ap0r[0] = 0;
 267                 cpu_if->vgic_ap0r[1] = 0;
 268                 cpu_if->vgic_ap0r[2] = 0;
 269                 cpu_if->vgic_ap0r[3] = 0;
 270                 cpu_if->vgic_ap1r[0] = 0;
 271                 cpu_if->vgic_ap1r[1] = 0;
 272                 cpu_if->vgic_ap1r[2] = 0;
 273                 cpu_if->vgic_ap1r[3] = 0;
 274         }
 275
 276         val = read_gicreg(ICC_SRE_EL2);
 277         write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
 278
 279         if (!cpu_if->vgic_sre) {
 280                 /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
 281                 isb();
 282                 write_gicreg(1, ICC_SRE_EL1);
 283         }
 284 }
 285
 286 void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
 287 {
 288         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 289         u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 290         u64 val;
 291         u32 nr_pre_bits;
 292         int i;
 293
 294         /*
 295          * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
 296          * Group0 interrupt (as generated in GICv2 mode) to be
 297          * delivered as a FIQ to the guest, with potentially fatal
 298          * consequences. So we must make sure that ICC_SRE_EL1 has
 299          * been actually programmed with the value we want before
 300          * starting to mess with the rest of the GIC, and VMCR_EL2 in
 301          * particular.
 302          */
 303         if (!cpu_if->vgic_sre) {
 304                 write_gicreg(0, ICC_SRE_EL1);
 305                 isb();
 306                 write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
 307         }
 308
 309         val = read_gicreg(ICH_VTR_EL2);
 310         nr_pre_bits = vtr_to_nr_pre_bits(val);
 311
 312         if (used_lrs) {
 313                 write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
 314
 315                 switch (nr_pre_bits) {
 316                 case 7:
 317                         __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[3], 3);
 318                         __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[2], 2);
 319                 case 6:
 320                         __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[1], 1);
 321                 default:
 322                         __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[0], 0);
 323                 }
 324
 325                 switch (nr_pre_bits) {
 326                 case 7:
 327                         __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[3], 3);
 328                         __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[2], 2);
 329                 case 6:
 330                         __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[1], 1);
 331                 default:
 332                         __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[0], 0);
 333                 }
 334
 335                 for (i = 0; i < used_lrs; i++)
 336                         __gic_v3_set_lr(cpu_if->vgic_lr[i], i);
 337         } else {
 338                 /*
 339                  * If we need to trap system registers, we must write
 340                  * ICH_HCR_EL2 anyway, even if no interrupts are being
 341                  * injected,
 342                  */
 343                 if (static_branch_unlikely(&vgic_v3_cpuif_trap))
 344                         write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
 345         }
 346
 347         /*
 348          * Ensures that the above will have reached the
 349          * (re)distributors. This ensure the guest will read the
 350          * correct values from the memory-mapped interface.
 351          */
 352         if (!cpu_if->vgic_sre) {
 353                 isb();
 354                 dsb(sy);
 355         }
 356
 357         /*
 358          * Prevent the guest from touching the GIC system registers if
 359          * SRE isn't enabled for GICv3 emulation.
 360          */
 361         write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
 362                      ICC_SRE_EL2);
 363 }
 364
 365 void __hyp_text __vgic_v3_init_lrs(void)
 366 {
 367         int max_lr_idx = vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2));
 368         int i;
 369
 370         for (i = 0; i <= max_lr_idx; i++)
 371                 __gic_v3_set_lr(0, i);
 372 }
 373
 374 u64 __hyp_text __vgic_v3_get_ich_vtr_el2(void)
 375 {
 376         return read_gicreg(ICH_VTR_EL2);
 377 }
 378
 379 u64 __hyp_text __vgic_v3_read_vmcr(void)
 380 {
 381         return read_gicreg(ICH_VMCR_EL2);
 382 }
 383
 384 void __hyp_text __vgic_v3_write_vmcr(u32 vmcr)
 385 {
 386         write_gicreg(vmcr, ICH_VMCR_EL2);
 387 }
 388
 389 #ifdef CONFIG_ARM64
 390
 391 static int __hyp_text __vgic_v3_bpr_min(void)
 392 {
 393         /* See Pseudocode for VPriorityGroup */
 394         return 8 - vtr_to_nr_pre_bits(read_gicreg(ICH_VTR_EL2));
 395 }
 396
 397 static int __hyp_text __vgic_v3_get_group(struct kvm_vcpu *vcpu)
 398 {
 399         u32 esr = kvm_vcpu_get_hsr(vcpu);
 400         u8 crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
 401
 402         return crm != 8;
 403 }
 404
 405 #define GICv3_IDLE_PRIORITY     0xff
 406
 407 static int __hyp_text __vgic_v3_highest_priority_lr(struct kvm_vcpu *vcpu,
 408                                                     u32 vmcr,
 409                                                     u64 *lr_val)
 410 {
 411         unsigned int used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 412         u8 priority = GICv3_IDLE_PRIORITY;
 413         int i, lr = -1;
 414
 415         for (i = 0; i < used_lrs; i++) {
 416                 u64 val = __gic_v3_get_lr(i);
 417                 u8 lr_prio = (val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
 418
 419                 /* Not pending in the state? */
 420                 if ((val & ICH_LR_STATE) != ICH_LR_PENDING_BIT)
 421                         continue;
 422
 423                 /* Group-0 interrupt, but Group-0 disabled? */
 424                 if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK))
 425                         continue;
 426
 427                 /* Group-1 interrupt, but Group-1 disabled? */
 428                 if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK))
 429                         continue;
 430
 431                 /* Not the highest priority? */
 432                 if (lr_prio >= priority)
 433                         continue;
 434
 435                 /* This is a candidate */
 436                 priority = lr_prio;
 437                 *lr_val = val;
 438                 lr = i;
 439         }
 440
 441         if (lr == -1)
 442                 *lr_val = ICC_IAR1_EL1_SPURIOUS;
 443
 444         return lr;
 445 }
 446
 447 static int __hyp_text __vgic_v3_find_active_lr(struct kvm_vcpu *vcpu,
 448                                                int intid, u64 *lr_val)
 449 {
 450         unsigned int used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 451         int i;
 452
 453         for (i = 0; i < used_lrs; i++) {
 454                 u64 val = __gic_v3_get_lr(i);
 455
 456                 if ((val & ICH_LR_VIRTUAL_ID_MASK) == intid &&
 457                     (val & ICH_LR_ACTIVE_BIT)) {
 458                         *lr_val = val;
 459                         return i;
 460                 }
 461         }
 462
 463         *lr_val = ICC_IAR1_EL1_SPURIOUS;
 464         return -1;
 465 }
 466
 467 static int __hyp_text __vgic_v3_get_highest_active_priority(void)
 468 {
 469         u8 nr_apr_regs = vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
 470         u32 hap = 0;
 471         int i;
 472
 473         for (i = 0; i < nr_apr_regs; i++) {
 474                 u32 val;
 475
 476                 /*
 477                  * The ICH_AP0Rn_EL2 and ICH_AP1Rn_EL2 registers
 478                  * contain the active priority levels for this VCPU
 479                  * for the maximum number of supported priority
 480                  * levels, and we return the full priority level only
 481                  * if the BPR is programmed to its minimum, otherwise
 482                  * we return a combination of the priority level and
 483                  * subpriority, as determined by the setting of the
 484                  * BPR, but without the full subpriority.
 485                  */
 486                 val  = __vgic_v3_read_ap0rn(i);
 487                 val |= __vgic_v3_read_ap1rn(i);
 488                 if (!val) {
 489                         hap += 32;
 490                         continue;
 491                 }
 492
 493                 return (hap + __ffs(val)) << __vgic_v3_bpr_min();
 494         }
 495
 496         return GICv3_IDLE_PRIORITY;
 497 }
 498
 499 static unsigned int __hyp_text __vgic_v3_get_bpr0(u32 vmcr)
 500 {
 501         return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 502 }
 503
 504 static unsigned int __hyp_text __vgic_v3_get_bpr1(u32 vmcr)
 505 {
 506         unsigned int bpr;
 507
 508         if (vmcr & ICH_VMCR_CBPR_MASK) {
 509                 bpr = __vgic_v3_get_bpr0(vmcr);
 510                 if (bpr < 7)
 511                         bpr++;
 512         } else {
 513                 bpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 514         }
 515
 516         return bpr;
 517 }
 518
 519 /*
 520  * Convert a priority to a preemption level, taking the relevant BPR
 521  * into account by zeroing the sub-priority bits.
 522  */
 523 static u8 __hyp_text __vgic_v3_pri_to_pre(u8 pri, u32 vmcr, int grp)
 524 {
 525         unsigned int bpr;
 526
 527         if (!grp)
 528                 bpr = __vgic_v3_get_bpr0(vmcr) + 1;
 529         else
 530                 bpr = __vgic_v3_get_bpr1(vmcr);
 531
 532         return pri & (GENMASK(7, 0) << bpr);
 533 }
 534
 535 /*
 536  * The priority value is independent of any of the BPR values, so we
 537  * normalize it using the minumal BPR value. This guarantees that no
 538  * matter what the guest does with its BPR, we can always set/get the
 539  * same value of a priority.
 540  */
 541 static void __hyp_text __vgic_v3_set_active_priority(u8 pri, u32 vmcr, int grp)
 542 {
 543         u8 pre, ap;
 544         u32 val;
 545         int apr;
 546
 547         pre = __vgic_v3_pri_to_pre(pri, vmcr, grp);
 548         ap = pre >> __vgic_v3_bpr_min();
 549         apr = ap / 32;
 550
 551         if (!grp) {
 552                 val = __vgic_v3_read_ap0rn(apr);
 553                 __vgic_v3_write_ap0rn(val | BIT(ap % 32), apr);
 554         } else {
 555                 val = __vgic_v3_read_ap1rn(apr);
 556                 __vgic_v3_write_ap1rn(val | BIT(ap % 32), apr);
 557         }
 558 }
 559
 560 static int __hyp_text __vgic_v3_clear_highest_active_priority(void)
 561 {
 562         u8 nr_apr_regs = vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
 563         u32 hap = 0;
 564         int i;
 565
 566         for (i = 0; i < nr_apr_regs; i++) {
 567                 u32 ap0, ap1;
 568                 int c0, c1;
 569
 570                 ap0 = __vgic_v3_read_ap0rn(i);
 571                 ap1 = __vgic_v3_read_ap1rn(i);
 572                 if (!ap0 && !ap1) {
 573                         hap += 32;
 574                         continue;
 575                 }
 576
 577                 c0 = ap0 ? __ffs(ap0) : 32;
 578                 c1 = ap1 ? __ffs(ap1) : 32;
 579
 580                 /* Always clear the LSB, which is the highest priority */
 581                 if (c0 < c1) {
 582                         ap0 &= ~BIT(c0);
 583                         __vgic_v3_write_ap0rn(ap0, i);
 584                         hap += c0;
 585                 } else {
 586                         ap1 &= ~BIT(c1);
 587                         __vgic_v3_write_ap1rn(ap1, i);
 588                         hap += c1;
 589                 }
 590
 591                 /* Rescale to 8 bits of priority */
 592                 return hap << __vgic_v3_bpr_min();
 593         }
 594
 595         return GICv3_IDLE_PRIORITY;
 596 }
 597
 598 static void __hyp_text __vgic_v3_read_iar(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 599 {
 600         u64 lr_val;
 601         u8 lr_prio, pmr;
 602         int lr, grp;
 603
 604         grp = __vgic_v3_get_group(vcpu);
 605
 606         lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
 607         if (lr < 0)
 608                 goto spurious;
 609
 610         if (grp != !!(lr_val & ICH_LR_GROUP))
 611                 goto spurious;
 612
 613         pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 614         lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
 615         if (pmr <= lr_prio)
 616                 goto spurious;
 617
 618         if (__vgic_v3_get_highest_active_priority() <= __vgic_v3_pri_to_pre(lr_prio, vmcr, grp))
 619                 goto spurious;
 620
 621         lr_val &= ~ICH_LR_STATE;
 622         /* No active state for LPIs */
 623         if ((lr_val & ICH_LR_VIRTUAL_ID_MASK) <= VGIC_MAX_SPI)
 624                 lr_val |= ICH_LR_ACTIVE_BIT;
 625         __gic_v3_set_lr(lr_val, lr);
 626         __vgic_v3_set_active_priority(lr_prio, vmcr, grp);
 627         vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
 628         return;
 629
 630 spurious:
 631         vcpu_set_reg(vcpu, rt, ICC_IAR1_EL1_SPURIOUS);
 632 }
 633
 634 static void __hyp_text __vgic_v3_clear_active_lr(int lr, u64 lr_val)
 635 {
 636         lr_val &= ~ICH_LR_ACTIVE_BIT;
 637         if (lr_val & ICH_LR_HW) {
 638                 u32 pid;
 639
 640                 pid = (lr_val & ICH_LR_PHYS_ID_MASK) >> ICH_LR_PHYS_ID_SHIFT;
 641                 gic_write_dir(pid);
 642         }
 643
 644         __gic_v3_set_lr(lr_val, lr);
 645 }
 646
 647 static void __hyp_text __vgic_v3_bump_eoicount(void)
 648 {
 649         u32 hcr;
 650
 651         hcr = read_gicreg(ICH_HCR_EL2);
 652         hcr += 1 << ICH_HCR_EOIcount_SHIFT;
 653         write_gicreg(hcr, ICH_HCR_EL2);
 654 }
 655
 656 static void __hyp_text __vgic_v3_write_dir(struct kvm_vcpu *vcpu,
 657                                            u32 vmcr, int rt)
 658 {
 659         u32 vid = vcpu_get_reg(vcpu, rt);
 660         u64 lr_val;
 661         int lr;
 662
 663         /* EOImode == 0, nothing to be done here */
 664         if (!(vmcr & ICH_VMCR_EOIM_MASK))
 665                 return;
 666
 667         /* No deactivate to be performed on an LPI */
 668         if (vid >= VGIC_MIN_LPI)
 669                 return;
 670
 671         lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
 672         if (lr == -1) {
 673                 __vgic_v3_bump_eoicount();
 674                 return;
 675         }
 676
 677         __vgic_v3_clear_active_lr(lr, lr_val);
 678 }
 679
 680 static void __hyp_text __vgic_v3_write_eoir(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 681 {
 682         u32 vid = vcpu_get_reg(vcpu, rt);
 683         u64 lr_val;
 684         u8 lr_prio, act_prio;
 685         int lr, grp;
 686
 687         grp = __vgic_v3_get_group(vcpu);
 688
 689         /* Drop priority in any case */
 690         act_prio = __vgic_v3_clear_highest_active_priority();
 691
 692         /* If EOIing an LPI, no deactivate to be performed */
 693         if (vid >= VGIC_MIN_LPI)
 694                 return;
 695
 696         /* EOImode == 1, nothing to be done here */
 697         if (vmcr & ICH_VMCR_EOIM_MASK)
 698                 return;
 699
 700         lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
 701         if (lr == -1) {
 702                 __vgic_v3_bump_eoicount();
 703                 return;
 704         }
 705
 706         lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
 707
 708         /* If priorities or group do not match, the guest has fscked-up. */
 709         if (grp != !!(lr_val & ICH_LR_GROUP) ||
 710             __vgic_v3_pri_to_pre(lr_prio, vmcr, grp) != act_prio)
 711                 return;
 712
 713         /* Let's now perform the deactivation */
 714         __vgic_v3_clear_active_lr(lr, lr_val);
 715 }
 716
 717 static void __hyp_text __vgic_v3_read_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 718 {
 719         vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK));
 720 }
 721
 722 static void __hyp_text __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 723 {
 724         vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
 725 }
 726
 727 static void __hyp_text __vgic_v3_write_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 728 {
 729         u64 val = vcpu_get_reg(vcpu, rt);
 730
 731         if (val & 1)
 732                 vmcr |= ICH_VMCR_ENG0_MASK;
 733         else
 734                 vmcr &= ~ICH_VMCR_ENG0_MASK;
 735
 736         __vgic_v3_write_vmcr(vmcr);
 737 }
 738
 739 static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 740 {
 741         u64 val = vcpu_get_reg(vcpu, rt);
 742
 743         if (val & 1)
 744                 vmcr |= ICH_VMCR_ENG1_MASK;
 745         else
 746                 vmcr &= ~ICH_VMCR_ENG1_MASK;
 747
 748         __vgic_v3_write_vmcr(vmcr);
 749 }
 750
 751 static void __hyp_text __vgic_v3_read_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 752 {
 753         vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr0(vmcr));
 754 }
 755
 756 static void __hyp_text __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 757 {
 758         vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
 759 }
 760
 761 static void __hyp_text __vgic_v3_write_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 762 {
 763         u64 val = vcpu_get_reg(vcpu, rt);
 764         u8 bpr_min = __vgic_v3_bpr_min() - 1;
 765
 766         /* Enforce BPR limiting */
 767         if (val < bpr_min)
 768                 val = bpr_min;
 769
 770         val <<= ICH_VMCR_BPR0_SHIFT;
 771         val &= ICH_VMCR_BPR0_MASK;
 772         vmcr &= ~ICH_VMCR_BPR0_MASK;
 773         vmcr |= val;
 774
 775         __vgic_v3_write_vmcr(vmcr);
 776 }
 777
 778 static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 779 {
 780         u64 val = vcpu_get_reg(vcpu, rt);
 781         u8 bpr_min = __vgic_v3_bpr_min();
 782
 783         if (vmcr & ICH_VMCR_CBPR_MASK)
 784                 return;
 785
 786         /* Enforce BPR limiting */
 787         if (val < bpr_min)
 788                 val = bpr_min;
 789
 790         val <<= ICH_VMCR_BPR1_SHIFT;
 791         val &= ICH_VMCR_BPR1_MASK;
 792         vmcr &= ~ICH_VMCR_BPR1_MASK;
 793         vmcr |= val;
 794
 795         __vgic_v3_write_vmcr(vmcr);
 796 }
 797
 798 static void __hyp_text __vgic_v3_read_apxrn(struct kvm_vcpu *vcpu, int rt, int n)
 799 {
 800         u32 val;
 801
 802         if (!__vgic_v3_get_group(vcpu))
 803                 val = __vgic_v3_read_ap0rn(n);
 804         else
 805                 val = __vgic_v3_read_ap1rn(n);
 806
 807         vcpu_set_reg(vcpu, rt, val);
 808 }
 809
 810 static void __hyp_text __vgic_v3_write_apxrn(struct kvm_vcpu *vcpu, int rt, int n)
 811 {
 812         u32 val = vcpu_get_reg(vcpu, rt);
 813
 814         if (!__vgic_v3_get_group(vcpu))
 815                 __vgic_v3_write_ap0rn(val, n);
 816         else
 817                 __vgic_v3_write_ap1rn(val, n);
 818 }
 819
 820 static void __hyp_text __vgic_v3_read_apxr0(struct kvm_vcpu *vcpu,
 821                                             u32 vmcr, int rt)
 822 {
 823         __vgic_v3_read_apxrn(vcpu, rt, 0);
 824 }
 825
 826 static void __hyp_text __vgic_v3_read_apxr1(struct kvm_vcpu *vcpu,
 827                                             u32 vmcr, int rt)
 828 {
 829         __vgic_v3_read_apxrn(vcpu, rt, 1);
 830 }
 831
 832 static void __hyp_text __vgic_v3_read_apxr2(struct kvm_vcpu *vcpu,
 833                                             u32 vmcr, int rt)
 834 {
 835         __vgic_v3_read_apxrn(vcpu, rt, 2);
 836 }
 837
 838 static void __hyp_text __vgic_v3_read_apxr3(struct kvm_vcpu *vcpu,
 839                                             u32 vmcr, int rt)
 840 {
 841         __vgic_v3_read_apxrn(vcpu, rt, 3);
 842 }
 843
 844 static void __hyp_text __vgic_v3_write_apxr0(struct kvm_vcpu *vcpu,
 845                                              u32 vmcr, int rt)
 846 {
 847         __vgic_v3_write_apxrn(vcpu, rt, 0);
 848 }
 849
 850 static void __hyp_text __vgic_v3_write_apxr1(struct kvm_vcpu *vcpu,
 851                                              u32 vmcr, int rt)
 852 {
 853         __vgic_v3_write_apxrn(vcpu, rt, 1);
 854 }
 855
 856 static void __hyp_text __vgic_v3_write_apxr2(struct kvm_vcpu *vcpu,
 857                                              u32 vmcr, int rt)
 858 {
 859         __vgic_v3_write_apxrn(vcpu, rt, 2);
 860 }
 861
 862 static void __hyp_text __vgic_v3_write_apxr3(struct kvm_vcpu *vcpu,
 863                                              u32 vmcr, int rt)
 864 {
 865         __vgic_v3_write_apxrn(vcpu, rt, 3);
 866 }
 867
 868 static void __hyp_text __vgic_v3_read_hppir(struct kvm_vcpu *vcpu,
 869                                             u32 vmcr, int rt)
 870 {
 871         u64 lr_val;
 872         int lr, lr_grp, grp;
 873
 874         grp = __vgic_v3_get_group(vcpu);
 875
 876         lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
 877         if (lr == -1)
 878                 goto spurious;
 879
 880         lr_grp = !!(lr_val & ICH_LR_GROUP);
 881         if (lr_grp != grp)
 882                 lr_val = ICC_IAR1_EL1_SPURIOUS;
 883
 884 spurious:
 885         vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
 886 }
 887
 888 static void __hyp_text __vgic_v3_read_pmr(struct kvm_vcpu *vcpu,
 889                                           u32 vmcr, int rt)
 890 {
 891         vmcr &= ICH_VMCR_PMR_MASK;
 892         vmcr >>= ICH_VMCR_PMR_SHIFT;
 893         vcpu_set_reg(vcpu, rt, vmcr);
 894 }
 895
 896 static void __hyp_text __vgic_v3_write_pmr(struct kvm_vcpu *vcpu,
 897                                            u32 vmcr, int rt)
 898 {
 899         u32 val = vcpu_get_reg(vcpu, rt);
 900
 901         val <<= ICH_VMCR_PMR_SHIFT;
 902         val &= ICH_VMCR_PMR_MASK;
 903         vmcr &= ~ICH_VMCR_PMR_MASK;
 904         vmcr |= val;
 905
 906         write_gicreg(vmcr, ICH_VMCR_EL2);
 907 }
 908
 909 static void __hyp_text __vgic_v3_read_rpr(struct kvm_vcpu *vcpu,
 910                                           u32 vmcr, int rt)
 911 {
 912         u32 val = __vgic_v3_get_highest_active_priority();
 913         vcpu_set_reg(vcpu, rt, val);
 914 }
 915
 916 static void __hyp_text __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu,
 917                                            u32 vmcr, int rt)
 918 {
 919         u32 vtr, val;
 920
 921         vtr = read_gicreg(ICH_VTR_EL2);
 922         /* PRIbits */
 923         val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
 924         /* IDbits */
 925         val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
 926         /* SEIS */
 927         val |= ((vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT;
 928         /* A3V */
 929         val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
 930         /* EOImode */
 931         val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
 932         /* CBPR */
 933         val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 934
 935         vcpu_set_reg(vcpu, rt, val);
 936 }
 937
 938 static void __hyp_text __vgic_v3_write_ctlr(struct kvm_vcpu *vcpu,
 939                                             u32 vmcr, int rt)
 940 {
 941         u32 val = vcpu_get_reg(vcpu, rt);
 942
 943         if (val & ICC_CTLR_EL1_CBPR_MASK)
 944                 vmcr |= ICH_VMCR_CBPR_MASK;
 945         else
 946                 vmcr &= ~ICH_VMCR_CBPR_MASK;
 947
 948         if (val & ICC_CTLR_EL1_EOImode_MASK)
 949                 vmcr |= ICH_VMCR_EOIM_MASK;
 950         else
 951                 vmcr &= ~ICH_VMCR_EOIM_MASK;
 952
 953         write_gicreg(vmcr, ICH_VMCR_EL2);
 954 }
 955
 956 int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
 957 {
 958         int rt;
 959         u32 esr;
 960         u32 vmcr;
 961         void (*fn)(struct kvm_vcpu *, u32, int);
 962         bool is_read;
 963         u32 sysreg;
 964
 965         esr = kvm_vcpu_get_hsr(vcpu);
 966         if (vcpu_mode_is_32bit(vcpu)) {
 967                 if (!kvm_condition_valid(vcpu))
 968                         return 1;
 969
 970                 sysreg = esr_cp15_to_sysreg(esr);
 971         } else {
 972                 sysreg = esr_sys64_to_sysreg(esr);
 973         }
 974
 975         is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
 976
 977         switch (sysreg) {
 978         case SYS_ICC_IAR0_EL1:
 979         case SYS_ICC_IAR1_EL1:
 980                 if (unlikely(!is_read))
 981                         return 0;
 982                 fn = __vgic_v3_read_iar;
 983                 break;
 984         case SYS_ICC_EOIR0_EL1:
 985         case SYS_ICC_EOIR1_EL1:
 986                 if (unlikely(is_read))
 987                         return 0;
 988                 fn = __vgic_v3_write_eoir;
 989                 break;
 990         case SYS_ICC_IGRPEN1_EL1:
 991                 if (is_read)
 992                         fn = __vgic_v3_read_igrpen1;
 993                 else
 994                         fn = __vgic_v3_write_igrpen1;
 995                 break;
 996         case SYS_ICC_BPR1_EL1:
 997                 if (is_read)
 998                         fn = __vgic_v3_read_bpr1;
 999                 else
1000                         fn = __vgic_v3_write_bpr1;
1001                 break;
1002         case SYS_ICC_AP0Rn_EL1(0):
1003         case SYS_ICC_AP1Rn_EL1(0):
1004                 if (is_read)
1005                         fn = __vgic_v3_read_apxr0;
1006                 else
1007                         fn = __vgic_v3_write_apxr0;
1008                 break;
1009         case SYS_ICC_AP0Rn_EL1(1):
1010         case SYS_ICC_AP1Rn_EL1(1):
1011                 if (is_read)
1012                         fn = __vgic_v3_read_apxr1;
1013                 else
1014                         fn = __vgic_v3_write_apxr1;
1015                 break;
1016         case SYS_ICC_AP0Rn_EL1(2):
1017         case SYS_ICC_AP1Rn_EL1(2):
1018                 if (is_read)
1019                         fn = __vgic_v3_read_apxr2;
1020                 else
1021                         fn = __vgic_v3_write_apxr2;
1022                 break;
1023         case SYS_ICC_AP0Rn_EL1(3):
1024         case SYS_ICC_AP1Rn_EL1(3):
1025                 if (is_read)
1026                         fn = __vgic_v3_read_apxr3;
1027                 else
1028                         fn = __vgic_v3_write_apxr3;
1029                 break;
1030         case SYS_ICC_HPPIR0_EL1:
1031         case SYS_ICC_HPPIR1_EL1:
1032                 if (unlikely(!is_read))
1033                         return 0;
1034                 fn = __vgic_v3_read_hppir;
1035                 break;
1036         case SYS_ICC_IGRPEN0_EL1:
1037                 if (is_read)
1038                         fn = __vgic_v3_read_igrpen0;
1039                 else
1040                         fn = __vgic_v3_write_igrpen0;
1041                 break;
1042         case SYS_ICC_BPR0_EL1:
1043                 if (is_read)
1044                         fn = __vgic_v3_read_bpr0;
1045                 else
1046                         fn = __vgic_v3_write_bpr0;
1047                 break;
1048         case SYS_ICC_DIR_EL1:
1049                 if (unlikely(is_read))
1050                         return 0;
1051                 fn = __vgic_v3_write_dir;
1052                 break;
1053         case SYS_ICC_RPR_EL1:
1054                 if (unlikely(!is_read))
1055                         return 0;
1056                 fn = __vgic_v3_read_rpr;
1057                 break;
1058         case SYS_ICC_CTLR_EL1:
1059                 if (is_read)
1060                         fn = __vgic_v3_read_ctlr;
1061                 else
1062                         fn = __vgic_v3_write_ctlr;
1063                 break;
1064         case SYS_ICC_PMR_EL1:
1065                 if (is_read)
1066                         fn = __vgic_v3_read_pmr;
1067                 else
1068                         fn = __vgic_v3_write_pmr;
1069                 break;
1070         default:
1071                 return 0;
1072         }
1073
1074         vmcr = __vgic_v3_read_vmcr();
1075         rt = kvm_vcpu_sys_get_rt(vcpu);
1076         fn(vcpu, vmcr, rt);
1077
1078         return 1;
1079 }
1080
1081 #endif