virt/kvm/arm/vgic/vgic-mmio-v2.c

   1 /*
   2  * VGICv2 MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/irqchip/arm-gic.h>
  15 #include <linux/kvm.h>
  16 #include <linux/kvm_host.h>
  17 #include <linux/nospec.h>
  18
  19 #include <kvm/iodev.h>
  20 #include <kvm/arm_vgic.h>
  21
  22 #include "vgic.h"
  23 #include "vgic-mmio.h"
  24
  25 static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
  26                                             gpa_t addr, unsigned int len)
  27 {
  28         u32 value;
  29
  30         switch (addr & 0x0c) {
  31         case GIC_DIST_CTRL:
  32                 value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0;
  33                 break;
  34         case GIC_DIST_CTR:
  35                 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
  36                 value = (value >> 5) - 1;
  37                 value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
  38                 break;
  39         case GIC_DIST_IIDR:
  40                 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
  41                 break;
  42         default:
  43                 return 0;
  44         }
  45
  46         return value;
  47 }
  48
  49 static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
  50                                     gpa_t addr, unsigned int len,
  51                                     unsigned long val)
  52 {
  53         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
  54         bool was_enabled = dist->enabled;
  55
  56         switch (addr & 0x0c) {
  57         case GIC_DIST_CTRL:
  58                 dist->enabled = val & GICD_ENABLE;
  59                 if (!was_enabled && dist->enabled)
  60                         vgic_kick_vcpus(vcpu->kvm);
  61                 break;
  62         case GIC_DIST_CTR:
  63         case GIC_DIST_IIDR:
  64                 /* Nothing to do */
  65                 return;
  66         }
  67 }
  68
  69 static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
  70                                  gpa_t addr, unsigned int len,
  71                                  unsigned long val)
  72 {
  73         int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
  74         int intid = val & 0xf;
  75         int targets = (val >> 16) & 0xff;
  76         int mode = (val >> 24) & 0x03;
  77         int c;
  78         struct kvm_vcpu *vcpu;
  79
  80         switch (mode) {
  81         case 0x0:               /* as specified by targets */
  82                 break;
  83         case 0x1:
  84                 targets = (1U << nr_vcpus) - 1;                 /* all, ... */
  85                 targets &= ~(1U << source_vcpu->vcpu_id);       /* but self */
  86                 break;
  87         case 0x2:               /* this very vCPU only */
  88                 targets = (1U << source_vcpu->vcpu_id);
  89                 break;
  90         case 0x3:               /* reserved */
  91                 return;
  92         }
  93
  94         kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
  95                 struct vgic_irq *irq;
  96
  97                 if (!(targets & (1U << c)))
  98                         continue;
  99
 100                 irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
 101
 102                 spin_lock(&irq->irq_lock);
 103                 irq->pending_latch = true;
 104                 irq->source |= 1U << source_vcpu->vcpu_id;
 105
 106                 vgic_queue_irq_unlock(source_vcpu->kvm, irq);
 107                 vgic_put_irq(source_vcpu->kvm, irq);
 108         }
 109 }
 110
 111 static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
 112                                            gpa_t addr, unsigned int len)
 113 {
 114         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 115         int i;
 116         u64 val = 0;
 117
 118         for (i = 0; i < len; i++) {
 119                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 120
 121                 val |= (u64)irq->targets << (i * 8);
 122
 123                 vgic_put_irq(vcpu->kvm, irq);
 124         }
 125
 126         return val;
 127 }
 128
 129 static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
 130                                    gpa_t addr, unsigned int len,
 131                                    unsigned long val)
 132 {
 133         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 134         u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
 135         int i;
 136
 137         /* GICD_ITARGETSR[0-7] are read-only */
 138         if (intid < VGIC_NR_PRIVATE_IRQS)
 139                 return;
 140
 141         for (i = 0; i < len; i++) {
 142                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
 143                 int target;
 144
 145                 spin_lock(&irq->irq_lock);
 146
 147                 irq->targets = (val >> (i * 8)) & cpu_mask;
 148                 target = irq->targets ? __ffs(irq->targets) : 0;
 149                 irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
 150
 151                 spin_unlock(&irq->irq_lock);
 152                 vgic_put_irq(vcpu->kvm, irq);
 153         }
 154 }
 155
 156 static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
 157                                             gpa_t addr, unsigned int len)
 158 {
 159         u32 intid = addr & 0x0f;
 160         int i;
 161         u64 val = 0;
 162
 163         for (i = 0; i < len; i++) {
 164                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 165
 166                 val |= (u64)irq->source << (i * 8);
 167
 168                 vgic_put_irq(vcpu->kvm, irq);
 169         }
 170         return val;
 171 }
 172
 173 static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
 174                                      gpa_t addr, unsigned int len,
 175                                      unsigned long val)
 176 {
 177         u32 intid = addr & 0x0f;
 178         int i;
 179
 180         for (i = 0; i < len; i++) {
 181                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 182
 183                 spin_lock(&irq->irq_lock);
 184
 185                 irq->source &= ~((val >> (i * 8)) & 0xff);
 186                 if (!irq->source)
 187                         irq->pending_latch = false;
 188
 189                 spin_unlock(&irq->irq_lock);
 190                 vgic_put_irq(vcpu->kvm, irq);
 191         }
 192 }
 193
 194 static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
 195                                      gpa_t addr, unsigned int len,
 196                                      unsigned long val)
 197 {
 198         u32 intid = addr & 0x0f;
 199         int i;
 200
 201         for (i = 0; i < len; i++) {
 202                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 203
 204                 spin_lock(&irq->irq_lock);
 205
 206                 irq->source |= (val >> (i * 8)) & 0xff;
 207
 208                 if (irq->source) {
 209                         irq->pending_latch = true;
 210                         vgic_queue_irq_unlock(vcpu->kvm, irq);
 211                 } else {
 212                         spin_unlock(&irq->irq_lock);
 213                 }
 214                 vgic_put_irq(vcpu->kvm, irq);
 215         }
 216 }
 217
 218 #define GICC_ARCH_VERSION_V2    0x2
 219
 220 /* These are for userland accesses only, there is no guest-facing emulation. */
 221 static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu,
 222                                            gpa_t addr, unsigned int len)
 223 {
 224         struct vgic_vmcr vmcr;
 225         u32 val;
 226
 227         vgic_get_vmcr(vcpu, &vmcr);
 228
 229         switch (addr & 0xff) {
 230         case GIC_CPU_CTRL:
 231                 val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;
 232                 val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;
 233                 val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;
 234                 val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;
 235                 val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;
 236                 val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;
 237
 238                 break;
 239         case GIC_CPU_PRIMASK:
 240                 /*
 241                  * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
 242                  * the PMR field as GICH_VMCR.VMPriMask rather than
 243                  * GICC_PMR.Priority, so we expose the upper five bits of
 244                  * priority mask to userspace using the lower bits in the
 245                  * unsigned long.
 246                  */
 247                 val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>
 248                         GICV_PMR_PRIORITY_SHIFT;
 249                 break;
 250         case GIC_CPU_BINPOINT:
 251                 val = vmcr.bpr;
 252                 break;
 253         case GIC_CPU_ALIAS_BINPOINT:
 254                 val = vmcr.abpr;
 255                 break;
 256         case GIC_CPU_IDENT:
 257                 val = ((PRODUCT_ID_KVM << 20) |
 258                        (GICC_ARCH_VERSION_V2 << 16) |
 259                        IMPLEMENTER_ARM);
 260                 break;
 261         default:
 262                 return 0;
 263         }
 264
 265         return val;
 266 }
 267
 268 static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu,
 269                                    gpa_t addr, unsigned int len,
 270                                    unsigned long val)
 271 {
 272         struct vgic_vmcr vmcr;
 273
 274         vgic_get_vmcr(vcpu, &vmcr);
 275
 276         switch (addr & 0xff) {
 277         case GIC_CPU_CTRL:
 278                 vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);
 279                 vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1);
 280                 vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl);
 281                 vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn);
 282                 vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);
 283                 vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS);
 284
 285                 break;
 286         case GIC_CPU_PRIMASK:
 287                 /*
 288                  * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
 289                  * the PMR field as GICH_VMCR.VMPriMask rather than
 290                  * GICC_PMR.Priority, so we expose the upper five bits of
 291                  * priority mask to userspace using the lower bits in the
 292                  * unsigned long.
 293                  */
 294                 vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) &
 295                         GICV_PMR_PRIORITY_MASK;
 296                 break;
 297         case GIC_CPU_BINPOINT:
 298                 vmcr.bpr = val;
 299                 break;
 300         case GIC_CPU_ALIAS_BINPOINT:
 301                 vmcr.abpr = val;
 302                 break;
 303         }
 304
 305         vgic_set_vmcr(vcpu, &vmcr);
 306 }
 307
 308 static unsigned long vgic_mmio_read_apr(struct kvm_vcpu *vcpu,
 309                                         gpa_t addr, unsigned int len)
 310 {
 311         int n; /* which APRn is this */
 312
 313         n = (addr >> 2) & 0x3;
 314
 315         if (kvm_vgic_global_state.type == VGIC_V2) {
 316                 /* GICv2 hardware systems support max. 32 groups */
 317                 if (n != 0)
 318                         return 0;
 319                 return vcpu->arch.vgic_cpu.vgic_v2.vgic_apr;
 320         } else {
 321                 struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
 322
 323                 if (n > vgic_v3_max_apr_idx(vcpu))
 324                         return 0;
 325
 326                 n = array_index_nospec(n, 4);
 327
 328                 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */
 329                 return vgicv3->vgic_ap1r[n];
 330         }
 331 }
 332
 333 static void vgic_mmio_write_apr(struct kvm_vcpu *vcpu,
 334                                 gpa_t addr, unsigned int len,
 335                                 unsigned long val)
 336 {
 337         int n; /* which APRn is this */
 338
 339         n = (addr >> 2) & 0x3;
 340
 341         if (kvm_vgic_global_state.type == VGIC_V2) {
 342                 /* GICv2 hardware systems support max. 32 groups */
 343                 if (n != 0)
 344                         return;
 345                 vcpu->arch.vgic_cpu.vgic_v2.vgic_apr = val;
 346         } else {
 347                 struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
 348
 349                 if (n > vgic_v3_max_apr_idx(vcpu))
 350                         return;
 351
 352                 n = array_index_nospec(n, 4);
 353
 354                 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */
 355                 vgicv3->vgic_ap1r[n] = val;
 356         }
 357 }
 358
 359 static const struct vgic_register_region vgic_v2_dist_registers[] = {
 360         REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
 361                 vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
 362                 VGIC_ACCESS_32bit),
 363         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
 364                 vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,
 365                 VGIC_ACCESS_32bit),
 366         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
 367                 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
 368                 VGIC_ACCESS_32bit),
 369         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
 370                 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
 371                 VGIC_ACCESS_32bit),
 372         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
 373                 vgic_mmio_read_pending, vgic_mmio_write_spending, NULL, NULL, 1,
 374                 VGIC_ACCESS_32bit),
 375         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
 376                 vgic_mmio_read_pending, vgic_mmio_write_cpending, NULL, NULL, 1,
 377                 VGIC_ACCESS_32bit),
 378         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
 379                 vgic_mmio_read_active, vgic_mmio_write_sactive,
 380                 NULL, vgic_mmio_uaccess_write_sactive, 1,
 381                 VGIC_ACCESS_32bit),
 382         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
 383                 vgic_mmio_read_active, vgic_mmio_write_cactive,
 384                 NULL, vgic_mmio_uaccess_write_cactive, 1,
 385                 VGIC_ACCESS_32bit),
 386         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
 387                 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
 388                 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 389         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
 390                 vgic_mmio_read_target, vgic_mmio_write_target, NULL, NULL, 8,
 391                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 392         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
 393                 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
 394                 VGIC_ACCESS_32bit),
 395         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
 396                 vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
 397                 VGIC_ACCESS_32bit),
 398         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
 399                 vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
 400                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 401         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
 402                 vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
 403                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 404 };
 405
 406 static const struct vgic_register_region vgic_v2_cpu_registers[] = {
 407         REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
 408                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 409                 VGIC_ACCESS_32bit),
 410         REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK,
 411                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 412                 VGIC_ACCESS_32bit),
 413         REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT,
 414                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 415                 VGIC_ACCESS_32bit),
 416         REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT,
 417                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 418                 VGIC_ACCESS_32bit),
 419         REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO,
 420                 vgic_mmio_read_apr, vgic_mmio_write_apr, 16,
 421                 VGIC_ACCESS_32bit),
 422         REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
 423                 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
 424                 VGIC_ACCESS_32bit),
 425 };
 426
 427 unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
 428 {
 429         dev->regions = vgic_v2_dist_registers;
 430         dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
 431
 432         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 433
 434         return SZ_4K;
 435 }
 436
 437 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
 438 {
 439         const struct vgic_register_region *region;
 440         struct vgic_io_device iodev;
 441         struct vgic_reg_attr reg_attr;
 442         struct kvm_vcpu *vcpu;
 443         gpa_t addr;
 444         int ret;
 445
 446         ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
 447         if (ret)
 448                 return ret;
 449
 450         vcpu = reg_attr.vcpu;
 451         addr = reg_attr.addr;
 452
 453         switch (attr->group) {
 454         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
 455                 iodev.regions = vgic_v2_dist_registers;
 456                 iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
 457                 iodev.base_addr = 0;
 458                 break;
 459         case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
 460                 iodev.regions = vgic_v2_cpu_registers;
 461                 iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
 462                 iodev.base_addr = 0;
 463                 break;
 464         default:
 465                 return -ENXIO;
 466         }
 467
 468         /* We only support aligned 32-bit accesses. */
 469         if (addr & 3)
 470                 return -ENXIO;
 471
 472         region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
 473         if (!region)
 474                 return -ENXIO;
 475
 476         return 0;
 477 }
 478
 479 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 480                           int offset, u32 *val)
 481 {
 482         struct vgic_io_device dev = {
 483                 .regions = vgic_v2_cpu_registers,
 484                 .nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
 485                 .iodev_type = IODEV_CPUIF,
 486         };
 487
 488         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
 489 }
 490
 491 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 492                          int offset, u32 *val)
 493 {
 494         struct vgic_io_device dev = {
 495                 .regions = vgic_v2_dist_registers,
 496                 .nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
 497                 .iodev_type = IODEV_DIST,
 498         };
 499
 500         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
 501 }