virt/kvm/arm/vgic/vgic-mmio-v3.c

   1 /*
   2  * VGICv3 MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/irqchip/arm-gic-v3.h>
  15 #include <linux/kvm.h>
  16 #include <linux/kvm_host.h>
  17 #include <kvm/iodev.h>
  18 #include <kvm/arm_vgic.h>
  19
  20 #include <asm/kvm_emulate.h>
  21
  22 #include "vgic.h"
  23 #include "vgic-mmio.h"
  24
  25 /* extract @num bytes at @offset bytes offset in data */
  26 unsigned long extract_bytes(u64 data, unsigned int offset,
  27                             unsigned int num)
  28 {
  29         return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
  30 }
  31
  32 /* allows updates of any half of a 64-bit register (or the whole thing) */
  33 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
  34                      unsigned long val)
  35 {
  36         int lower = (offset & 4) * 8;
  37         int upper = lower + 8 * len - 1;
  38
  39         reg &= ~GENMASK_ULL(upper, lower);
  40         val &= GENMASK_ULL(len * 8 - 1, 0);
  41
  42         return reg | ((u64)val << lower);
  43 }
  44
  45 #ifdef CONFIG_KVM_ARM_VGIC_V3_ITS
  46 bool vgic_has_its(struct kvm *kvm)
  47 {
  48         struct vgic_dist *dist = &kvm->arch.vgic;
  49
  50         if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
  51                 return false;
  52
  53         return dist->has_its;
  54 }
  55 #endif
  56
  57 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
  58                                             gpa_t addr, unsigned int len)
  59 {
  60         u32 value = 0;
  61
  62         switch (addr & 0x0c) {
  63         case GICD_CTLR:
  64                 if (vcpu->kvm->arch.vgic.enabled)
  65                         value |= GICD_CTLR_ENABLE_SS_G1;
  66                 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
  67                 break;
  68         case GICD_TYPER:
  69                 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
  70                 value = (value >> 5) - 1;
  71                 if (vgic_has_its(vcpu->kvm)) {
  72                         value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
  73                         value |= GICD_TYPER_LPIS;
  74                 } else {
  75                         value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
  76                 }
  77                 break;
  78         case GICD_IIDR:
  79                 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
  80                 break;
  81         default:
  82                 return 0;
  83         }
  84
  85         return value;
  86 }
  87
  88 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
  89                                     gpa_t addr, unsigned int len,
  90                                     unsigned long val)
  91 {
  92         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
  93         bool was_enabled = dist->enabled;
  94
  95         switch (addr & 0x0c) {
  96         case GICD_CTLR:
  97                 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
  98
  99                 if (!was_enabled && dist->enabled)
 100                         vgic_kick_vcpus(vcpu->kvm);
 101                 break;
 102         case GICD_TYPER:
 103         case GICD_IIDR:
 104                 return;
 105         }
 106 }
 107
 108 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
 109                                             gpa_t addr, unsigned int len)
 110 {
 111         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 112         struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 113         unsigned long ret = 0;
 114
 115         if (!irq)
 116                 return 0;
 117
 118         /* The upper word is RAZ for us. */
 119         if (!(addr & 4))
 120                 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
 121
 122         vgic_put_irq(vcpu->kvm, irq);
 123         return ret;
 124 }
 125
 126 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
 127                                     gpa_t addr, unsigned int len,
 128                                     unsigned long val)
 129 {
 130         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 131         struct vgic_irq *irq;
 132
 133         /* The upper word is WI for us since we don't implement Aff3. */
 134         if (addr & 4)
 135                 return;
 136
 137         irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 138
 139         if (!irq)
 140                 return;
 141
 142         spin_lock(&irq->irq_lock);
 143
 144         /* We only care about and preserve Aff0, Aff1 and Aff2. */
 145         irq->mpidr = val & GENMASK(23, 0);
 146         irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
 147
 148         spin_unlock(&irq->irq_lock);
 149         vgic_put_irq(vcpu->kvm, irq);
 150 }
 151
 152 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
 153                                              gpa_t addr, unsigned int len)
 154 {
 155         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 156
 157         return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
 158 }
 159
 160
 161 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
 162                                      gpa_t addr, unsigned int len,
 163                                      unsigned long val)
 164 {
 165         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 166         bool was_enabled = vgic_cpu->lpis_enabled;
 167
 168         if (!vgic_has_its(vcpu->kvm))
 169                 return;
 170
 171         vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
 172
 173         if (!was_enabled && vgic_cpu->lpis_enabled)
 174                 vgic_enable_lpis(vcpu);
 175 }
 176
 177 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
 178                                               gpa_t addr, unsigned int len)
 179 {
 180         unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
 181         int target_vcpu_id = vcpu->vcpu_id;
 182         u64 value;
 183
 184         value = (u64)(mpidr & GENMASK(23, 0)) << 32;
 185         value |= ((target_vcpu_id & 0xffff) << 8);
 186         if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
 187                 value |= GICR_TYPER_LAST;
 188         if (vgic_has_its(vcpu->kvm))
 189                 value |= GICR_TYPER_PLPIS;
 190
 191         return extract_bytes(value, addr & 7, len);
 192 }
 193
 194 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
 195                                              gpa_t addr, unsigned int len)
 196 {
 197         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 198 }
 199
 200 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
 201                                               gpa_t addr, unsigned int len)
 202 {
 203         switch (addr & 0xffff) {
 204         case GICD_PIDR2:
 205                 /* report a GICv3 compliant implementation */
 206                 return 0x3b;
 207         }
 208
 209         return 0;
 210 }
 211
 212 /* We want to avoid outer shareable. */
 213 u64 vgic_sanitise_shareability(u64 field)
 214 {
 215         switch (field) {
 216         case GIC_BASER_OuterShareable:
 217                 return GIC_BASER_InnerShareable;
 218         default:
 219                 return field;
 220         }
 221 }
 222
 223 /* Avoid any inner non-cacheable mapping. */
 224 u64 vgic_sanitise_inner_cacheability(u64 field)
 225 {
 226         switch (field) {
 227         case GIC_BASER_CACHE_nCnB:
 228         case GIC_BASER_CACHE_nC:
 229                 return GIC_BASER_CACHE_RaWb;
 230         default:
 231                 return field;
 232         }
 233 }
 234
 235 /* Non-cacheable or same-as-inner are OK. */
 236 u64 vgic_sanitise_outer_cacheability(u64 field)
 237 {
 238         switch (field) {
 239         case GIC_BASER_CACHE_SameAsInner:
 240         case GIC_BASER_CACHE_nC:
 241                 return field;
 242         default:
 243                 return GIC_BASER_CACHE_nC;
 244         }
 245 }
 246
 247 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
 248                         u64 (*sanitise_fn)(u64))
 249 {
 250         u64 field = (reg & field_mask) >> field_shift;
 251
 252         field = sanitise_fn(field) << field_shift;
 253         return (reg & ~field_mask) | field;
 254 }
 255
 256 #define PROPBASER_RES0_MASK                                             \
 257         (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
 258 #define PENDBASER_RES0_MASK                                             \
 259         (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) |      \
 260          GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
 261
 262 static u64 vgic_sanitise_pendbaser(u64 reg)
 263 {
 264         reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
 265                                   GICR_PENDBASER_SHAREABILITY_SHIFT,
 266                                   vgic_sanitise_shareability);
 267         reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
 268                                   GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
 269                                   vgic_sanitise_inner_cacheability);
 270         reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
 271                                   GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
 272                                   vgic_sanitise_outer_cacheability);
 273
 274         reg &= ~PENDBASER_RES0_MASK;
 275         reg &= ~GENMASK_ULL(51, 48);
 276
 277         return reg;
 278 }
 279
 280 static u64 vgic_sanitise_propbaser(u64 reg)
 281 {
 282         reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
 283                                   GICR_PROPBASER_SHAREABILITY_SHIFT,
 284                                   vgic_sanitise_shareability);
 285         reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
 286                                   GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
 287                                   vgic_sanitise_inner_cacheability);
 288         reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
 289                                   GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
 290                                   vgic_sanitise_outer_cacheability);
 291
 292         reg &= ~PROPBASER_RES0_MASK;
 293         reg &= ~GENMASK_ULL(51, 48);
 294         return reg;
 295 }
 296
 297 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
 298                                              gpa_t addr, unsigned int len)
 299 {
 300         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 301
 302         return extract_bytes(dist->propbaser, addr & 7, len);
 303 }
 304
 305 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
 306                                      gpa_t addr, unsigned int len,
 307                                      unsigned long val)
 308 {
 309         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 310         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 311         u64 old_propbaser, propbaser;
 312
 313         /* Storing a value with LPIs already enabled is undefined */
 314         if (vgic_cpu->lpis_enabled)
 315                 return;
 316
 317         do {
 318                 old_propbaser = dist->propbaser;
 319                 propbaser = old_propbaser;
 320                 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
 321                 propbaser = vgic_sanitise_propbaser(propbaser);
 322         } while (cmpxchg64(&dist->propbaser, old_propbaser,
 323                            propbaser) != old_propbaser);
 324 }
 325
 326 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
 327                                              gpa_t addr, unsigned int len)
 328 {
 329         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 330
 331         return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
 332 }
 333
 334 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
 335                                      gpa_t addr, unsigned int len,
 336                                      unsigned long val)
 337 {
 338         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 339         u64 old_pendbaser, pendbaser;
 340
 341         /* Storing a value with LPIs already enabled is undefined */
 342         if (vgic_cpu->lpis_enabled)
 343                 return;
 344
 345         do {
 346                 old_pendbaser = vgic_cpu->pendbaser;
 347                 pendbaser = old_pendbaser;
 348                 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
 349                 pendbaser = vgic_sanitise_pendbaser(pendbaser);
 350         } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
 351                            pendbaser) != old_pendbaser);
 352 }
 353
 354 /*
 355  * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 356  * redistributors, while SPIs are covered by registers in the distributor
 357  * block. Trying to set private IRQs in this block gets ignored.
 358  * We take some special care here to fix the calculation of the register
 359  * offset.
 360  */
 361 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc)   \
 362         {                                                               \
 363                 .reg_offset = off,                                      \
 364                 .bits_per_irq = bpi,                                    \
 365                 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,                \
 366                 .access_flags = acc,                                    \
 367                 .read = vgic_mmio_read_raz,                             \
 368                 .write = vgic_mmio_write_wi,                            \
 369         }, {                                                            \
 370                 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,   \
 371                 .bits_per_irq = bpi,                                    \
 372                 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,       \
 373                 .access_flags = acc,                                    \
 374                 .read = rd,                                             \
 375                 .write = wr,                                            \
 376         }
 377
 378 static const struct vgic_register_region vgic_v3_dist_registers[] = {
 379         REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
 380                 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
 381                 VGIC_ACCESS_32bit),
 382         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
 383                 vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
 384                 VGIC_ACCESS_32bit),
 385         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
 386                 vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
 387                 VGIC_ACCESS_32bit),
 388         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
 389                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
 390                 VGIC_ACCESS_32bit),
 391         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
 392                 vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
 393                 VGIC_ACCESS_32bit),
 394         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
 395                 vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
 396                 VGIC_ACCESS_32bit),
 397         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
 398                 vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
 399                 VGIC_ACCESS_32bit),
 400         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
 401                 vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
 402                 VGIC_ACCESS_32bit),
 403         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
 404                 vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
 405                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 406         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
 407                 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
 408                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 409         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
 410                 vgic_mmio_read_config, vgic_mmio_write_config, 2,
 411                 VGIC_ACCESS_32bit),
 412         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
 413                 vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
 414                 VGIC_ACCESS_32bit),
 415         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
 416                 vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,
 417                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 418         REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
 419                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 420                 VGIC_ACCESS_32bit),
 421 };
 422
 423 static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
 424         REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
 425                 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
 426                 VGIC_ACCESS_32bit),
 427         REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
 428                 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
 429                 VGIC_ACCESS_32bit),
 430         REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
 431                 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
 432                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 433         REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
 434                 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
 435                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 436         REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
 437                 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
 438                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 439         REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
 440                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 441                 VGIC_ACCESS_32bit),
 442 };
 443
 444 static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
 445         REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
 446                 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
 447                 VGIC_ACCESS_32bit),
 448         REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
 449                 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
 450                 VGIC_ACCESS_32bit),
 451         REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
 452                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
 453                 VGIC_ACCESS_32bit),
 454         REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
 455                 vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
 456                 VGIC_ACCESS_32bit),
 457         REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
 458                 vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
 459                 VGIC_ACCESS_32bit),
 460         REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
 461                 vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
 462                 VGIC_ACCESS_32bit),
 463         REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
 464                 vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
 465                 VGIC_ACCESS_32bit),
 466         REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
 467                 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
 468                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 469         REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
 470                 vgic_mmio_read_config, vgic_mmio_write_config, 8,
 471                 VGIC_ACCESS_32bit),
 472         REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
 473                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 474                 VGIC_ACCESS_32bit),
 475         REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
 476                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 477                 VGIC_ACCESS_32bit),
 478 };
 479
 480 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
 481 {
 482         dev->regions = vgic_v3_dist_registers;
 483         dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 484
 485         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 486
 487         return SZ_64K;
 488 }
 489
 490 int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
 491 {
 492         struct kvm_vcpu *vcpu;
 493         int c, ret = 0;
 494
 495         kvm_for_each_vcpu(c, vcpu, kvm) {
 496                 gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
 497                 gpa_t sgi_base = rd_base + SZ_64K;
 498                 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 499                 struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
 500
 501                 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
 502                 rd_dev->base_addr = rd_base;
 503                 rd_dev->iodev_type = IODEV_REDIST;
 504                 rd_dev->regions = vgic_v3_rdbase_registers;
 505                 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
 506                 rd_dev->redist_vcpu = vcpu;
 507
 508                 mutex_lock(&kvm->slots_lock);
 509                 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
 510                                               SZ_64K, &rd_dev->dev);
 511                 mutex_unlock(&kvm->slots_lock);
 512
 513                 if (ret)
 514                         break;
 515
 516                 kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
 517                 sgi_dev->base_addr = sgi_base;
 518                 sgi_dev->iodev_type = IODEV_REDIST;
 519                 sgi_dev->regions = vgic_v3_sgibase_registers;
 520                 sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
 521                 sgi_dev->redist_vcpu = vcpu;
 522
 523                 mutex_lock(&kvm->slots_lock);
 524                 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
 525                                               SZ_64K, &sgi_dev->dev);
 526                 mutex_unlock(&kvm->slots_lock);
 527                 if (ret) {
 528                         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 529                                                   &rd_dev->dev);
 530                         break;
 531                 }
 532         }
 533
 534         if (ret) {
 535                 /* The current c failed, so we start with the previous one. */
 536                 for (c--; c >= 0; c--) {
 537                         struct vgic_cpu *vgic_cpu;
 538
 539                         vcpu = kvm_get_vcpu(kvm, c);
 540                         vgic_cpu = &vcpu->arch.vgic_cpu;
 541                         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 542                                                   &vgic_cpu->rd_iodev.dev);
 543                         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 544                                                   &vgic_cpu->sgi_iodev.dev);
 545                 }
 546         }
 547
 548         return ret;
 549 }
 550
 551 /*
 552  * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
 553  * generation register ICC_SGI1R_EL1) with a given VCPU.
 554  * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
 555  * return -1.
 556  */
 557 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
 558 {
 559         unsigned long affinity;
 560         int level0;
 561
 562         /*
 563          * Split the current VCPU's MPIDR into affinity level 0 and the
 564          * rest as this is what we have to compare against.
 565          */
 566         affinity = kvm_vcpu_get_mpidr_aff(vcpu);
 567         level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
 568         affinity &= ~MPIDR_LEVEL_MASK;
 569
 570         /* bail out if the upper three levels don't match */
 571         if (sgi_aff != affinity)
 572                 return -1;
 573
 574         /* Is this VCPU's bit set in the mask ? */
 575         if (!(sgi_cpu_mask & BIT(level0)))
 576                 return -1;
 577
 578         return level0;
 579 }
 580
 581 /*
 582  * The ICC_SGI* registers encode the affinity differently from the MPIDR,
 583  * so provide a wrapper to use the existing defines to isolate a certain
 584  * affinity level.
 585  */
 586 #define SGI_AFFINITY_LEVEL(reg, level) \
 587         ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
 588         >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
 589
 590 /**
 591  * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
 592  * @vcpu: The VCPU requesting a SGI
 593  * @reg: The value written into the ICC_SGI1R_EL1 register by that VCPU
 594  *
 595  * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
 596  * This will trap in sys_regs.c and call this function.
 597  * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
 598  * target processors as well as a bitmask of 16 Aff0 CPUs.
 599  * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
 600  * check for matching ones. If this bit is set, we signal all, but not the
 601  * calling VCPU.
 602  */
 603 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
 604 {
 605         struct kvm *kvm = vcpu->kvm;
 606         struct kvm_vcpu *c_vcpu;
 607         u16 target_cpus;
 608         u64 mpidr;
 609         int sgi, c;
 610         int vcpu_id = vcpu->vcpu_id;
 611         bool broadcast;
 612
 613         sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
 614         broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
 615         target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
 616         mpidr = SGI_AFFINITY_LEVEL(reg, 3);
 617         mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
 618         mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
 619
 620         /*
 621          * We iterate over all VCPUs to find the MPIDRs matching the request.
 622          * If we have handled one CPU, we clear its bit to detect early
 623          * if we are already finished. This avoids iterating through all
 624          * VCPUs when most of the times we just signal a single VCPU.
 625          */
 626         kvm_for_each_vcpu(c, c_vcpu, kvm) {
 627                 struct vgic_irq *irq;
 628
 629                 /* Exit early if we have dealt with all requested CPUs */
 630                 if (!broadcast && target_cpus == 0)
 631                         break;
 632
 633                 /* Don't signal the calling VCPU */
 634                 if (broadcast && c == vcpu_id)
 635                         continue;
 636
 637                 if (!broadcast) {
 638                         int level0;
 639
 640                         level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
 641                         if (level0 == -1)
 642                                 continue;
 643
 644                         /* remove this matching VCPU from the mask */
 645                         target_cpus &= ~BIT(level0);
 646                 }
 647
 648                 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
 649
 650                 spin_lock(&irq->irq_lock);
 651                 irq->pending = true;
 652
 653                 vgic_queue_irq_unlock(vcpu->kvm, irq);
 654                 vgic_put_irq(vcpu->kvm, irq);
 655         }
 656 }