virt/kvm/arm/vgic/vgic-mmio.c

   1 /*
   2  * VGIC MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/bitops.h>
  15 #include <linux/bsearch.h>
  16 #include <linux/kvm.h>
  17 #include <linux/kvm_host.h>
  18 #include <kvm/iodev.h>
  19 #include <kvm/arm_arch_timer.h>
  20 #include <kvm/arm_vgic.h>
  21
  22 #include "vgic.h"
  23 #include "vgic-mmio.h"
  24
  25 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
  26                                  gpa_t addr, unsigned int len)
  27 {
  28         return 0;
  29 }
  30
  31 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
  32                                  gpa_t addr, unsigned int len)
  33 {
  34         return -1UL;
  35 }
  36
  37 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
  38                         unsigned int len, unsigned long val)
  39 {
  40         /* Ignore */
  41 }
  42
  43 int vgic_mmio_uaccess_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
  44                                unsigned int len, unsigned long val)
  45 {
  46         /* Ignore */
  47         return 0;
  48 }
  49
  50 unsigned long vgic_mmio_read_group(struct kvm_vcpu *vcpu,
  51                                    gpa_t addr, unsigned int len)
  52 {
  53         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  54         u32 value = 0;
  55         int i;
  56
  57         /* Loop over all IRQs affected by this read */
  58         for (i = 0; i < len * 8; i++) {
  59                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  60
  61                 if (irq->group)
  62                         value |= BIT(i);
  63
  64                 vgic_put_irq(vcpu->kvm, irq);
  65         }
  66
  67         return value;
  68 }
  69
  70 void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
  71                            unsigned int len, unsigned long val)
  72 {
  73         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  74         int i;
  75         unsigned long flags;
  76
  77         for (i = 0; i < len * 8; i++) {
  78                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  79
  80                 spin_lock_irqsave(&irq->irq_lock, flags);
  81                 irq->group = !!(val & BIT(i));
  82                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
  83
  84                 vgic_put_irq(vcpu->kvm, irq);
  85         }
  86 }
  87
  88 /*
  89  * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
  90  * of the enabled bit, so there is only one function for both here.
  91  */
  92 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
  93                                     gpa_t addr, unsigned int len)
  94 {
  95         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  96         u32 value = 0;
  97         int i;
  98
  99         /* Loop over all IRQs affected by this read */
 100         for (i = 0; i < len * 8; i++) {
 101                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 102
 103                 if (irq->enabled)
 104                         value |= (1U << i);
 105
 106                 vgic_put_irq(vcpu->kvm, irq);
 107         }
 108
 109         return value;
 110 }
 111
 112 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
 113                              gpa_t addr, unsigned int len,
 114                              unsigned long val)
 115 {
 116         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 117         int i;
 118         unsigned long flags;
 119
 120         for_each_set_bit(i, &val, len * 8) {
 121                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 122
 123                 spin_lock_irqsave(&irq->irq_lock, flags);
 124                 irq->enabled = true;
 125                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 126
 127                 vgic_put_irq(vcpu->kvm, irq);
 128         }
 129 }
 130
 131 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
 132                              gpa_t addr, unsigned int len,
 133                              unsigned long val)
 134 {
 135         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 136         int i;
 137         unsigned long flags;
 138
 139         for_each_set_bit(i, &val, len * 8) {
 140                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 141
 142                 spin_lock_irqsave(&irq->irq_lock, flags);
 143
 144                 irq->enabled = false;
 145
 146                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 147                 vgic_put_irq(vcpu->kvm, irq);
 148         }
 149 }
 150
 151 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
 152                                      gpa_t addr, unsigned int len)
 153 {
 154         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 155         u32 value = 0;
 156         int i;
 157
 158         /* Loop over all IRQs affected by this read */
 159         for (i = 0; i < len * 8; i++) {
 160                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 161                 unsigned long flags;
 162
 163                 spin_lock_irqsave(&irq->irq_lock, flags);
 164                 if (irq_is_pending(irq))
 165                         value |= (1U << i);
 166                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 167
 168                 vgic_put_irq(vcpu->kvm, irq);
 169         }
 170
 171         return value;
 172 }
 173
 174 /*
 175  * This function will return the VCPU that performed the MMIO access and
 176  * trapped from within the VM, and will return NULL if this is a userspace
 177  * access.
 178  *
 179  * We can disable preemption locally around accessing the per-CPU variable,
 180  * and use the resolved vcpu pointer after enabling preemption again, because
 181  * even if the current thread is migrated to another CPU, reading the per-CPU
 182  * value later will give us the same value as we update the per-CPU variable
 183  * in the preempt notifier handlers.
 184  */
 185 static struct kvm_vcpu *vgic_get_mmio_requester_vcpu(void)
 186 {
 187         struct kvm_vcpu *vcpu;
 188
 189         preempt_disable();
 190         vcpu = kvm_arm_get_running_vcpu();
 191         preempt_enable();
 192         return vcpu;
 193 }
 194
 195 /* Must be called with irq->irq_lock held */
 196 static void vgic_hw_irq_spending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 197                                  bool is_uaccess)
 198 {
 199         if (is_uaccess)
 200                 return;
 201
 202         irq->pending_latch = true;
 203         vgic_irq_set_phys_active(irq, true);
 204 }
 205
 206 static bool is_vgic_v2_sgi(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
 207 {
 208         return (vgic_irq_is_sgi(irq->intid) &&
 209                 vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2);
 210 }
 211
 212 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
 213                               gpa_t addr, unsigned int len,
 214                               unsigned long val)
 215 {
 216         bool is_uaccess = !vgic_get_mmio_requester_vcpu();
 217         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 218         int i;
 219         unsigned long flags;
 220
 221         for_each_set_bit(i, &val, len * 8) {
 222                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 223
 224                 /* GICD_ISPENDR0 SGI bits are WI */
 225                 if (is_vgic_v2_sgi(vcpu, irq)) {
 226                         vgic_put_irq(vcpu->kvm, irq);
 227                         continue;
 228                 }
 229
 230                 spin_lock_irqsave(&irq->irq_lock, flags);
 231                 if (irq->hw)
 232                         vgic_hw_irq_spending(vcpu, irq, is_uaccess);
 233                 else
 234                         irq->pending_latch = true;
 235                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 236                 vgic_put_irq(vcpu->kvm, irq);
 237         }
 238 }
 239
 240 /* Must be called with irq->irq_lock held */
 241 static void vgic_hw_irq_cpending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 242                                  bool is_uaccess)
 243 {
 244         if (is_uaccess)
 245                 return;
 246
 247         irq->pending_latch = false;
 248
 249         /*
 250          * We don't want the guest to effectively mask the physical
 251          * interrupt by doing a write to SPENDR followed by a write to
 252          * CPENDR for HW interrupts, so we clear the active state on
 253          * the physical side if the virtual interrupt is not active.
 254          * This may lead to taking an additional interrupt on the
 255          * host, but that should not be a problem as the worst that
 256          * can happen is an additional vgic injection.  We also clear
 257          * the pending state to maintain proper semantics for edge HW
 258          * interrupts.
 259          */
 260         vgic_irq_set_phys_pending(irq, false);
 261         if (!irq->active)
 262                 vgic_irq_set_phys_active(irq, false);
 263 }
 264
 265 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
 266                               gpa_t addr, unsigned int len,
 267                               unsigned long val)
 268 {
 269         bool is_uaccess = !vgic_get_mmio_requester_vcpu();
 270         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 271         int i;
 272         unsigned long flags;
 273
 274         for_each_set_bit(i, &val, len * 8) {
 275                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 276
 277                 /* GICD_ICPENDR0 SGI bits are WI */
 278                 if (is_vgic_v2_sgi(vcpu, irq)) {
 279                         vgic_put_irq(vcpu->kvm, irq);
 280                         continue;
 281                 }
 282
 283                 spin_lock_irqsave(&irq->irq_lock, flags);
 284
 285                 if (irq->hw)
 286                         vgic_hw_irq_cpending(vcpu, irq, is_uaccess);
 287                 else
 288                         irq->pending_latch = false;
 289
 290                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 291                 vgic_put_irq(vcpu->kvm, irq);
 292         }
 293 }
 294
 295 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
 296                                     gpa_t addr, unsigned int len)
 297 {
 298         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 299         u32 value = 0;
 300         int i;
 301
 302         /* Loop over all IRQs affected by this read */
 303         for (i = 0; i < len * 8; i++) {
 304                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 305
 306                 if (irq->active)
 307                         value |= (1U << i);
 308
 309                 vgic_put_irq(vcpu->kvm, irq);
 310         }
 311
 312         return value;
 313 }
 314
 315 /* Must be called with irq->irq_lock held */
 316 static void vgic_hw_irq_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 317                                       bool active, bool is_uaccess)
 318 {
 319         if (is_uaccess)
 320                 return;
 321
 322         irq->active = active;
 323         vgic_irq_set_phys_active(irq, active);
 324 }
 325
 326 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 327                                     bool active)
 328 {
 329         unsigned long flags;
 330         struct kvm_vcpu *requester_vcpu = vgic_get_mmio_requester_vcpu();
 331
 332         spin_lock_irqsave(&irq->irq_lock, flags);
 333
 334         if (irq->hw) {
 335                 vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
 336         } else {
 337                 u32 model = vcpu->kvm->arch.vgic.vgic_model;
 338                 u8 active_source;
 339
 340                 irq->active = active;
 341
 342                 /*
 343                  * The GICv2 architecture indicates that the source CPUID for
 344                  * an SGI should be provided during an EOI which implies that
 345                  * the active state is stored somewhere, but at the same time
 346                  * this state is not architecturally exposed anywhere and we
 347                  * have no way of knowing the right source.
 348                  *
 349                  * This may lead to a VCPU not being able to receive
 350                  * additional instances of a particular SGI after migration
 351                  * for a GICv2 VM on some GIC implementations.  Oh well.
 352                  */
 353                 active_source = (requester_vcpu) ? requester_vcpu->vcpu_id : 0;
 354
 355                 if (model == KVM_DEV_TYPE_ARM_VGIC_V2 &&
 356                     active && vgic_irq_is_sgi(irq->intid))
 357                         irq->active_source = active_source;
 358         }
 359
 360         if (irq->active)
 361                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 362         else
 363                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 364 }
 365
 366 /*
 367  * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
 368  * is not queued on some running VCPU's LRs, because then the change to the
 369  * active state can be overwritten when the VCPU's state is synced coming back
 370  * from the guest.
 371  *
 372  * For shared interrupts, we have to stop all the VCPUs because interrupts can
 373  * be migrated while we don't hold the IRQ locks and we don't want to be
 374  * chasing moving targets.
 375  *
 376  * For private interrupts we don't have to do anything because userspace
 377  * accesses to the VGIC state already require all VCPUs to be stopped, and
 378  * only the VCPU itself can modify its private interrupts active state, which
 379  * guarantees that the VCPU is not running.
 380  */
 381 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
 382 {
 383         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
 384             intid >= VGIC_NR_PRIVATE_IRQS)
 385                 kvm_arm_halt_guest(vcpu->kvm);
 386 }
 387
 388 /* See vgic_change_active_prepare */
 389 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
 390 {
 391         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
 392             intid >= VGIC_NR_PRIVATE_IRQS)
 393                 kvm_arm_resume_guest(vcpu->kvm);
 394 }
 395
 396 static void __vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 397                                       gpa_t addr, unsigned int len,
 398                                       unsigned long val)
 399 {
 400         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 401         int i;
 402
 403         for_each_set_bit(i, &val, len * 8) {
 404                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 405                 vgic_mmio_change_active(vcpu, irq, false);
 406                 vgic_put_irq(vcpu->kvm, irq);
 407         }
 408 }
 409
 410 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 411                              gpa_t addr, unsigned int len,
 412                              unsigned long val)
 413 {
 414         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 415
 416         mutex_lock(&vcpu->kvm->lock);
 417         vgic_change_active_prepare(vcpu, intid);
 418
 419         __vgic_mmio_write_cactive(vcpu, addr, len, val);
 420
 421         vgic_change_active_finish(vcpu, intid);
 422         mutex_unlock(&vcpu->kvm->lock);
 423 }
 424
 425 int vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
 426                                      gpa_t addr, unsigned int len,
 427                                      unsigned long val)
 428 {
 429         __vgic_mmio_write_cactive(vcpu, addr, len, val);
 430         return 0;
 431 }
 432
 433 static void __vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 434                                       gpa_t addr, unsigned int len,
 435                                       unsigned long val)
 436 {
 437         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 438         int i;
 439
 440         for_each_set_bit(i, &val, len * 8) {
 441                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 442                 vgic_mmio_change_active(vcpu, irq, true);
 443                 vgic_put_irq(vcpu->kvm, irq);
 444         }
 445 }
 446
 447 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 448                              gpa_t addr, unsigned int len,
 449                              unsigned long val)
 450 {
 451         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 452
 453         mutex_lock(&vcpu->kvm->lock);
 454         vgic_change_active_prepare(vcpu, intid);
 455
 456         __vgic_mmio_write_sactive(vcpu, addr, len, val);
 457
 458         vgic_change_active_finish(vcpu, intid);
 459         mutex_unlock(&vcpu->kvm->lock);
 460 }
 461
 462 int vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
 463                                      gpa_t addr, unsigned int len,
 464                                      unsigned long val)
 465 {
 466         __vgic_mmio_write_sactive(vcpu, addr, len, val);
 467         return 0;
 468 }
 469
 470 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
 471                                       gpa_t addr, unsigned int len)
 472 {
 473         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 474         int i;
 475         u64 val = 0;
 476
 477         for (i = 0; i < len; i++) {
 478                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 479
 480                 val |= (u64)irq->priority << (i * 8);
 481
 482                 vgic_put_irq(vcpu->kvm, irq);
 483         }
 484
 485         return val;
 486 }
 487
 488 /*
 489  * We currently don't handle changing the priority of an interrupt that
 490  * is already pending on a VCPU. If there is a need for this, we would
 491  * need to make this VCPU exit and re-evaluate the priorities, potentially
 492  * leading to this interrupt getting presented now to the guest (if it has
 493  * been masked by the priority mask before).
 494  */
 495 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
 496                               gpa_t addr, unsigned int len,
 497                               unsigned long val)
 498 {
 499         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 500         int i;
 501         unsigned long flags;
 502
 503         for (i = 0; i < len; i++) {
 504                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 505
 506                 spin_lock_irqsave(&irq->irq_lock, flags);
 507                 /* Narrow the priority range to what we actually support */
 508                 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
 509                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 510
 511                 vgic_put_irq(vcpu->kvm, irq);
 512         }
 513 }
 514
 515 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
 516                                     gpa_t addr, unsigned int len)
 517 {
 518         u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
 519         u32 value = 0;
 520         int i;
 521
 522         for (i = 0; i < len * 4; i++) {
 523                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 524
 525                 if (irq->config == VGIC_CONFIG_EDGE)
 526                         value |= (2U << (i * 2));
 527
 528                 vgic_put_irq(vcpu->kvm, irq);
 529         }
 530
 531         return value;
 532 }
 533
 534 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
 535                             gpa_t addr, unsigned int len,
 536                             unsigned long val)
 537 {
 538         u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
 539         int i;
 540         unsigned long flags;
 541
 542         for (i = 0; i < len * 4; i++) {
 543                 struct vgic_irq *irq;
 544
 545                 /*
 546                  * The configuration cannot be changed for SGIs in general,
 547                  * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
 548                  * code relies on PPIs being level triggered, so we also
 549                  * make them read-only here.
 550                  */
 551                 if (intid + i < VGIC_NR_PRIVATE_IRQS)
 552                         continue;
 553
 554                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 555                 spin_lock_irqsave(&irq->irq_lock, flags);
 556
 557                 if (test_bit(i * 2 + 1, &val))
 558                         irq->config = VGIC_CONFIG_EDGE;
 559                 else
 560                         irq->config = VGIC_CONFIG_LEVEL;
 561
 562                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 563                 vgic_put_irq(vcpu->kvm, irq);
 564         }
 565 }
 566
 567 u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
 568 {
 569         int i;
 570         u64 val = 0;
 571         int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 572
 573         for (i = 0; i < 32; i++) {
 574                 struct vgic_irq *irq;
 575
 576                 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
 577                         continue;
 578
 579                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 580                 if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
 581                         val |= (1U << i);
 582
 583                 vgic_put_irq(vcpu->kvm, irq);
 584         }
 585
 586         return val;
 587 }
 588
 589 void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
 590                                     const u64 val)
 591 {
 592         int i;
 593         int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 594         unsigned long flags;
 595
 596         for (i = 0; i < 32; i++) {
 597                 struct vgic_irq *irq;
 598                 bool new_level;
 599
 600                 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
 601                         continue;
 602
 603                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 604
 605                 /*
 606                  * Line level is set irrespective of irq type
 607                  * (level or edge) to avoid dependency that VM should
 608                  * restore irq config before line level.
 609                  */
 610                 new_level = !!(val & (1U << i));
 611                 spin_lock_irqsave(&irq->irq_lock, flags);
 612                 irq->line_level = new_level;
 613                 if (new_level)
 614                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 615                 else
 616                         spin_unlock_irqrestore(&irq->irq_lock, flags);
 617
 618                 vgic_put_irq(vcpu->kvm, irq);
 619         }
 620 }
 621
 622 static int match_region(const void *key, const void *elt)
 623 {
 624         const unsigned int offset = (unsigned long)key;
 625         const struct vgic_register_region *region = elt;
 626
 627         if (offset < region->reg_offset)
 628                 return -1;
 629
 630         if (offset >= region->reg_offset + region->len)
 631                 return 1;
 632
 633         return 0;
 634 }
 635
 636 const struct vgic_register_region *
 637 vgic_find_mmio_region(const struct vgic_register_region *regions,
 638                       int nr_regions, unsigned int offset)
 639 {
 640         return bsearch((void *)(uintptr_t)offset, regions, nr_regions,
 641                        sizeof(regions[0]), match_region);
 642 }
 643
 644 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 645 {
 646         if (kvm_vgic_global_state.type == VGIC_V2)
 647                 vgic_v2_set_vmcr(vcpu, vmcr);
 648         else
 649                 vgic_v3_set_vmcr(vcpu, vmcr);
 650 }
 651
 652 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 653 {
 654         if (kvm_vgic_global_state.type == VGIC_V2)
 655                 vgic_v2_get_vmcr(vcpu, vmcr);
 656         else
 657                 vgic_v3_get_vmcr(vcpu, vmcr);
 658 }
 659
 660 /*
 661  * kvm_mmio_read_buf() returns a value in a format where it can be converted
 662  * to a byte array and be directly observed as the guest wanted it to appear
 663  * in memory if it had done the store itself, which is LE for the GIC, as the
 664  * guest knows the GIC is always LE.
 665  *
 666  * We convert this value to the CPUs native format to deal with it as a data
 667  * value.
 668  */
 669 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
 670 {
 671         unsigned long data = kvm_mmio_read_buf(val, len);
 672
 673         switch (len) {
 674         case 1:
 675                 return data;
 676         case 2:
 677                 return le16_to_cpu(data);
 678         case 4:
 679                 return le32_to_cpu(data);
 680         default:
 681                 return le64_to_cpu(data);
 682         }
 683 }
 684
 685 /*
 686  * kvm_mmio_write_buf() expects a value in a format such that if converted to
 687  * a byte array it is observed as the guest would see it if it could perform
 688  * the load directly.  Since the GIC is LE, and the guest knows this, the
 689  * guest expects a value in little endian format.
 690  *
 691  * We convert the data value from the CPUs native format to LE so that the
 692  * value is returned in the proper format.
 693  */
 694 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
 695                                 unsigned long data)
 696 {
 697         switch (len) {
 698         case 1:
 699                 break;
 700         case 2:
 701                 data = cpu_to_le16(data);
 702                 break;
 703         case 4:
 704                 data = cpu_to_le32(data);
 705                 break;
 706         default:
 707                 data = cpu_to_le64(data);
 708         }
 709
 710         kvm_mmio_write_buf(buf, len, data);
 711 }
 712
 713 static
 714 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
 715 {
 716         return container_of(dev, struct vgic_io_device, dev);
 717 }
 718
 719 static bool check_region(const struct kvm *kvm,
 720                          const struct vgic_register_region *region,
 721                          gpa_t addr, int len)
 722 {
 723         int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 724
 725         switch (len) {
 726         case sizeof(u8):
 727                 flags = VGIC_ACCESS_8bit;
 728                 break;
 729         case sizeof(u32):
 730                 flags = VGIC_ACCESS_32bit;
 731                 break;
 732         case sizeof(u64):
 733                 flags = VGIC_ACCESS_64bit;
 734                 break;
 735         default:
 736                 return false;
 737         }
 738
 739         if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
 740                 if (!region->bits_per_irq)
 741                         return true;
 742
 743                 /* Do we access a non-allocated IRQ? */
 744                 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
 745         }
 746
 747         return false;
 748 }
 749
 750 const struct vgic_register_region *
 751 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
 752                      gpa_t addr, int len)
 753 {
 754         const struct vgic_register_region *region;
 755
 756         region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
 757                                        addr - iodev->base_addr);
 758         if (!region || !check_region(vcpu->kvm, region, addr, len))
 759                 return NULL;
 760
 761         return region;
 762 }
 763
 764 static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 765                              gpa_t addr, u32 *val)
 766 {
 767         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 768         const struct vgic_register_region *region;
 769         struct kvm_vcpu *r_vcpu;
 770
 771         region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
 772         if (!region) {
 773                 *val = 0;
 774                 return 0;
 775         }
 776
 777         r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
 778         if (region->uaccess_read)
 779                 *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
 780         else
 781                 *val = region->read(r_vcpu, addr, sizeof(u32));
 782
 783         return 0;
 784 }
 785
 786 static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 787                               gpa_t addr, const u32 *val)
 788 {
 789         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 790         const struct vgic_register_region *region;
 791         struct kvm_vcpu *r_vcpu;
 792
 793         region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
 794         if (!region)
 795                 return 0;
 796
 797         r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
 798         if (region->uaccess_write)
 799                 return region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
 800
 801         region->write(r_vcpu, addr, sizeof(u32), *val);
 802         return 0;
 803 }
 804
 805 /*
 806  * Userland access to VGIC registers.
 807  */
 808 int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
 809                  bool is_write, int offset, u32 *val)
 810 {
 811         if (is_write)
 812                 return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
 813         else
 814                 return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
 815 }
 816
 817 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 818                               gpa_t addr, int len, void *val)
 819 {
 820         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 821         const struct vgic_register_region *region;
 822         unsigned long data = 0;
 823
 824         region = vgic_get_mmio_region(vcpu, iodev, addr, len);
 825         if (!region) {
 826                 memset(val, 0, len);
 827                 return 0;
 828         }
 829
 830         switch (iodev->iodev_type) {
 831         case IODEV_CPUIF:
 832                 data = region->read(vcpu, addr, len);
 833                 break;
 834         case IODEV_DIST:
 835                 data = region->read(vcpu, addr, len);
 836                 break;
 837         case IODEV_REDIST:
 838                 data = region->read(iodev->redist_vcpu, addr, len);
 839                 break;
 840         case IODEV_ITS:
 841                 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
 842                 break;
 843         }
 844
 845         vgic_data_host_to_mmio_bus(val, len, data);
 846         return 0;
 847 }
 848
 849 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 850                                gpa_t addr, int len, const void *val)
 851 {
 852         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 853         const struct vgic_register_region *region;
 854         unsigned long data = vgic_data_mmio_bus_to_host(val, len);
 855
 856         region = vgic_get_mmio_region(vcpu, iodev, addr, len);
 857         if (!region)
 858                 return 0;
 859
 860         switch (iodev->iodev_type) {
 861         case IODEV_CPUIF:
 862                 region->write(vcpu, addr, len, data);
 863                 break;
 864         case IODEV_DIST:
 865                 region->write(vcpu, addr, len, data);
 866                 break;
 867         case IODEV_REDIST:
 868                 region->write(iodev->redist_vcpu, addr, len, data);
 869                 break;
 870         case IODEV_ITS:
 871                 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
 872                 break;
 873         }
 874
 875         return 0;
 876 }
 877
 878 struct kvm_io_device_ops kvm_io_gic_ops = {
 879         .read = dispatch_mmio_read,
 880         .write = dispatch_mmio_write,
 881 };
 882
 883 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
 884                              enum vgic_type type)
 885 {
 886         struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
 887         int ret = 0;
 888         unsigned int len;
 889
 890         switch (type) {
 891         case VGIC_V2:
 892                 len = vgic_v2_init_dist_iodev(io_device);
 893                 break;
 894         case VGIC_V3:
 895                 len = vgic_v3_init_dist_iodev(io_device);
 896                 break;
 897         default:
 898                 BUG_ON(1);
 899         }
 900
 901         io_device->base_addr = dist_base_address;
 902         io_device->iodev_type = IODEV_DIST;
 903         io_device->redist_vcpu = NULL;
 904
 905         mutex_lock(&kvm->slots_lock);
 906         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
 907                                       len, &io_device->dev);
 908         mutex_unlock(&kvm->slots_lock);
 909
 910         return ret;
 911 }