2 * VGIC MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/bsearch.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/iodev.h>
19 #include <kvm/arm_vgic.h>
22 #include "vgic-mmio.h"
24 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
25 gpa_t addr, unsigned int len)
30 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
31 gpa_t addr, unsigned int len)
36 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
37 unsigned int len, unsigned long val)
43 * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
44 * of the enabled bit, so there is only one function for both here.
46 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
47 gpa_t addr, unsigned int len)
49 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
53 /* Loop over all IRQs affected by this read */
54 for (i = 0; i < len * 8; i++) {
55 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
60 vgic_put_irq(vcpu->kvm, irq);
66 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
67 gpa_t addr, unsigned int len,
70 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
73 for_each_set_bit(i, &val, len * 8) {
74 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
76 spin_lock(&irq->irq_lock);
78 vgic_queue_irq_unlock(vcpu->kvm, irq);
80 vgic_put_irq(vcpu->kvm, irq);
84 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
85 gpa_t addr, unsigned int len,
88 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
91 for_each_set_bit(i, &val, len * 8) {
92 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
94 spin_lock(&irq->irq_lock);
98 spin_unlock(&irq->irq_lock);
99 vgic_put_irq(vcpu->kvm, irq);
103 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
104 gpa_t addr, unsigned int len)
106 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
110 /* Loop over all IRQs affected by this read */
111 for (i = 0; i < len * 8; i++) {
112 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
115 spin_lock_irqsave(&irq->irq_lock, flags);
116 if (irq_is_pending(irq))
118 spin_unlock_irqrestore(&irq->irq_lock, flags);
120 vgic_put_irq(vcpu->kvm, irq);
126 static bool is_vgic_v2_sgi(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
128 return (vgic_irq_is_sgi(irq->intid) &&
129 vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2);
132 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
133 gpa_t addr, unsigned int len,
136 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
139 for_each_set_bit(i, &val, len * 8) {
140 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
142 /* GICD_ISPENDR0 SGI bits are WI */
143 if (is_vgic_v2_sgi(vcpu, irq)) {
144 vgic_put_irq(vcpu->kvm, irq);
148 spin_lock(&irq->irq_lock);
149 irq->pending_latch = true;
151 vgic_queue_irq_unlock(vcpu->kvm, irq);
152 vgic_put_irq(vcpu->kvm, irq);
156 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
157 gpa_t addr, unsigned int len,
160 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
163 for_each_set_bit(i, &val, len * 8) {
164 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
166 /* GICD_ICPENDR0 SGI bits are WI */
167 if (is_vgic_v2_sgi(vcpu, irq)) {
168 vgic_put_irq(vcpu->kvm, irq);
172 spin_lock(&irq->irq_lock);
174 irq->pending_latch = false;
176 spin_unlock(&irq->irq_lock);
177 vgic_put_irq(vcpu->kvm, irq);
181 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
182 gpa_t addr, unsigned int len)
184 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
188 /* Loop over all IRQs affected by this read */
189 for (i = 0; i < len * 8; i++) {
190 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
195 vgic_put_irq(vcpu->kvm, irq);
201 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
202 bool new_active_state)
204 struct kvm_vcpu *requester_vcpu;
205 spin_lock(&irq->irq_lock);
208 * The vcpu parameter here can mean multiple things depending on how
209 * this function is called; when handling a trap from the kernel it
210 * depends on the GIC version, and these functions are also called as
211 * part of save/restore from userspace.
213 * Therefore, we have to figure out the requester in a reliable way.
215 * When accessing VGIC state from user space, the requester_vcpu is
216 * NULL, which is fine, because we guarantee that no VCPUs are running
217 * when accessing VGIC state from user space so irq->vcpu->cpu is
220 requester_vcpu = kvm_arm_get_running_vcpu();
223 * If this virtual IRQ was written into a list register, we
224 * have to make sure the CPU that runs the VCPU thread has
225 * synced back the LR state to the struct vgic_irq.
227 * As long as the conditions below are true, we know the VCPU thread
228 * may be on its way back from the guest (we kicked the VCPU thread in
229 * vgic_change_active_prepare) and still has to sync back this IRQ,
230 * so we release and re-acquire the spin_lock to let the other thread
233 while (irq->vcpu && /* IRQ may have state in an LR somewhere */
234 irq->vcpu != requester_vcpu && /* Current thread is not the VCPU thread */
235 irq->vcpu->cpu != -1) /* VCPU thread is running */
236 cond_resched_lock(&irq->irq_lock);
238 irq->active = new_active_state;
239 if (new_active_state)
240 vgic_queue_irq_unlock(vcpu->kvm, irq);
242 spin_unlock(&irq->irq_lock);
246 * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
247 * is not queued on some running VCPU's LRs, because then the change to the
248 * active state can be overwritten when the VCPU's state is synced coming back
251 * For shared interrupts, we have to stop all the VCPUs because interrupts can
252 * be migrated while we don't hold the IRQ locks and we don't want to be
253 * chasing moving targets.
255 * For private interrupts we don't have to do anything because userspace
256 * accesses to the VGIC state already require all VCPUs to be stopped, and
257 * only the VCPU itself can modify its private interrupts active state, which
258 * guarantees that the VCPU is not running.
260 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
262 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
263 intid >= VGIC_NR_PRIVATE_IRQS)
264 kvm_arm_halt_guest(vcpu->kvm);
267 /* See vgic_change_active_prepare */
268 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
270 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
271 intid >= VGIC_NR_PRIVATE_IRQS)
272 kvm_arm_resume_guest(vcpu->kvm);
275 static void __vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
276 gpa_t addr, unsigned int len,
279 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
282 for_each_set_bit(i, &val, len * 8) {
283 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
284 vgic_mmio_change_active(vcpu, irq, false);
285 vgic_put_irq(vcpu->kvm, irq);
289 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
290 gpa_t addr, unsigned int len,
293 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
295 mutex_lock(&vcpu->kvm->lock);
296 vgic_change_active_prepare(vcpu, intid);
298 __vgic_mmio_write_cactive(vcpu, addr, len, val);
300 vgic_change_active_finish(vcpu, intid);
301 mutex_unlock(&vcpu->kvm->lock);
304 void vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
305 gpa_t addr, unsigned int len,
308 __vgic_mmio_write_cactive(vcpu, addr, len, val);
311 static void __vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
312 gpa_t addr, unsigned int len,
315 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
318 for_each_set_bit(i, &val, len * 8) {
319 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
320 vgic_mmio_change_active(vcpu, irq, true);
321 vgic_put_irq(vcpu->kvm, irq);
325 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
326 gpa_t addr, unsigned int len,
329 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
331 mutex_lock(&vcpu->kvm->lock);
332 vgic_change_active_prepare(vcpu, intid);
334 __vgic_mmio_write_sactive(vcpu, addr, len, val);
336 vgic_change_active_finish(vcpu, intid);
337 mutex_unlock(&vcpu->kvm->lock);
340 void vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
341 gpa_t addr, unsigned int len,
344 __vgic_mmio_write_sactive(vcpu, addr, len, val);
347 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
348 gpa_t addr, unsigned int len)
350 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
354 for (i = 0; i < len; i++) {
355 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
357 val |= (u64)irq->priority << (i * 8);
359 vgic_put_irq(vcpu->kvm, irq);
366 * We currently don't handle changing the priority of an interrupt that
367 * is already pending on a VCPU. If there is a need for this, we would
368 * need to make this VCPU exit and re-evaluate the priorities, potentially
369 * leading to this interrupt getting presented now to the guest (if it has
370 * been masked by the priority mask before).
372 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
373 gpa_t addr, unsigned int len,
376 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
379 for (i = 0; i < len; i++) {
380 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
382 spin_lock(&irq->irq_lock);
383 /* Narrow the priority range to what we actually support */
384 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
385 spin_unlock(&irq->irq_lock);
387 vgic_put_irq(vcpu->kvm, irq);
391 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
392 gpa_t addr, unsigned int len)
394 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
398 for (i = 0; i < len * 4; i++) {
399 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
401 if (irq->config == VGIC_CONFIG_EDGE)
402 value |= (2U << (i * 2));
404 vgic_put_irq(vcpu->kvm, irq);
410 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
411 gpa_t addr, unsigned int len,
414 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
417 for (i = 0; i < len * 4; i++) {
418 struct vgic_irq *irq;
421 * The configuration cannot be changed for SGIs in general,
422 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
423 * code relies on PPIs being level triggered, so we also
424 * make them read-only here.
426 if (intid + i < VGIC_NR_PRIVATE_IRQS)
429 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
430 spin_lock(&irq->irq_lock);
432 if (test_bit(i * 2 + 1, &val))
433 irq->config = VGIC_CONFIG_EDGE;
435 irq->config = VGIC_CONFIG_LEVEL;
437 spin_unlock(&irq->irq_lock);
438 vgic_put_irq(vcpu->kvm, irq);
442 u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
446 int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
448 for (i = 0; i < 32; i++) {
449 struct vgic_irq *irq;
451 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
454 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
455 if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
458 vgic_put_irq(vcpu->kvm, irq);
464 void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
468 int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
470 for (i = 0; i < 32; i++) {
471 struct vgic_irq *irq;
474 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
477 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
480 * Line level is set irrespective of irq type
481 * (level or edge) to avoid dependency that VM should
482 * restore irq config before line level.
484 new_level = !!(val & (1U << i));
485 spin_lock(&irq->irq_lock);
486 irq->line_level = new_level;
488 vgic_queue_irq_unlock(vcpu->kvm, irq);
490 spin_unlock(&irq->irq_lock);
492 vgic_put_irq(vcpu->kvm, irq);
496 static int match_region(const void *key, const void *elt)
498 const unsigned int offset = (unsigned long)key;
499 const struct vgic_register_region *region = elt;
501 if (offset < region->reg_offset)
504 if (offset >= region->reg_offset + region->len)
510 const struct vgic_register_region *
511 vgic_find_mmio_region(const struct vgic_register_region *regions,
512 int nr_regions, unsigned int offset)
514 return bsearch((void *)(uintptr_t)offset, regions, nr_regions,
515 sizeof(regions[0]), match_region);
518 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
520 if (kvm_vgic_global_state.type == VGIC_V2)
521 vgic_v2_set_vmcr(vcpu, vmcr);
523 vgic_v3_set_vmcr(vcpu, vmcr);
526 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
528 if (kvm_vgic_global_state.type == VGIC_V2)
529 vgic_v2_get_vmcr(vcpu, vmcr);
531 vgic_v3_get_vmcr(vcpu, vmcr);
535 * kvm_mmio_read_buf() returns a value in a format where it can be converted
536 * to a byte array and be directly observed as the guest wanted it to appear
537 * in memory if it had done the store itself, which is LE for the GIC, as the
538 * guest knows the GIC is always LE.
540 * We convert this value to the CPUs native format to deal with it as a data
543 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
545 unsigned long data = kvm_mmio_read_buf(val, len);
551 return le16_to_cpu(data);
553 return le32_to_cpu(data);
555 return le64_to_cpu(data);
560 * kvm_mmio_write_buf() expects a value in a format such that if converted to
561 * a byte array it is observed as the guest would see it if it could perform
562 * the load directly. Since the GIC is LE, and the guest knows this, the
563 * guest expects a value in little endian format.
565 * We convert the data value from the CPUs native format to LE so that the
566 * value is returned in the proper format.
568 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
575 data = cpu_to_le16(data);
578 data = cpu_to_le32(data);
581 data = cpu_to_le64(data);
584 kvm_mmio_write_buf(buf, len, data);
588 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
590 return container_of(dev, struct vgic_io_device, dev);
593 static bool check_region(const struct kvm *kvm,
594 const struct vgic_register_region *region,
597 int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
601 flags = VGIC_ACCESS_8bit;
604 flags = VGIC_ACCESS_32bit;
607 flags = VGIC_ACCESS_64bit;
613 if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
614 if (!region->bits_per_irq)
617 /* Do we access a non-allocated IRQ? */
618 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
624 const struct vgic_register_region *
625 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
628 const struct vgic_register_region *region;
630 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
631 addr - iodev->base_addr);
632 if (!region || !check_region(vcpu->kvm, region, addr, len))
638 static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
639 gpa_t addr, u32 *val)
641 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
642 const struct vgic_register_region *region;
643 struct kvm_vcpu *r_vcpu;
645 region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
651 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
652 if (region->uaccess_read)
653 *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
655 *val = region->read(r_vcpu, addr, sizeof(u32));
660 static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
661 gpa_t addr, const u32 *val)
663 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
664 const struct vgic_register_region *region;
665 struct kvm_vcpu *r_vcpu;
667 region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
671 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
672 if (region->uaccess_write)
673 region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
675 region->write(r_vcpu, addr, sizeof(u32), *val);
681 * Userland access to VGIC registers.
683 int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
684 bool is_write, int offset, u32 *val)
687 return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
689 return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
692 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
693 gpa_t addr, int len, void *val)
695 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
696 const struct vgic_register_region *region;
697 unsigned long data = 0;
699 region = vgic_get_mmio_region(vcpu, iodev, addr, len);
705 switch (iodev->iodev_type) {
707 data = region->read(vcpu, addr, len);
710 data = region->read(vcpu, addr, len);
713 data = region->read(iodev->redist_vcpu, addr, len);
716 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
720 vgic_data_host_to_mmio_bus(val, len, data);
724 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
725 gpa_t addr, int len, const void *val)
727 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
728 const struct vgic_register_region *region;
729 unsigned long data = vgic_data_mmio_bus_to_host(val, len);
731 region = vgic_get_mmio_region(vcpu, iodev, addr, len);
735 switch (iodev->iodev_type) {
737 region->write(vcpu, addr, len, data);
740 region->write(vcpu, addr, len, data);
743 region->write(iodev->redist_vcpu, addr, len, data);
746 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
753 struct kvm_io_device_ops kvm_io_gic_ops = {
754 .read = dispatch_mmio_read,
755 .write = dispatch_mmio_write,
758 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
761 struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
767 len = vgic_v2_init_dist_iodev(io_device);
770 len = vgic_v3_init_dist_iodev(io_device);
776 io_device->base_addr = dist_base_address;
777 io_device->iodev_type = IODEV_DIST;
778 io_device->redist_vcpu = NULL;
780 mutex_lock(&kvm->slots_lock);
781 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
782 len, &io_device->dev);
783 mutex_unlock(&kvm->slots_lock);