virt/kvm/arm/vgic/vgic-v2.c

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/irqchip/arm-gic.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_host.h>
  20 #include <kvm/arm_vgic.h>
  21 #include <asm/kvm_mmu.h>
  22
  23 #include "vgic.h"
  24
  25 static inline void vgic_v2_write_lr(int lr, u32 val)
  26 {
  27         void __iomem *base = kvm_vgic_global_state.vctrl_base;
  28
  29         writel_relaxed(val, base + GICH_LR0 + (lr * 4));
  30 }
  31
  32 void vgic_v2_init_lrs(void)
  33 {
  34         int i;
  35
  36         for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
  37                 vgic_v2_write_lr(i, 0);
  38 }
  39
  40 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
  41 {
  42         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  43
  44         cpuif->vgic_hcr |= GICH_HCR_UIE;
  45 }
  46
  47 static bool lr_signals_eoi_mi(u32 lr_val)
  48 {
  49         return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
  50                !(lr_val & GICH_LR_HW);
  51 }
  52
  53 /*
  54  * transfer the content of the LRs back into the corresponding ap_list:
  55  * - active bit is transferred as is
  56  * - pending bit is
  57  *   - transferred as is in case of edge sensitive IRQs
  58  *   - set to the line-level (resample time) for level sensitive IRQs
  59  */
  60 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
  61 {
  62         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  63         struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
  64         int lr;
  65
  66         DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
  67
  68         cpuif->vgic_hcr &= ~GICH_HCR_UIE;
  69
  70         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  71                 u32 val = cpuif->vgic_lr[lr];
  72                 u32 cpuid, intid = val & GICH_LR_VIRTUALID;
  73                 struct vgic_irq *irq;
  74
  75                 /* Extract the source vCPU id from the LR */
  76                 cpuid = val & GICH_LR_PHYSID_CPUID;
  77                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  78                 cpuid &= 7;
  79
  80                 /* Notify fds when the guest EOI'ed a level-triggered SPI */
  81                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  82                         kvm_notify_acked_irq(vcpu->kvm, 0,
  83                                              intid - VGIC_NR_PRIVATE_IRQS);
  84
  85                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  86
  87                 spin_lock(&irq->irq_lock);
  88
  89                 /* Always preserve the active bit */
  90                 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
  91
  92                 if (irq->active && vgic_irq_is_sgi(intid))
  93                         irq->active_source = cpuid;
  94
  95                 /* Edge is the only case where we preserve the pending bit */
  96                 if (irq->config == VGIC_CONFIG_EDGE &&
  97                     (val & GICH_LR_PENDING_BIT)) {
  98                         irq->pending_latch = true;
  99
 100                         if (vgic_irq_is_sgi(intid))
 101                                 irq->source |= (1 << cpuid);
 102                 }
 103
 104                 /*
 105                  * Clear soft pending state when level irqs have been acked.
 106                  */
 107                 if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))
 108                         irq->pending_latch = false;
 109
 110                 /*
 111                  * Level-triggered mapped IRQs are special because we only
 112                  * observe rising edges as input to the VGIC.
 113                  *
 114                  * If the guest never acked the interrupt we have to sample
 115                  * the physical line and set the line level, because the
 116                  * device state could have changed or we simply need to
 117                  * process the still pending interrupt later.
 118                  *
 119                  * If this causes us to lower the level, we have to also clear
 120                  * the physical active state, since we will otherwise never be
 121                  * told when the interrupt becomes asserted again.
 122                  */
 123                 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) {
 124                         irq->line_level = vgic_get_phys_line_level(irq);
 125
 126                         if (!irq->line_level)
 127                                 vgic_irq_set_phys_active(irq, false);
 128                 }
 129
 130                 spin_unlock(&irq->irq_lock);
 131                 vgic_put_irq(vcpu->kvm, irq);
 132         }
 133
 134         vgic_cpu->used_lrs = 0;
 135 }
 136
 137 /*
 138  * Populates the particular LR with the state of a given IRQ:
 139  * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 140  * - for a level sensitive IRQ the pending state value is unchanged;
 141  *   it is dictated directly by the input level
 142  *
 143  * If @irq describes an SGI with multiple sources, we choose the
 144  * lowest-numbered source VCPU and clear that bit in the source bitmap.
 145  *
 146  * The irq_lock must be held by the caller.
 147  */
 148 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 149 {
 150         u32 val = irq->intid;
 151         bool allow_pending = true;
 152
 153         if (irq->active) {
 154                 val |= GICH_LR_ACTIVE_BIT;
 155                 if (vgic_irq_is_sgi(irq->intid))
 156                         val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
 157                 if (vgic_irq_is_multi_sgi(irq)) {
 158                         allow_pending = false;
 159                         val |= GICH_LR_EOI;
 160                 }
 161         }
 162
 163         if (irq->group)
 164                 val |= GICH_LR_GROUP1;
 165
 166         if (irq->hw) {
 167                 val |= GICH_LR_HW;
 168                 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
 169                 /*
 170                  * Never set pending+active on a HW interrupt, as the
 171                  * pending state is kept at the physical distributor
 172                  * level.
 173                  */
 174                 if (irq->active)
 175                         allow_pending = false;
 176         } else {
 177                 if (irq->config == VGIC_CONFIG_LEVEL) {
 178                         val |= GICH_LR_EOI;
 179
 180                         /*
 181                          * Software resampling doesn't work very well
 182                          * if we allow P+A, so let's not do that.
 183                          */
 184                         if (irq->active)
 185                                 allow_pending = false;
 186                 }
 187         }
 188
 189         if (allow_pending && irq_is_pending(irq)) {
 190                 val |= GICH_LR_PENDING_BIT;
 191
 192                 if (irq->config == VGIC_CONFIG_EDGE)
 193                         irq->pending_latch = false;
 194
 195                 if (vgic_irq_is_sgi(irq->intid)) {
 196                         u32 src = ffs(irq->source);
 197
 198                         if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
 199                                            irq->intid))
 200                                 return;
 201
 202                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 203                         irq->source &= ~(1 << (src - 1));
 204                         if (irq->source) {
 205                                 irq->pending_latch = true;
 206                                 val |= GICH_LR_EOI;
 207                         }
 208                 }
 209         }
 210
 211         /*
 212          * Level-triggered mapped IRQs are special because we only observe
 213          * rising edges as input to the VGIC.  We therefore lower the line
 214          * level here, so that we can take new virtual IRQs.  See
 215          * vgic_v2_fold_lr_state for more info.
 216          */
 217         if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
 218                 irq->line_level = false;
 219
 220         /* The GICv2 LR only holds five bits of priority. */
 221         val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
 222
 223         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
 224 }
 225
 226 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
 227 {
 228         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
 229 }
 230
 231 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 232 {
 233         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 234         u32 vmcr;
 235
 236         vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
 237                 GICH_VMCR_ENABLE_GRP0_MASK;
 238         vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
 239                 GICH_VMCR_ENABLE_GRP1_MASK;
 240         vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
 241                 GICH_VMCR_ACK_CTL_MASK;
 242         vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
 243                 GICH_VMCR_FIQ_EN_MASK;
 244         vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
 245                 GICH_VMCR_CBPR_MASK;
 246         vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
 247                 GICH_VMCR_EOI_MODE_MASK;
 248         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
 249                 GICH_VMCR_ALIAS_BINPOINT_MASK;
 250         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
 251                 GICH_VMCR_BINPOINT_MASK;
 252         vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
 253                  GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
 254
 255         cpu_if->vgic_vmcr = vmcr;
 256 }
 257
 258 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 259 {
 260         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 261         u32 vmcr;
 262
 263         vmcr = cpu_if->vgic_vmcr;
 264
 265         vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
 266                 GICH_VMCR_ENABLE_GRP0_SHIFT;
 267         vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
 268                 GICH_VMCR_ENABLE_GRP1_SHIFT;
 269         vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
 270                 GICH_VMCR_ACK_CTL_SHIFT;
 271         vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
 272                 GICH_VMCR_FIQ_EN_SHIFT;
 273         vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
 274                 GICH_VMCR_CBPR_SHIFT;
 275         vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
 276                 GICH_VMCR_EOI_MODE_SHIFT;
 277
 278         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
 279                         GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 280         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
 281                         GICH_VMCR_BINPOINT_SHIFT;
 282         vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
 283                         GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
 284 }
 285
 286 void vgic_v2_enable(struct kvm_vcpu *vcpu)
 287 {
 288         /*
 289          * By forcing VMCR to zero, the GIC will restore the binary
 290          * points to their reset values. Anything else resets to zero
 291          * anyway.
 292          */
 293         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 294
 295         /* Get the show on the road... */
 296         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 297 }
 298
 299 /* check for overlapping regions and for regions crossing the end of memory */
 300 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
 301 {
 302         if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
 303                 return false;
 304         if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
 305                 return false;
 306
 307         if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
 308                 return true;
 309         if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
 310                 return true;
 311
 312         return false;
 313 }
 314
 315 int vgic_v2_map_resources(struct kvm *kvm)
 316 {
 317         struct vgic_dist *dist = &kvm->arch.vgic;
 318         int ret = 0;
 319
 320         if (vgic_ready(kvm))
 321                 goto out;
 322
 323         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 324             IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
 325                 kvm_err("Need to set vgic cpu and dist addresses first\n");
 326                 ret = -ENXIO;
 327                 goto out;
 328         }
 329
 330         if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
 331                 kvm_err("VGIC CPU and dist frames overlap\n");
 332                 ret = -EINVAL;
 333                 goto out;
 334         }
 335
 336         /*
 337          * Initialize the vgic if this hasn't already been done on demand by
 338          * accessing the vgic state from userspace.
 339          */
 340         ret = vgic_init(kvm);
 341         if (ret) {
 342                 kvm_err("Unable to initialize VGIC dynamic data structures\n");
 343                 goto out;
 344         }
 345
 346         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
 347         if (ret) {
 348                 kvm_err("Unable to register VGIC MMIO regions\n");
 349                 goto out;
 350         }
 351
 352         if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 353                 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
 354                                             kvm_vgic_global_state.vcpu_base,
 355                                             KVM_VGIC_V2_CPU_SIZE, true);
 356                 if (ret) {
 357                         kvm_err("Unable to remap VGIC CPU to VCPU\n");
 358                         goto out;
 359                 }
 360         }
 361
 362         dist->ready = true;
 363
 364 out:
 365         return ret;
 366 }
 367
 368 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
 369
 370 /**
 371  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 372  * @node:       pointer to the DT node
 373  *
 374  * Returns 0 if a GICv2 has been found, returns an error code otherwise
 375  */
 376 int vgic_v2_probe(const struct gic_kvm_info *info)
 377 {
 378         int ret;
 379         u32 vtr;
 380
 381         if (!info->vctrl.start) {
 382                 kvm_err("GICH not present in the firmware table\n");
 383                 return -ENXIO;
 384         }
 385
 386         if (!PAGE_ALIGNED(info->vcpu.start) ||
 387             !PAGE_ALIGNED(resource_size(&info->vcpu))) {
 388                 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
 389
 390                 ret = create_hyp_io_mappings(info->vcpu.start,
 391                                              resource_size(&info->vcpu),
 392                                              &kvm_vgic_global_state.vcpu_base_va,
 393                                              &kvm_vgic_global_state.vcpu_hyp_va);
 394                 if (ret) {
 395                         kvm_err("Cannot map GICV into hyp\n");
 396                         goto out;
 397                 }
 398
 399                 static_branch_enable(&vgic_v2_cpuif_trap);
 400         }
 401
 402         ret = create_hyp_io_mappings(info->vctrl.start,
 403                                      resource_size(&info->vctrl),
 404                                      &kvm_vgic_global_state.vctrl_base,
 405                                      &kvm_vgic_global_state.vctrl_hyp);
 406         if (ret) {
 407                 kvm_err("Cannot map VCTRL into hyp\n");
 408                 goto out;
 409         }
 410
 411         vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
 412         kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
 413
 414         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 415         if (ret) {
 416                 kvm_err("Cannot register GICv2 KVM device\n");
 417                 goto out;
 418         }
 419
 420         kvm_vgic_global_state.can_emulate_gicv2 = true;
 421         kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 422         kvm_vgic_global_state.type = VGIC_V2;
 423         kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
 424
 425         kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
 426
 427         return 0;
 428 out:
 429         if (kvm_vgic_global_state.vctrl_base)
 430                 iounmap(kvm_vgic_global_state.vctrl_base);
 431         if (kvm_vgic_global_state.vcpu_base_va)
 432                 iounmap(kvm_vgic_global_state.vcpu_base_va);
 433
 434         return ret;
 435 }
 436
 437 static void save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
 438 {
 439         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 440         u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 441         u64 elrsr;
 442         int i;
 443
 444         elrsr = readl_relaxed(base + GICH_ELRSR0);
 445         if (unlikely(used_lrs > 32))
 446                 elrsr |= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32;
 447
 448         for (i = 0; i < used_lrs; i++) {
 449                 if (elrsr & (1UL << i))
 450                         cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
 451                 else
 452                         cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
 453
 454                 writel_relaxed(0, base + GICH_LR0 + (i * 4));
 455         }
 456 }
 457
 458 void vgic_v2_save_state(struct kvm_vcpu *vcpu)
 459 {
 460         void __iomem *base = kvm_vgic_global_state.vctrl_base;
 461         u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 462
 463         if (!base)
 464                 return;
 465
 466         if (used_lrs) {
 467                 save_lrs(vcpu, base);
 468                 writel_relaxed(0, base + GICH_HCR);
 469         }
 470 }
 471
 472 void vgic_v2_restore_state(struct kvm_vcpu *vcpu)
 473 {
 474         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 475         void __iomem *base = kvm_vgic_global_state.vctrl_base;
 476         u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 477         int i;
 478
 479         if (!base)
 480                 return;
 481
 482         if (used_lrs) {
 483                 writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
 484                 for (i = 0; i < used_lrs; i++) {
 485                         writel_relaxed(cpu_if->vgic_lr[i],
 486                                        base + GICH_LR0 + (i * 4));
 487                 }
 488         }
 489 }
 490
 491 void vgic_v2_load(struct kvm_vcpu *vcpu)
 492 {
 493         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 494
 495         writel_relaxed(cpu_if->vgic_vmcr,
 496                        kvm_vgic_global_state.vctrl_base + GICH_VMCR);
 497         writel_relaxed(cpu_if->vgic_apr,
 498                        kvm_vgic_global_state.vctrl_base + GICH_APR);
 499 }
 500
 501 void vgic_v2_vmcr_sync(struct kvm_vcpu *vcpu)
 502 {
 503         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 504
 505         cpu_if->vgic_vmcr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VMCR);
 506 }
 507
 508 void vgic_v2_put(struct kvm_vcpu *vcpu)
 509 {
 510         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 511
 512         vgic_v2_vmcr_sync(vcpu);
 513         cpu_if->vgic_apr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_APR);
 514 }