arch/arm64/boot/dts/qcom/sm8550.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2022, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/clock/qcom,rpmh.h>
   7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
   8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
   9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
  10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
  11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
  12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
  13 #include <dt-bindings/dma/qcom-gpi.h>
  14 #include <dt-bindings/firmware/qcom,scm.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
  18 #include <dt-bindings/mailbox/qcom-ipcc.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/power/qcom,rpmhpd.h>
  21 #include <dt-bindings/soc/qcom,gpr.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  24 #include <dt-bindings/phy/phy-qcom-qmp.h>
  25 #include <dt-bindings/thermal/thermal.h>
  26
  27 / {
  28         interrupt-parent = <&intc>;
  29
  30         #address-cells = <2>;
  31         #size-cells = <2>;
  32
  33         chosen { };
  34
  35         clocks {
  36                 xo_board: xo-board {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                 };
  40
  41                 sleep_clk: sleep-clk {
  42                         compatible = "fixed-clock";
  43                         #clock-cells = <0>;
  44                 };
  45
  46                 bi_tcxo_div2: bi-tcxo-div2-clk {
  47                         #clock-cells = <0>;
  48                         compatible = "fixed-factor-clock";
  49                         clocks = <&rpmhcc RPMH_CXO_CLK>;
  50                         clock-mult = <1>;
  51                         clock-div = <2>;
  52                 };
  53
  54                 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
  55                         #clock-cells = <0>;
  56                         compatible = "fixed-factor-clock";
  57                         clocks = <&rpmhcc RPMH_CXO_CLK_A>;
  58                         clock-mult = <1>;
  59                         clock-div = <2>;
  60                 };
  61
  62                 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
  63                         compatible = "fixed-clock";
  64                         #clock-cells = <0>;
  65                 };
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 CPU0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a510";
  75                         reg = <0 0>;
  76                         clocks = <&cpufreq_hw 0>;
  77                         enable-method = "psci";
  78                         next-level-cache = <&L2_0>;
  79                         power-domains = <&CPU_PD0>;
  80                         power-domain-names = "psci";
  81                         qcom,freq-domain = <&cpufreq_hw 0>;
  82                         capacity-dmips-mhz = <1024>;
  83                         dynamic-power-coefficient = <100>;
  84                         #cooling-cells = <2>;
  85                         L2_0: l2-cache {
  86                                 compatible = "cache";
  87                                 cache-level = <2>;
  88                                 cache-unified;
  89                                 next-level-cache = <&L3_0>;
  90                                 L3_0: l3-cache {
  91                                         compatible = "cache";
  92                                         cache-level = <3>;
  93                                         cache-unified;
  94                                 };
  95                         };
  96                 };
  97
  98                 CPU1: cpu@100 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a510";
 101                         reg = <0 0x100>;
 102                         clocks = <&cpufreq_hw 0>;
 103                         enable-method = "psci";
 104                         next-level-cache = <&L2_100>;
 105                         power-domains = <&CPU_PD1>;
 106                         power-domain-names = "psci";
 107                         qcom,freq-domain = <&cpufreq_hw 0>;
 108                         capacity-dmips-mhz = <1024>;
 109                         dynamic-power-coefficient = <100>;
 110                         #cooling-cells = <2>;
 111                         L2_100: l2-cache {
 112                                 compatible = "cache";
 113                                 cache-level = <2>;
 114                                 cache-unified;
 115                                 next-level-cache = <&L3_0>;
 116                         };
 117                 };
 118
 119                 CPU2: cpu@200 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a510";
 122                         reg = <0 0x200>;
 123                         clocks = <&cpufreq_hw 0>;
 124                         enable-method = "psci";
 125                         next-level-cache = <&L2_200>;
 126                         power-domains = <&CPU_PD2>;
 127                         power-domain-names = "psci";
 128                         qcom,freq-domain = <&cpufreq_hw 0>;
 129                         capacity-dmips-mhz = <1024>;
 130                         dynamic-power-coefficient = <100>;
 131                         #cooling-cells = <2>;
 132                         L2_200: l2-cache {
 133                                 compatible = "cache";
 134                                 cache-level = <2>;
 135                                 cache-unified;
 136                                 next-level-cache = <&L3_0>;
 137                         };
 138                 };
 139
 140                 CPU3: cpu@300 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a715";
 143                         reg = <0 0x300>;
 144                         clocks = <&cpufreq_hw 1>;
 145                         enable-method = "psci";
 146                         next-level-cache = <&L2_300>;
 147                         power-domains = <&CPU_PD3>;
 148                         power-domain-names = "psci";
 149                         qcom,freq-domain = <&cpufreq_hw 1>;
 150                         capacity-dmips-mhz = <1792>;
 151                         dynamic-power-coefficient = <270>;
 152                         #cooling-cells = <2>;
 153                         L2_300: l2-cache {
 154                                 compatible = "cache";
 155                                 cache-level = <2>;
 156                                 cache-unified;
 157                                 next-level-cache = <&L3_0>;
 158                         };
 159                 };
 160
 161                 CPU4: cpu@400 {
 162                         device_type = "cpu";
 163                         compatible = "arm,cortex-a715";
 164                         reg = <0 0x400>;
 165                         clocks = <&cpufreq_hw 1>;
 166                         enable-method = "psci";
 167                         next-level-cache = <&L2_400>;
 168                         power-domains = <&CPU_PD4>;
 169                         power-domain-names = "psci";
 170                         qcom,freq-domain = <&cpufreq_hw 1>;
 171                         capacity-dmips-mhz = <1792>;
 172                         dynamic-power-coefficient = <270>;
 173                         #cooling-cells = <2>;
 174                         L2_400: l2-cache {
 175                                 compatible = "cache";
 176                                 cache-level = <2>;
 177                                 cache-unified;
 178                                 next-level-cache = <&L3_0>;
 179                         };
 180                 };
 181
 182                 CPU5: cpu@500 {
 183                         device_type = "cpu";
 184                         compatible = "arm,cortex-a710";
 185                         reg = <0 0x500>;
 186                         clocks = <&cpufreq_hw 1>;
 187                         enable-method = "psci";
 188                         next-level-cache = <&L2_500>;
 189                         power-domains = <&CPU_PD5>;
 190                         power-domain-names = "psci";
 191                         qcom,freq-domain = <&cpufreq_hw 1>;
 192                         capacity-dmips-mhz = <1792>;
 193                         dynamic-power-coefficient = <270>;
 194                         #cooling-cells = <2>;
 195                         L2_500: l2-cache {
 196                                 compatible = "cache";
 197                                 cache-level = <2>;
 198                                 cache-unified;
 199                                 next-level-cache = <&L3_0>;
 200                         };
 201                 };
 202
 203                 CPU6: cpu@600 {
 204                         device_type = "cpu";
 205                         compatible = "arm,cortex-a710";
 206                         reg = <0 0x600>;
 207                         clocks = <&cpufreq_hw 1>;
 208                         enable-method = "psci";
 209                         next-level-cache = <&L2_600>;
 210                         power-domains = <&CPU_PD6>;
 211                         power-domain-names = "psci";
 212                         qcom,freq-domain = <&cpufreq_hw 1>;
 213                         capacity-dmips-mhz = <1792>;
 214                         dynamic-power-coefficient = <270>;
 215                         #cooling-cells = <2>;
 216                         L2_600: l2-cache {
 217                                 compatible = "cache";
 218                                 cache-level = <2>;
 219                                 cache-unified;
 220                                 next-level-cache = <&L3_0>;
 221                         };
 222                 };
 223
 224                 CPU7: cpu@700 {
 225                         device_type = "cpu";
 226                         compatible = "arm,cortex-x3";
 227                         reg = <0 0x700>;
 228                         clocks = <&cpufreq_hw 2>;
 229                         enable-method = "psci";
 230                         next-level-cache = <&L2_700>;
 231                         power-domains = <&CPU_PD7>;
 232                         power-domain-names = "psci";
 233                         qcom,freq-domain = <&cpufreq_hw 2>;
 234                         capacity-dmips-mhz = <1894>;
 235                         dynamic-power-coefficient = <588>;
 236                         #cooling-cells = <2>;
 237                         L2_700: l2-cache {
 238                                 compatible = "cache";
 239                                 cache-level = <2>;
 240                                 cache-unified;
 241                                 next-level-cache = <&L3_0>;
 242                         };
 243                 };
 244
 245                 cpu-map {
 246                         cluster0 {
 247                                 core0 {
 248                                         cpu = <&CPU0>;
 249                                 };
 250
 251                                 core1 {
 252                                         cpu = <&CPU1>;
 253                                 };
 254
 255                                 core2 {
 256                                         cpu = <&CPU2>;
 257                                 };
 258
 259                                 core3 {
 260                                         cpu = <&CPU3>;
 261                                 };
 262
 263                                 core4 {
 264                                         cpu = <&CPU4>;
 265                                 };
 266
 267                                 core5 {
 268                                         cpu = <&CPU5>;
 269                                 };
 270
 271                                 core6 {
 272                                         cpu = <&CPU6>;
 273                                 };
 274
 275                                 core7 {
 276                                         cpu = <&CPU7>;
 277                                 };
 278                         };
 279                 };
 280
 281                 idle-states {
 282                         entry-method = "psci";
 283
 284                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 285                                 compatible = "arm,idle-state";
 286                                 idle-state-name = "silver-rail-power-collapse";
 287                                 arm,psci-suspend-param = <0x40000004>;
 288                                 entry-latency-us = <800>;
 289                                 exit-latency-us = <750>;
 290                                 min-residency-us = <4090>;
 291                                 local-timer-stop;
 292                         };
 293
 294                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 295                                 compatible = "arm,idle-state";
 296                                 idle-state-name = "gold-rail-power-collapse";
 297                                 arm,psci-suspend-param = <0x40000004>;
 298                                 entry-latency-us = <600>;
 299                                 exit-latency-us = <1550>;
 300                                 min-residency-us = <4791>;
 301                                 local-timer-stop;
 302                         };
 303                 };
 304
 305                 domain-idle-states {
 306                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 307                                 compatible = "domain-idle-state";
 308                                 arm,psci-suspend-param = <0x41000044>;
 309                                 entry-latency-us = <1050>;
 310                                 exit-latency-us = <2500>;
 311                                 min-residency-us = <5309>;
 312                         };
 313
 314                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 315                                 compatible = "domain-idle-state";
 316                                 arm,psci-suspend-param = <0x4100c344>;
 317                                 entry-latency-us = <2700>;
 318                                 exit-latency-us = <3500>;
 319                                 min-residency-us = <13959>;
 320                         };
 321                 };
 322         };
 323
 324         firmware {
 325                 scm: scm {
 326                         compatible = "qcom,scm-sm8550", "qcom,scm";
 327                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 328                 };
 329         };
 330
 331         clk_virt: interconnect-0 {
 332                 compatible = "qcom,sm8550-clk-virt";
 333                 #interconnect-cells = <2>;
 334                 qcom,bcm-voters = <&apps_bcm_voter>;
 335         };
 336
 337         mc_virt: interconnect-1 {
 338                 compatible = "qcom,sm8550-mc-virt";
 339                 #interconnect-cells = <2>;
 340                 qcom,bcm-voters = <&apps_bcm_voter>;
 341         };
 342
 343         memory@a0000000 {
 344                 device_type = "memory";
 345                 /* We expect the bootloader to fill in the size */
 346                 reg = <0 0xa0000000 0 0>;
 347         };
 348
 349         pmu {
 350                 compatible = "arm,armv8-pmuv3";
 351                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 352         };
 353
 354         psci {
 355                 compatible = "arm,psci-1.0";
 356                 method = "smc";
 357
 358                 CPU_PD0: power-domain-cpu0 {
 359                         #power-domain-cells = <0>;
 360                         power-domains = <&CLUSTER_PD>;
 361                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 362                 };
 363
 364                 CPU_PD1: power-domain-cpu1 {
 365                         #power-domain-cells = <0>;
 366                         power-domains = <&CLUSTER_PD>;
 367                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 368                 };
 369
 370                 CPU_PD2: power-domain-cpu2 {
 371                         #power-domain-cells = <0>;
 372                         power-domains = <&CLUSTER_PD>;
 373                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 374                 };
 375
 376                 CPU_PD3: power-domain-cpu3 {
 377                         #power-domain-cells = <0>;
 378                         power-domains = <&CLUSTER_PD>;
 379                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 380                 };
 381
 382                 CPU_PD4: power-domain-cpu4 {
 383                         #power-domain-cells = <0>;
 384                         power-domains = <&CLUSTER_PD>;
 385                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 386                 };
 387
 388                 CPU_PD5: power-domain-cpu5 {
 389                         #power-domain-cells = <0>;
 390                         power-domains = <&CLUSTER_PD>;
 391                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 392                 };
 393
 394                 CPU_PD6: power-domain-cpu6 {
 395                         #power-domain-cells = <0>;
 396                         power-domains = <&CLUSTER_PD>;
 397                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 398                 };
 399
 400                 CPU_PD7: power-domain-cpu7 {
 401                         #power-domain-cells = <0>;
 402                         power-domains = <&CLUSTER_PD>;
 403                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 404                 };
 405
 406                 CLUSTER_PD: power-domain-cluster {
 407                         #power-domain-cells = <0>;
 408                         domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
 409                 };
 410         };
 411
 412         reserved_memory: reserved-memory {
 413                 #address-cells = <2>;
 414                 #size-cells = <2>;
 415                 ranges;
 416
 417                 hyp_mem: hyp-region@80000000 {
 418                         reg = <0 0x80000000 0 0xa00000>;
 419                         no-map;
 420                 };
 421
 422                 cpusys_vm_mem: cpusys-vm-region@80a00000 {
 423                         reg = <0 0x80a00000 0 0x400000>;
 424                         no-map;
 425                 };
 426
 427                 hyp_tags_mem: hyp-tags-region@80e00000 {
 428                         reg = <0 0x80e00000 0 0x3d0000>;
 429                         no-map;
 430                 };
 431
 432                 xbl_sc_mem: xbl-sc-region@d8100000 {
 433                         reg = <0 0xd8100000 0 0x40000>;
 434                         no-map;
 435                 };
 436
 437                 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
 438                         reg = <0 0x811d0000 0 0x30000>;
 439                         no-map;
 440                 };
 441
 442                 /* merged xbl_dt_log, xbl_ramdump, aop_image */
 443                 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
 444                         reg = <0 0x81a00000 0 0x260000>;
 445                         no-map;
 446                 };
 447
 448                 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
 449                         compatible = "qcom,cmd-db";
 450                         reg = <0 0x81c60000 0 0x20000>;
 451                         no-map;
 452                 };
 453
 454                 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */
 455                 aop_config_merged_mem: aop-config-merged-region@81c80000 {
 456                         reg = <0 0x81c80000 0 0x74000>;
 457                         no-map;
 458                 };
 459
 460                 /* secdata region can be reused by apps */
 461                 smem: smem@81d00000 {
 462                         compatible = "qcom,smem";
 463                         reg = <0 0x81d00000 0 0x200000>;
 464                         hwlocks = <&tcsr_mutex 3>;
 465                         no-map;
 466                 };
 467
 468                 adsp_mhi_mem: adsp-mhi-region@81f00000 {
 469                         reg = <0 0x81f00000 0 0x20000>;
 470                         no-map;
 471                 };
 472
 473                 global_sync_mem: global-sync-region@82600000 {
 474                         reg = <0 0x82600000 0 0x100000>;
 475                         no-map;
 476                 };
 477
 478                 tz_stat_mem: tz-stat-region@82700000 {
 479                         reg = <0 0x82700000 0 0x100000>;
 480                         no-map;
 481                 };
 482
 483                 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
 484                         reg = <0 0x82800000 0 0x4600000>;
 485                         no-map;
 486                 };
 487
 488                 mpss_mem: mpss-region@8a800000 {
 489                         reg = <0 0x8a800000 0 0x10800000>;
 490                         no-map;
 491                 };
 492
 493                 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
 494                         reg = <0 0x9b000000 0 0x80000>;
 495                         no-map;
 496                 };
 497
 498                 ipa_fw_mem: ipa-fw-region@9b080000 {
 499                         reg = <0 0x9b080000 0 0x10000>;
 500                         no-map;
 501                 };
 502
 503                 ipa_gsi_mem: ipa-gsi-region@9b090000 {
 504                         reg = <0 0x9b090000 0 0xa000>;
 505                         no-map;
 506                 };
 507
 508                 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
 509                         reg = <0 0x9b09a000 0 0x2000>;
 510                         no-map;
 511                 };
 512
 513                 spss_region_mem: spss-region@9b100000 {
 514                         reg = <0 0x9b100000 0 0x180000>;
 515                         no-map;
 516                 };
 517
 518                 /* First part of the "SPU secure shared memory" region */
 519                 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
 520                         reg = <0 0x9b280000 0 0x60000>;
 521                         no-map;
 522                 };
 523
 524                 /* Second part of the "SPU secure shared memory" region */
 525                 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
 526                         reg = <0 0x9b2e0000 0 0x20000>;
 527                         no-map;
 528                 };
 529
 530                 camera_mem: camera-region@9b300000 {
 531                         reg = <0 0x9b300000 0 0x800000>;
 532                         no-map;
 533                 };
 534
 535                 video_mem: video-region@9bb00000 {
 536                         reg = <0 0x9bb00000 0 0x700000>;
 537                         no-map;
 538                 };
 539
 540                 cvp_mem: cvp-region@9c200000 {
 541                         reg = <0 0x9c200000 0 0x700000>;
 542                         no-map;
 543                 };
 544
 545                 cdsp_mem: cdsp-region@9c900000 {
 546                         reg = <0 0x9c900000 0 0x2000000>;
 547                         no-map;
 548                 };
 549
 550                 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
 551                         reg = <0 0x9e900000 0 0x80000>;
 552                         no-map;
 553                 };
 554
 555                 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
 556                         reg = <0 0x9e980000 0 0x80000>;
 557                         no-map;
 558                 };
 559
 560                 adspslpi_mem: adspslpi-region@9ea00000 {
 561                         reg = <0 0x9ea00000 0 0x4080000>;
 562                         no-map;
 563                 };
 564
 565                 /* uefi region can be reused by apps */
 566
 567                 /* Linux kernel image is loaded at 0xa8000000 */
 568
 569                 rmtfs_mem: rmtfs-region@d4a80000 {
 570                         compatible = "qcom,rmtfs-mem";
 571                         reg = <0x0 0xd4a80000 0x0 0x280000>;
 572                         no-map;
 573
 574                         qcom,client-id = <1>;
 575                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 576                 };
 577
 578                 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
 579                         reg = <0 0xd4d00000 0 0x3300000>;
 580                         no-map;
 581                 };
 582
 583                 tz_reserved_mem: tz-reserved-region@d8000000 {
 584                         reg = <0 0xd8000000 0 0x100000>;
 585                         no-map;
 586                 };
 587
 588                 cpucp_fw_mem: cpucp-fw-region@d8140000 {
 589                         reg = <0 0xd8140000 0 0x1c0000>;
 590                         no-map;
 591                 };
 592
 593                 qtee_mem: qtee-region@d8300000 {
 594                         reg = <0 0xd8300000 0 0x500000>;
 595                         no-map;
 596                 };
 597
 598                 ta_mem: ta-region@d8800000 {
 599                         reg = <0 0xd8800000 0 0x8a00000>;
 600                         no-map;
 601                 };
 602
 603                 tz_tags_mem: tz-tags-region@e1200000 {
 604                         reg = <0 0xe1200000 0 0x2740000>;
 605                         no-map;
 606                 };
 607
 608                 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
 609                         reg = <0 0xe6440000 0 0x279000>;
 610                         no-map;
 611                 };
 612
 613                 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
 614                         reg = <0 0xf3600000 0 0x4aee000>;
 615                         no-map;
 616                 };
 617
 618                 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
 619                         reg = <0 0xf80ee000 0 0x1000>;
 620                         no-map;
 621                 };
 622
 623                 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
 624                         reg = <0 0xf80ef000 0 0x9000>;
 625                         no-map;
 626                 };
 627
 628                 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
 629                         reg = <0 0xf80f8000 0 0x4000>;
 630                         no-map;
 631                 };
 632
 633                 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
 634                         reg = <0 0xf80fc000 0 0x4000>;
 635                         no-map;
 636                 };
 637
 638                 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
 639                         reg = <0 0xf8100000 0 0x100000>;
 640                         no-map;
 641                 };
 642
 643                 oem_vm_mem: oem-vm-region@f8400000 {
 644                         reg = <0 0xf8400000 0 0x4800000>;
 645                         no-map;
 646                 };
 647
 648                 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
 649                         reg = <0 0xfcc00000 0 0x4000>;
 650                         no-map;
 651                 };
 652
 653                 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
 654                         reg = <0 0xfcc04000 0 0x100000>;
 655                         no-map;
 656                 };
 657
 658                 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
 659                         reg = <0 0xfce00000 0 0x2900000>;
 660                         no-map;
 661                 };
 662
 663                 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
 664                         reg = <0 0xff700000 0 0x100000>;
 665                         no-map;
 666                 };
 667         };
 668
 669         smp2p-adsp {
 670                 compatible = "qcom,smp2p";
 671                 qcom,smem = <443>, <429>;
 672                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 673                                              IPCC_MPROC_SIGNAL_SMP2P
 674                                              IRQ_TYPE_EDGE_RISING>;
 675                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 676                                 IPCC_MPROC_SIGNAL_SMP2P>;
 677
 678                 qcom,local-pid = <0>;
 679                 qcom,remote-pid = <2>;
 680
 681                 smp2p_adsp_out: master-kernel {
 682                         qcom,entry-name = "master-kernel";
 683                         #qcom,smem-state-cells = <1>;
 684                 };
 685
 686                 smp2p_adsp_in: slave-kernel {
 687                         qcom,entry-name = "slave-kernel";
 688                         interrupt-controller;
 689                         #interrupt-cells = <2>;
 690                 };
 691         };
 692
 693         smp2p-cdsp {
 694                 compatible = "qcom,smp2p";
 695                 qcom,smem = <94>, <432>;
 696                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 697                                              IPCC_MPROC_SIGNAL_SMP2P
 698                                              IRQ_TYPE_EDGE_RISING>;
 699                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 700                                 IPCC_MPROC_SIGNAL_SMP2P>;
 701
 702                 qcom,local-pid = <0>;
 703                 qcom,remote-pid = <5>;
 704
 705                 smp2p_cdsp_out: master-kernel {
 706                         qcom,entry-name = "master-kernel";
 707                         #qcom,smem-state-cells = <1>;
 708                 };
 709
 710                 smp2p_cdsp_in: slave-kernel {
 711                         qcom,entry-name = "slave-kernel";
 712                         interrupt-controller;
 713                         #interrupt-cells = <2>;
 714                 };
 715         };
 716
 717         smp2p-modem {
 718                 compatible = "qcom,smp2p";
 719                 qcom,smem = <435>, <428>;
 720                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 721                                              IPCC_MPROC_SIGNAL_SMP2P
 722                                              IRQ_TYPE_EDGE_RISING>;
 723                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 724                                 IPCC_MPROC_SIGNAL_SMP2P>;
 725
 726                 qcom,local-pid = <0>;
 727                 qcom,remote-pid = <1>;
 728
 729                 smp2p_modem_out: master-kernel {
 730                         qcom,entry-name = "master-kernel";
 731                         #qcom,smem-state-cells = <1>;
 732                 };
 733
 734                 smp2p_modem_in: slave-kernel {
 735                         qcom,entry-name = "slave-kernel";
 736                         interrupt-controller;
 737                         #interrupt-cells = <2>;
 738                 };
 739
 740                 ipa_smp2p_out: ipa-ap-to-modem {
 741                         qcom,entry-name = "ipa";
 742                         #qcom,smem-state-cells = <1>;
 743                 };
 744
 745                 ipa_smp2p_in: ipa-modem-to-ap {
 746                         qcom,entry-name = "ipa";
 747                         interrupt-controller;
 748                         #interrupt-cells = <2>;
 749                 };
 750         };
 751
 752         soc: soc@0 {
 753                 compatible = "simple-bus";
 754                 ranges = <0 0 0 0 0x10 0>;
 755                 dma-ranges = <0 0 0 0 0x10 0>;
 756
 757                 #address-cells = <2>;
 758                 #size-cells = <2>;
 759
 760                 gcc: clock-controller@100000 {
 761                         compatible = "qcom,sm8550-gcc";
 762                         reg = <0 0x00100000 0 0x1f4200>;
 763                         #clock-cells = <1>;
 764                         #reset-cells = <1>;
 765                         #power-domain-cells = <1>;
 766                         clocks = <&bi_tcxo_div2>, <&sleep_clk>,
 767                                  <&pcie0_phy>,
 768                                  <&pcie1_phy>,
 769                                  <&pcie_1_phy_aux_clk>,
 770                                  <&ufs_mem_phy 0>,
 771                                  <&ufs_mem_phy 1>,
 772                                  <&ufs_mem_phy 2>,
 773                                  <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 774                 };
 775
 776                 ipcc: mailbox@408000 {
 777                         compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
 778                         reg = <0 0x00408000 0 0x1000>;
 779                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 780                         interrupt-controller;
 781                         #interrupt-cells = <3>;
 782                         #mbox-cells = <2>;
 783                 };
 784
 785                 gpi_dma2: dma-controller@800000 {
 786                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
 787                         #dma-cells = <3>;
 788                         reg = <0 0x00800000 0 0x60000>;
 789                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 790                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 791                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 792                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 793                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 794                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 795                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 796                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 797                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 798                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 799                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 800                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 801                         dma-channels = <12>;
 802                         dma-channel-mask = <0x3e>;
 803                         iommus = <&apps_smmu 0x436 0>;
 804                         status = "disabled";
 805                 };
 806
 807                 qupv3_id_1: geniqup@8c0000 {
 808                         compatible = "qcom,geni-se-qup";
 809                         reg = <0 0x008c0000 0 0x2000>;
 810                         ranges;
 811                         clock-names = "m-ahb", "s-ahb";
 812                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 813                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 814                         iommus = <&apps_smmu 0x423 0>;
 815                         #address-cells = <2>;
 816                         #size-cells = <2>;
 817                         status = "disabled";
 818
 819                         i2c8: i2c@880000 {
 820                                 compatible = "qcom,geni-i2c";
 821                                 reg = <0 0x00880000 0 0x4000>;
 822                                 clock-names = "se";
 823                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 824                                 pinctrl-names = "default";
 825                                 pinctrl-0 = <&qup_i2c8_data_clk>;
 826                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 827                                 #address-cells = <1>;
 828                                 #size-cells = <0>;
 829                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 830                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 831                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 832                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 833                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 834                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 835                                 dma-names = "tx", "rx";
 836                                 status = "disabled";
 837                         };
 838
 839                         spi8: spi@880000 {
 840                                 compatible = "qcom,geni-spi";
 841                                 reg = <0 0x00880000 0 0x4000>;
 842                                 clock-names = "se";
 843                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 844                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 845                                 pinctrl-names = "default";
 846                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
 847                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 848                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 849                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 850                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 851                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 852                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 853                                 dma-names = "tx", "rx";
 854                                 #address-cells = <1>;
 855                                 #size-cells = <0>;
 856                                 status = "disabled";
 857                         };
 858
 859                         i2c9: i2c@884000 {
 860                                 compatible = "qcom,geni-i2c";
 861                                 reg = <0 0x00884000 0 0x4000>;
 862                                 clock-names = "se";
 863                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 864                                 pinctrl-names = "default";
 865                                 pinctrl-0 = <&qup_i2c9_data_clk>;
 866                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 867                                 #address-cells = <1>;
 868                                 #size-cells = <0>;
 869                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 870                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 871                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 872                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 873                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 874                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 875                                 dma-names = "tx", "rx";
 876                                 status = "disabled";
 877                         };
 878
 879                         spi9: spi@884000 {
 880                                 compatible = "qcom,geni-spi";
 881                                 reg = <0 0x00884000 0 0x4000>;
 882                                 clock-names = "se";
 883                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 884                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 885                                 pinctrl-names = "default";
 886                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
 887                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 888                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 889                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 890                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 891                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 892                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 893                                 dma-names = "tx", "rx";
 894                                 #address-cells = <1>;
 895                                 #size-cells = <0>;
 896                                 status = "disabled";
 897                         };
 898
 899                         i2c10: i2c@888000 {
 900                                 compatible = "qcom,geni-i2c";
 901                                 reg = <0 0x00888000 0 0x4000>;
 902                                 clock-names = "se";
 903                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 904                                 pinctrl-names = "default";
 905                                 pinctrl-0 = <&qup_i2c10_data_clk>;
 906                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 907                                 #address-cells = <1>;
 908                                 #size-cells = <0>;
 909                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 910                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 911                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 912                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 913                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 914                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 915                                 dma-names = "tx", "rx";
 916                                 status = "disabled";
 917                         };
 918
 919                         spi10: spi@888000 {
 920                                 compatible = "qcom,geni-spi";
 921                                 reg = <0 0x00888000 0 0x4000>;
 922                                 clock-names = "se";
 923                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 924                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 925                                 pinctrl-names = "default";
 926                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
 927                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 928                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 929                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 930                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 931                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 932                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 933                                 dma-names = "tx", "rx";
 934                                 #address-cells = <1>;
 935                                 #size-cells = <0>;
 936                                 status = "disabled";
 937                         };
 938
 939                         i2c11: i2c@88c000 {
 940                                 compatible = "qcom,geni-i2c";
 941                                 reg = <0 0x0088c000 0 0x4000>;
 942                                 clock-names = "se";
 943                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 944                                 pinctrl-names = "default";
 945                                 pinctrl-0 = <&qup_i2c11_data_clk>;
 946                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 947                                 #address-cells = <1>;
 948                                 #size-cells = <0>;
 949                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 950                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 951                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 952                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 953                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 954                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 955                                 dma-names = "tx", "rx";
 956                                 status = "disabled";
 957                         };
 958
 959                         spi11: spi@88c000 {
 960                                 compatible = "qcom,geni-spi";
 961                                 reg = <0 0x0088c000 0 0x4000>;
 962                                 clock-names = "se";
 963                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 964                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 965                                 pinctrl-names = "default";
 966                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
 967                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 968                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 969                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 970                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 971                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 972                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 973                                 dma-names = "tx", "rx";
 974                                 #address-cells = <1>;
 975                                 #size-cells = <0>;
 976                                 status = "disabled";
 977                         };
 978
 979                         i2c12: i2c@890000 {
 980                                 compatible = "qcom,geni-i2c";
 981                                 reg = <0 0x00890000 0 0x4000>;
 982                                 clock-names = "se";
 983                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 984                                 pinctrl-names = "default";
 985                                 pinctrl-0 = <&qup_i2c12_data_clk>;
 986                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 987                                 #address-cells = <1>;
 988                                 #size-cells = <0>;
 989                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 990                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 991                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 992                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 993                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 994                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 995                                 dma-names = "tx", "rx";
 996                                 status = "disabled";
 997                         };
 998
 999                         spi12: spi@890000 {
1000                                 compatible = "qcom,geni-spi";
1001                                 reg = <0 0x00890000 0 0x4000>;
1002                                 clock-names = "se";
1003                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1004                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1005                                 pinctrl-names = "default";
1006                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1007                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1008                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1009                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1010                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1011                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1012                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1013                                 dma-names = "tx", "rx";
1014                                 #address-cells = <1>;
1015                                 #size-cells = <0>;
1016                                 status = "disabled";
1017                         };
1018
1019                         i2c13: i2c@894000 {
1020                                 compatible = "qcom,geni-i2c";
1021                                 reg = <0 0x00894000 0 0x4000>;
1022                                 clock-names = "se";
1023                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1024                                 pinctrl-names = "default";
1025                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1026                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1027                                 #address-cells = <1>;
1028                                 #size-cells = <0>;
1029                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1030                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1031                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1032                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1033                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1034                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1035                                 dma-names = "tx", "rx";
1036                                 status = "disabled";
1037                         };
1038
1039                         spi13: spi@894000 {
1040                                 compatible = "qcom,geni-spi";
1041                                 reg = <0 0x00894000 0 0x4000>;
1042                                 clock-names = "se";
1043                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1044                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1045                                 pinctrl-names = "default";
1046                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1047                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1048                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1049                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1050                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1051                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053                                 dma-names = "tx", "rx";
1054                                 #address-cells = <1>;
1055                                 #size-cells = <0>;
1056                                 status = "disabled";
1057                         };
1058
1059                         uart14: serial@898000 {
1060                                 compatible = "qcom,geni-uart";
1061                                 reg = <0 0x898000 0 0x4000>;
1062                                 clock-names = "se";
1063                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064                                 pinctrl-names = "default";
1065                                 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1066                                 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1067                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1068                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1069                                 interconnect-names = "qup-core", "qup-config";
1070                                 status = "disabled";
1071                         };
1072
1073                         i2c15: i2c@89c000 {
1074                                 compatible = "qcom,geni-i2c";
1075                                 reg = <0 0x0089c000 0 0x4000>;
1076                                 clock-names = "se";
1077                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1078                                 pinctrl-names = "default";
1079                                 pinctrl-0 = <&qup_i2c15_data_clk>;
1080                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1081                                 #address-cells = <1>;
1082                                 #size-cells = <0>;
1083                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1084                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1085                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1086                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1087                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1088                                        <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1089                                 dma-names = "tx", "rx";
1090                                 status = "disabled";
1091                         };
1092
1093                         spi15: spi@89c000 {
1094                                 compatible = "qcom,geni-spi";
1095                                 reg = <0 0x0089c000 0 0x4000>;
1096                                 clock-names = "se";
1097                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1098                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1099                                 pinctrl-names = "default";
1100                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1101                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1102                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1103                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1104                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1105                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1106                                        <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1107                                 dma-names = "tx", "rx";
1108                                 #address-cells = <1>;
1109                                 #size-cells = <0>;
1110                                 status = "disabled";
1111                         };
1112                 };
1113
1114                 i2c_master_hub_0: geniqup@9c0000 {
1115                         compatible = "qcom,geni-se-i2c-master-hub";
1116                         reg = <0x0 0x009c0000 0x0 0x2000>;
1117                         clock-names = "s-ahb";
1118                         clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
1119                         #address-cells = <2>;
1120                         #size-cells = <2>;
1121                         ranges;
1122                         status = "disabled";
1123
1124                         i2c_hub_0: i2c@980000 {
1125                                 compatible = "qcom,geni-i2c-master-hub";
1126                                 reg = <0x0 0x00980000 0x0 0x4000>;
1127                                 clock-names = "se", "core";
1128                                 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
1129                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1130                                 pinctrl-names = "default";
1131                                 pinctrl-0 = <&hub_i2c0_data_clk>;
1132                                 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
1133                                 #address-cells = <1>;
1134                                 #size-cells = <0>;
1135                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1136                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1137                                 interconnect-names = "qup-core", "qup-config";
1138                                 status = "disabled";
1139                         };
1140
1141                         i2c_hub_1: i2c@984000 {
1142                                 compatible = "qcom,geni-i2c-master-hub";
1143                                 reg = <0x0 0x00984000 0x0 0x4000>;
1144                                 clock-names = "se", "core";
1145                                 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
1146                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1147                                 pinctrl-names = "default";
1148                                 pinctrl-0 = <&hub_i2c1_data_clk>;
1149                                 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1150                                 #address-cells = <1>;
1151                                 #size-cells = <0>;
1152                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1153                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1154                                 interconnect-names = "qup-core", "qup-config";
1155                                 status = "disabled";
1156                         };
1157
1158                         i2c_hub_2: i2c@988000 {
1159                                 compatible = "qcom,geni-i2c-master-hub";
1160                                 reg = <0x0 0x00988000 0x0 0x4000>;
1161                                 clock-names = "se", "core";
1162                                 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
1163                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1164                                 pinctrl-names = "default";
1165                                 pinctrl-0 = <&hub_i2c2_data_clk>;
1166                                 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1167                                 #address-cells = <1>;
1168                                 #size-cells = <0>;
1169                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1170                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1171                                 interconnect-names = "qup-core", "qup-config";
1172                                 status = "disabled";
1173                         };
1174
1175                         i2c_hub_3: i2c@98c000 {
1176                                 compatible = "qcom,geni-i2c-master-hub";
1177                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1178                                 clock-names = "se", "core";
1179                                 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
1180                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1181                                 pinctrl-names = "default";
1182                                 pinctrl-0 = <&hub_i2c3_data_clk>;
1183                                 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1184                                 #address-cells = <1>;
1185                                 #size-cells = <0>;
1186                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1187                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1188                                 interconnect-names = "qup-core", "qup-config";
1189                                 status = "disabled";
1190                         };
1191
1192                         i2c_hub_4: i2c@990000 {
1193                                 compatible = "qcom,geni-i2c-master-hub";
1194                                 reg = <0x0 0x00990000 0x0 0x4000>;
1195                                 clock-names = "se", "core";
1196                                 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
1197                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1198                                 pinctrl-names = "default";
1199                                 pinctrl-0 = <&hub_i2c4_data_clk>;
1200                                 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1201                                 #address-cells = <1>;
1202                                 #size-cells = <0>;
1203                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1204                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1205                                 interconnect-names = "qup-core", "qup-config";
1206                                 status = "disabled";
1207                         };
1208
1209                         i2c_hub_5: i2c@994000 {
1210                                 compatible = "qcom,geni-i2c-master-hub";
1211                                 reg = <0 0x00994000 0 0x4000>;
1212                                 clock-names = "se", "core";
1213                                 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
1214                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1215                                 pinctrl-names = "default";
1216                                 pinctrl-0 = <&hub_i2c5_data_clk>;
1217                                 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
1218                                 #address-cells = <1>;
1219                                 #size-cells = <0>;
1220                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1221                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1222                                 interconnect-names = "qup-core", "qup-config";
1223                                 status = "disabled";
1224                         };
1225
1226                         i2c_hub_6: i2c@998000 {
1227                                 compatible = "qcom,geni-i2c-master-hub";
1228                                 reg = <0 0x00998000 0 0x4000>;
1229                                 clock-names = "se", "core";
1230                                 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
1231                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1232                                 pinctrl-names = "default";
1233                                 pinctrl-0 = <&hub_i2c6_data_clk>;
1234                                 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
1235                                 #address-cells = <1>;
1236                                 #size-cells = <0>;
1237                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1238                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1239                                 interconnect-names = "qup-core", "qup-config";
1240                                 status = "disabled";
1241                         };
1242
1243                         i2c_hub_7: i2c@99c000 {
1244                                 compatible = "qcom,geni-i2c-master-hub";
1245                                 reg = <0 0x0099c000 0 0x4000>;
1246                                 clock-names = "se", "core";
1247                                 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
1248                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1249                                 pinctrl-names = "default";
1250                                 pinctrl-0 = <&hub_i2c7_data_clk>;
1251                                 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
1252                                 #address-cells = <1>;
1253                                 #size-cells = <0>;
1254                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1255                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1256                                 interconnect-names = "qup-core", "qup-config";
1257                                 status = "disabled";
1258                         };
1259
1260                         i2c_hub_8: i2c@9a0000 {
1261                                 compatible = "qcom,geni-i2c-master-hub";
1262                                 reg = <0 0x009a0000 0 0x4000>;
1263                                 clock-names = "se", "core";
1264                                 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
1265                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1266                                 pinctrl-names = "default";
1267                                 pinctrl-0 = <&hub_i2c8_data_clk>;
1268                                 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
1269                                 #address-cells = <1>;
1270                                 #size-cells = <0>;
1271                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1272                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1273                                 interconnect-names = "qup-core", "qup-config";
1274                                 status = "disabled";
1275                         };
1276
1277                         i2c_hub_9: i2c@9a4000 {
1278                                 compatible = "qcom,geni-i2c-master-hub";
1279                                 reg = <0 0x009a4000 0 0x4000>;
1280                                 clock-names = "se", "core";
1281                                 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
1282                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1283                                 pinctrl-names = "default";
1284                                 pinctrl-0 = <&hub_i2c9_data_clk>;
1285                                 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
1286                                 #address-cells = <1>;
1287                                 #size-cells = <0>;
1288                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1289                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1290                                 interconnect-names = "qup-core", "qup-config";
1291                                 status = "disabled";
1292                         };
1293                 };
1294
1295                 gpi_dma1: dma-controller@a00000 {
1296                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1297                         #dma-cells = <3>;
1298                         reg = <0 0x00a00000 0 0x60000>;
1299                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1300                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1301                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1302                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1303                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1304                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1305                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1306                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1307                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1308                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1309                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1310                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1311                         dma-channels = <12>;
1312                         dma-channel-mask = <0x1e>;
1313                         iommus = <&apps_smmu 0xb6 0>;
1314                         status = "disabled";
1315                 };
1316
1317                 qupv3_id_0: geniqup@ac0000 {
1318                         compatible = "qcom,geni-se-qup";
1319                         reg = <0 0x00ac0000 0 0x2000>;
1320                         ranges;
1321                         clock-names = "m-ahb", "s-ahb";
1322                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1323                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1324                         iommus = <&apps_smmu 0xa3 0>;
1325                         interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1326                         interconnect-names = "qup-core";
1327                         #address-cells = <2>;
1328                         #size-cells = <2>;
1329                         status = "disabled";
1330
1331                         i2c0: i2c@a80000 {
1332                                 compatible = "qcom,geni-i2c";
1333                                 reg = <0 0x00a80000 0 0x4000>;
1334                                 clock-names = "se";
1335                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1336                                 pinctrl-names = "default";
1337                                 pinctrl-0 = <&qup_i2c0_data_clk>;
1338                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1339                                 #address-cells = <1>;
1340                                 #size-cells = <0>;
1341                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1342                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1343                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1344                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1345                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1346                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1347                                 dma-names = "tx", "rx";
1348                                 status = "disabled";
1349                         };
1350
1351                         spi0: spi@a80000 {
1352                                 compatible = "qcom,geni-spi";
1353                                 reg = <0 0x00a80000 0 0x4000>;
1354                                 clock-names = "se";
1355                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1356                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1357                                 pinctrl-names = "default";
1358                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1359                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1360                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1361                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1362                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1363                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1364                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1365                                 dma-names = "tx", "rx";
1366                                 #address-cells = <1>;
1367                                 #size-cells = <0>;
1368                                 status = "disabled";
1369                         };
1370
1371                         i2c1: i2c@a84000 {
1372                                 compatible = "qcom,geni-i2c";
1373                                 reg = <0 0x00a84000 0 0x4000>;
1374                                 clock-names = "se";
1375                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1376                                 pinctrl-names = "default";
1377                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1378                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1379                                 #address-cells = <1>;
1380                                 #size-cells = <0>;
1381                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1382                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1383                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1384                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1385                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1386                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1387                                 dma-names = "tx", "rx";
1388                                 status = "disabled";
1389                         };
1390
1391                         spi1: spi@a84000 {
1392                                 compatible = "qcom,geni-spi";
1393                                 reg = <0 0x00a84000 0 0x4000>;
1394                                 clock-names = "se";
1395                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1396                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1397                                 pinctrl-names = "default";
1398                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1399                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1400                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1401                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1402                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1403                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1404                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1405                                 dma-names = "tx", "rx";
1406                                 #address-cells = <1>;
1407                                 #size-cells = <0>;
1408                                 status = "disabled";
1409                         };
1410
1411                         i2c2: i2c@a88000 {
1412                                 compatible = "qcom,geni-i2c";
1413                                 reg = <0 0x00a88000 0 0x4000>;
1414                                 clock-names = "se";
1415                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1416                                 pinctrl-names = "default";
1417                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1418                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1419                                 #address-cells = <1>;
1420                                 #size-cells = <0>;
1421                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1422                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1423                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1424                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1425                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1426                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1427                                 dma-names = "tx", "rx";
1428                                 status = "disabled";
1429                         };
1430
1431                         spi2: spi@a88000 {
1432                                 compatible = "qcom,geni-spi";
1433                                 reg = <0 0x00a88000 0 0x4000>;
1434                                 clock-names = "se";
1435                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1436                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1437                                 pinctrl-names = "default";
1438                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1439                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1440                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1441                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1442                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1443                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1444                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1445                                 dma-names = "tx", "rx";
1446                                 #address-cells = <1>;
1447                                 #size-cells = <0>;
1448                                 status = "disabled";
1449                         };
1450
1451                         i2c3: i2c@a8c000 {
1452                                 compatible = "qcom,geni-i2c";
1453                                 reg = <0 0x00a8c000 0 0x4000>;
1454                                 clock-names = "se";
1455                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1456                                 pinctrl-names = "default";
1457                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1458                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1459                                 #address-cells = <1>;
1460                                 #size-cells = <0>;
1461                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1462                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1463                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1464                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1465                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1466                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1467                                 dma-names = "tx", "rx";
1468                                 status = "disabled";
1469                         };
1470
1471                         spi3: spi@a8c000 {
1472                                 compatible = "qcom,geni-spi";
1473                                 reg = <0 0x00a8c000 0 0x4000>;
1474                                 clock-names = "se";
1475                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1476                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1477                                 pinctrl-names = "default";
1478                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1479                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1480                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1481                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1482                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1483                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1484                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1485                                 dma-names = "tx", "rx";
1486                                 #address-cells = <1>;
1487                                 #size-cells = <0>;
1488                                 status = "disabled";
1489                         };
1490
1491                         i2c4: i2c@a90000 {
1492                                 compatible = "qcom,geni-i2c";
1493                                 reg = <0 0x00a90000 0 0x4000>;
1494                                 clock-names = "se";
1495                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1496                                 pinctrl-names = "default";
1497                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1498                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1499                                 #address-cells = <1>;
1500                                 #size-cells = <0>;
1501                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1502                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1503                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1504                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1505                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1506                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1507                                 dma-names = "tx", "rx";
1508                                 status = "disabled";
1509                         };
1510
1511                         spi4: spi@a90000 {
1512                                 compatible = "qcom,geni-spi";
1513                                 reg = <0 0x00a90000 0 0x4000>;
1514                                 clock-names = "se";
1515                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1516                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1517                                 pinctrl-names = "default";
1518                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1519                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1520                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1521                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1522                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1523                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1524                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1525                                 dma-names = "tx", "rx";
1526                                 #address-cells = <1>;
1527                                 #size-cells = <0>;
1528                                 status = "disabled";
1529                         };
1530
1531                         i2c5: i2c@a94000 {
1532                                 compatible = "qcom,geni-i2c";
1533                                 reg = <0 0x00a94000 0 0x4000>;
1534                                 clock-names = "se";
1535                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1536                                 pinctrl-names = "default";
1537                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1538                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1539                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1540                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1541                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1542                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1543                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1544                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1545                                 dma-names = "tx", "rx";
1546                                 #address-cells = <1>;
1547                                 #size-cells = <0>;
1548                                 status = "disabled";
1549                         };
1550
1551                         spi5: spi@a94000 {
1552                                 compatible = "qcom,geni-spi";
1553                                 reg = <0 0x00a94000 0 0x4000>;
1554                                 clock-names = "se";
1555                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1556                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1557                                 pinctrl-names = "default";
1558                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1559                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1560                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1561                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1562                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1563                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1564                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1565                                 dma-names = "tx", "rx";
1566                                 #address-cells = <1>;
1567                                 #size-cells = <0>;
1568                                 status = "disabled";
1569                         };
1570
1571                         i2c6: i2c@a98000 {
1572                                 compatible = "qcom,geni-i2c";
1573                                 reg = <0 0x00a98000 0 0x4000>;
1574                                 clock-names = "se";
1575                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1576                                 pinctrl-names = "default";
1577                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1578                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1579                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1580                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1581                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1582                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1583                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1584                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1585                                 dma-names = "tx", "rx";
1586                                 #address-cells = <1>;
1587                                 #size-cells = <0>;
1588                                 status = "disabled";
1589                         };
1590
1591                         spi6: spi@a98000 {
1592                                 compatible = "qcom,geni-spi";
1593                                 reg = <0 0x00a98000 0 0x4000>;
1594                                 clock-names = "se";
1595                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1596                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1597                                 pinctrl-names = "default";
1598                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1599                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1600                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1601                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1602                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1603                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1604                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1605                                 dma-names = "tx", "rx";
1606                                 #address-cells = <1>;
1607                                 #size-cells = <0>;
1608                                 status = "disabled";
1609                         };
1610
1611                         uart7: serial@a9c000 {
1612                                 compatible = "qcom,geni-debug-uart";
1613                                 reg = <0 0x00a9c000 0 0x4000>;
1614                                 clock-names = "se";
1615                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1616                                 pinctrl-names = "default";
1617                                 pinctrl-0 = <&qup_uart7_default>;
1618                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1619                                 interconnect-names = "qup-core", "qup-config";
1620                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1621                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1622                                 status = "disabled";
1623                         };
1624                 };
1625
1626                 cnoc_main: interconnect@1500000 {
1627                         compatible = "qcom,sm8550-cnoc-main";
1628                         reg = <0 0x01500000 0 0x13080>;
1629                         #interconnect-cells = <2>;
1630                         qcom,bcm-voters = <&apps_bcm_voter>;
1631                 };
1632
1633                 config_noc: interconnect@1600000 {
1634                         compatible = "qcom,sm8550-config-noc";
1635                         reg = <0 0x01600000 0 0x6200>;
1636                         #interconnect-cells = <2>;
1637                         qcom,bcm-voters = <&apps_bcm_voter>;
1638                 };
1639
1640                 system_noc: interconnect@1680000 {
1641                         compatible = "qcom,sm8550-system-noc";
1642                         reg = <0 0x01680000 0 0x1d080>;
1643                         #interconnect-cells = <2>;
1644                         qcom,bcm-voters = <&apps_bcm_voter>;
1645                 };
1646
1647                 pcie_noc: interconnect@16c0000 {
1648                         compatible = "qcom,sm8550-pcie-anoc";
1649                         reg = <0 0x016c0000 0 0x12200>;
1650                         #interconnect-cells = <2>;
1651                         clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1652                                  <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
1653                         qcom,bcm-voters = <&apps_bcm_voter>;
1654                 };
1655
1656                 aggre1_noc: interconnect@16e0000 {
1657                         compatible = "qcom,sm8550-aggre1-noc";
1658                         reg = <0 0x016e0000 0 0x14400>;
1659                         #interconnect-cells = <2>;
1660                         clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1661                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1662                         qcom,bcm-voters = <&apps_bcm_voter>;
1663                 };
1664
1665                 aggre2_noc: interconnect@1700000 {
1666                         compatible = "qcom,sm8550-aggre2-noc";
1667                         reg = <0 0x01700000 0 0x1e400>;
1668                         #interconnect-cells = <2>;
1669                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1670                         qcom,bcm-voters = <&apps_bcm_voter>;
1671                 };
1672
1673                 mmss_noc: interconnect@1780000 {
1674                         compatible = "qcom,sm8550-mmss-noc";
1675                         reg = <0 0x01780000 0 0x5b800>;
1676                         #interconnect-cells = <2>;
1677                         qcom,bcm-voters = <&apps_bcm_voter>;
1678                 };
1679
1680                 rng: rng@10c3000 {
1681                         compatible = "qcom,sm8550-trng", "qcom,trng";
1682                         reg = <0 0x010c3000 0 0x1000>;
1683                 };
1684
1685                 pcie0: pci@1c00000 {
1686                         device_type = "pci";
1687                         compatible = "qcom,pcie-sm8550";
1688                         reg = <0 0x01c00000 0 0x3000>,
1689                               <0 0x60000000 0 0xf1d>,
1690                               <0 0x60000f20 0 0xa8>,
1691                               <0 0x60001000 0 0x1000>,
1692                               <0 0x60100000 0 0x100000>;
1693                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1694                         #address-cells = <3>;
1695                         #size-cells = <2>;
1696                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1697                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1698                         bus-range = <0x00 0xff>;
1699
1700                         dma-coherent;
1701
1702                         linux,pci-domain = <0>;
1703                         num-lanes = <2>;
1704
1705                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1706                         interrupt-names = "msi";
1707
1708                         #interrupt-cells = <1>;
1709                         interrupt-map-mask = <0 0 0 0x7>;
1710                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1711                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1712                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1713                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1714
1715                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1716                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1717                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1718                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1719                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1720                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1721                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
1722                         clock-names = "aux",
1723                                       "cfg",
1724                                       "bus_master",
1725                                       "bus_slave",
1726                                       "slave_q2a",
1727                                       "ddrss_sf_tbu",
1728                                       "noc_aggr";
1729
1730                         interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1731                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1732                         interconnect-names = "pcie-mem", "cpu-pcie";
1733
1734                         iommu-map = <0x0   &apps_smmu 0x1400 0x1>,
1735                                     <0x100 &apps_smmu 0x1401 0x1>;
1736
1737                         resets = <&gcc GCC_PCIE_0_BCR>;
1738                         reset-names = "pci";
1739
1740                         power-domains = <&gcc PCIE_0_GDSC>;
1741
1742                         phys = <&pcie0_phy>;
1743                         phy-names = "pciephy";
1744
1745                         status = "disabled";
1746                 };
1747
1748                 pcie0_phy: phy@1c06000 {
1749                         compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1750                         reg = <0 0x01c06000 0 0x2000>;
1751
1752                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1753                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1754                                  <&tcsr TCSR_PCIE_0_CLKREF_EN>,
1755                                  <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1756                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1757                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1758                                       "pipe";
1759
1760                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1761                         reset-names = "phy";
1762
1763                         assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1764                         assigned-clock-rates = <100000000>;
1765
1766                         power-domains = <&gcc PCIE_0_PHY_GDSC>;
1767
1768                         #clock-cells = <0>;
1769                         clock-output-names = "pcie0_pipe_clk";
1770
1771                         #phy-cells = <0>;
1772
1773                         status = "disabled";
1774                 };
1775
1776                 pcie1: pci@1c08000 {
1777                         device_type = "pci";
1778                         compatible = "qcom,pcie-sm8550";
1779                         reg = <0x0 0x01c08000 0x0 0x3000>,
1780                               <0x0 0x40000000 0x0 0xf1d>,
1781                               <0x0 0x40000f20 0x0 0xa8>,
1782                               <0x0 0x40001000 0x0 0x1000>,
1783                               <0x0 0x40100000 0x0 0x100000>;
1784                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1785                         #address-cells = <3>;
1786                         #size-cells = <2>;
1787                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1788                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1789                         bus-range = <0x00 0xff>;
1790
1791                         dma-coherent;
1792
1793                         linux,pci-domain = <1>;
1794                         num-lanes = <2>;
1795
1796                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1797                         interrupt-names = "msi";
1798
1799                         #interrupt-cells = <1>;
1800                         interrupt-map-mask = <0 0 0 0x7>;
1801                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805
1806                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1807                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1808                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1809                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1810                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1811                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1812                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1813                                  <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
1814                         clock-names = "aux",
1815                                       "cfg",
1816                                       "bus_master",
1817                                       "bus_slave",
1818                                       "slave_q2a",
1819                                       "ddrss_sf_tbu",
1820                                       "noc_aggr",
1821                                       "cnoc_sf_axi";
1822
1823                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1824                         assigned-clock-rates = <19200000>;
1825
1826                         interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1827                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1828                         interconnect-names = "pcie-mem", "cpu-pcie";
1829
1830                         iommu-map = <0x0   &apps_smmu 0x1480 0x1>,
1831                                     <0x100 &apps_smmu 0x1481 0x1>;
1832
1833                         resets = <&gcc GCC_PCIE_1_BCR>,
1834                                 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
1835                         reset-names = "pci", "link_down";
1836
1837                         power-domains = <&gcc PCIE_1_GDSC>;
1838
1839                         phys = <&pcie1_phy>;
1840                         phy-names = "pciephy";
1841
1842                         status = "disabled";
1843                 };
1844
1845                 pcie1_phy: phy@1c0e000 {
1846                         compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1847                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1848
1849                         clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1850                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1851                                  <&tcsr TCSR_PCIE_1_CLKREF_EN>,
1852                                  <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1853                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1854                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1855                                       "pipe";
1856
1857                         resets = <&gcc GCC_PCIE_1_PHY_BCR>,
1858                                  <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
1859                         reset-names = "phy", "phy_nocsr";
1860
1861                         assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1862                         assigned-clock-rates = <100000000>;
1863
1864                         power-domains = <&gcc PCIE_1_PHY_GDSC>;
1865
1866                         #clock-cells = <0>;
1867                         clock-output-names = "pcie1_pipe_clk";
1868
1869                         #phy-cells = <0>;
1870
1871                         status = "disabled";
1872                 };
1873
1874                 cryptobam: dma-controller@1dc4000 {
1875                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1876                         reg = <0x0 0x01dc4000 0x0 0x28000>;
1877                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1878                         #dma-cells = <1>;
1879                         qcom,ee = <0>;
1880                         qcom,controlled-remotely;
1881                         iommus = <&apps_smmu 0x480 0x0>,
1882                                  <&apps_smmu 0x481 0x0>;
1883                 };
1884
1885                 crypto: crypto@1dfa000 {
1886                         compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1887                         reg = <0x0 0x01dfa000 0x0 0x6000>;
1888                         dmas = <&cryptobam 4>, <&cryptobam 5>;
1889                         dma-names = "rx", "tx";
1890                         iommus = <&apps_smmu 0x480 0x0>,
1891                                  <&apps_smmu 0x481 0x0>;
1892                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1893                         interconnect-names = "memory";
1894                 };
1895
1896                 ufs_mem_phy: phy@1d80000 {
1897                         compatible = "qcom,sm8550-qmp-ufs-phy";
1898                         reg = <0x0 0x01d80000 0x0 0x2000>;
1899                         clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
1900                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1901                         clock-names = "ref", "ref_aux";
1902
1903                         power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1904
1905                         resets = <&ufs_mem_hc 0>;
1906                         reset-names = "ufsphy";
1907
1908                         #clock-cells = <1>;
1909                         #phy-cells = <0>;
1910
1911                         status = "disabled";
1912                 };
1913
1914                 ufs_mem_hc: ufs@1d84000 {
1915                         compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1916                                      "jedec,ufs-2.0";
1917                         reg = <0x0 0x01d84000 0x0 0x3000>;
1918                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1919                         phys = <&ufs_mem_phy>;
1920                         phy-names = "ufsphy";
1921                         lanes-per-direction = <2>;
1922                         #reset-cells = <1>;
1923                         resets = <&gcc GCC_UFS_PHY_BCR>;
1924                         reset-names = "rst";
1925
1926                         power-domains = <&gcc UFS_PHY_GDSC>;
1927                         required-opps = <&rpmhpd_opp_nom>;
1928
1929                         iommus = <&apps_smmu 0x60 0x0>;
1930                         dma-coherent;
1931
1932                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1933                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
1934
1935                         interconnect-names = "ufs-ddr", "cpu-ufs";
1936                         clock-names = "core_clk",
1937                                       "bus_aggr_clk",
1938                                       "iface_clk",
1939                                       "core_clk_unipro",
1940                                       "ref_clk",
1941                                       "tx_lane0_sync_clk",
1942                                       "rx_lane0_sync_clk",
1943                                       "rx_lane1_sync_clk";
1944                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1945                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1946                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1947                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1948                                  <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
1949                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1950                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1951                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1952                         freq-table-hz =
1953                                 <75000000 300000000>,
1954                                 <0 0>,
1955                                 <0 0>,
1956                                 <75000000 300000000>,
1957                                 <100000000 403000000>,
1958                                 <0 0>,
1959                                 <0 0>,
1960                                 <0 0>;
1961                         qcom,ice = <&ice>;
1962
1963                         status = "disabled";
1964                 };
1965
1966                 ice: crypto@1d88000 {
1967                         compatible = "qcom,sm8550-inline-crypto-engine",
1968                                      "qcom,inline-crypto-engine";
1969                         reg = <0 0x01d88000 0 0x8000>;
1970                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1971                 };
1972
1973                 tcsr_mutex: hwlock@1f40000 {
1974                         compatible = "qcom,tcsr-mutex";
1975                         reg = <0 0x01f40000 0 0x20000>;
1976                         #hwlock-cells = <1>;
1977                 };
1978
1979                 tcsr: clock-controller@1fc0000 {
1980                         compatible = "qcom,sm8550-tcsr", "syscon";
1981                         reg = <0 0x01fc0000 0 0x30000>;
1982                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1983                         #clock-cells = <1>;
1984                         #reset-cells = <1>;
1985                 };
1986
1987                 gpucc: clock-controller@3d90000 {
1988                         compatible = "qcom,sm8550-gpucc";
1989                         reg = <0 0x03d90000 0 0xa000>;
1990                         clocks = <&bi_tcxo_div2>,
1991                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1992                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1993                         #clock-cells = <1>;
1994                         #reset-cells = <1>;
1995                         #power-domain-cells = <1>;
1996                 };
1997
1998                 remoteproc_mpss: remoteproc@4080000 {
1999                         compatible = "qcom,sm8550-mpss-pas";
2000                         reg = <0x0 0x04080000 0x0 0x4040>;
2001
2002                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2003                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2004                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2005                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2006                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2007                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2008                         interrupt-names = "wdog", "fatal", "ready", "handover",
2009                                           "stop-ack", "shutdown-ack";
2010
2011                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2012                         clock-names = "xo";
2013
2014                         power-domains = <&rpmhpd RPMHPD_CX>,
2015                                         <&rpmhpd RPMHPD_MSS>;
2016                         power-domain-names = "cx", "mss";
2017
2018                         interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2019
2020                         memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2021
2022                         qcom,qmp = <&aoss_qmp>;
2023
2024                         qcom,smem-states = <&smp2p_modem_out 0>;
2025                         qcom,smem-state-names = "stop";
2026
2027                         status = "disabled";
2028
2029                         glink-edge {
2030                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2031                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2032                                                              IRQ_TYPE_EDGE_RISING>;
2033                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2034                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2035                                 label = "mpss";
2036                                 qcom,remote-pid = <1>;
2037                         };
2038                 };
2039
2040                 lpass_wsa2macro: codec@6aa0000 {
2041                         compatible = "qcom,sm8550-lpass-wsa-macro";
2042                         reg = <0 0x06aa0000 0 0x1000>;
2043                         clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2044                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2045                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2046                                  <&lpass_vamacro>;
2047                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2048                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2049                         assigned-clock-rates = <19200000>;
2050
2051                         #clock-cells = <0>;
2052                         clock-output-names = "wsa2-mclk";
2053                         pinctrl-names = "default";
2054                         pinctrl-0 = <&wsa2_swr_active>;
2055                         #sound-dai-cells = <1>;
2056                 };
2057
2058                 swr3: soundwire-controller@6ab0000 {
2059                         compatible = "qcom,soundwire-v2.0.0";
2060                         reg = <0 0x06ab0000 0 0x10000>;
2061                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2062                         clocks = <&lpass_wsa2macro>;
2063                         clock-names = "iface";
2064                         label = "WSA2";
2065
2066                         qcom,din-ports = <4>;
2067                         qcom,dout-ports = <9>;
2068
2069                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2070                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2071                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2072                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2073                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2074                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2075                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2076                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2077                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2078
2079                         #address-cells = <2>;
2080                         #size-cells = <0>;
2081                         #sound-dai-cells = <1>;
2082                         status = "disabled";
2083                 };
2084
2085                 lpass_rxmacro: codec@6ac0000 {
2086                         compatible = "qcom,sm8550-lpass-rx-macro";
2087                         reg = <0 0x06ac0000 0 0x1000>;
2088                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2089                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2090                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2091                                  <&lpass_vamacro>;
2092                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2093
2094                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2095                         assigned-clock-rates = <19200000>;
2096
2097                         #clock-cells = <0>;
2098                         clock-output-names = "mclk";
2099                         pinctrl-names = "default";
2100                         pinctrl-0 = <&rx_swr_active>;
2101                         #sound-dai-cells = <1>;
2102                 };
2103
2104                 swr1: soundwire-controller@6ad0000 {
2105                         compatible = "qcom,soundwire-v2.0.0";
2106                         reg = <0 0x06ad0000 0 0x10000>;
2107                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2108                         clocks = <&lpass_rxmacro>;
2109                         clock-names = "iface";
2110                         label = "RX";
2111
2112                         qcom,din-ports = <0>;
2113                         qcom,dout-ports = <10>;
2114
2115                         qcom,ports-sinterval =          /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2116                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2117                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2118                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2119                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2120                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2121                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2122                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2123                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2124
2125                         #address-cells = <2>;
2126                         #size-cells = <0>;
2127                         #sound-dai-cells = <1>;
2128                         status = "disabled";
2129                 };
2130
2131                 lpass_txmacro: codec@6ae0000 {
2132                         compatible = "qcom,sm8550-lpass-tx-macro";
2133                         reg = <0 0x06ae0000 0 0x1000>;
2134                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2135                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2136                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2137                                  <&lpass_vamacro>;
2138                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2139                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2140
2141                         assigned-clock-rates = <19200000>;
2142
2143                         #clock-cells = <0>;
2144                         clock-output-names = "mclk";
2145                         pinctrl-names = "default";
2146                         pinctrl-0 = <&tx_swr_active>;
2147                         #sound-dai-cells = <1>;
2148                 };
2149
2150                 lpass_wsamacro: codec@6b00000 {
2151                         compatible = "qcom,sm8550-lpass-wsa-macro";
2152                         reg = <0 0x06b00000 0 0x1000>;
2153                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2154                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2155                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2156                                  <&lpass_vamacro>;
2157                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2158
2159                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2160                         assigned-clock-rates = <19200000>;
2161
2162                         #clock-cells = <0>;
2163                         clock-output-names = "mclk";
2164                         pinctrl-names = "default";
2165                         pinctrl-0 = <&wsa_swr_active>;
2166                         #sound-dai-cells = <1>;
2167                 };
2168
2169                 swr0: soundwire-controller@6b10000 {
2170                         compatible = "qcom,soundwire-v2.0.0";
2171                         reg = <0 0x06b10000 0 0x10000>;
2172                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2173                         clocks = <&lpass_wsamacro>;
2174                         clock-names = "iface";
2175                         label = "WSA";
2176
2177                         qcom,din-ports = <4>;
2178                         qcom,dout-ports = <9>;
2179
2180                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2181                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2182                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2183                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2184                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2185                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2186                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2187                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2188                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2189
2190                         #address-cells = <2>;
2191                         #size-cells = <0>;
2192                         #sound-dai-cells = <1>;
2193                         status = "disabled";
2194                 };
2195
2196                 swr2: soundwire-controller@6d30000 {
2197                         compatible = "qcom,soundwire-v2.0.0";
2198                         reg = <0 0x06d30000 0 0x10000>;
2199                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2200                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2201                         interrupt-names = "core", "wakeup";
2202                         clocks = <&lpass_vamacro>;
2203                         clock-names = "iface";
2204                         label = "TX";
2205
2206                         qcom,din-ports = <4>;
2207                         qcom,dout-ports = <0>;
2208                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2209                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x01 0x01>;
2210                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2211                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2212                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2213                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2214                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2215                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2216                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x02 0x00 0x00>;
2217
2218                         #address-cells = <2>;
2219                         #size-cells = <0>;
2220                         #sound-dai-cells = <1>;
2221                         status = "disabled";
2222                 };
2223
2224                 lpass_vamacro: codec@6d44000 {
2225                         compatible = "qcom,sm8550-lpass-va-macro";
2226                         reg = <0 0x06d44000 0 0x1000>;
2227                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2228                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2229                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2230                         clock-names = "mclk", "macro", "dcodec";
2231
2232                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2233                         assigned-clock-rates = <19200000>;
2234
2235                         #clock-cells = <0>;
2236                         clock-output-names = "fsgen";
2237                         #sound-dai-cells = <1>;
2238                 };
2239
2240                 lpass_tlmm: pinctrl@6e80000 {
2241                         compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2242                         reg = <0 0x06e80000 0 0x20000>,
2243                               <0 0x07250000 0 0x10000>;
2244                         gpio-controller;
2245                         #gpio-cells = <2>;
2246                         gpio-ranges = <&lpass_tlmm 0 0 23>;
2247
2248                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2249                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2250                         clock-names = "core", "audio";
2251
2252                         tx_swr_active: tx-swr-active-state {
2253                                 clk-pins {
2254                                         pins = "gpio0";
2255                                         function = "swr_tx_clk";
2256                                         drive-strength = <2>;
2257                                         slew-rate = <1>;
2258                                         bias-disable;
2259                                 };
2260
2261                                 data-pins {
2262                                         pins = "gpio1", "gpio2", "gpio14";
2263                                         function = "swr_tx_data";
2264                                         drive-strength = <2>;
2265                                         slew-rate = <1>;
2266                                         bias-bus-hold;
2267                                 };
2268                         };
2269
2270                         rx_swr_active: rx-swr-active-state {
2271                                 clk-pins {
2272                                         pins = "gpio3";
2273                                         function = "swr_rx_clk";
2274                                         drive-strength = <2>;
2275                                         slew-rate = <1>;
2276                                         bias-disable;
2277                                 };
2278
2279                                 data-pins {
2280                                         pins = "gpio4", "gpio5";
2281                                         function = "swr_rx_data";
2282                                         drive-strength = <2>;
2283                                         slew-rate = <1>;
2284                                         bias-bus-hold;
2285                                 };
2286                         };
2287
2288                         dmic01_default: dmic01-default-state {
2289                                 clk-pins {
2290                                         pins = "gpio6";
2291                                         function = "dmic1_clk";
2292                                         drive-strength = <8>;
2293                                         output-high;
2294                                 };
2295
2296                                 data-pins {
2297                                         pins = "gpio7";
2298                                         function = "dmic1_data";
2299                                         drive-strength = <8>;
2300                                         input-enable;
2301                                 };
2302                         };
2303
2304                         dmic02_default: dmic02-default-state {
2305                                 clk-pins {
2306                                         pins = "gpio8";
2307                                         function = "dmic2_clk";
2308                                         drive-strength = <8>;
2309                                         output-high;
2310                                 };
2311
2312                                 data-pins {
2313                                         pins = "gpio9";
2314                                         function = "dmic2_data";
2315                                         drive-strength = <8>;
2316                                         input-enable;
2317                                 };
2318                         };
2319
2320                         wsa_swr_active: wsa-swr-active-state {
2321                                 clk-pins {
2322                                         pins = "gpio10";
2323                                         function = "wsa_swr_clk";
2324                                         drive-strength = <2>;
2325                                         slew-rate = <1>;
2326                                         bias-disable;
2327                                 };
2328
2329                                 data-pins {
2330                                         pins = "gpio11";
2331                                         function = "wsa_swr_data";
2332                                         drive-strength = <2>;
2333                                         slew-rate = <1>;
2334                                         bias-bus-hold;
2335                                 };
2336                         };
2337
2338                         wsa2_swr_active: wsa2-swr-active-state {
2339                                 clk-pins {
2340                                         pins = "gpio15";
2341                                         function = "wsa2_swr_clk";
2342                                         drive-strength = <2>;
2343                                         slew-rate = <1>;
2344                                         bias-disable;
2345                                 };
2346
2347                                 data-pins {
2348                                         pins = "gpio16";
2349                                         function = "wsa2_swr_data";
2350                                         drive-strength = <2>;
2351                                         slew-rate = <1>;
2352                                         bias-bus-hold;
2353                                 };
2354                         };
2355                 };
2356
2357                 lpass_lpiaon_noc: interconnect@7400000 {
2358                         compatible = "qcom,sm8550-lpass-lpiaon-noc";
2359                         reg = <0 0x07400000 0 0x19080>;
2360                         #interconnect-cells = <2>;
2361                         qcom,bcm-voters = <&apps_bcm_voter>;
2362                 };
2363
2364                 lpass_lpicx_noc: interconnect@7430000 {
2365                         compatible = "qcom,sm8550-lpass-lpicx-noc";
2366                         reg = <0 0x07430000 0 0x3a200>;
2367                         #interconnect-cells = <2>;
2368                         qcom,bcm-voters = <&apps_bcm_voter>;
2369                 };
2370
2371                 lpass_ag_noc: interconnect@7e40000 {
2372                         compatible = "qcom,sm8550-lpass-ag-noc";
2373                         reg = <0 0x07e40000 0 0xe080>;
2374                         #interconnect-cells = <2>;
2375                         qcom,bcm-voters = <&apps_bcm_voter>;
2376                 };
2377
2378                 sdhc_2: mmc@8804000 {
2379                         compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2380                         reg = <0 0x08804000 0 0x1000>;
2381
2382                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2383                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2384                         interrupt-names = "hc_irq", "pwr_irq";
2385
2386                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2387                                  <&gcc GCC_SDCC2_APPS_CLK>,
2388                                  <&rpmhcc RPMH_CXO_CLK>;
2389                         clock-names = "iface", "core", "xo";
2390                         iommus = <&apps_smmu 0x540 0>;
2391                         qcom,dll-config = <0x0007642c>;
2392                         qcom,ddr-config = <0x80040868>;
2393                         power-domains = <&rpmhpd RPMHPD_CX>;
2394                         operating-points-v2 = <&sdhc2_opp_table>;
2395
2396                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2397                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2398                         interconnect-names = "sdhc-ddr", "cpu-sdhc";
2399                         bus-width = <4>;
2400                         dma-coherent;
2401
2402                         /* Forbid SDR104/SDR50 - broken hw! */
2403                         sdhci-caps-mask = <0x3 0>;
2404
2405                         status = "disabled";
2406
2407                         sdhc2_opp_table: opp-table {
2408                                 compatible = "operating-points-v2";
2409
2410                                 opp-19200000 {
2411                                         opp-hz = /bits/ 64 <19200000>;
2412                                         required-opps = <&rpmhpd_opp_min_svs>;
2413                                 };
2414
2415                                 opp-50000000 {
2416                                         opp-hz = /bits/ 64 <50000000>;
2417                                         required-opps = <&rpmhpd_opp_low_svs>;
2418                                 };
2419
2420                                 opp-100000000 {
2421                                         opp-hz = /bits/ 64 <100000000>;
2422                                         required-opps = <&rpmhpd_opp_svs>;
2423                                 };
2424
2425                                 opp-202000000 {
2426                                         opp-hz = /bits/ 64 <202000000>;
2427                                         required-opps = <&rpmhpd_opp_svs_l1>;
2428                                 };
2429                         };
2430                 };
2431
2432                 videocc: clock-controller@aaf0000 {
2433                         compatible = "qcom,sm8550-videocc";
2434                         reg = <0 0x0aaf0000 0 0x10000>;
2435                         clocks = <&bi_tcxo_div2>,
2436                                  <&gcc GCC_VIDEO_AHB_CLK>;
2437                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2438                         required-opps = <&rpmhpd_opp_low_svs>;
2439                         #clock-cells = <1>;
2440                         #reset-cells = <1>;
2441                         #power-domain-cells = <1>;
2442                 };
2443
2444                 camcc: clock-controller@ade0000 {
2445                         compatible = "qcom,sm8550-camcc";
2446                         reg = <0 0x0ade0000 0 0x20000>;
2447                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2448                                  <&bi_tcxo_div2>,
2449                                  <&bi_tcxo_ao_div2>,
2450                                  <&sleep_clk>;
2451                         power-domains = <&rpmhpd SM8550_MMCX>;
2452                         required-opps = <&rpmhpd_opp_low_svs>;
2453                         #clock-cells = <1>;
2454                         #reset-cells = <1>;
2455                         #power-domain-cells = <1>;
2456                 };
2457
2458                 mdss: display-subsystem@ae00000 {
2459                         compatible = "qcom,sm8550-mdss";
2460                         reg = <0 0x0ae00000 0 0x1000>;
2461                         reg-names = "mdss";
2462
2463                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2464                         interrupt-controller;
2465                         #interrupt-cells = <1>;
2466
2467                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2468                                  <&gcc GCC_DISP_AHB_CLK>,
2469                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2470                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2471
2472                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2473
2474                         power-domains = <&dispcc MDSS_GDSC>;
2475
2476                         interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2477                                         <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2478                         interconnect-names = "mdp0-mem", "mdp1-mem";
2479
2480                         iommus = <&apps_smmu 0x1c00 0x2>;
2481
2482                         #address-cells = <2>;
2483                         #size-cells = <2>;
2484                         ranges;
2485
2486                         status = "disabled";
2487
2488                         mdss_mdp: display-controller@ae01000 {
2489                                 compatible = "qcom,sm8550-dpu";
2490                                 reg = <0 0x0ae01000 0 0x8f000>,
2491                                       <0 0x0aeb0000 0 0x2008>;
2492                                 reg-names = "mdp", "vbif";
2493
2494                                 interrupt-parent = <&mdss>;
2495                                 interrupts = <0>;
2496
2497                                 clocks = <&gcc GCC_DISP_AHB_CLK>,
2498                                          <&gcc GCC_DISP_HF_AXI_CLK>,
2499                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2500                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2501                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2502                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2503                                 clock-names = "bus",
2504                                               "nrt_bus",
2505                                               "iface",
2506                                               "lut",
2507                                               "core",
2508                                               "vsync";
2509
2510                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2511
2512                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2513                                 assigned-clock-rates = <19200000>;
2514
2515                                 operating-points-v2 = <&mdp_opp_table>;
2516
2517                                 ports {
2518                                         #address-cells = <1>;
2519                                         #size-cells = <0>;
2520
2521                                         port@0 {
2522                                                 reg = <0>;
2523                                                 dpu_intf1_out: endpoint {
2524                                                         remote-endpoint = <&mdss_dsi0_in>;
2525                                                 };
2526                                         };
2527
2528                                         port@1 {
2529                                                 reg = <1>;
2530                                                 dpu_intf2_out: endpoint {
2531                                                         remote-endpoint = <&mdss_dsi1_in>;
2532                                                 };
2533                                         };
2534
2535                                         port@2 {
2536                                                 reg = <2>;
2537                                                 dpu_intf0_out: endpoint {
2538                                                         remote-endpoint = <&mdss_dp0_in>;
2539                                                 };
2540                                         };
2541                                 };
2542
2543                                 mdp_opp_table: opp-table {
2544                                         compatible = "operating-points-v2";
2545
2546                                         opp-200000000 {
2547                                                 opp-hz = /bits/ 64 <200000000>;
2548                                                 required-opps = <&rpmhpd_opp_low_svs>;
2549                                         };
2550
2551                                         opp-325000000 {
2552                                                 opp-hz = /bits/ 64 <325000000>;
2553                                                 required-opps = <&rpmhpd_opp_svs>;
2554                                         };
2555
2556                                         opp-375000000 {
2557                                                 opp-hz = /bits/ 64 <375000000>;
2558                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2559                                         };
2560
2561                                         opp-514000000 {
2562                                                 opp-hz = /bits/ 64 <514000000>;
2563                                                 required-opps = <&rpmhpd_opp_nom>;
2564                                         };
2565                                 };
2566                         };
2567
2568                         mdss_dp0: displayport-controller@ae90000 {
2569                                 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2570                                 reg = <0 0xae90000 0 0x200>,
2571                                       <0 0xae90200 0 0x200>,
2572                                       <0 0xae90400 0 0xc00>,
2573                                       <0 0xae91000 0 0x400>,
2574                                       <0 0xae91400 0 0x400>;
2575                                 interrupt-parent = <&mdss>;
2576                                 interrupts = <12>;
2577                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2578                                          <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
2579                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
2580                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
2581                                          <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
2582                                 clock-names = "core_iface",
2583                                               "core_aux",
2584                                               "ctrl_link",
2585                                               "ctrl_link_iface",
2586                                               "stream_pixel";
2587
2588                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2589                                                   <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
2590                                 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2591                                                          <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2592
2593                                 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
2594                                 phy-names = "dp";
2595
2596                                 #sound-dai-cells = <0>;
2597
2598                                 operating-points-v2 = <&dp_opp_table>;
2599                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2600
2601                                 status = "disabled";
2602
2603                                 ports {
2604                                         #address-cells = <1>;
2605                                         #size-cells = <0>;
2606
2607                                         port@0 {
2608                                                 reg = <0>;
2609                                                 mdss_dp0_in: endpoint {
2610                                                         remote-endpoint = <&dpu_intf0_out>;
2611                                                 };
2612                                         };
2613
2614                                         port@1 {
2615                                                 reg = <1>;
2616                                                 mdss_dp0_out: endpoint {
2617                                                 };
2618                                         };
2619                                 };
2620
2621                                 dp_opp_table: opp-table {
2622                                         compatible = "operating-points-v2";
2623
2624                                         opp-162000000 {
2625                                                 opp-hz = /bits/ 64 <162000000>;
2626                                                 required-opps = <&rpmhpd_opp_low_svs_d1>;
2627                                         };
2628
2629                                         opp-270000000 {
2630                                                 opp-hz = /bits/ 64 <270000000>;
2631                                                 required-opps = <&rpmhpd_opp_low_svs>;
2632                                         };
2633
2634                                         opp-540000000 {
2635                                                 opp-hz = /bits/ 64 <540000000>;
2636                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2637                                         };
2638
2639                                         opp-810000000 {
2640                                                 opp-hz = /bits/ 64 <810000000>;
2641                                                 required-opps = <&rpmhpd_opp_nom>;
2642                                         };
2643                                 };
2644                         };
2645
2646                         mdss_dsi0: dsi@ae94000 {
2647                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2648                                 reg = <0 0x0ae94000 0 0x400>;
2649                                 reg-names = "dsi_ctrl";
2650
2651                                 interrupt-parent = <&mdss>;
2652                                 interrupts = <4>;
2653
2654                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2655                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2656                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2657                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2658                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2659                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2660                                 clock-names = "byte",
2661                                               "byte_intf",
2662                                               "pixel",
2663                                               "core",
2664                                               "iface",
2665                                               "bus";
2666
2667                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2668
2669                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2670                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2671                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2672                                                          <&mdss_dsi0_phy 1>;
2673
2674                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2675
2676                                 phys = <&mdss_dsi0_phy>;
2677                                 phy-names = "dsi";
2678
2679                                 #address-cells = <1>;
2680                                 #size-cells = <0>;
2681
2682                                 status = "disabled";
2683
2684                                 ports {
2685                                         #address-cells = <1>;
2686                                         #size-cells = <0>;
2687
2688                                         port@0 {
2689                                                 reg = <0>;
2690                                                 mdss_dsi0_in: endpoint {
2691                                                         remote-endpoint = <&dpu_intf1_out>;
2692                                                 };
2693                                         };
2694
2695                                         port@1 {
2696                                                 reg = <1>;
2697                                                 mdss_dsi0_out: endpoint {
2698                                                 };
2699                                         };
2700                                 };
2701
2702                                 mdss_dsi_opp_table: opp-table {
2703                                         compatible = "operating-points-v2";
2704
2705                                         opp-187500000 {
2706                                                 opp-hz = /bits/ 64 <187500000>;
2707                                                 required-opps = <&rpmhpd_opp_low_svs>;
2708                                         };
2709
2710                                         opp-300000000 {
2711                                                 opp-hz = /bits/ 64 <300000000>;
2712                                                 required-opps = <&rpmhpd_opp_svs>;
2713                                         };
2714
2715                                         opp-358000000 {
2716                                                 opp-hz = /bits/ 64 <358000000>;
2717                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2718                                         };
2719                                 };
2720                         };
2721
2722                         mdss_dsi0_phy: phy@ae95000 {
2723                                 compatible = "qcom,sm8550-dsi-phy-4nm";
2724                                 reg = <0 0x0ae95000 0 0x200>,
2725                                       <0 0x0ae95200 0 0x280>,
2726                                       <0 0x0ae95500 0 0x400>;
2727                                 reg-names = "dsi_phy",
2728                                             "dsi_phy_lane",
2729                                             "dsi_pll";
2730
2731                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2732                                          <&rpmhcc RPMH_CXO_CLK>;
2733                                 clock-names = "iface", "ref";
2734
2735                                 #clock-cells = <1>;
2736                                 #phy-cells = <0>;
2737
2738                                 status = "disabled";
2739                         };
2740
2741                         mdss_dsi1: dsi@ae96000 {
2742                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2743                                 reg = <0 0x0ae96000 0 0x400>;
2744                                 reg-names = "dsi_ctrl";
2745
2746                                 interrupt-parent = <&mdss>;
2747                                 interrupts = <5>;
2748
2749                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2750                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2751                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2752                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2753                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2754                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2755                                 clock-names = "byte",
2756                                               "byte_intf",
2757                                               "pixel",
2758                                               "core",
2759                                               "iface",
2760                                               "bus";
2761
2762                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2763
2764                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2765                                                   <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2766                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2767                                                          <&mdss_dsi1_phy 1>;
2768
2769                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2770
2771                                 phys = <&mdss_dsi1_phy>;
2772                                 phy-names = "dsi";
2773
2774                                 #address-cells = <1>;
2775                                 #size-cells = <0>;
2776
2777                                 status = "disabled";
2778
2779                                 ports {
2780                                         #address-cells = <1>;
2781                                         #size-cells = <0>;
2782
2783                                         port@0 {
2784                                                 reg = <0>;
2785                                                 mdss_dsi1_in: endpoint {
2786                                                         remote-endpoint = <&dpu_intf2_out>;
2787                                                 };
2788                                         };
2789
2790                                         port@1 {
2791                                                 reg = <1>;
2792                                                 mdss_dsi1_out: endpoint {
2793                                                 };
2794                                         };
2795                                 };
2796                         };
2797
2798                         mdss_dsi1_phy: phy@ae97000 {
2799                                 compatible = "qcom,sm8550-dsi-phy-4nm";
2800                                 reg = <0 0x0ae97000 0 0x200>,
2801                                       <0 0x0ae97200 0 0x280>,
2802                                       <0 0x0ae97500 0 0x400>;
2803                                 reg-names = "dsi_phy",
2804                                             "dsi_phy_lane",
2805                                             "dsi_pll";
2806
2807                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2808                                          <&rpmhcc RPMH_CXO_CLK>;
2809                                 clock-names = "iface", "ref";
2810
2811                                 #clock-cells = <1>;
2812                                 #phy-cells = <0>;
2813
2814                                 status = "disabled";
2815                         };
2816                 };
2817
2818                 dispcc: clock-controller@af00000 {
2819                         compatible = "qcom,sm8550-dispcc";
2820                         reg = <0 0x0af00000 0 0x20000>;
2821                         clocks = <&bi_tcxo_div2>,
2822                                  <&bi_tcxo_ao_div2>,
2823                                  <&gcc GCC_DISP_AHB_CLK>,
2824                                  <&sleep_clk>,
2825                                  <&mdss_dsi0_phy 0>,
2826                                  <&mdss_dsi0_phy 1>,
2827                                  <&mdss_dsi1_phy 0>,
2828                                  <&mdss_dsi1_phy 1>,
2829                                  <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2830                                  <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
2831                                  <0>, /* dp1 */
2832                                  <0>,
2833                                  <0>, /* dp2 */
2834                                  <0>,
2835                                  <0>, /* dp3 */
2836                                  <0>;
2837                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2838                         required-opps = <&rpmhpd_opp_low_svs>;
2839                         #clock-cells = <1>;
2840                         #reset-cells = <1>;
2841                         #power-domain-cells = <1>;
2842                 };
2843
2844                 usb_1_hsphy: phy@88e3000 {
2845                         compatible = "qcom,sm8550-snps-eusb2-phy";
2846                         reg = <0x0 0x088e3000 0x0 0x154>;
2847                         #phy-cells = <0>;
2848
2849                         clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
2850                         clock-names = "ref";
2851
2852                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2853
2854                         status = "disabled";
2855                 };
2856
2857                 usb_dp_qmpphy: phy@88e8000 {
2858                         compatible = "qcom,sm8550-qmp-usb3-dp-phy";
2859                         reg = <0x0 0x088e8000 0x0 0x3000>;
2860
2861                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2862                                  <&rpmhcc RPMH_CXO_CLK>,
2863                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2864                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2865                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2866
2867                         power-domains = <&gcc USB3_PHY_GDSC>;
2868
2869                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2870                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2871                         reset-names = "phy", "common";
2872
2873                         #clock-cells = <1>;
2874                         #phy-cells = <1>;
2875
2876                         status = "disabled";
2877
2878                         ports {
2879                                 #address-cells = <1>;
2880                                 #size-cells = <0>;
2881
2882                                 port@0 {
2883                                         reg = <0>;
2884
2885                                         usb_dp_qmpphy_out: endpoint {
2886                                         };
2887                                 };
2888
2889                                 port@1 {
2890                                         reg = <1>;
2891
2892                                         usb_dp_qmpphy_usb_ss_in: endpoint {
2893                                         };
2894                                 };
2895
2896                                 port@2 {
2897                                         reg = <2>;
2898
2899                                         usb_dp_qmpphy_dp_in: endpoint {
2900                                         };
2901                                 };
2902                         };
2903                 };
2904
2905                 usb_1: usb@a6f8800 {
2906                         compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
2907                         reg = <0x0 0x0a6f8800 0x0 0x400>;
2908                         #address-cells = <2>;
2909                         #size-cells = <2>;
2910                         ranges;
2911
2912                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2913                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2914                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2915                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2916                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2917                                  <&tcsr TCSR_USB3_CLKREF_EN>;
2918                         clock-names = "cfg_noc",
2919                                       "core",
2920                                       "iface",
2921                                       "sleep",
2922                                       "mock_utmi",
2923                                       "xo";
2924
2925                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2926                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2927                         assigned-clock-rates = <19200000>, <200000000>;
2928
2929                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2930                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
2931                                               <&pdc 15 IRQ_TYPE_EDGE_RISING>,
2932                                               <&pdc 14 IRQ_TYPE_EDGE_RISING>;
2933                         interrupt-names = "hs_phy_irq",
2934                                           "ss_phy_irq",
2935                                           "dm_hs_phy_irq",
2936                                           "dp_hs_phy_irq";
2937
2938                         power-domains = <&gcc USB30_PRIM_GDSC>;
2939                         required-opps = <&rpmhpd_opp_nom>;
2940
2941                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2942
2943                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2944                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2945                         interconnect-names = "usb-ddr", "apps-usb";
2946
2947                         status = "disabled";
2948
2949                         usb_1_dwc3: usb@a600000 {
2950                                 compatible = "snps,dwc3";
2951                                 reg = <0x0 0x0a600000 0x0 0xcd00>;
2952                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2953                                 iommus = <&apps_smmu 0x40 0x0>;
2954                                 snps,dis_u2_susphy_quirk;
2955                                 snps,dis_enblslpm_quirk;
2956                                 snps,usb3_lpm_capable;
2957                                 phys = <&usb_1_hsphy>,
2958                                        <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
2959                                 phy-names = "usb2-phy", "usb3-phy";
2960
2961                                 ports {
2962                                         #address-cells = <1>;
2963                                         #size-cells = <0>;
2964
2965                                         port@0 {
2966                                                 reg = <0>;
2967
2968                                                 usb_1_dwc3_hs: endpoint {
2969                                                 };
2970                                         };
2971
2972                                         port@1 {
2973                                                 reg = <1>;
2974
2975                                                 usb_1_dwc3_ss: endpoint {
2976                                                 };
2977                                         };
2978                                 };
2979                         };
2980                 };
2981
2982                 pdc: interrupt-controller@b220000 {
2983                         compatible = "qcom,sm8550-pdc", "qcom,pdc";
2984                         reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
2985                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2986                                           <125 63 1>, <126 716 12>,
2987                                           <138 251 5>;
2988                         #interrupt-cells = <2>;
2989                         interrupt-parent = <&intc>;
2990                         interrupt-controller;
2991                 };
2992
2993                 tsens0: thermal-sensor@c271000 {
2994                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2995                         reg = <0 0x0c271000 0 0x1000>, /* TM */
2996                               <0 0x0c222000 0 0x1000>; /* SROT */
2997                         #qcom,sensors = <16>;
2998                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2999                                      <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
3000                         interrupt-names = "uplow", "critical";
3001                         #thermal-sensor-cells = <1>;
3002                 };
3003
3004                 tsens1: thermal-sensor@c272000 {
3005                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3006                         reg = <0 0x0c272000 0 0x1000>, /* TM */
3007                               <0 0x0c223000 0 0x1000>; /* SROT */
3008                         #qcom,sensors = <16>;
3009                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3010                                      <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
3011                         interrupt-names = "uplow", "critical";
3012                         #thermal-sensor-cells = <1>;
3013                 };
3014
3015                 tsens2: thermal-sensor@c273000 {
3016                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3017                         reg = <0 0x0c273000 0 0x1000>, /* TM */
3018                               <0 0x0c224000 0 0x1000>; /* SROT */
3019                         #qcom,sensors = <16>;
3020                         interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
3021                                      <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
3022                         interrupt-names = "uplow", "critical";
3023                         #thermal-sensor-cells = <1>;
3024                 };
3025
3026                 aoss_qmp: power-management@c300000 {
3027                         compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3028                         reg = <0 0x0c300000 0 0x400>;
3029                         interrupt-parent = <&ipcc>;
3030                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3031                                                      IRQ_TYPE_EDGE_RISING>;
3032                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3033
3034                         #clock-cells = <0>;
3035                 };
3036
3037                 sram@c3f0000 {
3038                         compatible = "qcom,rpmh-stats";
3039                         reg = <0 0x0c3f0000 0 0x400>;
3040                 };
3041
3042                 spmi_bus: spmi@c400000 {
3043                         compatible = "qcom,spmi-pmic-arb";
3044                         reg = <0 0x0c400000 0 0x3000>,
3045                               <0 0x0c500000 0 0x4000000>,
3046                               <0 0x0c440000 0 0x80000>,
3047                               <0 0x0c4c0000 0 0x20000>,
3048                               <0 0x0c42d000 0 0x4000>;
3049                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3050                         interrupt-names = "periph_irq";
3051                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3052                         qcom,ee = <0>;
3053                         qcom,channel = <0>;
3054                         qcom,bus-id = <0>;
3055                         #address-cells = <2>;
3056                         #size-cells = <0>;
3057                         interrupt-controller;
3058                         #interrupt-cells = <4>;
3059                 };
3060
3061                 tlmm: pinctrl@f100000 {
3062                         compatible = "qcom,sm8550-tlmm";
3063                         reg = <0 0x0f100000 0 0x300000>;
3064                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3065                         gpio-controller;
3066                         #gpio-cells = <2>;
3067                         interrupt-controller;
3068                         #interrupt-cells = <2>;
3069                         gpio-ranges = <&tlmm 0 0 211>;
3070                         wakeup-parent = <&pdc>;
3071
3072                         hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3073                                 /* SDA, SCL */
3074                                 pins = "gpio16", "gpio17";
3075                                 function = "i2chub0_se0";
3076                                 drive-strength = <2>;
3077                                 bias-pull-up;
3078                         };
3079
3080                         hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3081                                 /* SDA, SCL */
3082                                 pins = "gpio18", "gpio19";
3083                                 function = "i2chub0_se1";
3084                                 drive-strength = <2>;
3085                                 bias-pull-up;
3086                         };
3087
3088                         hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3089                                 /* SDA, SCL */
3090                                 pins = "gpio20", "gpio21";
3091                                 function = "i2chub0_se2";
3092                                 drive-strength = <2>;
3093                                 bias-pull-up;
3094                         };
3095
3096                         hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3097                                 /* SDA, SCL */
3098                                 pins = "gpio22", "gpio23";
3099                                 function = "i2chub0_se3";
3100                                 drive-strength = <2>;
3101                                 bias-pull-up;
3102                         };
3103
3104                         hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3105                                 /* SDA, SCL */
3106                                 pins = "gpio4", "gpio5";
3107                                 function = "i2chub0_se4";
3108                                 drive-strength = <2>;
3109                                 bias-pull-up;
3110                         };
3111
3112                         hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3113                                 /* SDA, SCL */
3114                                 pins = "gpio6", "gpio7";
3115                                 function = "i2chub0_se5";
3116                                 drive-strength = <2>;
3117                                 bias-pull-up;
3118                         };
3119
3120                         hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3121                                 /* SDA, SCL */
3122                                 pins = "gpio8", "gpio9";
3123                                 function = "i2chub0_se6";
3124                                 drive-strength = <2>;
3125                                 bias-pull-up;
3126                         };
3127
3128                         hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3129                                 /* SDA, SCL */
3130                                 pins = "gpio10", "gpio11";
3131                                 function = "i2chub0_se7";
3132                                 drive-strength = <2>;
3133                                 bias-pull-up;
3134                         };
3135
3136                         hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3137                                 /* SDA, SCL */
3138                                 pins = "gpio206", "gpio207";
3139                                 function = "i2chub0_se8";
3140                                 drive-strength = <2>;
3141                                 bias-pull-up;
3142                         };
3143
3144                         hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3145                                 /* SDA, SCL */
3146                                 pins = "gpio84", "gpio85";
3147                                 function = "i2chub0_se9";
3148                                 drive-strength = <2>;
3149                                 bias-pull-up;
3150                         };
3151
3152                         pcie0_default_state: pcie0-default-state {
3153                                 perst-pins {
3154                                         pins = "gpio94";
3155                                         function = "gpio";
3156                                         drive-strength = <2>;
3157                                         bias-pull-down;
3158                                 };
3159
3160                                 clkreq-pins {
3161                                         pins = "gpio95";
3162                                         function = "pcie0_clk_req_n";
3163                                         drive-strength = <2>;
3164                                         bias-pull-up;
3165                                 };
3166
3167                                 wake-pins {
3168                                         pins = "gpio96";
3169                                         function = "gpio";
3170                                         drive-strength = <2>;
3171                                         bias-pull-up;
3172                                 };
3173                         };
3174
3175                         pcie1_default_state: pcie1-default-state {
3176                                 perst-pins {
3177                                         pins = "gpio97";
3178                                         function = "gpio";
3179                                         drive-strength = <2>;
3180                                         bias-pull-down;
3181                                 };
3182
3183                                 clkreq-pins {
3184                                         pins = "gpio98";
3185                                         function = "pcie1_clk_req_n";
3186                                         drive-strength = <2>;
3187                                         bias-pull-up;
3188                                 };
3189
3190                                 wake-pins {
3191                                         pins = "gpio99";
3192                                         function = "gpio";
3193                                         drive-strength = <2>;
3194                                         bias-pull-up;
3195                                 };
3196                         };
3197
3198                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3199                                 /* SDA, SCL */
3200                                 pins = "gpio28", "gpio29";
3201                                 function = "qup1_se0";
3202                                 drive-strength = <2>;
3203                                 bias-pull-up = <2200>;
3204                         };
3205
3206                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3207                                 /* SDA, SCL */
3208                                 pins = "gpio32", "gpio33";
3209                                 function = "qup1_se1";
3210                                 drive-strength = <2>;
3211                                 bias-pull-up = <2200>;
3212                         };
3213
3214                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3215                                 /* SDA, SCL */
3216                                 pins = "gpio36", "gpio37";
3217                                 function = "qup1_se2";
3218                                 drive-strength = <2>;
3219                                 bias-pull-up = <2200>;
3220                         };
3221
3222                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3223                                 /* SDA, SCL */
3224                                 pins = "gpio40", "gpio41";
3225                                 function = "qup1_se3";
3226                                 drive-strength = <2>;
3227                                 bias-pull-up = <2200>;
3228                         };
3229
3230                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3231                                 /* SDA, SCL */
3232                                 pins = "gpio44", "gpio45";
3233                                 function = "qup1_se4";
3234                                 drive-strength = <2>;
3235                                 bias-pull-up = <2200>;
3236                         };
3237
3238                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3239                                 /* SDA, SCL */
3240                                 pins = "gpio52", "gpio53";
3241                                 function = "qup1_se5";
3242                                 drive-strength = <2>;
3243                                 bias-pull-up = <2200>;
3244                         };
3245
3246                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3247                                 /* SDA, SCL */
3248                                 pins = "gpio48", "gpio49";
3249                                 function = "qup1_se6";
3250                                 drive-strength = <2>;
3251                                 bias-pull-up = <2200>;
3252                         };
3253
3254                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3255                                 scl-pins {
3256                                         pins = "gpio57";
3257                                         function = "qup2_se0_l1_mira";
3258                                         drive-strength = <2>;
3259                                         bias-pull-up = <2200>;
3260                                 };
3261
3262                                 sda-pins {
3263                                         pins = "gpio56";
3264                                         function = "qup2_se0_l0_mira";
3265                                         drive-strength = <2>;
3266                                         bias-pull-up = <2200>;
3267                                 };
3268                         };
3269
3270                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3271                                 /* SDA, SCL */
3272                                 pins = "gpio60", "gpio61";
3273                                 function = "qup2_se1";
3274                                 drive-strength = <2>;
3275                                 bias-pull-up = <2200>;
3276                         };
3277
3278                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3279                                 /* SDA, SCL */
3280                                 pins = "gpio64", "gpio65";
3281                                 function = "qup2_se2";
3282                                 drive-strength = <2>;
3283                                 bias-pull-up = <2200>;
3284                         };
3285
3286                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3287                                 /* SDA, SCL */
3288                                 pins = "gpio68", "gpio69";
3289                                 function = "qup2_se3";
3290                                 drive-strength = <2>;
3291                                 bias-pull-up = <2200>;
3292                         };
3293
3294                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3295                                 /* SDA, SCL */
3296                                 pins = "gpio2", "gpio3";
3297                                 function = "qup2_se4";
3298                                 drive-strength = <2>;
3299                                 bias-pull-up = <2200>;
3300                         };
3301
3302                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3303                                 /* SDA, SCL */
3304                                 pins = "gpio80", "gpio81";
3305                                 function = "qup2_se5";
3306                                 drive-strength = <2>;
3307                                 bias-pull-up = <2200>;
3308                         };
3309
3310                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3311                                 /* SDA, SCL */
3312                                 pins = "gpio72", "gpio106";
3313                                 function = "qup2_se7";
3314                                 drive-strength = <2>;
3315                                 bias-pull-up = <2200>;
3316                         };
3317
3318                         qup_spi0_cs: qup-spi0-cs-state {
3319                                 pins = "gpio31";
3320                                 function = "qup1_se0";
3321                                 drive-strength = <6>;
3322                                 bias-disable;
3323                         };
3324
3325                         qup_spi0_data_clk: qup-spi0-data-clk-state {
3326                                 /* MISO, MOSI, CLK */
3327                                 pins = "gpio28", "gpio29", "gpio30";
3328                                 function = "qup1_se0";
3329                                 drive-strength = <6>;
3330                                 bias-disable;
3331                         };
3332
3333                         qup_spi1_cs: qup-spi1-cs-state {
3334                                 pins = "gpio35";
3335                                 function = "qup1_se1";
3336                                 drive-strength = <6>;
3337                                 bias-disable;
3338                         };
3339
3340                         qup_spi1_data_clk: qup-spi1-data-clk-state {
3341                                 /* MISO, MOSI, CLK */
3342                                 pins = "gpio32", "gpio33", "gpio34";
3343                                 function = "qup1_se1";
3344                                 drive-strength = <6>;
3345                                 bias-disable;
3346                         };
3347
3348                         qup_spi2_cs: qup-spi2-cs-state {
3349                                 pins = "gpio39";
3350                                 function = "qup1_se2";
3351                                 drive-strength = <6>;
3352                                 bias-disable;
3353                         };
3354
3355                         qup_spi2_data_clk: qup-spi2-data-clk-state {
3356                                 /* MISO, MOSI, CLK */
3357                                 pins = "gpio36", "gpio37", "gpio38";
3358                                 function = "qup1_se2";
3359                                 drive-strength = <6>;
3360                                 bias-disable;
3361                         };
3362
3363                         qup_spi3_cs: qup-spi3-cs-state {
3364                                 pins = "gpio43";
3365                                 function = "qup1_se3";
3366                                 drive-strength = <6>;
3367                                 bias-disable;
3368                         };
3369
3370                         qup_spi3_data_clk: qup-spi3-data-clk-state {
3371                                 /* MISO, MOSI, CLK */
3372                                 pins = "gpio40", "gpio41", "gpio42";
3373                                 function = "qup1_se3";
3374                                 drive-strength = <6>;
3375                                 bias-disable;
3376                         };
3377
3378                         qup_spi4_cs: qup-spi4-cs-state {
3379                                 pins = "gpio47";
3380                                 function = "qup1_se4";
3381                                 drive-strength = <6>;
3382                                 bias-disable;
3383                         };
3384
3385                         qup_spi4_data_clk: qup-spi4-data-clk-state {
3386                                 /* MISO, MOSI, CLK */
3387                                 pins = "gpio44", "gpio45", "gpio46";
3388                                 function = "qup1_se4";
3389                                 drive-strength = <6>;
3390                                 bias-disable;
3391                         };
3392
3393                         qup_spi5_cs: qup-spi5-cs-state {
3394                                 pins = "gpio55";
3395                                 function = "qup1_se5";
3396                                 drive-strength = <6>;
3397                                 bias-disable;
3398                         };
3399
3400                         qup_spi5_data_clk: qup-spi5-data-clk-state {
3401                                 /* MISO, MOSI, CLK */
3402                                 pins = "gpio52", "gpio53", "gpio54";
3403                                 function = "qup1_se5";
3404                                 drive-strength = <6>;
3405                                 bias-disable;
3406                         };
3407
3408                         qup_spi6_cs: qup-spi6-cs-state {
3409                                 pins = "gpio51";
3410                                 function = "qup1_se6";
3411                                 drive-strength = <6>;
3412                                 bias-disable;
3413                         };
3414
3415                         qup_spi6_data_clk: qup-spi6-data-clk-state {
3416                                 /* MISO, MOSI, CLK */
3417                                 pins = "gpio48", "gpio49", "gpio50";
3418                                 function = "qup1_se6";
3419                                 drive-strength = <6>;
3420                                 bias-disable;
3421                         };
3422
3423                         qup_spi8_cs: qup-spi8-cs-state {
3424                                 pins = "gpio59";
3425                                 function = "qup2_se0_l3_mira";
3426                                 drive-strength = <6>;
3427                                 bias-disable;
3428                         };
3429
3430                         qup_spi8_data_clk: qup-spi8-data-clk-state {
3431                                 /* MISO, MOSI, CLK */
3432                                 pins = "gpio56", "gpio57", "gpio58";
3433                                 function = "qup2_se0_l2_mira";
3434                                 drive-strength = <6>;
3435                                 bias-disable;
3436                         };
3437
3438                         qup_spi9_cs: qup-spi9-cs-state {
3439                                 pins = "gpio63";
3440                                 function = "qup2_se1";
3441                                 drive-strength = <6>;
3442                                 bias-disable;
3443                         };
3444
3445                         qup_spi9_data_clk: qup-spi9-data-clk-state {
3446                                 /* MISO, MOSI, CLK */
3447                                 pins = "gpio60", "gpio61", "gpio62";
3448                                 function = "qup2_se1";
3449                                 drive-strength = <6>;
3450                                 bias-disable;
3451                         };
3452
3453                         qup_spi10_cs: qup-spi10-cs-state {
3454                                 pins = "gpio67";
3455                                 function = "qup2_se2";
3456                                 drive-strength = <6>;
3457                                 bias-disable;
3458                         };
3459
3460                         qup_spi10_data_clk: qup-spi10-data-clk-state {
3461                                 /* MISO, MOSI, CLK */
3462                                 pins = "gpio64", "gpio65", "gpio66";
3463                                 function = "qup2_se2";
3464                                 drive-strength = <6>;
3465                                 bias-disable;
3466                         };
3467
3468                         qup_spi11_cs: qup-spi11-cs-state {
3469                                 pins = "gpio71";
3470                                 function = "qup2_se3";
3471                                 drive-strength = <6>;
3472                                 bias-disable;
3473                         };
3474
3475                         qup_spi11_data_clk: qup-spi11-data-clk-state {
3476                                 /* MISO, MOSI, CLK */
3477                                 pins = "gpio68", "gpio69", "gpio70";
3478                                 function = "qup2_se3";
3479                                 drive-strength = <6>;
3480                                 bias-disable;
3481                         };
3482
3483                         qup_spi12_cs: qup-spi12-cs-state {
3484                                 pins = "gpio119";
3485                                 function = "qup2_se4";
3486                                 drive-strength = <6>;
3487                                 bias-disable;
3488                         };
3489
3490                         qup_spi12_data_clk: qup-spi12-data-clk-state {
3491                                 /* MISO, MOSI, CLK */
3492                                 pins = "gpio2", "gpio3", "gpio118";
3493                                 function = "qup2_se4";
3494                                 drive-strength = <6>;
3495                                 bias-disable;
3496                         };
3497
3498                         qup_spi13_cs: qup-spi13-cs-state {
3499                                 pins = "gpio83";
3500                                 function = "qup2_se5";
3501                                 drive-strength = <6>;
3502                                 bias-disable;
3503                         };
3504
3505                         qup_spi13_data_clk: qup-spi13-data-clk-state {
3506                                 /* MISO, MOSI, CLK */
3507                                 pins = "gpio80", "gpio81", "gpio82";
3508                                 function = "qup2_se5";
3509                                 drive-strength = <6>;
3510                                 bias-disable;
3511                         };
3512
3513                         qup_spi15_cs: qup-spi15-cs-state {
3514                                 pins = "gpio75";
3515                                 function = "qup2_se7";
3516                                 drive-strength = <6>;
3517                                 bias-disable;
3518                         };
3519
3520                         qup_spi15_data_clk: qup-spi15-data-clk-state {
3521                                 /* MISO, MOSI, CLK */
3522                                 pins = "gpio72", "gpio106", "gpio74";
3523                                 function = "qup2_se7";
3524                                 drive-strength = <6>;
3525                                 bias-disable;
3526                         };
3527
3528                         qup_uart7_default: qup-uart7-default-state {
3529                                 /* TX, RX */
3530                                 pins = "gpio26", "gpio27";
3531                                 function = "qup1_se7";
3532                                 drive-strength = <2>;
3533                                 bias-disable;
3534                         };
3535
3536                         qup_uart14_default: qup-uart14-default-state {
3537                                 /* TX, RX */
3538                                 pins = "gpio78", "gpio79";
3539                                 function = "qup2_se6";
3540                                 drive-strength = <2>;
3541                                 bias-pull-up;
3542                         };
3543
3544                         qup_uart14_cts_rts: qup-uart14-cts-rts-state {
3545                                 /* CTS, RTS */
3546                                 pins = "gpio76", "gpio77";
3547                                 function = "qup2_se6";
3548                                 drive-strength = <2>;
3549                                 bias-pull-down;
3550                         };
3551
3552                         sdc2_sleep: sdc2-sleep-state {
3553                                 clk-pins {
3554                                         pins = "sdc2_clk";
3555                                         bias-disable;
3556                                         drive-strength = <2>;
3557                                 };
3558
3559                                 cmd-pins {
3560                                         pins = "sdc2_cmd";
3561                                         bias-pull-up;
3562                                         drive-strength = <2>;
3563                                 };
3564
3565                                 data-pins {
3566                                         pins = "sdc2_data";
3567                                         bias-pull-up;
3568                                         drive-strength = <2>;
3569                                 };
3570                         };
3571
3572                         sdc2_default: sdc2-default-state {
3573                                 clk-pins {
3574                                         pins = "sdc2_clk";
3575                                         bias-disable;
3576                                         drive-strength = <16>;
3577                                 };
3578
3579                                 cmd-pins {
3580                                         pins = "sdc2_cmd";
3581                                         bias-pull-up;
3582                                         drive-strength = <10>;
3583                                 };
3584
3585                                 data-pins {
3586                                         pins = "sdc2_data";
3587                                         bias-pull-up;
3588                                         drive-strength = <10>;
3589                                 };
3590                         };
3591                 };
3592
3593                 apps_smmu: iommu@15000000 {
3594                         compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3595                         reg = <0 0x15000000 0 0x100000>;
3596                         #iommu-cells = <2>;
3597                         #global-interrupts = <1>;
3598                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3599                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3600                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3601                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3602                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3603                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3604                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3605                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3606                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3607                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3608                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3609                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3610                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3611                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3612                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3613                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3614                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3615                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3616                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3617                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3618                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3619                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3620                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3621                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3622                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3623                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3624                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3625                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3626                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3627                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3628                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3629                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3630                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3631                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3632                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3633                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3634                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3635                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3636                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3637                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3638                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3639                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3640                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3641                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3642                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3643                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3644                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3645                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3646                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3647                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3648                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3649                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3650                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3651                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3652                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3653                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3654                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3655                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3656                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3657                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3658                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3659                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3660                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3661                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3662                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3663                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3664                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3665                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3666                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3667                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3668                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3669                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3670                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3671                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3672                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3673                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3674                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3675                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3676                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3677                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3678                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3679                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3680                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3681                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3682                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3683                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3684                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3685                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3686                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3687                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3688                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3689                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3690                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3691                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3692                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3693                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3694                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
3695                 };
3696
3697                 intc: interrupt-controller@17100000 {
3698                         compatible = "arm,gic-v3";
3699                         reg = <0 0x17100000 0 0x10000>,         /* GICD */
3700                               <0 0x17180000 0 0x200000>;        /* GICR * 8 */
3701                         ranges;
3702                         #interrupt-cells = <3>;
3703                         interrupt-controller;
3704                         #redistributor-regions = <1>;
3705                         redistributor-stride = <0 0x40000>;
3706                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
3707                         #address-cells = <2>;
3708                         #size-cells = <2>;
3709
3710                         gic_its: msi-controller@17140000 {
3711                                 compatible = "arm,gic-v3-its";
3712                                 reg = <0 0x17140000 0 0x20000>;
3713                                 msi-controller;
3714                                 #msi-cells = <1>;
3715                         };
3716                 };
3717
3718                 timer@17420000 {
3719                         compatible = "arm,armv7-timer-mem";
3720                         reg = <0 0x17420000 0 0x1000>;
3721                         ranges = <0 0 0 0x20000000>;
3722                         #address-cells = <1>;
3723                         #size-cells = <1>;
3724
3725                         frame@17421000 {
3726                                 reg = <0x17421000 0x1000>,
3727                                       <0x17422000 0x1000>;
3728                                 frame-number = <0>;
3729                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3730                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3731                         };
3732
3733                         frame@17423000 {
3734                                 reg = <0x17423000 0x1000>;
3735                                 frame-number = <1>;
3736                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3737                                 status = "disabled";
3738                         };
3739
3740                         frame@17425000 {
3741                                 reg = <0x17425000 0x1000>;
3742                                 frame-number = <2>;
3743                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3744                                 status = "disabled";
3745                         };
3746
3747                         frame@17427000 {
3748                                 reg = <0x17427000 0x1000>;
3749                                 frame-number = <3>;
3750                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3751                                 status = "disabled";
3752                         };
3753
3754                         frame@17429000 {
3755                                 reg = <0x17429000 0x1000>;
3756                                 frame-number = <4>;
3757                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3758                                 status = "disabled";
3759                         };
3760
3761                         frame@1742b000 {
3762                                 reg = <0x1742b000 0x1000>;
3763                                 frame-number = <5>;
3764                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3765                                 status = "disabled";
3766                         };
3767
3768                         frame@1742d000 {
3769                                 reg = <0x1742d000 0x1000>;
3770                                 frame-number = <6>;
3771                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3772                                 status = "disabled";
3773                         };
3774                 };
3775
3776                 apps_rsc: rsc@17a00000 {
3777                         label = "apps_rsc";
3778                         compatible = "qcom,rpmh-rsc";
3779                         reg = <0 0x17a00000 0 0x10000>,
3780                               <0 0x17a10000 0 0x10000>,
3781                               <0 0x17a20000 0 0x10000>,
3782                               <0 0x17a30000 0 0x10000>;
3783                         reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3784                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3785                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3786                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3787                         qcom,tcs-offset = <0xd00>;
3788                         qcom,drv-id = <2>;
3789                         qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
3790                                           <WAKE_TCS      2>, <CONTROL_TCS   0>;
3791                         power-domains = <&CLUSTER_PD>;
3792
3793                         apps_bcm_voter: bcm-voter {
3794                                 compatible = "qcom,bcm-voter";
3795                         };
3796
3797                         rpmhcc: clock-controller {
3798                                 compatible = "qcom,sm8550-rpmh-clk";
3799                                 #clock-cells = <1>;
3800                                 clock-names = "xo";
3801                                 clocks = <&xo_board>;
3802                         };
3803
3804                         rpmhpd: power-controller {
3805                                 compatible = "qcom,sm8550-rpmhpd";
3806                                 #power-domain-cells = <1>;
3807                                 operating-points-v2 = <&rpmhpd_opp_table>;
3808
3809                                 rpmhpd_opp_table: opp-table {
3810                                         compatible = "operating-points-v2";
3811
3812                                         rpmhpd_opp_ret: opp-16 {
3813                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3814                                         };
3815
3816                                         rpmhpd_opp_min_svs: opp-48 {
3817                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3818                                         };
3819
3820                                         rpmhpd_opp_low_svs_d2: opp-52 {
3821                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
3822                                         };
3823
3824                                         rpmhpd_opp_low_svs_d1: opp-56 {
3825                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3826                                         };
3827
3828                                         rpmhpd_opp_low_svs_d0: opp-60 {
3829                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
3830                                         };
3831
3832                                         rpmhpd_opp_low_svs: opp-64 {
3833                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3834                                         };
3835
3836                                         rpmhpd_opp_low_svs_l1: opp-80 {
3837                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
3838                                         };
3839
3840                                         rpmhpd_opp_svs: opp-128 {
3841                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3842                                         };
3843
3844                                         rpmhpd_opp_svs_l0: opp-144 {
3845                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
3846                                         };
3847
3848                                         rpmhpd_opp_svs_l1: opp-192 {
3849                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3850                                         };
3851
3852                                         rpmhpd_opp_nom: opp-256 {
3853                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3854                                         };
3855
3856                                         rpmhpd_opp_nom_l1: opp-320 {
3857                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3858                                         };
3859
3860                                         rpmhpd_opp_nom_l2: opp-336 {
3861                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3862                                         };
3863
3864                                         rpmhpd_opp_turbo: opp-384 {
3865                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3866                                         };
3867
3868                                         rpmhpd_opp_turbo_l1: opp-416 {
3869                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3870                                         };
3871                                 };
3872                         };
3873                 };
3874
3875                 cpufreq_hw: cpufreq@17d91000 {
3876                         compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
3877                         reg = <0 0x17d91000 0 0x1000>,
3878                               <0 0x17d92000 0 0x1000>,
3879                               <0 0x17d93000 0 0x1000>;
3880                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3881                         clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
3882                         clock-names = "xo", "alternate";
3883                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
3884                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3885                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
3886                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3887                         #freq-domain-cells = <1>;
3888                         #clock-cells = <1>;
3889                 };
3890
3891                 pmu@24091000 {
3892                         compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3893                         reg = <0 0x24091000 0 0x1000>;
3894                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3895                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3896
3897                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3898
3899                         llcc_bwmon_opp_table: opp-table {
3900                                 compatible = "operating-points-v2";
3901
3902                                 opp-0 {
3903                                         opp-peak-kBps = <2086000>;
3904                                 };
3905
3906                                 opp-1 {
3907                                         opp-peak-kBps = <2929000>;
3908                                 };
3909
3910                                 opp-2 {
3911                                         opp-peak-kBps = <5931000>;
3912                                 };
3913
3914                                 opp-3 {
3915                                         opp-peak-kBps = <6515000>;
3916                                 };
3917
3918                                 opp-4 {
3919                                         opp-peak-kBps = <7980000>;
3920                                 };
3921
3922                                 opp-5 {
3923                                         opp-peak-kBps = <10437000>;
3924                                 };
3925
3926                                 opp-6 {
3927                                         opp-peak-kBps = <12157000>;
3928                                 };
3929
3930                                 opp-7 {
3931                                         opp-peak-kBps = <14060000>;
3932                                 };
3933
3934                                 opp-8 {
3935                                         opp-peak-kBps = <16113000>;
3936                                 };
3937                         };
3938                 };
3939
3940                 pmu@240b6400 {
3941                         compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
3942                         reg = <0 0x240b6400 0 0x600>;
3943                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3944                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3945
3946                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3947
3948                         cpu_bwmon_opp_table: opp-table {
3949                                 compatible = "operating-points-v2";
3950
3951                                 opp-0 {
3952                                         opp-peak-kBps = <4577000>;
3953                                 };
3954
3955                                 opp-1 {
3956                                         opp-peak-kBps = <7110000>;
3957                                 };
3958
3959                                 opp-2 {
3960                                         opp-peak-kBps = <9155000>;
3961                                 };
3962
3963                                 opp-3 {
3964                                         opp-peak-kBps = <12298000>;
3965                                 };
3966
3967                                 opp-4 {
3968                                         opp-peak-kBps = <14236000>;
3969                                 };
3970
3971                                 opp-5 {
3972                                         opp-peak-kBps = <16265000>;
3973                                 };
3974                         };
3975                 };
3976
3977                 gem_noc: interconnect@24100000 {
3978                         compatible = "qcom,sm8550-gem-noc";
3979                         reg = <0 0x24100000 0 0xbb800>;
3980                         #interconnect-cells = <2>;
3981                         qcom,bcm-voters = <&apps_bcm_voter>;
3982                 };
3983
3984                 system-cache-controller@25000000 {
3985                         compatible = "qcom,sm8550-llcc";
3986                         reg = <0 0x25000000 0 0x200000>,
3987                               <0 0x25200000 0 0x200000>,
3988                               <0 0x25400000 0 0x200000>,
3989                               <0 0x25600000 0 0x200000>,
3990                               <0 0x25800000 0 0x200000>;
3991                         reg-names = "llcc0_base",
3992                                     "llcc1_base",
3993                                     "llcc2_base",
3994                                     "llcc3_base",
3995                                     "llcc_broadcast_base";
3996                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
3997                 };
3998
3999                 remoteproc_adsp: remoteproc@30000000 {
4000                         compatible = "qcom,sm8550-adsp-pas";
4001                         reg = <0x0 0x30000000 0x0 0x100>;
4002
4003                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4004                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4005                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4006                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4007                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4008                         interrupt-names = "wdog", "fatal", "ready",
4009                                           "handover", "stop-ack";
4010
4011                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4012                         clock-names = "xo";
4013
4014                         power-domains = <&rpmhpd RPMHPD_LCX>,
4015                                         <&rpmhpd RPMHPD_LMX>;
4016                         power-domain-names = "lcx", "lmx";
4017
4018                         interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
4019
4020                         memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4021
4022                         qcom,qmp = <&aoss_qmp>;
4023
4024                         qcom,smem-states = <&smp2p_adsp_out 0>;
4025                         qcom,smem-state-names = "stop";
4026
4027                         status = "disabled";
4028
4029                         remoteproc_adsp_glink: glink-edge {
4030                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4031                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4032                                                              IRQ_TYPE_EDGE_RISING>;
4033                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
4034                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4035
4036                                 label = "lpass";
4037                                 qcom,remote-pid = <2>;
4038
4039                                 fastrpc {
4040                                         compatible = "qcom,fastrpc";
4041                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4042                                         label = "adsp";
4043                                         #address-cells = <1>;
4044                                         #size-cells = <0>;
4045
4046                                         compute-cb@3 {
4047                                                 compatible = "qcom,fastrpc-compute-cb";
4048                                                 reg = <3>;
4049                                                 iommus = <&apps_smmu 0x1003 0x80>,
4050                                                          <&apps_smmu 0x1063 0x0>;
4051                                         };
4052
4053                                         compute-cb@4 {
4054                                                 compatible = "qcom,fastrpc-compute-cb";
4055                                                 reg = <4>;
4056                                                 iommus = <&apps_smmu 0x1004 0x80>,
4057                                                          <&apps_smmu 0x1064 0x0>;
4058                                         };
4059
4060                                         compute-cb@5 {
4061                                                 compatible = "qcom,fastrpc-compute-cb";
4062                                                 reg = <5>;
4063                                                 iommus = <&apps_smmu 0x1005 0x80>,
4064                                                          <&apps_smmu 0x1065 0x0>;
4065                                         };
4066
4067                                         compute-cb@6 {
4068                                                 compatible = "qcom,fastrpc-compute-cb";
4069                                                 reg = <6>;
4070                                                 iommus = <&apps_smmu 0x1006 0x80>,
4071                                                          <&apps_smmu 0x1066 0x0>;
4072                                         };
4073
4074                                         compute-cb@7 {
4075                                                 compatible = "qcom,fastrpc-compute-cb";
4076                                                 reg = <7>;
4077                                                 iommus = <&apps_smmu 0x1007 0x80>,
4078                                                          <&apps_smmu 0x1067 0x0>;
4079                                         };
4080                                 };
4081
4082                                 gpr {
4083                                         compatible = "qcom,gpr";
4084                                         qcom,glink-channels = "adsp_apps";
4085                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
4086                                         qcom,intents = <512 20>;
4087                                         #address-cells = <1>;
4088                                         #size-cells = <0>;
4089
4090                                         q6apm: service@1 {
4091                                                 compatible = "qcom,q6apm";
4092                                                 reg = <GPR_APM_MODULE_IID>;
4093                                                 #sound-dai-cells = <0>;
4094                                                 qcom,protection-domain = "avs/audio",
4095                                                                          "msm/adsp/audio_pd";
4096
4097                                                 q6apmdai: dais {
4098                                                         compatible = "qcom,q6apm-dais";
4099                                                         iommus = <&apps_smmu 0x1001 0x80>,
4100                                                                  <&apps_smmu 0x1061 0x0>;
4101                                                 };
4102
4103                                                 q6apmbedai: bedais {
4104                                                         compatible = "qcom,q6apm-lpass-dais";
4105                                                         #sound-dai-cells = <1>;
4106                                                 };
4107                                         };
4108
4109                                         q6prm: service@2 {
4110                                                 compatible = "qcom,q6prm";
4111                                                 reg = <GPR_PRM_MODULE_IID>;
4112                                                 qcom,protection-domain = "avs/audio",
4113                                                                          "msm/adsp/audio_pd";
4114
4115                                                 q6prmcc: clock-controller {
4116                                                         compatible = "qcom,q6prm-lpass-clocks";
4117                                                         #clock-cells = <2>;
4118                                                 };
4119                                         };
4120                                 };
4121                         };
4122                 };
4123
4124                 nsp_noc: interconnect@320c0000 {
4125                         compatible = "qcom,sm8550-nsp-noc";
4126                         reg = <0 0x320c0000 0 0xe080>;
4127                         #interconnect-cells = <2>;
4128                         qcom,bcm-voters = <&apps_bcm_voter>;
4129                 };
4130
4131                 remoteproc_cdsp: remoteproc@32300000 {
4132                         compatible = "qcom,sm8550-cdsp-pas";
4133                         reg = <0x0 0x32300000 0x0 0x1400000>;
4134
4135                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4136                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4137                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
4138                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
4139                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
4140                         interrupt-names = "wdog", "fatal", "ready",
4141                                           "handover", "stop-ack";
4142
4143                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4144                         clock-names = "xo";
4145
4146                         power-domains = <&rpmhpd RPMHPD_CX>,
4147                                         <&rpmhpd RPMHPD_MXC>,
4148                                         <&rpmhpd RPMHPD_NSP>;
4149                         power-domain-names = "cx", "mxc", "nsp";
4150
4151                         interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4152
4153                         memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4154
4155                         qcom,qmp = <&aoss_qmp>;
4156
4157                         qcom,smem-states = <&smp2p_cdsp_out 0>;
4158                         qcom,smem-state-names = "stop";
4159
4160                         status = "disabled";
4161
4162                         glink-edge {
4163                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4164                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4165                                                              IRQ_TYPE_EDGE_RISING>;
4166                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
4167                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4168
4169                                 label = "cdsp";
4170                                 qcom,remote-pid = <5>;
4171
4172                                 fastrpc {
4173                                         compatible = "qcom,fastrpc";
4174                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4175                                         label = "cdsp";
4176                                         #address-cells = <1>;
4177                                         #size-cells = <0>;
4178
4179                                         compute-cb@1 {
4180                                                 compatible = "qcom,fastrpc-compute-cb";
4181                                                 reg = <1>;
4182                                                 iommus = <&apps_smmu 0x1961 0x0>,
4183                                                          <&apps_smmu 0x0c01 0x20>,
4184                                                          <&apps_smmu 0x19c1 0x10>;
4185                                         };
4186
4187                                         compute-cb@2 {
4188                                                 compatible = "qcom,fastrpc-compute-cb";
4189                                                 reg = <2>;
4190                                                 iommus = <&apps_smmu 0x1962 0x0>,
4191                                                          <&apps_smmu 0x0c02 0x20>,
4192                                                          <&apps_smmu 0x19c2 0x10>;
4193                                         };
4194
4195                                         compute-cb@3 {
4196                                                 compatible = "qcom,fastrpc-compute-cb";
4197                                                 reg = <3>;
4198                                                 iommus = <&apps_smmu 0x1963 0x0>,
4199                                                          <&apps_smmu 0x0c03 0x20>,
4200                                                          <&apps_smmu 0x19c3 0x10>;
4201                                         };
4202
4203                                         compute-cb@4 {
4204                                                 compatible = "qcom,fastrpc-compute-cb";
4205                                                 reg = <4>;
4206                                                 iommus = <&apps_smmu 0x1964 0x0>,
4207                                                          <&apps_smmu 0x0c04 0x20>,
4208                                                          <&apps_smmu 0x19c4 0x10>;
4209                                         };
4210
4211                                         compute-cb@5 {
4212                                                 compatible = "qcom,fastrpc-compute-cb";
4213                                                 reg = <5>;
4214                                                 iommus = <&apps_smmu 0x1965 0x0>,
4215                                                          <&apps_smmu 0x0c05 0x20>,
4216                                                          <&apps_smmu 0x19c5 0x10>;
4217                                         };
4218
4219                                         compute-cb@6 {
4220                                                 compatible = "qcom,fastrpc-compute-cb";
4221                                                 reg = <6>;
4222                                                 iommus = <&apps_smmu 0x1966 0x0>,
4223                                                          <&apps_smmu 0x0c06 0x20>,
4224                                                          <&apps_smmu 0x19c6 0x10>;
4225                                         };
4226
4227                                         compute-cb@7 {
4228                                                 compatible = "qcom,fastrpc-compute-cb";
4229                                                 reg = <7>;
4230                                                 iommus = <&apps_smmu 0x1967 0x0>,
4231                                                          <&apps_smmu 0x0c07 0x20>,
4232                                                          <&apps_smmu 0x19c7 0x10>;
4233                                         };
4234
4235                                         compute-cb@8 {
4236                                                 compatible = "qcom,fastrpc-compute-cb";
4237                                                 reg = <8>;
4238                                                 iommus = <&apps_smmu 0x1968 0x0>,
4239                                                          <&apps_smmu 0x0c08 0x20>,
4240                                                          <&apps_smmu 0x19c8 0x10>;
4241                                         };
4242
4243                                         /* note: secure cb9 in downstream */
4244                                 };
4245                         };
4246                 };
4247         };
4248
4249         thermal-zones {
4250                 aoss0-thermal {
4251                         polling-delay-passive = <0>;
4252                         polling-delay = <0>;
4253                         thermal-sensors = <&tsens0 0>;
4254
4255                         trips {
4256                                 thermal-engine-config {
4257                                         temperature = <125000>;
4258                                         hysteresis = <1000>;
4259                                         type = "passive";
4260                                 };
4261
4262                                 reset-mon-config {
4263                                         temperature = <115000>;
4264                                         hysteresis = <5000>;
4265                                         type = "passive";
4266                                 };
4267                         };
4268                 };
4269
4270                 cpuss0-thermal {
4271                         polling-delay-passive = <0>;
4272                         polling-delay = <0>;
4273                         thermal-sensors = <&tsens0 1>;
4274
4275                         trips {
4276                                 thermal-engine-config {
4277                                         temperature = <125000>;
4278                                         hysteresis = <1000>;
4279                                         type = "passive";
4280                                 };
4281
4282                                 reset-mon-config {
4283                                         temperature = <115000>;
4284                                         hysteresis = <5000>;
4285                                         type = "passive";
4286                                 };
4287                         };
4288                 };
4289
4290                 cpuss1-thermal {
4291                         polling-delay-passive = <0>;
4292                         polling-delay = <0>;
4293                         thermal-sensors = <&tsens0 2>;
4294
4295                         trips {
4296                                 thermal-engine-config {
4297                                         temperature = <125000>;
4298                                         hysteresis = <1000>;
4299                                         type = "passive";
4300                                 };
4301
4302                                 reset-mon-config {
4303                                         temperature = <115000>;
4304                                         hysteresis = <5000>;
4305                                         type = "passive";
4306                                 };
4307                         };
4308                 };
4309
4310                 cpuss2-thermal {
4311                         polling-delay-passive = <0>;
4312                         polling-delay = <0>;
4313                         thermal-sensors = <&tsens0 3>;
4314
4315                         trips {
4316                                 thermal-engine-config {
4317                                         temperature = <125000>;
4318                                         hysteresis = <1000>;
4319                                         type = "passive";
4320                                 };
4321
4322                                 reset-mon-config {
4323                                         temperature = <115000>;
4324                                         hysteresis = <5000>;
4325                                         type = "passive";
4326                                 };
4327                         };
4328                 };
4329
4330                 cpuss3-thermal {
4331                         polling-delay-passive = <0>;
4332                         polling-delay = <0>;
4333                         thermal-sensors = <&tsens0 4>;
4334
4335                         trips {
4336                                 thermal-engine-config {
4337                                         temperature = <125000>;
4338                                         hysteresis = <1000>;
4339                                         type = "passive";
4340                                 };
4341
4342                                 reset-mon-config {
4343                                         temperature = <115000>;
4344                                         hysteresis = <5000>;
4345                                         type = "passive";
4346                                 };
4347                         };
4348                 };
4349
4350                 cpu3-top-thermal {
4351                         polling-delay-passive = <0>;
4352                         polling-delay = <0>;
4353                         thermal-sensors = <&tsens0 5>;
4354
4355                         trips {
4356                                 cpu3_top_alert0: trip-point0 {
4357                                         temperature = <90000>;
4358                                         hysteresis = <2000>;
4359                                         type = "passive";
4360                                 };
4361
4362                                 cpu3_top_alert1: trip-point1 {
4363                                         temperature = <95000>;
4364                                         hysteresis = <2000>;
4365                                         type = "passive";
4366                                 };
4367
4368                                 cpu3_top_crit: cpu-critical {
4369                                         temperature = <110000>;
4370                                         hysteresis = <1000>;
4371                                         type = "critical";
4372                                 };
4373                         };
4374                 };
4375
4376                 cpu3-bottom-thermal {
4377                         polling-delay-passive = <0>;
4378                         polling-delay = <0>;
4379                         thermal-sensors = <&tsens0 6>;
4380
4381                         trips {
4382                                 cpu3_bottom_alert0: trip-point0 {
4383                                         temperature = <90000>;
4384                                         hysteresis = <2000>;
4385                                         type = "passive";
4386                                 };
4387
4388                                 cpu3_bottom_alert1: trip-point1 {
4389                                         temperature = <95000>;
4390                                         hysteresis = <2000>;
4391                                         type = "passive";
4392                                 };
4393
4394                                 cpu3_bottom_crit: cpu-critical {
4395                                         temperature = <110000>;
4396                                         hysteresis = <1000>;
4397                                         type = "critical";
4398                                 };
4399                         };
4400                 };
4401
4402                 cpu4-top-thermal {
4403                         polling-delay-passive = <0>;
4404                         polling-delay = <0>;
4405                         thermal-sensors = <&tsens0 7>;
4406
4407                         trips {
4408                                 cpu4_top_alert0: trip-point0 {
4409                                         temperature = <90000>;
4410                                         hysteresis = <2000>;
4411                                         type = "passive";
4412                                 };
4413
4414                                 cpu4_top_alert1: trip-point1 {
4415                                         temperature = <95000>;
4416                                         hysteresis = <2000>;
4417                                         type = "passive";
4418                                 };
4419
4420                                 cpu4_top_crit: cpu-critical {
4421                                         temperature = <110000>;
4422                                         hysteresis = <1000>;
4423                                         type = "critical";
4424                                 };
4425                         };
4426                 };
4427
4428                 cpu4-bottom-thermal {
4429                         polling-delay-passive = <0>;
4430                         polling-delay = <0>;
4431                         thermal-sensors = <&tsens0 8>;
4432
4433                         trips {
4434                                 cpu4_bottom_alert0: trip-point0 {
4435                                         temperature = <90000>;
4436                                         hysteresis = <2000>;
4437                                         type = "passive";
4438                                 };
4439
4440                                 cpu4_bottom_alert1: trip-point1 {
4441                                         temperature = <95000>;
4442                                         hysteresis = <2000>;
4443                                         type = "passive";
4444                                 };
4445
4446                                 cpu4_bottom_crit: cpu-critical {
4447                                         temperature = <110000>;
4448                                         hysteresis = <1000>;
4449                                         type = "critical";
4450                                 };
4451                         };
4452                 };
4453
4454                 cpu5-top-thermal {
4455                         polling-delay-passive = <0>;
4456                         polling-delay = <0>;
4457                         thermal-sensors = <&tsens0 9>;
4458
4459                         trips {
4460                                 cpu5_top_alert0: trip-point0 {
4461                                         temperature = <90000>;
4462                                         hysteresis = <2000>;
4463                                         type = "passive";
4464                                 };
4465
4466                                 cpu5_top_alert1: trip-point1 {
4467                                         temperature = <95000>;
4468                                         hysteresis = <2000>;
4469                                         type = "passive";
4470                                 };
4471
4472                                 cpu5_top_crit: cpu-critical {
4473                                         temperature = <110000>;
4474                                         hysteresis = <1000>;
4475                                         type = "critical";
4476                                 };
4477                         };
4478                 };
4479
4480                 cpu5-bottom-thermal {
4481                         polling-delay-passive = <0>;
4482                         polling-delay = <0>;
4483                         thermal-sensors = <&tsens0 10>;
4484
4485                         trips {
4486                                 cpu5_bottom_alert0: trip-point0 {
4487                                         temperature = <90000>;
4488                                         hysteresis = <2000>;
4489                                         type = "passive";
4490                                 };
4491
4492                                 cpu5_bottom_alert1: trip-point1 {
4493                                         temperature = <95000>;
4494                                         hysteresis = <2000>;
4495                                         type = "passive";
4496                                 };
4497
4498                                 cpu5_bottom_crit: cpu-critical {
4499                                         temperature = <110000>;
4500                                         hysteresis = <1000>;
4501                                         type = "critical";
4502                                 };
4503                         };
4504                 };
4505
4506                 cpu6-top-thermal {
4507                         polling-delay-passive = <0>;
4508                         polling-delay = <0>;
4509                         thermal-sensors = <&tsens0 11>;
4510
4511                         trips {
4512                                 cpu6_top_alert0: trip-point0 {
4513                                         temperature = <90000>;
4514                                         hysteresis = <2000>;
4515                                         type = "passive";
4516                                 };
4517
4518                                 cpu6_top_alert1: trip-point1 {
4519                                         temperature = <95000>;
4520                                         hysteresis = <2000>;
4521                                         type = "passive";
4522                                 };
4523
4524                                 cpu6_top_crit: cpu-critical {
4525                                         temperature = <110000>;
4526                                         hysteresis = <1000>;
4527                                         type = "critical";
4528                                 };
4529                         };
4530                 };
4531
4532                 cpu6-bottom-thermal {
4533                         polling-delay-passive = <0>;
4534                         polling-delay = <0>;
4535                         thermal-sensors = <&tsens0 12>;
4536
4537                         trips {
4538                                 cpu6_bottom_alert0: trip-point0 {
4539                                         temperature = <90000>;
4540                                         hysteresis = <2000>;
4541                                         type = "passive";
4542                                 };
4543
4544                                 cpu6_bottom_alert1: trip-point1 {
4545                                         temperature = <95000>;
4546                                         hysteresis = <2000>;
4547                                         type = "passive";
4548                                 };
4549
4550                                 cpu6_bottom_crit: cpu-critical {
4551                                         temperature = <110000>;
4552                                         hysteresis = <1000>;
4553                                         type = "critical";
4554                                 };
4555                         };
4556                 };
4557
4558                 cpu7-top-thermal {
4559                         polling-delay-passive = <0>;
4560                         polling-delay = <0>;
4561                         thermal-sensors = <&tsens0 13>;
4562
4563                         trips {
4564                                 cpu7_top_alert0: trip-point0 {
4565                                         temperature = <90000>;
4566                                         hysteresis = <2000>;
4567                                         type = "passive";
4568                                 };
4569
4570                                 cpu7_top_alert1: trip-point1 {
4571                                         temperature = <95000>;
4572                                         hysteresis = <2000>;
4573                                         type = "passive";
4574                                 };
4575
4576                                 cpu7_top_crit: cpu-critical {
4577                                         temperature = <110000>;
4578                                         hysteresis = <1000>;
4579                                         type = "critical";
4580                                 };
4581                         };
4582                 };
4583
4584                 cpu7-middle-thermal {
4585                         polling-delay-passive = <0>;
4586                         polling-delay = <0>;
4587                         thermal-sensors = <&tsens0 14>;
4588
4589                         trips {
4590                                 cpu7_middle_alert0: trip-point0 {
4591                                         temperature = <90000>;
4592                                         hysteresis = <2000>;
4593                                         type = "passive";
4594                                 };
4595
4596                                 cpu7_middle_alert1: trip-point1 {
4597                                         temperature = <95000>;
4598                                         hysteresis = <2000>;
4599                                         type = "passive";
4600                                 };
4601
4602                                 cpu7_middle_crit: cpu-critical {
4603                                         temperature = <110000>;
4604                                         hysteresis = <1000>;
4605                                         type = "critical";
4606                                 };
4607                         };
4608                 };
4609
4610                 cpu7-bottom-thermal {
4611                         polling-delay-passive = <0>;
4612                         polling-delay = <0>;
4613                         thermal-sensors = <&tsens0 15>;
4614
4615                         trips {
4616                                 cpu7_bottom_alert0: trip-point0 {
4617                                         temperature = <90000>;
4618                                         hysteresis = <2000>;
4619                                         type = "passive";
4620                                 };
4621
4622                                 cpu7_bottom_alert1: trip-point1 {
4623                                         temperature = <95000>;
4624                                         hysteresis = <2000>;
4625                                         type = "passive";
4626                                 };
4627
4628                                 cpu7_bottom_crit: cpu-critical {
4629                                         temperature = <110000>;
4630                                         hysteresis = <1000>;
4631                                         type = "critical";
4632                                 };
4633                         };
4634                 };
4635
4636                 aoss1-thermal {
4637                         polling-delay-passive = <0>;
4638                         polling-delay = <0>;
4639                         thermal-sensors = <&tsens1 0>;
4640
4641                         trips {
4642                                 thermal-engine-config {
4643                                         temperature = <125000>;
4644                                         hysteresis = <1000>;
4645                                         type = "passive";
4646                                 };
4647
4648                                 reset-mon-config {
4649                                         temperature = <115000>;
4650                                         hysteresis = <5000>;
4651                                         type = "passive";
4652                                 };
4653                         };
4654                 };
4655
4656                 cpu0-thermal {
4657                         polling-delay-passive = <0>;
4658                         polling-delay = <0>;
4659                         thermal-sensors = <&tsens1 1>;
4660
4661                         trips {
4662                                 cpu0_alert0: trip-point0 {
4663                                         temperature = <90000>;
4664                                         hysteresis = <2000>;
4665                                         type = "passive";
4666                                 };
4667
4668                                 cpu0_alert1: trip-point1 {
4669                                         temperature = <95000>;
4670                                         hysteresis = <2000>;
4671                                         type = "passive";
4672                                 };
4673
4674                                 cpu0_crit: cpu-critical {
4675                                         temperature = <110000>;
4676                                         hysteresis = <1000>;
4677                                         type = "critical";
4678                                 };
4679                         };
4680                 };
4681
4682                 cpu1-thermal {
4683                         polling-delay-passive = <0>;
4684                         polling-delay = <0>;
4685                         thermal-sensors = <&tsens1 2>;
4686
4687                         trips {
4688                                 cpu1_alert0: trip-point0 {
4689                                         temperature = <90000>;
4690                                         hysteresis = <2000>;
4691                                         type = "passive";
4692                                 };
4693
4694                                 cpu1_alert1: trip-point1 {
4695                                         temperature = <95000>;
4696                                         hysteresis = <2000>;
4697                                         type = "passive";
4698                                 };
4699
4700                                 cpu1_crit: cpu-critical {
4701                                         temperature = <110000>;
4702                                         hysteresis = <1000>;
4703                                         type = "critical";
4704                                 };
4705                         };
4706                 };
4707
4708                 cpu2-thermal {
4709                         polling-delay-passive = <0>;
4710                         polling-delay = <0>;
4711                         thermal-sensors = <&tsens1 3>;
4712
4713                         trips {
4714                                 cpu2_alert0: trip-point0 {
4715                                         temperature = <90000>;
4716                                         hysteresis = <2000>;
4717                                         type = "passive";
4718                                 };
4719
4720                                 cpu2_alert1: trip-point1 {
4721                                         temperature = <95000>;
4722                                         hysteresis = <2000>;
4723                                         type = "passive";
4724                                 };
4725
4726                                 cpu2_crit: cpu-critical {
4727                                         temperature = <110000>;
4728                                         hysteresis = <1000>;
4729                                         type = "critical";
4730                                 };
4731                         };
4732                 };
4733
4734                 cdsp0-thermal {
4735                         polling-delay-passive = <10>;
4736                         polling-delay = <0>;
4737                         thermal-sensors = <&tsens2 4>;
4738
4739                         trips {
4740                                 thermal-engine-config {
4741                                         temperature = <125000>;
4742                                         hysteresis = <1000>;
4743                                         type = "passive";
4744                                 };
4745
4746                                 thermal-hal-config {
4747                                         temperature = <125000>;
4748                                         hysteresis = <1000>;
4749                                         type = "passive";
4750                                 };
4751
4752                                 reset-mon-config {
4753                                         temperature = <115000>;
4754                                         hysteresis = <5000>;
4755                                         type = "passive";
4756                                 };
4757
4758                                 cdsp0_junction_config: junction-config {
4759                                         temperature = <95000>;
4760                                         hysteresis = <5000>;
4761                                         type = "passive";
4762                                 };
4763                         };
4764                 };
4765
4766                 cdsp1-thermal {
4767                         polling-delay-passive = <10>;
4768                         polling-delay = <0>;
4769                         thermal-sensors = <&tsens2 5>;
4770
4771                         trips {
4772                                 thermal-engine-config {
4773                                         temperature = <125000>;
4774                                         hysteresis = <1000>;
4775                                         type = "passive";
4776                                 };
4777
4778                                 thermal-hal-config {
4779                                         temperature = <125000>;
4780                                         hysteresis = <1000>;
4781                                         type = "passive";
4782                                 };
4783
4784                                 reset-mon-config {
4785                                         temperature = <115000>;
4786                                         hysteresis = <5000>;
4787                                         type = "passive";
4788                                 };
4789
4790                                 cdsp1_junction_config: junction-config {
4791                                         temperature = <95000>;
4792                                         hysteresis = <5000>;
4793                                         type = "passive";
4794                                 };
4795                         };
4796                 };
4797
4798                 cdsp2-thermal {
4799                         polling-delay-passive = <10>;
4800                         polling-delay = <0>;
4801                         thermal-sensors = <&tsens2 6>;
4802
4803                         trips {
4804                                 thermal-engine-config {
4805                                         temperature = <125000>;
4806                                         hysteresis = <1000>;
4807                                         type = "passive";
4808                                 };
4809
4810                                 thermal-hal-config {
4811                                         temperature = <125000>;
4812                                         hysteresis = <1000>;
4813                                         type = "passive";
4814                                 };
4815
4816                                 reset-mon-config {
4817                                         temperature = <115000>;
4818                                         hysteresis = <5000>;
4819                                         type = "passive";
4820                                 };
4821
4822                                 cdsp2_junction_config: junction-config {
4823                                         temperature = <95000>;
4824                                         hysteresis = <5000>;
4825                                         type = "passive";
4826                                 };
4827                         };
4828                 };
4829
4830                 cdsp3-thermal {
4831                         polling-delay-passive = <10>;
4832                         polling-delay = <0>;
4833                         thermal-sensors = <&tsens2 7>;
4834
4835                         trips {
4836                                 thermal-engine-config {
4837                                         temperature = <125000>;
4838                                         hysteresis = <1000>;
4839                                         type = "passive";
4840                                 };
4841
4842                                 thermal-hal-config {
4843                                         temperature = <125000>;
4844                                         hysteresis = <1000>;
4845                                         type = "passive";
4846                                 };
4847
4848                                 reset-mon-config {
4849                                         temperature = <115000>;
4850                                         hysteresis = <5000>;
4851                                         type = "passive";
4852                                 };
4853
4854                                 cdsp3_junction_config: junction-config {
4855                                         temperature = <95000>;
4856                                         hysteresis = <5000>;
4857                                         type = "passive";
4858                                 };
4859                         };
4860                 };
4861
4862                 video-thermal {
4863                         polling-delay-passive = <0>;
4864                         polling-delay = <0>;
4865                         thermal-sensors = <&tsens1 8>;
4866
4867                         trips {
4868                                 thermal-engine-config {
4869                                         temperature = <125000>;
4870                                         hysteresis = <1000>;
4871                                         type = "passive";
4872                                 };
4873
4874                                 reset-mon-config {
4875                                         temperature = <115000>;
4876                                         hysteresis = <5000>;
4877                                         type = "passive";
4878                                 };
4879                         };
4880                 };
4881
4882                 mem-thermal {
4883                         polling-delay-passive = <10>;
4884                         polling-delay = <0>;
4885                         thermal-sensors = <&tsens1 9>;
4886
4887                         trips {
4888                                 thermal-engine-config {
4889                                         temperature = <125000>;
4890                                         hysteresis = <1000>;
4891                                         type = "passive";
4892                                 };
4893
4894                                 ddr_config0: ddr0-config {
4895                                         temperature = <90000>;
4896                                         hysteresis = <5000>;
4897                                         type = "passive";
4898                                 };
4899
4900                                 reset-mon-config {
4901                                         temperature = <115000>;
4902                                         hysteresis = <5000>;
4903                                         type = "passive";
4904                                 };
4905                         };
4906                 };
4907
4908                 modem0-thermal {
4909                         polling-delay-passive = <0>;
4910                         polling-delay = <0>;
4911                         thermal-sensors = <&tsens1 10>;
4912
4913                         trips {
4914                                 thermal-engine-config {
4915                                         temperature = <125000>;
4916                                         hysteresis = <1000>;
4917                                         type = "passive";
4918                                 };
4919
4920                                 mdmss0_config0: mdmss0-config0 {
4921                                         temperature = <102000>;
4922                                         hysteresis = <3000>;
4923                                         type = "passive";
4924                                 };
4925
4926                                 mdmss0_config1: mdmss0-config1 {
4927                                         temperature = <105000>;
4928                                         hysteresis = <3000>;
4929                                         type = "passive";
4930                                 };
4931
4932                                 reset-mon-config {
4933                                         temperature = <115000>;
4934                                         hysteresis = <5000>;
4935                                         type = "passive";
4936                                 };
4937                         };
4938                 };
4939
4940                 modem1-thermal {
4941                         polling-delay-passive = <0>;
4942                         polling-delay = <0>;
4943                         thermal-sensors = <&tsens1 11>;
4944
4945                         trips {
4946                                 thermal-engine-config {
4947                                         temperature = <125000>;
4948                                         hysteresis = <1000>;
4949                                         type = "passive";
4950                                 };
4951
4952                                 mdmss1_config0: mdmss1-config0 {
4953                                         temperature = <102000>;
4954                                         hysteresis = <3000>;
4955                                         type = "passive";
4956                                 };
4957
4958                                 mdmss1_config1: mdmss1-config1 {
4959                                         temperature = <105000>;
4960                                         hysteresis = <3000>;
4961                                         type = "passive";
4962                                 };
4963
4964                                 reset-mon-config {
4965                                         temperature = <115000>;
4966                                         hysteresis = <5000>;
4967                                         type = "passive";
4968                                 };
4969                         };
4970                 };
4971
4972                 modem2-thermal {
4973                         polling-delay-passive = <0>;
4974                         polling-delay = <0>;
4975                         thermal-sensors = <&tsens1 12>;
4976
4977                         trips {
4978                                 thermal-engine-config {
4979                                         temperature = <125000>;
4980                                         hysteresis = <1000>;
4981                                         type = "passive";
4982                                 };
4983
4984                                 mdmss2_config0: mdmss2-config0 {
4985                                         temperature = <102000>;
4986                                         hysteresis = <3000>;
4987                                         type = "passive";
4988                                 };
4989
4990                                 mdmss2_config1: mdmss2-config1 {
4991                                         temperature = <105000>;
4992                                         hysteresis = <3000>;
4993                                         type = "passive";
4994                                 };
4995
4996                                 reset-mon-config {
4997                                         temperature = <115000>;
4998                                         hysteresis = <5000>;
4999                                         type = "passive";
5000                                 };
5001                         };
5002                 };
5003
5004                 modem3-thermal {
5005                         polling-delay-passive = <0>;
5006                         polling-delay = <0>;
5007                         thermal-sensors = <&tsens1 13>;
5008
5009                         trips {
5010                                 thermal-engine-config {
5011                                         temperature = <125000>;
5012                                         hysteresis = <1000>;
5013                                         type = "passive";
5014                                 };
5015
5016                                 mdmss3_config0: mdmss3-config0 {
5017                                         temperature = <102000>;
5018                                         hysteresis = <3000>;
5019                                         type = "passive";
5020                                 };
5021
5022                                 mdmss3_config1: mdmss3-config1 {
5023                                         temperature = <105000>;
5024                                         hysteresis = <3000>;
5025                                         type = "passive";
5026                                 };
5027
5028                                 reset-mon-config {
5029                                         temperature = <115000>;
5030                                         hysteresis = <5000>;
5031                                         type = "passive";
5032                                 };
5033                         };
5034                 };
5035
5036                 camera0-thermal {
5037                         polling-delay-passive = <0>;
5038                         polling-delay = <0>;
5039                         thermal-sensors = <&tsens1 14>;
5040
5041                         trips {
5042                                 thermal-engine-config {
5043                                         temperature = <125000>;
5044                                         hysteresis = <1000>;
5045                                         type = "passive";
5046                                 };
5047
5048                                 reset-mon-config {
5049                                         temperature = <115000>;
5050                                         hysteresis = <5000>;
5051                                         type = "passive";
5052                                 };
5053                         };
5054                 };
5055
5056                 camera1-thermal {
5057                         polling-delay-passive = <0>;
5058                         polling-delay = <0>;
5059                         thermal-sensors = <&tsens1 15>;
5060
5061                         trips {
5062                                 thermal-engine-config {
5063                                         temperature = <125000>;
5064                                         hysteresis = <1000>;
5065                                         type = "passive";
5066                                 };
5067
5068                                 reset-mon-config {
5069                                         temperature = <115000>;
5070                                         hysteresis = <5000>;
5071                                         type = "passive";
5072                                 };
5073                         };
5074                 };
5075
5076                 aoss2-thermal {
5077                         polling-delay-passive = <0>;
5078                         polling-delay = <0>;
5079                         thermal-sensors = <&tsens2 0>;
5080
5081                         trips {
5082                                 thermal-engine-config {
5083                                         temperature = <125000>;
5084                                         hysteresis = <1000>;
5085                                         type = "passive";
5086                                 };
5087
5088                                 reset-mon-config {
5089                                         temperature = <115000>;
5090                                         hysteresis = <5000>;
5091                                         type = "passive";
5092                                 };
5093                         };
5094                 };
5095
5096                 gpuss-0-thermal {
5097                         polling-delay-passive = <10>;
5098                         polling-delay = <0>;
5099                         thermal-sensors = <&tsens2 1>;
5100
5101                         trips {
5102                                 thermal-engine-config {
5103                                         temperature = <125000>;
5104                                         hysteresis = <1000>;
5105                                         type = "passive";
5106                                 };
5107
5108                                 thermal-hal-config {
5109                                         temperature = <125000>;
5110                                         hysteresis = <1000>;
5111                                         type = "passive";
5112                                 };
5113
5114                                 reset-mon-config {
5115                                         temperature = <115000>;
5116                                         hysteresis = <5000>;
5117                                         type = "passive";
5118                                 };
5119
5120                                 gpu0_junction_config: junction-config {
5121                                         temperature = <95000>;
5122                                         hysteresis = <5000>;
5123                                         type = "passive";
5124                                 };
5125                         };
5126                 };
5127
5128                 gpuss-1-thermal {
5129                         polling-delay-passive = <10>;
5130                         polling-delay = <0>;
5131                         thermal-sensors = <&tsens2 2>;
5132
5133                         trips {
5134                                 thermal-engine-config {
5135                                         temperature = <125000>;
5136                                         hysteresis = <1000>;
5137                                         type = "passive";
5138                                 };
5139
5140                                 thermal-hal-config {
5141                                         temperature = <125000>;
5142                                         hysteresis = <1000>;
5143                                         type = "passive";
5144                                 };
5145
5146                                 reset-mon-config {
5147                                         temperature = <115000>;
5148                                         hysteresis = <5000>;
5149                                         type = "passive";
5150                                 };
5151
5152                                 gpu1_junction_config: junction-config {
5153                                         temperature = <95000>;
5154                                         hysteresis = <5000>;
5155                                         type = "passive";
5156                                 };
5157                         };
5158                 };
5159
5160                 gpuss-2-thermal {
5161                         polling-delay-passive = <10>;
5162                         polling-delay = <0>;
5163                         thermal-sensors = <&tsens2 3>;
5164
5165                         trips {
5166                                 thermal-engine-config {
5167                                         temperature = <125000>;
5168                                         hysteresis = <1000>;
5169                                         type = "passive";
5170                                 };
5171
5172                                 thermal-hal-config {
5173                                         temperature = <125000>;
5174                                         hysteresis = <1000>;
5175                                         type = "passive";
5176                                 };
5177
5178                                 reset-mon-config {
5179                                         temperature = <115000>;
5180                                         hysteresis = <5000>;
5181                                         type = "passive";
5182                                 };
5183
5184                                 gpu2_junction_config: junction-config {
5185                                         temperature = <95000>;
5186                                         hysteresis = <5000>;
5187                                         type = "passive";
5188                                 };
5189                         };
5190                 };
5191
5192                 gpuss-3-thermal {
5193                         polling-delay-passive = <10>;
5194                         polling-delay = <0>;
5195                         thermal-sensors = <&tsens2 4>;
5196
5197                         trips {
5198                                 thermal-engine-config {
5199                                         temperature = <125000>;
5200                                         hysteresis = <1000>;
5201                                         type = "passive";
5202                                 };
5203
5204                                 thermal-hal-config {
5205                                         temperature = <125000>;
5206                                         hysteresis = <1000>;
5207                                         type = "passive";
5208                                 };
5209
5210                                 reset-mon-config {
5211                                         temperature = <115000>;
5212                                         hysteresis = <5000>;
5213                                         type = "passive";
5214                                 };
5215
5216                                 gpu3_junction_config: junction-config {
5217                                         temperature = <95000>;
5218                                         hysteresis = <5000>;
5219                                         type = "passive";
5220                                 };
5221                         };
5222                 };
5223
5224                 gpuss-4-thermal {
5225                         polling-delay-passive = <10>;
5226                         polling-delay = <0>;
5227                         thermal-sensors = <&tsens2 5>;
5228
5229                         trips {
5230                                 thermal-engine-config {
5231                                         temperature = <125000>;
5232                                         hysteresis = <1000>;
5233                                         type = "passive";
5234                                 };
5235
5236                                 thermal-hal-config {
5237                                         temperature = <125000>;
5238                                         hysteresis = <1000>;
5239                                         type = "passive";
5240                                 };
5241
5242                                 reset-mon-config {
5243                                         temperature = <115000>;
5244                                         hysteresis = <5000>;
5245                                         type = "passive";
5246                                 };
5247
5248                                 gpu4_junction_config: junction-config {
5249                                         temperature = <95000>;
5250                                         hysteresis = <5000>;
5251                                         type = "passive";
5252                                 };
5253                         };
5254                 };
5255
5256                 gpuss-5-thermal {
5257                         polling-delay-passive = <10>;
5258                         polling-delay = <0>;
5259                         thermal-sensors = <&tsens2 6>;
5260
5261                         trips {
5262                                 thermal-engine-config {
5263                                         temperature = <125000>;
5264                                         hysteresis = <1000>;
5265                                         type = "passive";
5266                                 };
5267
5268                                 thermal-hal-config {
5269                                         temperature = <125000>;
5270                                         hysteresis = <1000>;
5271                                         type = "passive";
5272                                 };
5273
5274                                 reset-mon-config {
5275                                         temperature = <115000>;
5276                                         hysteresis = <5000>;
5277                                         type = "passive";
5278                                 };
5279
5280                                 gpu5_junction_config: junction-config {
5281                                         temperature = <95000>;
5282                                         hysteresis = <5000>;
5283                                         type = "passive";
5284                                 };
5285                         };
5286                 };
5287
5288                 gpuss-6-thermal {
5289                         polling-delay-passive = <10>;
5290                         polling-delay = <0>;
5291                         thermal-sensors = <&tsens2 7>;
5292
5293                         trips {
5294                                 thermal-engine-config {
5295                                         temperature = <125000>;
5296                                         hysteresis = <1000>;
5297                                         type = "passive";
5298                                 };
5299
5300                                 thermal-hal-config {
5301                                         temperature = <125000>;
5302                                         hysteresis = <1000>;
5303                                         type = "passive";
5304                                 };
5305
5306                                 reset-mon-config {
5307                                         temperature = <115000>;
5308                                         hysteresis = <5000>;
5309                                         type = "passive";
5310                                 };
5311
5312                                 gpu6_junction_config: junction-config {
5313                                         temperature = <95000>;
5314                                         hysteresis = <5000>;
5315                                         type = "passive";
5316                                 };
5317                         };
5318                 };
5319
5320                 gpuss-7-thermal {
5321                         polling-delay-passive = <10>;
5322                         polling-delay = <0>;
5323                         thermal-sensors = <&tsens2 8>;
5324
5325                         trips {
5326                                 thermal-engine-config {
5327                                         temperature = <125000>;
5328                                         hysteresis = <1000>;
5329                                         type = "passive";
5330                                 };
5331
5332                                 thermal-hal-config {
5333                                         temperature = <125000>;
5334                                         hysteresis = <1000>;
5335                                         type = "passive";
5336                                 };
5337
5338                                 reset-mon-config {
5339                                         temperature = <115000>;
5340                                         hysteresis = <5000>;
5341                                         type = "passive";
5342                                 };
5343
5344                                 gpu7_junction_config: junction-config {
5345                                         temperature = <95000>;
5346                                         hysteresis = <5000>;
5347                                         type = "passive";
5348                                 };
5349                         };
5350                 };
5351         };
5352
5353         timer {
5354                 compatible = "arm,armv8-timer";
5355                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5356                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5357                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5358                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5359         };
5360 };